1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 */ 67 /* 68 * SERIALIZATION API RULES: 69 * 70 * - We must call lwkt_serialize_handler_enable() prior to enabling the 71 * hardware interrupt and lwkt_serialize_handler_disable() after disabling 72 * the hardware interrupt in order to avoid handler execution races from 73 * scheduled interrupt threads. 74 */ 75 76 #include "opt_ifpoll.h" 77 78 #include <sys/param.h> 79 #include <sys/bus.h> 80 #include <sys/endian.h> 81 #include <sys/interrupt.h> 82 #include <sys/kernel.h> 83 #include <sys/ktr.h> 84 #include <sys/malloc.h> 85 #include <sys/mbuf.h> 86 #include <sys/proc.h> 87 #include <sys/rman.h> 88 #include <sys/serialize.h> 89 #include <sys/socket.h> 90 #include <sys/sockio.h> 91 #include <sys/sysctl.h> 92 #include <sys/systm.h> 93 94 #include <net/bpf.h> 95 #include <net/ethernet.h> 96 #include <net/if.h> 97 #include <net/if_arp.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_poll.h> 101 #include <net/ifq_var.h> 102 #include <net/vlan/if_vlan_var.h> 103 #include <net/vlan/if_vlan_ether.h> 104 105 #include <netinet/ip.h> 106 #include <netinet/tcp.h> 107 #include <netinet/udp.h> 108 109 #include <bus/pci/pcivar.h> 110 #include <bus/pci/pcireg.h> 111 112 #include <dev/netif/ig_hal/e1000_api.h> 113 #include <dev/netif/ig_hal/e1000_82571.h> 114 #include <dev/netif/em/if_em.h> 115 116 #define DEBUG_HW 0 117 118 #define EM_NAME "Intel(R) PRO/1000 Network Connection " 119 #define EM_VER " 7.3.4" 120 121 #define _EM_DEVICE(id, ret) \ 122 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER } 123 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100) 124 #define EM_DEVICE(id) _EM_DEVICE(id, 0) 125 #define EM_DEVICE_NULL { 0, 0, 0, NULL } 126 127 static const struct em_vendor_info em_vendor_info_array[] = { 128 EM_DEVICE(82540EM), 129 EM_DEVICE(82540EM_LOM), 130 EM_DEVICE(82540EP), 131 EM_DEVICE(82540EP_LOM), 132 EM_DEVICE(82540EP_LP), 133 134 EM_DEVICE(82541EI), 135 EM_DEVICE(82541ER), 136 EM_DEVICE(82541ER_LOM), 137 EM_DEVICE(82541EI_MOBILE), 138 EM_DEVICE(82541GI), 139 EM_DEVICE(82541GI_LF), 140 EM_DEVICE(82541GI_MOBILE), 141 142 EM_DEVICE(82542), 143 144 EM_DEVICE(82543GC_FIBER), 145 EM_DEVICE(82543GC_COPPER), 146 147 EM_DEVICE(82544EI_COPPER), 148 EM_DEVICE(82544EI_FIBER), 149 EM_DEVICE(82544GC_COPPER), 150 EM_DEVICE(82544GC_LOM), 151 152 EM_DEVICE(82545EM_COPPER), 153 EM_DEVICE(82545EM_FIBER), 154 EM_DEVICE(82545GM_COPPER), 155 EM_DEVICE(82545GM_FIBER), 156 EM_DEVICE(82545GM_SERDES), 157 158 EM_DEVICE(82546EB_COPPER), 159 EM_DEVICE(82546EB_FIBER), 160 EM_DEVICE(82546EB_QUAD_COPPER), 161 EM_DEVICE(82546GB_COPPER), 162 EM_DEVICE(82546GB_FIBER), 163 EM_DEVICE(82546GB_SERDES), 164 EM_DEVICE(82546GB_PCIE), 165 EM_DEVICE(82546GB_QUAD_COPPER), 166 EM_DEVICE(82546GB_QUAD_COPPER_KSP3), 167 168 EM_DEVICE(82547EI), 169 EM_DEVICE(82547EI_MOBILE), 170 EM_DEVICE(82547GI), 171 172 EM_EMX_DEVICE(82571EB_COPPER), 173 EM_EMX_DEVICE(82571EB_FIBER), 174 EM_EMX_DEVICE(82571EB_SERDES), 175 EM_EMX_DEVICE(82571EB_SERDES_DUAL), 176 EM_EMX_DEVICE(82571EB_SERDES_QUAD), 177 EM_EMX_DEVICE(82571EB_QUAD_COPPER), 178 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP), 179 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP), 180 EM_EMX_DEVICE(82571EB_QUAD_FIBER), 181 EM_EMX_DEVICE(82571PT_QUAD_COPPER), 182 183 EM_EMX_DEVICE(82572EI_COPPER), 184 EM_EMX_DEVICE(82572EI_FIBER), 185 EM_EMX_DEVICE(82572EI_SERDES), 186 EM_EMX_DEVICE(82572EI), 187 188 EM_EMX_DEVICE(82573E), 189 EM_EMX_DEVICE(82573E_IAMT), 190 EM_EMX_DEVICE(82573L), 191 192 EM_DEVICE(82583V), 193 194 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT), 195 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT), 196 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT), 197 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT), 198 199 EM_DEVICE(ICH8_IGP_M_AMT), 200 EM_DEVICE(ICH8_IGP_AMT), 201 EM_DEVICE(ICH8_IGP_C), 202 EM_DEVICE(ICH8_IFE), 203 EM_DEVICE(ICH8_IFE_GT), 204 EM_DEVICE(ICH8_IFE_G), 205 EM_DEVICE(ICH8_IGP_M), 206 EM_DEVICE(ICH8_82567V_3), 207 208 EM_DEVICE(ICH9_IGP_M_AMT), 209 EM_DEVICE(ICH9_IGP_AMT), 210 EM_DEVICE(ICH9_IGP_C), 211 EM_DEVICE(ICH9_IGP_M), 212 EM_DEVICE(ICH9_IGP_M_V), 213 EM_DEVICE(ICH9_IFE), 214 EM_DEVICE(ICH9_IFE_GT), 215 EM_DEVICE(ICH9_IFE_G), 216 EM_DEVICE(ICH9_BM), 217 218 EM_EMX_DEVICE(82574L), 219 EM_EMX_DEVICE(82574LA), 220 221 EM_DEVICE(ICH10_R_BM_LM), 222 EM_DEVICE(ICH10_R_BM_LF), 223 EM_DEVICE(ICH10_R_BM_V), 224 EM_DEVICE(ICH10_D_BM_LM), 225 EM_DEVICE(ICH10_D_BM_LF), 226 EM_DEVICE(ICH10_D_BM_V), 227 228 EM_DEVICE(PCH_M_HV_LM), 229 EM_DEVICE(PCH_M_HV_LC), 230 EM_DEVICE(PCH_D_HV_DM), 231 EM_DEVICE(PCH_D_HV_DC), 232 233 EM_DEVICE(PCH2_LV_LM), 234 EM_DEVICE(PCH2_LV_V), 235 236 /* required last entry */ 237 EM_DEVICE_NULL 238 }; 239 240 static int em_probe(device_t); 241 static int em_attach(device_t); 242 static int em_detach(device_t); 243 static int em_shutdown(device_t); 244 static int em_suspend(device_t); 245 static int em_resume(device_t); 246 247 static void em_init(void *); 248 static void em_stop(struct adapter *); 249 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 250 static void em_start(struct ifnet *, struct ifaltq_subque *); 251 #ifdef IFPOLL_ENABLE 252 static void em_npoll(struct ifnet *, struct ifpoll_info *); 253 static void em_npoll_compat(struct ifnet *, void *, int); 254 #endif 255 static void em_watchdog(struct ifnet *); 256 static void em_media_status(struct ifnet *, struct ifmediareq *); 257 static int em_media_change(struct ifnet *); 258 static void em_timer(void *); 259 260 static void em_intr(void *); 261 static void em_intr_mask(void *); 262 static void em_intr_body(struct adapter *, boolean_t); 263 static void em_rxeof(struct adapter *, int); 264 static void em_txeof(struct adapter *); 265 static void em_tx_collect(struct adapter *); 266 static void em_tx_purge(struct adapter *); 267 static void em_enable_intr(struct adapter *); 268 static void em_disable_intr(struct adapter *); 269 270 static int em_dma_malloc(struct adapter *, bus_size_t, 271 struct em_dma_alloc *); 272 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 273 static void em_init_tx_ring(struct adapter *); 274 static int em_init_rx_ring(struct adapter *); 275 static int em_create_tx_ring(struct adapter *); 276 static int em_create_rx_ring(struct adapter *); 277 static void em_destroy_tx_ring(struct adapter *, int); 278 static void em_destroy_rx_ring(struct adapter *, int); 279 static int em_newbuf(struct adapter *, int, int); 280 static int em_encap(struct adapter *, struct mbuf **, int *, int *); 281 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *, 282 struct mbuf *); 283 static int em_txcsum(struct adapter *, struct mbuf *, 284 uint32_t *, uint32_t *); 285 static int em_tso_pullup(struct adapter *, struct mbuf **); 286 static int em_tso_setup(struct adapter *, struct mbuf *, 287 uint32_t *, uint32_t *); 288 289 static int em_get_hw_info(struct adapter *); 290 static int em_is_valid_eaddr(const uint8_t *); 291 static int em_alloc_pci_res(struct adapter *); 292 static void em_free_pci_res(struct adapter *); 293 static int em_reset(struct adapter *); 294 static void em_setup_ifp(struct adapter *); 295 static void em_init_tx_unit(struct adapter *); 296 static void em_init_rx_unit(struct adapter *); 297 static void em_update_stats(struct adapter *); 298 static void em_set_promisc(struct adapter *); 299 static void em_disable_promisc(struct adapter *); 300 static void em_set_multi(struct adapter *); 301 static void em_update_link_status(struct adapter *); 302 static void em_smartspeed(struct adapter *); 303 static void em_set_itr(struct adapter *, uint32_t); 304 static void em_disable_aspm(struct adapter *); 305 306 /* Hardware workarounds */ 307 static int em_82547_fifo_workaround(struct adapter *, int); 308 static void em_82547_update_fifo_head(struct adapter *, int); 309 static int em_82547_tx_fifo_reset(struct adapter *); 310 static void em_82547_move_tail(void *); 311 static void em_82547_move_tail_serialized(struct adapter *); 312 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY); 313 314 static void em_print_debug_info(struct adapter *); 315 static void em_print_nvm_info(struct adapter *); 316 static void em_print_hw_stats(struct adapter *); 317 318 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 319 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 320 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 321 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 322 static void em_add_sysctl(struct adapter *adapter); 323 324 /* Management and WOL Support */ 325 static void em_get_mgmt(struct adapter *); 326 static void em_rel_mgmt(struct adapter *); 327 static void em_get_hw_control(struct adapter *); 328 static void em_rel_hw_control(struct adapter *); 329 static void em_enable_wol(device_t); 330 331 static device_method_t em_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, em_probe), 334 DEVMETHOD(device_attach, em_attach), 335 DEVMETHOD(device_detach, em_detach), 336 DEVMETHOD(device_shutdown, em_shutdown), 337 DEVMETHOD(device_suspend, em_suspend), 338 DEVMETHOD(device_resume, em_resume), 339 DEVMETHOD_END 340 }; 341 342 static driver_t em_driver = { 343 "em", 344 em_methods, 345 sizeof(struct adapter), 346 }; 347 348 static devclass_t em_devclass; 349 350 DECLARE_DUMMY_MODULE(if_em); 351 MODULE_DEPEND(em, ig_hal, 1, 1, 1); 352 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL); 353 354 /* 355 * Tunables 356 */ 357 static int em_int_throttle_ceil = EM_DEFAULT_ITR; 358 static int em_rxd = EM_DEFAULT_RXD; 359 static int em_txd = EM_DEFAULT_TXD; 360 static int em_smart_pwr_down = 0; 361 362 /* Controls whether promiscuous also shows bad packets */ 363 static int em_debug_sbp = FALSE; 364 365 static int em_82573_workaround = 1; 366 static int em_msi_enable = 1; 367 368 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil); 369 TUNABLE_INT("hw.em.rxd", &em_rxd); 370 TUNABLE_INT("hw.em.txd", &em_txd); 371 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 372 TUNABLE_INT("hw.em.sbp", &em_debug_sbp); 373 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround); 374 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable); 375 376 /* Global used in WOL setup with multiport cards */ 377 static int em_global_quad_port_a = 0; 378 379 /* Set this to one to display debug statistics */ 380 static int em_display_debug_stats = 0; 381 382 #if !defined(KTR_IF_EM) 383 #define KTR_IF_EM KTR_ALL 384 #endif 385 KTR_INFO_MASTER(if_em); 386 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin"); 387 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end"); 388 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet"); 389 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet"); 390 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean"); 391 #define logif(name) KTR_LOG(if_em_ ## name) 392 393 static int 394 em_probe(device_t dev) 395 { 396 const struct em_vendor_info *ent; 397 uint16_t vid, did; 398 399 vid = pci_get_vendor(dev); 400 did = pci_get_device(dev); 401 402 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) { 403 if (vid == ent->vendor_id && did == ent->device_id) { 404 device_set_desc(dev, ent->desc); 405 device_set_async_attach(dev, TRUE); 406 return (ent->ret); 407 } 408 } 409 return (ENXIO); 410 } 411 412 static int 413 em_attach(device_t dev) 414 { 415 struct adapter *adapter = device_get_softc(dev); 416 struct ifnet *ifp = &adapter->arpcom.ac_if; 417 int tsize, rsize; 418 int error = 0; 419 uint16_t eeprom_data, device_id, apme_mask; 420 driver_intr_t *intr_func; 421 422 adapter->dev = adapter->osdep.dev = dev; 423 424 callout_init_mp(&adapter->timer); 425 callout_init_mp(&adapter->tx_fifo_timer); 426 427 /* Determine hardware and mac info */ 428 error = em_get_hw_info(adapter); 429 if (error) { 430 device_printf(dev, "Identify hardware failed\n"); 431 goto fail; 432 } 433 434 /* Setup PCI resources */ 435 error = em_alloc_pci_res(adapter); 436 if (error) { 437 device_printf(dev, "Allocation of PCI resources failed\n"); 438 goto fail; 439 } 440 441 /* 442 * For ICH8 and family we need to map the flash memory, 443 * and this must happen after the MAC is identified. 444 */ 445 if (adapter->hw.mac.type == e1000_ich8lan || 446 adapter->hw.mac.type == e1000_ich9lan || 447 adapter->hw.mac.type == e1000_ich10lan || 448 adapter->hw.mac.type == e1000_pchlan || 449 adapter->hw.mac.type == e1000_pch2lan) { 450 adapter->flash_rid = EM_BAR_FLASH; 451 452 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 453 &adapter->flash_rid, RF_ACTIVE); 454 if (adapter->flash == NULL) { 455 device_printf(dev, "Mapping of Flash failed\n"); 456 error = ENXIO; 457 goto fail; 458 } 459 adapter->osdep.flash_bus_space_tag = 460 rman_get_bustag(adapter->flash); 461 adapter->osdep.flash_bus_space_handle = 462 rman_get_bushandle(adapter->flash); 463 464 /* 465 * This is used in the shared code 466 * XXX this goof is actually not used. 467 */ 468 adapter->hw.flash_address = (uint8_t *)adapter->flash; 469 } 470 471 switch (adapter->hw.mac.type) { 472 case e1000_82571: 473 case e1000_82572: 474 /* 475 * Pullup extra 4bytes into the first data segment, see: 476 * 82571/82572 specification update errata #7 477 * 478 * NOTE: 479 * 4bytes instead of 2bytes, which are mentioned in the 480 * errata, are pulled; mainly to keep rest of the data 481 * properly aligned. 482 */ 483 adapter->flags |= EM_FLAG_TSO_PULLEX; 484 /* FALL THROUGH */ 485 486 case e1000_82573: 487 case e1000_82574: 488 case e1000_80003es2lan: 489 adapter->flags |= EM_FLAG_TSO; 490 break; 491 492 default: 493 break; 494 } 495 496 /* Do Shared Code initialization */ 497 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 498 device_printf(dev, "Setup of Shared code failed\n"); 499 error = ENXIO; 500 goto fail; 501 } 502 503 e1000_get_bus_info(&adapter->hw); 504 505 /* 506 * Validate number of transmit and receive descriptors. It 507 * must not exceed hardware maximum, and must be multiple 508 * of E1000_DBA_ALIGN. 509 */ 510 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 || 511 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 512 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 513 em_txd < EM_MIN_TXD) { 514 if (adapter->hw.mac.type < e1000_82544) 515 adapter->num_tx_desc = EM_MAX_TXD_82543; 516 else 517 adapter->num_tx_desc = EM_DEFAULT_TXD; 518 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 519 adapter->num_tx_desc, em_txd); 520 } else { 521 adapter->num_tx_desc = em_txd; 522 } 523 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 || 524 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 525 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 526 em_rxd < EM_MIN_RXD) { 527 if (adapter->hw.mac.type < e1000_82544) 528 adapter->num_rx_desc = EM_MAX_RXD_82543; 529 else 530 adapter->num_rx_desc = EM_DEFAULT_RXD; 531 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 532 adapter->num_rx_desc, em_rxd); 533 } else { 534 adapter->num_rx_desc = em_rxd; 535 } 536 537 adapter->hw.mac.autoneg = DO_AUTO_NEG; 538 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 539 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 540 adapter->rx_buffer_len = MCLBYTES; 541 542 /* 543 * Interrupt throttle rate 544 */ 545 if (em_int_throttle_ceil == 0) { 546 adapter->int_throttle_ceil = 0; 547 } else { 548 int throttle = em_int_throttle_ceil; 549 550 if (throttle < 0) 551 throttle = EM_DEFAULT_ITR; 552 553 /* Recalculate the tunable value to get the exact frequency. */ 554 throttle = 1000000000 / 256 / throttle; 555 556 /* Upper 16bits of ITR is reserved and should be zero */ 557 if (throttle & 0xffff0000) 558 throttle = 1000000000 / 256 / EM_DEFAULT_ITR; 559 560 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 561 } 562 563 e1000_init_script_state_82541(&adapter->hw, TRUE); 564 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 565 566 /* Copper options */ 567 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 568 adapter->hw.phy.mdix = AUTO_ALL_MODES; 569 adapter->hw.phy.disable_polarity_correction = FALSE; 570 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 571 } 572 573 /* Set the frame limits assuming standard ethernet sized frames. */ 574 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 575 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN; 576 577 /* This controls when hardware reports transmit completion status. */ 578 adapter->hw.mac.report_tx_early = 1; 579 580 /* 581 * Create top level busdma tag 582 */ 583 error = bus_dma_tag_create(NULL, 1, 0, 584 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 585 NULL, NULL, 586 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 587 0, &adapter->parent_dtag); 588 if (error) { 589 device_printf(dev, "could not create top level DMA tag\n"); 590 goto fail; 591 } 592 593 /* 594 * Allocate Transmit Descriptor ring 595 */ 596 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 597 EM_DBA_ALIGN); 598 error = em_dma_malloc(adapter, tsize, &adapter->txdma); 599 if (error) { 600 device_printf(dev, "Unable to allocate tx_desc memory\n"); 601 goto fail; 602 } 603 adapter->tx_desc_base = adapter->txdma.dma_vaddr; 604 605 /* 606 * Allocate Receive Descriptor ring 607 */ 608 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 609 EM_DBA_ALIGN); 610 error = em_dma_malloc(adapter, rsize, &adapter->rxdma); 611 if (error) { 612 device_printf(dev, "Unable to allocate rx_desc memory\n"); 613 goto fail; 614 } 615 adapter->rx_desc_base = adapter->rxdma.dma_vaddr; 616 617 /* Allocate multicast array memory. */ 618 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES, 619 M_DEVBUF, M_WAITOK); 620 621 /* Indicate SOL/IDER usage */ 622 if (e1000_check_reset_block(&adapter->hw)) { 623 device_printf(dev, 624 "PHY reset is blocked due to SOL/IDER session.\n"); 625 } 626 627 /* 628 * Start from a known state, this is important in reading the 629 * nvm and mac from that. 630 */ 631 e1000_reset_hw(&adapter->hw); 632 633 /* Make sure we have a good EEPROM before we read from it */ 634 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 635 /* 636 * Some PCI-E parts fail the first check due to 637 * the link being in sleep state, call it again, 638 * if it fails a second time its a real issue. 639 */ 640 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 641 device_printf(dev, 642 "The EEPROM Checksum Is Not Valid\n"); 643 error = EIO; 644 goto fail; 645 } 646 } 647 648 /* Copy the permanent MAC address out of the EEPROM */ 649 if (e1000_read_mac_addr(&adapter->hw) < 0) { 650 device_printf(dev, "EEPROM read error while reading MAC" 651 " address\n"); 652 error = EIO; 653 goto fail; 654 } 655 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) { 656 device_printf(dev, "Invalid MAC address\n"); 657 error = EIO; 658 goto fail; 659 } 660 661 /* Allocate transmit descriptors and buffers */ 662 error = em_create_tx_ring(adapter); 663 if (error) { 664 device_printf(dev, "Could not setup transmit structures\n"); 665 goto fail; 666 } 667 668 /* Allocate receive descriptors and buffers */ 669 error = em_create_rx_ring(adapter); 670 if (error) { 671 device_printf(dev, "Could not setup receive structures\n"); 672 goto fail; 673 } 674 675 /* Manually turn off all interrupts */ 676 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 677 678 /* Determine if we have to control management hardware */ 679 if (e1000_enable_mng_pass_thru(&adapter->hw)) 680 adapter->flags |= EM_FLAG_HAS_MGMT; 681 682 /* 683 * Setup Wake-on-Lan 684 */ 685 apme_mask = EM_EEPROM_APME; 686 eeprom_data = 0; 687 switch (adapter->hw.mac.type) { 688 case e1000_82542: 689 case e1000_82543: 690 break; 691 692 case e1000_82573: 693 case e1000_82583: 694 adapter->flags |= EM_FLAG_HAS_AMT; 695 /* FALL THROUGH */ 696 697 case e1000_82546: 698 case e1000_82546_rev_3: 699 case e1000_82571: 700 case e1000_82572: 701 case e1000_80003es2lan: 702 if (adapter->hw.bus.func == 1) { 703 e1000_read_nvm(&adapter->hw, 704 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 705 } else { 706 e1000_read_nvm(&adapter->hw, 707 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 708 } 709 break; 710 711 case e1000_ich8lan: 712 case e1000_ich9lan: 713 case e1000_ich10lan: 714 case e1000_pchlan: 715 case e1000_pch2lan: 716 apme_mask = E1000_WUC_APME; 717 adapter->flags |= EM_FLAG_HAS_AMT; 718 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 719 break; 720 721 default: 722 e1000_read_nvm(&adapter->hw, 723 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 724 break; 725 } 726 if (eeprom_data & apme_mask) 727 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 728 729 /* 730 * We have the eeprom settings, now apply the special cases 731 * where the eeprom may be wrong or the board won't support 732 * wake on lan on a particular port 733 */ 734 device_id = pci_get_device(dev); 735 switch (device_id) { 736 case E1000_DEV_ID_82546GB_PCIE: 737 adapter->wol = 0; 738 break; 739 740 case E1000_DEV_ID_82546EB_FIBER: 741 case E1000_DEV_ID_82546GB_FIBER: 742 case E1000_DEV_ID_82571EB_FIBER: 743 /* 744 * Wake events only supported on port A for dual fiber 745 * regardless of eeprom setting 746 */ 747 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 748 E1000_STATUS_FUNC_1) 749 adapter->wol = 0; 750 break; 751 752 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 753 case E1000_DEV_ID_82571EB_QUAD_COPPER: 754 case E1000_DEV_ID_82571EB_QUAD_FIBER: 755 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 756 /* if quad port adapter, disable WoL on all but port A */ 757 if (em_global_quad_port_a != 0) 758 adapter->wol = 0; 759 /* Reset for multiple quad port adapters */ 760 if (++em_global_quad_port_a == 4) 761 em_global_quad_port_a = 0; 762 break; 763 } 764 765 /* XXX disable wol */ 766 adapter->wol = 0; 767 768 /* Setup OS specific network interface */ 769 em_setup_ifp(adapter); 770 771 /* Add sysctl tree, must after em_setup_ifp() */ 772 em_add_sysctl(adapter); 773 774 #ifdef IFPOLL_ENABLE 775 /* Polling setup */ 776 ifpoll_compat_setup(&adapter->npoll, 777 &adapter->sysctl_ctx, adapter->sysctl_tree, device_get_unit(dev), 778 ifp->if_serializer); 779 #endif 780 781 /* Reset the hardware */ 782 error = em_reset(adapter); 783 if (error) { 784 device_printf(dev, "Unable to reset the hardware\n"); 785 goto fail; 786 } 787 788 /* Initialize statistics */ 789 em_update_stats(adapter); 790 791 adapter->hw.mac.get_link_status = 1; 792 em_update_link_status(adapter); 793 794 /* Do we need workaround for 82544 PCI-X adapter? */ 795 if (adapter->hw.bus.type == e1000_bus_type_pcix && 796 adapter->hw.mac.type == e1000_82544) 797 adapter->pcix_82544 = TRUE; 798 else 799 adapter->pcix_82544 = FALSE; 800 801 if (adapter->pcix_82544) { 802 /* 803 * 82544 on PCI-X may split one TX segment 804 * into two TX descs, so we double its number 805 * of spare TX desc here. 806 */ 807 adapter->spare_tx_desc = 2 * EM_TX_SPARE; 808 } else { 809 adapter->spare_tx_desc = EM_TX_SPARE; 810 } 811 if (adapter->flags & EM_FLAG_TSO) 812 adapter->spare_tx_desc = EM_TX_SPARE_TSO; 813 adapter->tx_wreg_nsegs = EM_DEFAULT_TXWREG; 814 815 /* 816 * Keep following relationship between spare_tx_desc, oact_tx_desc 817 * and tx_int_nsegs: 818 * (spare_tx_desc + EM_TX_RESERVED) <= 819 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs 820 */ 821 adapter->oact_tx_desc = adapter->num_tx_desc / 8; 822 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX) 823 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX; 824 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED) 825 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED; 826 827 adapter->tx_int_nsegs = adapter->num_tx_desc / 16; 828 if (adapter->tx_int_nsegs < adapter->oact_tx_desc) 829 adapter->tx_int_nsegs = adapter->oact_tx_desc; 830 831 /* Non-AMT based hardware can now take control from firmware */ 832 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 833 EM_FLAG_HAS_MGMT && adapter->hw.mac.type >= e1000_82571) 834 em_get_hw_control(adapter); 835 836 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 837 838 /* 839 * Missing Interrupt Following ICR read: 840 * 841 * 82571/82572 specification update errata #76 842 * 82573 specification update errata #31 843 * 82574 specification update errata #12 844 * 82583 specification update errata #4 845 */ 846 intr_func = em_intr; 847 if ((adapter->flags & EM_FLAG_SHARED_INTR) && 848 (adapter->hw.mac.type == e1000_82571 || 849 adapter->hw.mac.type == e1000_82572 || 850 adapter->hw.mac.type == e1000_82573 || 851 adapter->hw.mac.type == e1000_82574 || 852 adapter->hw.mac.type == e1000_82583)) 853 intr_func = em_intr_mask; 854 855 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE, 856 intr_func, adapter, &adapter->intr_tag, 857 ifp->if_serializer); 858 if (error) { 859 device_printf(dev, "Failed to register interrupt handler"); 860 ether_ifdetach(&adapter->arpcom.ac_if); 861 goto fail; 862 } 863 return (0); 864 fail: 865 em_detach(dev); 866 return (error); 867 } 868 869 static int 870 em_detach(device_t dev) 871 { 872 struct adapter *adapter = device_get_softc(dev); 873 874 if (device_is_attached(dev)) { 875 struct ifnet *ifp = &adapter->arpcom.ac_if; 876 877 lwkt_serialize_enter(ifp->if_serializer); 878 879 em_stop(adapter); 880 881 e1000_phy_hw_reset(&adapter->hw); 882 883 em_rel_mgmt(adapter); 884 em_rel_hw_control(adapter); 885 886 if (adapter->wol) { 887 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 888 E1000_WUC_PME_EN); 889 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 890 em_enable_wol(dev); 891 } 892 893 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag); 894 895 lwkt_serialize_exit(ifp->if_serializer); 896 897 ether_ifdetach(ifp); 898 } else if (adapter->memory != NULL) { 899 em_rel_hw_control(adapter); 900 } 901 bus_generic_detach(dev); 902 903 em_free_pci_res(adapter); 904 905 em_destroy_tx_ring(adapter, adapter->num_tx_desc); 906 em_destroy_rx_ring(adapter, adapter->num_rx_desc); 907 908 /* Free Transmit Descriptor ring */ 909 if (adapter->tx_desc_base) 910 em_dma_free(adapter, &adapter->txdma); 911 912 /* Free Receive Descriptor ring */ 913 if (adapter->rx_desc_base) 914 em_dma_free(adapter, &adapter->rxdma); 915 916 /* Free top level busdma tag */ 917 if (adapter->parent_dtag != NULL) 918 bus_dma_tag_destroy(adapter->parent_dtag); 919 920 /* Free sysctl tree */ 921 if (adapter->sysctl_tree != NULL) 922 sysctl_ctx_free(&adapter->sysctl_ctx); 923 924 if (adapter->mta != NULL) 925 kfree(adapter->mta, M_DEVBUF); 926 927 return (0); 928 } 929 930 static int 931 em_shutdown(device_t dev) 932 { 933 return em_suspend(dev); 934 } 935 936 static int 937 em_suspend(device_t dev) 938 { 939 struct adapter *adapter = device_get_softc(dev); 940 struct ifnet *ifp = &adapter->arpcom.ac_if; 941 942 lwkt_serialize_enter(ifp->if_serializer); 943 944 em_stop(adapter); 945 946 em_rel_mgmt(adapter); 947 em_rel_hw_control(adapter); 948 949 if (adapter->wol) { 950 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 951 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 952 em_enable_wol(dev); 953 } 954 955 lwkt_serialize_exit(ifp->if_serializer); 956 957 return bus_generic_suspend(dev); 958 } 959 960 static int 961 em_resume(device_t dev) 962 { 963 struct adapter *adapter = device_get_softc(dev); 964 struct ifnet *ifp = &adapter->arpcom.ac_if; 965 966 lwkt_serialize_enter(ifp->if_serializer); 967 968 if (adapter->hw.mac.type == e1000_pch2lan) 969 e1000_resume_workarounds_pchlan(&adapter->hw); 970 971 em_init(adapter); 972 em_get_mgmt(adapter); 973 if_devstart(ifp); 974 975 lwkt_serialize_exit(ifp->if_serializer); 976 977 return bus_generic_resume(dev); 978 } 979 980 static void 981 em_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 982 { 983 struct adapter *adapter = ifp->if_softc; 984 struct mbuf *m_head; 985 int idx = -1, nsegs = 0; 986 987 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 988 ASSERT_SERIALIZED(ifp->if_serializer); 989 990 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 991 return; 992 993 if (!adapter->link_active) { 994 ifq_purge(&ifp->if_snd); 995 return; 996 } 997 998 while (!ifq_is_empty(&ifp->if_snd)) { 999 /* Now do we at least have a minimal? */ 1000 if (EM_IS_OACTIVE(adapter)) { 1001 em_tx_collect(adapter); 1002 if (EM_IS_OACTIVE(adapter)) { 1003 ifq_set_oactive(&ifp->if_snd); 1004 adapter->no_tx_desc_avail1++; 1005 break; 1006 } 1007 } 1008 1009 logif(pkt_txqueue); 1010 m_head = ifq_dequeue(&ifp->if_snd); 1011 if (m_head == NULL) 1012 break; 1013 1014 if (em_encap(adapter, &m_head, &nsegs, &idx)) { 1015 IFNET_STAT_INC(ifp, oerrors, 1); 1016 em_tx_collect(adapter); 1017 continue; 1018 } 1019 1020 if (nsegs >= adapter->tx_wreg_nsegs && idx >= 0) { 1021 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1022 nsegs = 0; 1023 idx = -1; 1024 } 1025 1026 /* Send a copy of the frame to the BPF listener */ 1027 ETHER_BPF_MTAP(ifp, m_head); 1028 1029 /* Set timeout in case hardware has problems transmitting. */ 1030 ifp->if_timer = EM_TX_TIMEOUT; 1031 } 1032 if (idx >= 0) 1033 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1034 } 1035 1036 static int 1037 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1038 { 1039 struct adapter *adapter = ifp->if_softc; 1040 struct ifreq *ifr = (struct ifreq *)data; 1041 uint16_t eeprom_data = 0; 1042 int max_frame_size, mask, reinit; 1043 int error = 0; 1044 1045 ASSERT_SERIALIZED(ifp->if_serializer); 1046 1047 switch (command) { 1048 case SIOCSIFMTU: 1049 switch (adapter->hw.mac.type) { 1050 case e1000_82573: 1051 /* 1052 * 82573 only supports jumbo frames 1053 * if ASPM is disabled. 1054 */ 1055 e1000_read_nvm(&adapter->hw, 1056 NVM_INIT_3GIO_3, 1, &eeprom_data); 1057 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1058 max_frame_size = ETHER_MAX_LEN; 1059 break; 1060 } 1061 /* FALL THROUGH */ 1062 1063 /* Limit Jumbo Frame size */ 1064 case e1000_82571: 1065 case e1000_82572: 1066 case e1000_ich9lan: 1067 case e1000_ich10lan: 1068 case e1000_pch2lan: 1069 case e1000_82574: 1070 case e1000_82583: 1071 case e1000_80003es2lan: 1072 max_frame_size = 9234; 1073 break; 1074 1075 case e1000_pchlan: 1076 max_frame_size = 4096; 1077 break; 1078 1079 /* Adapters that do not support jumbo frames */ 1080 case e1000_82542: 1081 case e1000_ich8lan: 1082 max_frame_size = ETHER_MAX_LEN; 1083 break; 1084 1085 default: 1086 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1087 break; 1088 } 1089 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1090 ETHER_CRC_LEN) { 1091 error = EINVAL; 1092 break; 1093 } 1094 1095 ifp->if_mtu = ifr->ifr_mtu; 1096 adapter->max_frame_size = 1097 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1098 1099 if (ifp->if_flags & IFF_RUNNING) 1100 em_init(adapter); 1101 break; 1102 1103 case SIOCSIFFLAGS: 1104 if (ifp->if_flags & IFF_UP) { 1105 if ((ifp->if_flags & IFF_RUNNING)) { 1106 if ((ifp->if_flags ^ adapter->if_flags) & 1107 (IFF_PROMISC | IFF_ALLMULTI)) { 1108 em_disable_promisc(adapter); 1109 em_set_promisc(adapter); 1110 } 1111 } else { 1112 em_init(adapter); 1113 } 1114 } else if (ifp->if_flags & IFF_RUNNING) { 1115 em_stop(adapter); 1116 } 1117 adapter->if_flags = ifp->if_flags; 1118 break; 1119 1120 case SIOCADDMULTI: 1121 case SIOCDELMULTI: 1122 if (ifp->if_flags & IFF_RUNNING) { 1123 em_disable_intr(adapter); 1124 em_set_multi(adapter); 1125 if (adapter->hw.mac.type == e1000_82542 && 1126 adapter->hw.revision_id == E1000_REVISION_2) 1127 em_init_rx_unit(adapter); 1128 #ifdef IFPOLL_ENABLE 1129 if (!(ifp->if_flags & IFF_NPOLLING)) 1130 #endif 1131 em_enable_intr(adapter); 1132 } 1133 break; 1134 1135 case SIOCSIFMEDIA: 1136 /* Check SOL/IDER usage */ 1137 if (e1000_check_reset_block(&adapter->hw)) { 1138 device_printf(adapter->dev, "Media change is" 1139 " blocked due to SOL/IDER session.\n"); 1140 break; 1141 } 1142 /* FALL THROUGH */ 1143 1144 case SIOCGIFMEDIA: 1145 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1146 break; 1147 1148 case SIOCSIFCAP: 1149 reinit = 0; 1150 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1151 if (mask & IFCAP_RXCSUM) { 1152 ifp->if_capenable ^= IFCAP_RXCSUM; 1153 reinit = 1; 1154 } 1155 if (mask & IFCAP_TXCSUM) { 1156 ifp->if_capenable ^= IFCAP_TXCSUM; 1157 if (ifp->if_capenable & IFCAP_TXCSUM) 1158 ifp->if_hwassist |= EM_CSUM_FEATURES; 1159 else 1160 ifp->if_hwassist &= ~EM_CSUM_FEATURES; 1161 } 1162 if (mask & IFCAP_TSO) { 1163 ifp->if_capenable ^= IFCAP_TSO; 1164 if (ifp->if_capenable & IFCAP_TSO) 1165 ifp->if_hwassist |= CSUM_TSO; 1166 else 1167 ifp->if_hwassist &= ~CSUM_TSO; 1168 } 1169 if (mask & IFCAP_VLAN_HWTAGGING) { 1170 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1171 reinit = 1; 1172 } 1173 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1174 em_init(adapter); 1175 break; 1176 1177 default: 1178 error = ether_ioctl(ifp, command, data); 1179 break; 1180 } 1181 return (error); 1182 } 1183 1184 static void 1185 em_watchdog(struct ifnet *ifp) 1186 { 1187 struct adapter *adapter = ifp->if_softc; 1188 1189 ASSERT_SERIALIZED(ifp->if_serializer); 1190 1191 /* 1192 * The timer is set to 5 every time start queues a packet. 1193 * Then txeof keeps resetting it as long as it cleans at 1194 * least one descriptor. 1195 * Finally, anytime all descriptors are clean the timer is 1196 * set to 0. 1197 */ 1198 1199 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1200 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) { 1201 /* 1202 * If we reach here, all TX jobs are completed and 1203 * the TX engine should have been idled for some time. 1204 * We don't need to call if_devstart() here. 1205 */ 1206 ifq_clr_oactive(&ifp->if_snd); 1207 ifp->if_timer = 0; 1208 return; 1209 } 1210 1211 /* 1212 * If we are in this routine because of pause frames, then 1213 * don't reset the hardware. 1214 */ 1215 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1216 E1000_STATUS_TXOFF) { 1217 ifp->if_timer = EM_TX_TIMEOUT; 1218 return; 1219 } 1220 1221 if (e1000_check_for_link(&adapter->hw) == 0) 1222 if_printf(ifp, "watchdog timeout -- resetting\n"); 1223 1224 IFNET_STAT_INC(ifp, oerrors, 1); 1225 adapter->watchdog_events++; 1226 1227 em_init(adapter); 1228 1229 if (!ifq_is_empty(&ifp->if_snd)) 1230 if_devstart(ifp); 1231 } 1232 1233 static void 1234 em_init(void *xsc) 1235 { 1236 struct adapter *adapter = xsc; 1237 struct ifnet *ifp = &adapter->arpcom.ac_if; 1238 device_t dev = adapter->dev; 1239 1240 ASSERT_SERIALIZED(ifp->if_serializer); 1241 1242 em_stop(adapter); 1243 1244 /* Get the latest mac address, User can use a LAA */ 1245 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN); 1246 1247 /* Put the address into the Receive Address Array */ 1248 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1249 1250 /* 1251 * With the 82571 adapter, RAR[0] may be overwritten 1252 * when the other port is reset, we make a duplicate 1253 * in RAR[14] for that eventuality, this assures 1254 * the interface continues to function. 1255 */ 1256 if (adapter->hw.mac.type == e1000_82571) { 1257 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1258 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1259 E1000_RAR_ENTRIES - 1); 1260 } 1261 1262 /* Reset the hardware */ 1263 if (em_reset(adapter)) { 1264 device_printf(dev, "Unable to reset the hardware\n"); 1265 /* XXX em_stop()? */ 1266 return; 1267 } 1268 em_update_link_status(adapter); 1269 1270 /* Setup VLAN support, basic and offload if available */ 1271 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1272 1273 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1274 uint32_t ctrl; 1275 1276 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1277 ctrl |= E1000_CTRL_VME; 1278 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1279 } 1280 1281 /* Configure for OS presence */ 1282 em_get_mgmt(adapter); 1283 1284 /* Prepare transmit descriptors and buffers */ 1285 em_init_tx_ring(adapter); 1286 em_init_tx_unit(adapter); 1287 1288 /* Setup Multicast table */ 1289 em_set_multi(adapter); 1290 1291 /* Prepare receive descriptors and buffers */ 1292 if (em_init_rx_ring(adapter)) { 1293 device_printf(dev, "Could not setup receive structures\n"); 1294 em_stop(adapter); 1295 return; 1296 } 1297 em_init_rx_unit(adapter); 1298 1299 /* Don't lose promiscuous settings */ 1300 em_set_promisc(adapter); 1301 1302 ifp->if_flags |= IFF_RUNNING; 1303 ifq_clr_oactive(&ifp->if_snd); 1304 1305 callout_reset(&adapter->timer, hz, em_timer, adapter); 1306 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1307 1308 /* MSI/X configuration for 82574 */ 1309 if (adapter->hw.mac.type == e1000_82574) { 1310 int tmp; 1311 1312 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1313 tmp |= E1000_CTRL_EXT_PBA_CLR; 1314 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1315 /* 1316 * XXX MSIX 1317 * Set the IVAR - interrupt vector routing. 1318 * Each nibble represents a vector, high bit 1319 * is enable, other 3 bits are the MSIX table 1320 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1321 * Link (other) to 2, hence the magic number. 1322 */ 1323 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); 1324 } 1325 1326 #ifdef IFPOLL_ENABLE 1327 /* 1328 * Only enable interrupts if we are not polling, make sure 1329 * they are off otherwise. 1330 */ 1331 if (ifp->if_flags & IFF_NPOLLING) 1332 em_disable_intr(adapter); 1333 else 1334 #endif /* IFPOLL_ENABLE */ 1335 em_enable_intr(adapter); 1336 1337 /* AMT based hardware can now take control from firmware */ 1338 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 1339 (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT) && 1340 adapter->hw.mac.type >= e1000_82571) 1341 em_get_hw_control(adapter); 1342 } 1343 1344 #ifdef IFPOLL_ENABLE 1345 1346 static void 1347 em_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 1348 { 1349 struct adapter *adapter = ifp->if_softc; 1350 1351 ASSERT_SERIALIZED(ifp->if_serializer); 1352 1353 if (adapter->npoll.ifpc_stcount-- == 0) { 1354 uint32_t reg_icr; 1355 1356 adapter->npoll.ifpc_stcount = adapter->npoll.ifpc_stfrac; 1357 1358 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1359 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1360 callout_stop(&adapter->timer); 1361 adapter->hw.mac.get_link_status = 1; 1362 em_update_link_status(adapter); 1363 callout_reset(&adapter->timer, hz, em_timer, adapter); 1364 } 1365 } 1366 1367 em_rxeof(adapter, count); 1368 em_txeof(adapter); 1369 1370 if (!ifq_is_empty(&ifp->if_snd)) 1371 if_devstart(ifp); 1372 } 1373 1374 static void 1375 em_npoll(struct ifnet *ifp, struct ifpoll_info *info) 1376 { 1377 struct adapter *adapter = ifp->if_softc; 1378 1379 ASSERT_SERIALIZED(ifp->if_serializer); 1380 1381 if (info != NULL) { 1382 int cpuid = adapter->npoll.ifpc_cpuid; 1383 1384 info->ifpi_rx[cpuid].poll_func = em_npoll_compat; 1385 info->ifpi_rx[cpuid].arg = NULL; 1386 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 1387 1388 if (ifp->if_flags & IFF_RUNNING) 1389 em_disable_intr(adapter); 1390 ifq_set_cpuid(&ifp->if_snd, cpuid); 1391 } else { 1392 if (ifp->if_flags & IFF_RUNNING) 1393 em_enable_intr(adapter); 1394 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 1395 } 1396 } 1397 1398 #endif /* IFPOLL_ENABLE */ 1399 1400 static void 1401 em_intr(void *xsc) 1402 { 1403 em_intr_body(xsc, TRUE); 1404 } 1405 1406 static void 1407 em_intr_body(struct adapter *adapter, boolean_t chk_asserted) 1408 { 1409 struct ifnet *ifp = &adapter->arpcom.ac_if; 1410 uint32_t reg_icr; 1411 1412 logif(intr_beg); 1413 ASSERT_SERIALIZED(ifp->if_serializer); 1414 1415 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1416 1417 if (chk_asserted && 1418 ((adapter->hw.mac.type >= e1000_82571 && 1419 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1420 reg_icr == 0)) { 1421 logif(intr_end); 1422 return; 1423 } 1424 1425 /* 1426 * XXX: some laptops trigger several spurious interrupts 1427 * on em(4) when in the resume cycle. The ICR register 1428 * reports all-ones value in this case. Processing such 1429 * interrupts would lead to a freeze. I don't know why. 1430 */ 1431 if (reg_icr == 0xffffffff) { 1432 logif(intr_end); 1433 return; 1434 } 1435 1436 if (ifp->if_flags & IFF_RUNNING) { 1437 if (reg_icr & 1438 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) 1439 em_rxeof(adapter, -1); 1440 if (reg_icr & E1000_ICR_TXDW) { 1441 em_txeof(adapter); 1442 if (!ifq_is_empty(&ifp->if_snd)) 1443 if_devstart(ifp); 1444 } 1445 } 1446 1447 /* Link status change */ 1448 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1449 callout_stop(&adapter->timer); 1450 adapter->hw.mac.get_link_status = 1; 1451 em_update_link_status(adapter); 1452 1453 /* Deal with TX cruft when link lost */ 1454 em_tx_purge(adapter); 1455 1456 callout_reset(&adapter->timer, hz, em_timer, adapter); 1457 } 1458 1459 if (reg_icr & E1000_ICR_RXO) 1460 adapter->rx_overruns++; 1461 1462 logif(intr_end); 1463 } 1464 1465 static void 1466 em_intr_mask(void *xsc) 1467 { 1468 struct adapter *adapter = xsc; 1469 1470 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 1471 /* 1472 * NOTE: 1473 * ICR.INT_ASSERTED bit will never be set if IMS is 0, 1474 * so don't check it. 1475 */ 1476 em_intr_body(adapter, FALSE); 1477 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK); 1478 } 1479 1480 static void 1481 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1482 { 1483 struct adapter *adapter = ifp->if_softc; 1484 u_char fiber_type = IFM_1000_SX; 1485 1486 ASSERT_SERIALIZED(ifp->if_serializer); 1487 1488 em_update_link_status(adapter); 1489 1490 ifmr->ifm_status = IFM_AVALID; 1491 ifmr->ifm_active = IFM_ETHER; 1492 1493 if (!adapter->link_active) 1494 return; 1495 1496 ifmr->ifm_status |= IFM_ACTIVE; 1497 1498 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 1499 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 1500 if (adapter->hw.mac.type == e1000_82545) 1501 fiber_type = IFM_1000_LX; 1502 ifmr->ifm_active |= fiber_type | IFM_FDX; 1503 } else { 1504 switch (adapter->link_speed) { 1505 case 10: 1506 ifmr->ifm_active |= IFM_10_T; 1507 break; 1508 case 100: 1509 ifmr->ifm_active |= IFM_100_TX; 1510 break; 1511 1512 case 1000: 1513 ifmr->ifm_active |= IFM_1000_T; 1514 break; 1515 } 1516 if (adapter->link_duplex == FULL_DUPLEX) 1517 ifmr->ifm_active |= IFM_FDX; 1518 else 1519 ifmr->ifm_active |= IFM_HDX; 1520 } 1521 } 1522 1523 static int 1524 em_media_change(struct ifnet *ifp) 1525 { 1526 struct adapter *adapter = ifp->if_softc; 1527 struct ifmedia *ifm = &adapter->media; 1528 1529 ASSERT_SERIALIZED(ifp->if_serializer); 1530 1531 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1532 return (EINVAL); 1533 1534 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1535 case IFM_AUTO: 1536 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1537 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1538 break; 1539 1540 case IFM_1000_LX: 1541 case IFM_1000_SX: 1542 case IFM_1000_T: 1543 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1544 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1545 break; 1546 1547 case IFM_100_TX: 1548 adapter->hw.mac.autoneg = FALSE; 1549 adapter->hw.phy.autoneg_advertised = 0; 1550 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1551 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1552 else 1553 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1554 break; 1555 1556 case IFM_10_T: 1557 adapter->hw.mac.autoneg = FALSE; 1558 adapter->hw.phy.autoneg_advertised = 0; 1559 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1560 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1561 else 1562 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1563 break; 1564 1565 default: 1566 if_printf(ifp, "Unsupported media type\n"); 1567 break; 1568 } 1569 1570 em_init(adapter); 1571 1572 return (0); 1573 } 1574 1575 static int 1576 em_encap(struct adapter *adapter, struct mbuf **m_headp, 1577 int *segs_used, int *idx) 1578 { 1579 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1580 bus_dmamap_t map; 1581 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1582 struct e1000_tx_desc *ctxd = NULL; 1583 struct mbuf *m_head = *m_headp; 1584 uint32_t txd_upper, txd_lower, txd_used, cmd = 0; 1585 int maxsegs, nsegs, i, j, first, last = 0, error; 1586 1587 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1588 error = em_tso_pullup(adapter, m_headp); 1589 if (error) 1590 return error; 1591 m_head = *m_headp; 1592 } 1593 1594 txd_upper = txd_lower = 0; 1595 txd_used = 0; 1596 1597 /* 1598 * Capture the first descriptor index, this descriptor 1599 * will have the index of the EOP which is the only one 1600 * that now gets a DONE bit writeback. 1601 */ 1602 first = adapter->next_avail_tx_desc; 1603 tx_buffer = &adapter->tx_buffer_area[first]; 1604 tx_buffer_mapped = tx_buffer; 1605 map = tx_buffer->map; 1606 1607 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED; 1608 KASSERT(maxsegs >= adapter->spare_tx_desc, 1609 ("not enough spare TX desc")); 1610 if (adapter->pcix_82544) { 1611 /* Half it; see the comment in em_attach() */ 1612 maxsegs >>= 1; 1613 } 1614 if (maxsegs > EM_MAX_SCATTER) 1615 maxsegs = EM_MAX_SCATTER; 1616 1617 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp, 1618 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1619 if (error) { 1620 if (error == ENOBUFS) 1621 adapter->mbuf_alloc_failed++; 1622 else 1623 adapter->no_tx_dma_setup++; 1624 1625 m_freem(*m_headp); 1626 *m_headp = NULL; 1627 return error; 1628 } 1629 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1630 1631 m_head = *m_headp; 1632 adapter->tx_nsegs += nsegs; 1633 *segs_used += nsegs; 1634 1635 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1636 /* TSO will consume one TX desc */ 1637 i = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower); 1638 adapter->tx_nsegs += i; 1639 *segs_used += i; 1640 } else if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) { 1641 /* TX csum offloading will consume one TX desc */ 1642 i = em_txcsum(adapter, m_head, &txd_upper, &txd_lower); 1643 adapter->tx_nsegs += i; 1644 *segs_used += i; 1645 } 1646 1647 /* Handle VLAN tag */ 1648 if (m_head->m_flags & M_VLANTAG) { 1649 /* Set the vlan id. */ 1650 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16); 1651 /* Tell hardware to add tag */ 1652 txd_lower |= htole32(E1000_TXD_CMD_VLE); 1653 } 1654 1655 i = adapter->next_avail_tx_desc; 1656 1657 /* Set up our transmit descriptors */ 1658 for (j = 0; j < nsegs; j++) { 1659 /* If adapter is 82544 and on PCIX bus */ 1660 if(adapter->pcix_82544) { 1661 DESC_ARRAY desc_array; 1662 uint32_t array_elements, counter; 1663 1664 /* 1665 * Check the Address and Length combination and 1666 * split the data accordingly 1667 */ 1668 array_elements = em_82544_fill_desc(segs[j].ds_addr, 1669 segs[j].ds_len, &desc_array); 1670 for (counter = 0; counter < array_elements; counter++) { 1671 KKASSERT(txd_used < adapter->num_tx_desc_avail); 1672 1673 tx_buffer = &adapter->tx_buffer_area[i]; 1674 ctxd = &adapter->tx_desc_base[i]; 1675 1676 ctxd->buffer_addr = htole64( 1677 desc_array.descriptor[counter].address); 1678 ctxd->lower.data = htole32( 1679 E1000_TXD_CMD_IFCS | txd_lower | 1680 desc_array.descriptor[counter].length); 1681 ctxd->upper.data = htole32(txd_upper); 1682 1683 last = i; 1684 if (++i == adapter->num_tx_desc) 1685 i = 0; 1686 1687 txd_used++; 1688 } 1689 } else { 1690 tx_buffer = &adapter->tx_buffer_area[i]; 1691 ctxd = &adapter->tx_desc_base[i]; 1692 1693 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1694 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1695 txd_lower | segs[j].ds_len); 1696 ctxd->upper.data = htole32(txd_upper); 1697 1698 last = i; 1699 if (++i == adapter->num_tx_desc) 1700 i = 0; 1701 } 1702 } 1703 1704 adapter->next_avail_tx_desc = i; 1705 if (adapter->pcix_82544) { 1706 KKASSERT(adapter->num_tx_desc_avail > txd_used); 1707 adapter->num_tx_desc_avail -= txd_used; 1708 } else { 1709 KKASSERT(adapter->num_tx_desc_avail > nsegs); 1710 adapter->num_tx_desc_avail -= nsegs; 1711 } 1712 1713 tx_buffer->m_head = m_head; 1714 tx_buffer_mapped->map = tx_buffer->map; 1715 tx_buffer->map = map; 1716 1717 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) { 1718 adapter->tx_nsegs = 0; 1719 1720 /* 1721 * Report Status (RS) is turned on 1722 * every tx_int_nsegs descriptors. 1723 */ 1724 cmd = E1000_TXD_CMD_RS; 1725 1726 /* 1727 * Keep track of the descriptor, which will 1728 * be written back by hardware. 1729 */ 1730 adapter->tx_dd[adapter->tx_dd_tail] = last; 1731 EM_INC_TXDD_IDX(adapter->tx_dd_tail); 1732 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head); 1733 } 1734 1735 /* 1736 * Last Descriptor of Packet needs End Of Packet (EOP) 1737 */ 1738 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1739 1740 if (adapter->hw.mac.type == e1000_82547) { 1741 /* 1742 * Advance the Transmit Descriptor Tail (TDT), this tells the 1743 * E1000 that this frame is available to transmit. 1744 */ 1745 if (adapter->link_duplex == HALF_DUPLEX) { 1746 em_82547_move_tail_serialized(adapter); 1747 } else { 1748 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 1749 em_82547_update_fifo_head(adapter, 1750 m_head->m_pkthdr.len); 1751 } 1752 } else { 1753 /* 1754 * Defer TDT updating, until enough descriptors are setup 1755 */ 1756 *idx = i; 1757 } 1758 return (0); 1759 } 1760 1761 /* 1762 * 82547 workaround to avoid controller hang in half-duplex environment. 1763 * The workaround is to avoid queuing a large packet that would span 1764 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1765 * in this case. We do that only when FIFO is quiescent. 1766 */ 1767 static void 1768 em_82547_move_tail_serialized(struct adapter *adapter) 1769 { 1770 struct e1000_tx_desc *tx_desc; 1771 uint16_t hw_tdt, sw_tdt, length = 0; 1772 bool eop = 0; 1773 1774 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer); 1775 1776 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 1777 sw_tdt = adapter->next_avail_tx_desc; 1778 1779 while (hw_tdt != sw_tdt) { 1780 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1781 length += tx_desc->lower.flags.length; 1782 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1783 if (++hw_tdt == adapter->num_tx_desc) 1784 hw_tdt = 0; 1785 1786 if (eop) { 1787 if (em_82547_fifo_workaround(adapter, length)) { 1788 adapter->tx_fifo_wrk_cnt++; 1789 callout_reset(&adapter->tx_fifo_timer, 1, 1790 em_82547_move_tail, adapter); 1791 break; 1792 } 1793 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 1794 em_82547_update_fifo_head(adapter, length); 1795 length = 0; 1796 } 1797 } 1798 } 1799 1800 static void 1801 em_82547_move_tail(void *xsc) 1802 { 1803 struct adapter *adapter = xsc; 1804 struct ifnet *ifp = &adapter->arpcom.ac_if; 1805 1806 lwkt_serialize_enter(ifp->if_serializer); 1807 em_82547_move_tail_serialized(adapter); 1808 lwkt_serialize_exit(ifp->if_serializer); 1809 } 1810 1811 static int 1812 em_82547_fifo_workaround(struct adapter *adapter, int len) 1813 { 1814 int fifo_space, fifo_pkt_len; 1815 1816 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1817 1818 if (adapter->link_duplex == HALF_DUPLEX) { 1819 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 1820 1821 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1822 if (em_82547_tx_fifo_reset(adapter)) 1823 return (0); 1824 else 1825 return (1); 1826 } 1827 } 1828 return (0); 1829 } 1830 1831 static void 1832 em_82547_update_fifo_head(struct adapter *adapter, int len) 1833 { 1834 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1835 1836 /* tx_fifo_head is always 16 byte aligned */ 1837 adapter->tx_fifo_head += fifo_pkt_len; 1838 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) 1839 adapter->tx_fifo_head -= adapter->tx_fifo_size; 1840 } 1841 1842 static int 1843 em_82547_tx_fifo_reset(struct adapter *adapter) 1844 { 1845 uint32_t tctl; 1846 1847 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1848 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 1849 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 1850 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 1851 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 1852 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 1853 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 1854 /* Disable TX unit */ 1855 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 1856 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 1857 tctl & ~E1000_TCTL_EN); 1858 1859 /* Reset FIFO pointers */ 1860 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 1861 adapter->tx_head_addr); 1862 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 1863 adapter->tx_head_addr); 1864 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 1865 adapter->tx_head_addr); 1866 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 1867 adapter->tx_head_addr); 1868 1869 /* Re-enable TX unit */ 1870 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 1871 E1000_WRITE_FLUSH(&adapter->hw); 1872 1873 adapter->tx_fifo_head = 0; 1874 adapter->tx_fifo_reset_cnt++; 1875 1876 return (TRUE); 1877 } else { 1878 return (FALSE); 1879 } 1880 } 1881 1882 static void 1883 em_set_promisc(struct adapter *adapter) 1884 { 1885 struct ifnet *ifp = &adapter->arpcom.ac_if; 1886 uint32_t reg_rctl; 1887 1888 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1889 1890 if (ifp->if_flags & IFF_PROMISC) { 1891 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1892 /* Turn this on if you want to see bad packets */ 1893 if (em_debug_sbp) 1894 reg_rctl |= E1000_RCTL_SBP; 1895 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1896 } else if (ifp->if_flags & IFF_ALLMULTI) { 1897 reg_rctl |= E1000_RCTL_MPE; 1898 reg_rctl &= ~E1000_RCTL_UPE; 1899 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1900 } 1901 } 1902 1903 static void 1904 em_disable_promisc(struct adapter *adapter) 1905 { 1906 uint32_t reg_rctl; 1907 1908 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1909 1910 reg_rctl &= ~E1000_RCTL_UPE; 1911 reg_rctl &= ~E1000_RCTL_MPE; 1912 reg_rctl &= ~E1000_RCTL_SBP; 1913 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1914 } 1915 1916 static void 1917 em_set_multi(struct adapter *adapter) 1918 { 1919 struct ifnet *ifp = &adapter->arpcom.ac_if; 1920 struct ifmultiaddr *ifma; 1921 uint32_t reg_rctl = 0; 1922 uint8_t *mta; 1923 int mcnt = 0; 1924 1925 mta = adapter->mta; 1926 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1927 1928 if (adapter->hw.mac.type == e1000_82542 && 1929 adapter->hw.revision_id == E1000_REVISION_2) { 1930 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1931 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1932 e1000_pci_clear_mwi(&adapter->hw); 1933 reg_rctl |= E1000_RCTL_RST; 1934 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1935 msec_delay(5); 1936 } 1937 1938 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1939 if (ifma->ifma_addr->sa_family != AF_LINK) 1940 continue; 1941 1942 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1943 break; 1944 1945 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1946 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1947 mcnt++; 1948 } 1949 1950 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1951 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1952 reg_rctl |= E1000_RCTL_MPE; 1953 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1954 } else { 1955 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1956 } 1957 1958 if (adapter->hw.mac.type == e1000_82542 && 1959 adapter->hw.revision_id == E1000_REVISION_2) { 1960 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1961 reg_rctl &= ~E1000_RCTL_RST; 1962 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1963 msec_delay(5); 1964 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1965 e1000_pci_set_mwi(&adapter->hw); 1966 } 1967 } 1968 1969 /* 1970 * This routine checks for link status and updates statistics. 1971 */ 1972 static void 1973 em_timer(void *xsc) 1974 { 1975 struct adapter *adapter = xsc; 1976 struct ifnet *ifp = &adapter->arpcom.ac_if; 1977 1978 lwkt_serialize_enter(ifp->if_serializer); 1979 1980 em_update_link_status(adapter); 1981 em_update_stats(adapter); 1982 1983 /* Reset LAA into RAR[0] on 82571 */ 1984 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 1985 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1986 1987 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1988 em_print_hw_stats(adapter); 1989 1990 em_smartspeed(adapter); 1991 1992 callout_reset(&adapter->timer, hz, em_timer, adapter); 1993 1994 lwkt_serialize_exit(ifp->if_serializer); 1995 } 1996 1997 static void 1998 em_update_link_status(struct adapter *adapter) 1999 { 2000 struct e1000_hw *hw = &adapter->hw; 2001 struct ifnet *ifp = &adapter->arpcom.ac_if; 2002 device_t dev = adapter->dev; 2003 uint32_t link_check = 0; 2004 2005 /* Get the cached link value or read phy for real */ 2006 switch (hw->phy.media_type) { 2007 case e1000_media_type_copper: 2008 if (hw->mac.get_link_status) { 2009 /* Do the work to read phy */ 2010 e1000_check_for_link(hw); 2011 link_check = !hw->mac.get_link_status; 2012 if (link_check) /* ESB2 fix */ 2013 e1000_cfg_on_link_up(hw); 2014 } else { 2015 link_check = TRUE; 2016 } 2017 break; 2018 2019 case e1000_media_type_fiber: 2020 e1000_check_for_link(hw); 2021 link_check = 2022 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 2023 break; 2024 2025 case e1000_media_type_internal_serdes: 2026 e1000_check_for_link(hw); 2027 link_check = adapter->hw.mac.serdes_has_link; 2028 break; 2029 2030 case e1000_media_type_unknown: 2031 default: 2032 break; 2033 } 2034 2035 /* Now check for a transition */ 2036 if (link_check && adapter->link_active == 0) { 2037 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 2038 &adapter->link_duplex); 2039 2040 /* 2041 * Check if we should enable/disable SPEED_MODE bit on 2042 * 82571/82572 2043 */ 2044 if (adapter->link_speed != SPEED_1000 && 2045 (hw->mac.type == e1000_82571 || 2046 hw->mac.type == e1000_82572)) { 2047 int tarc0; 2048 2049 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2050 tarc0 &= ~SPEED_MODE_BIT; 2051 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2052 } 2053 if (bootverbose) { 2054 device_printf(dev, "Link is up %d Mbps %s\n", 2055 adapter->link_speed, 2056 ((adapter->link_duplex == FULL_DUPLEX) ? 2057 "Full Duplex" : "Half Duplex")); 2058 } 2059 adapter->link_active = 1; 2060 adapter->smartspeed = 0; 2061 ifp->if_baudrate = adapter->link_speed * 1000000; 2062 ifp->if_link_state = LINK_STATE_UP; 2063 if_link_state_change(ifp); 2064 } else if (!link_check && adapter->link_active == 1) { 2065 ifp->if_baudrate = adapter->link_speed = 0; 2066 adapter->link_duplex = 0; 2067 if (bootverbose) 2068 device_printf(dev, "Link is Down\n"); 2069 adapter->link_active = 0; 2070 #if 0 2071 /* Link down, disable watchdog */ 2072 if->if_timer = 0; 2073 #endif 2074 ifp->if_link_state = LINK_STATE_DOWN; 2075 if_link_state_change(ifp); 2076 } 2077 } 2078 2079 static void 2080 em_stop(struct adapter *adapter) 2081 { 2082 struct ifnet *ifp = &adapter->arpcom.ac_if; 2083 int i; 2084 2085 ASSERT_SERIALIZED(ifp->if_serializer); 2086 2087 em_disable_intr(adapter); 2088 2089 callout_stop(&adapter->timer); 2090 callout_stop(&adapter->tx_fifo_timer); 2091 2092 ifp->if_flags &= ~IFF_RUNNING; 2093 ifq_clr_oactive(&ifp->if_snd); 2094 ifp->if_timer = 0; 2095 2096 e1000_reset_hw(&adapter->hw); 2097 if (adapter->hw.mac.type >= e1000_82544) 2098 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2099 2100 for (i = 0; i < adapter->num_tx_desc; i++) { 2101 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i]; 2102 2103 if (tx_buffer->m_head != NULL) { 2104 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 2105 m_freem(tx_buffer->m_head); 2106 tx_buffer->m_head = NULL; 2107 } 2108 } 2109 2110 for (i = 0; i < adapter->num_rx_desc; i++) { 2111 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i]; 2112 2113 if (rx_buffer->m_head != NULL) { 2114 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 2115 m_freem(rx_buffer->m_head); 2116 rx_buffer->m_head = NULL; 2117 } 2118 } 2119 2120 if (adapter->fmp != NULL) 2121 m_freem(adapter->fmp); 2122 adapter->fmp = NULL; 2123 adapter->lmp = NULL; 2124 2125 adapter->csum_flags = 0; 2126 adapter->csum_lhlen = 0; 2127 adapter->csum_iphlen = 0; 2128 adapter->csum_thlen = 0; 2129 adapter->csum_mss = 0; 2130 adapter->csum_pktlen = 0; 2131 2132 adapter->tx_dd_head = 0; 2133 adapter->tx_dd_tail = 0; 2134 adapter->tx_nsegs = 0; 2135 } 2136 2137 static int 2138 em_get_hw_info(struct adapter *adapter) 2139 { 2140 device_t dev = adapter->dev; 2141 2142 /* Save off the information about this board */ 2143 adapter->hw.vendor_id = pci_get_vendor(dev); 2144 adapter->hw.device_id = pci_get_device(dev); 2145 adapter->hw.revision_id = pci_get_revid(dev); 2146 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev); 2147 adapter->hw.subsystem_device_id = pci_get_subdevice(dev); 2148 2149 /* Do Shared Code Init and Setup */ 2150 if (e1000_set_mac_type(&adapter->hw)) 2151 return ENXIO; 2152 return 0; 2153 } 2154 2155 static int 2156 em_alloc_pci_res(struct adapter *adapter) 2157 { 2158 device_t dev = adapter->dev; 2159 u_int intr_flags; 2160 int val, rid, msi_enable; 2161 2162 /* Enable bus mastering */ 2163 pci_enable_busmaster(dev); 2164 2165 adapter->memory_rid = EM_BAR_MEM; 2166 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2167 &adapter->memory_rid, RF_ACTIVE); 2168 if (adapter->memory == NULL) { 2169 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2170 return (ENXIO); 2171 } 2172 adapter->osdep.mem_bus_space_tag = 2173 rman_get_bustag(adapter->memory); 2174 adapter->osdep.mem_bus_space_handle = 2175 rman_get_bushandle(adapter->memory); 2176 2177 /* XXX This is quite goofy, it is not actually used */ 2178 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2179 2180 /* Only older adapters use IO mapping */ 2181 if (adapter->hw.mac.type > e1000_82543 && 2182 adapter->hw.mac.type < e1000_82571) { 2183 /* Figure our where our IO BAR is ? */ 2184 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) { 2185 val = pci_read_config(dev, rid, 4); 2186 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2187 adapter->io_rid = rid; 2188 break; 2189 } 2190 rid += 4; 2191 /* check for 64bit BAR */ 2192 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2193 rid += 4; 2194 } 2195 if (rid >= PCIR_CARDBUSCIS) { 2196 device_printf(dev, "Unable to locate IO BAR\n"); 2197 return (ENXIO); 2198 } 2199 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2200 &adapter->io_rid, RF_ACTIVE); 2201 if (adapter->ioport == NULL) { 2202 device_printf(dev, "Unable to allocate bus resource: " 2203 "ioport\n"); 2204 return (ENXIO); 2205 } 2206 adapter->hw.io_base = 0; 2207 adapter->osdep.io_bus_space_tag = 2208 rman_get_bustag(adapter->ioport); 2209 adapter->osdep.io_bus_space_handle = 2210 rman_get_bushandle(adapter->ioport); 2211 } 2212 2213 /* 2214 * Don't enable MSI-X on 82574, see: 2215 * 82574 specification update errata #15 2216 * 2217 * Don't enable MSI on PCI/PCI-X chips, see: 2218 * 82540 specification update errata #6 2219 * 82545 specification update errata #4 2220 * 2221 * Don't enable MSI on 82571/82572, see: 2222 * 82571/82572 specification update errata #63 2223 */ 2224 msi_enable = em_msi_enable; 2225 if (msi_enable && 2226 (!pci_is_pcie(dev) || 2227 adapter->hw.mac.type == e1000_82571 || 2228 adapter->hw.mac.type == e1000_82572)) 2229 msi_enable = 0; 2230 2231 adapter->intr_type = pci_alloc_1intr(dev, msi_enable, 2232 &adapter->intr_rid, &intr_flags); 2233 2234 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) { 2235 int unshared; 2236 2237 unshared = device_getenv_int(dev, "irq.unshared", 0); 2238 if (!unshared) { 2239 adapter->flags |= EM_FLAG_SHARED_INTR; 2240 if (bootverbose) 2241 device_printf(dev, "IRQ shared\n"); 2242 } else { 2243 intr_flags &= ~RF_SHAREABLE; 2244 if (bootverbose) 2245 device_printf(dev, "IRQ unshared\n"); 2246 } 2247 } 2248 2249 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 2250 &adapter->intr_rid, intr_flags); 2251 if (adapter->intr_res == NULL) { 2252 device_printf(dev, "Unable to allocate bus resource: " 2253 "interrupt\n"); 2254 return (ENXIO); 2255 } 2256 2257 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2258 adapter->hw.back = &adapter->osdep; 2259 return (0); 2260 } 2261 2262 static void 2263 em_free_pci_res(struct adapter *adapter) 2264 { 2265 device_t dev = adapter->dev; 2266 2267 if (adapter->intr_res != NULL) { 2268 bus_release_resource(dev, SYS_RES_IRQ, 2269 adapter->intr_rid, adapter->intr_res); 2270 } 2271 2272 if (adapter->intr_type == PCI_INTR_TYPE_MSI) 2273 pci_release_msi(dev); 2274 2275 if (adapter->memory != NULL) { 2276 bus_release_resource(dev, SYS_RES_MEMORY, 2277 adapter->memory_rid, adapter->memory); 2278 } 2279 2280 if (adapter->flash != NULL) { 2281 bus_release_resource(dev, SYS_RES_MEMORY, 2282 adapter->flash_rid, adapter->flash); 2283 } 2284 2285 if (adapter->ioport != NULL) { 2286 bus_release_resource(dev, SYS_RES_IOPORT, 2287 adapter->io_rid, adapter->ioport); 2288 } 2289 } 2290 2291 static int 2292 em_reset(struct adapter *adapter) 2293 { 2294 device_t dev = adapter->dev; 2295 uint16_t rx_buffer_size; 2296 uint32_t pba; 2297 2298 /* When hardware is reset, fifo_head is also reset */ 2299 adapter->tx_fifo_head = 0; 2300 2301 /* Set up smart power down as default off on newer adapters. */ 2302 if (!em_smart_pwr_down && 2303 (adapter->hw.mac.type == e1000_82571 || 2304 adapter->hw.mac.type == e1000_82572)) { 2305 uint16_t phy_tmp = 0; 2306 2307 /* Speed up time to link by disabling smart power down. */ 2308 e1000_read_phy_reg(&adapter->hw, 2309 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2310 phy_tmp &= ~IGP02E1000_PM_SPD; 2311 e1000_write_phy_reg(&adapter->hw, 2312 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2313 } 2314 2315 /* 2316 * Packet Buffer Allocation (PBA) 2317 * Writing PBA sets the receive portion of the buffer 2318 * the remainder is used for the transmit buffer. 2319 * 2320 * Devices before the 82547 had a Packet Buffer of 64K. 2321 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 2322 * After the 82547 the buffer was reduced to 40K. 2323 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 2324 * Note: default does not leave enough room for Jumbo Frame >10k. 2325 */ 2326 switch (adapter->hw.mac.type) { 2327 case e1000_82547: 2328 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 2329 if (adapter->max_frame_size > 8192) 2330 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2331 else 2332 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2333 adapter->tx_fifo_head = 0; 2334 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 2335 adapter->tx_fifo_size = 2336 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 2337 break; 2338 2339 /* Total Packet Buffer on these is 48K */ 2340 case e1000_82571: 2341 case e1000_82572: 2342 case e1000_80003es2lan: 2343 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2344 break; 2345 2346 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2347 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2348 break; 2349 2350 case e1000_82574: 2351 case e1000_82583: 2352 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2353 break; 2354 2355 case e1000_ich8lan: 2356 pba = E1000_PBA_8K; 2357 break; 2358 2359 case e1000_ich9lan: 2360 case e1000_ich10lan: 2361 #define E1000_PBA_10K 0x000A 2362 pba = E1000_PBA_10K; 2363 break; 2364 2365 case e1000_pchlan: 2366 case e1000_pch2lan: 2367 pba = E1000_PBA_26K; 2368 break; 2369 2370 default: 2371 /* Devices before 82547 had a Packet Buffer of 64K. */ 2372 if (adapter->max_frame_size > 8192) 2373 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2374 else 2375 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2376 } 2377 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2378 2379 /* 2380 * These parameters control the automatic generation (Tx) and 2381 * response (Rx) to Ethernet PAUSE frames. 2382 * - High water mark should allow for at least two frames to be 2383 * received after sending an XOFF. 2384 * - Low water mark works best when it is very near the high water mark. 2385 * This allows the receiver to restart by sending XON when it has 2386 * drained a bit. Here we use an arbitary value of 1500 which will 2387 * restart after one full frame is pulled from the buffer. There 2388 * could be several smaller frames in the buffer and if so they will 2389 * not trigger the XON until their total number reduces the buffer 2390 * by 1500. 2391 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2392 */ 2393 rx_buffer_size = 2394 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10; 2395 2396 adapter->hw.fc.high_water = rx_buffer_size - 2397 roundup2(adapter->max_frame_size, 1024); 2398 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 2399 2400 if (adapter->hw.mac.type == e1000_80003es2lan) 2401 adapter->hw.fc.pause_time = 0xFFFF; 2402 else 2403 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 2404 2405 adapter->hw.fc.send_xon = TRUE; 2406 2407 adapter->hw.fc.requested_mode = e1000_fc_full; 2408 2409 /* 2410 * Device specific overrides/settings 2411 */ 2412 switch (adapter->hw.mac.type) { 2413 case e1000_pchlan: 2414 /* Workaround: no TX flow ctrl for PCH */ 2415 adapter->hw.fc.requested_mode = e1000_fc_rx_pause; 2416 adapter->hw.fc.pause_time = 0xFFFF; /* override */ 2417 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) { 2418 adapter->hw.fc.high_water = 0x3500; 2419 adapter->hw.fc.low_water = 0x1500; 2420 } else { 2421 adapter->hw.fc.high_water = 0x5000; 2422 adapter->hw.fc.low_water = 0x3000; 2423 } 2424 adapter->hw.fc.refresh_time = 0x1000; 2425 break; 2426 2427 case e1000_pch2lan: 2428 adapter->hw.fc.high_water = 0x5C20; 2429 adapter->hw.fc.low_water = 0x5048; 2430 adapter->hw.fc.pause_time = 0x0650; 2431 adapter->hw.fc.refresh_time = 0x0400; 2432 /* Jumbos need adjusted PBA */ 2433 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) 2434 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12); 2435 else 2436 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26); 2437 break; 2438 2439 case e1000_ich9lan: 2440 case e1000_ich10lan: 2441 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) { 2442 adapter->hw.fc.high_water = 0x2800; 2443 adapter->hw.fc.low_water = 2444 adapter->hw.fc.high_water - 8; 2445 break; 2446 } 2447 /* FALL THROUGH */ 2448 default: 2449 if (adapter->hw.mac.type == e1000_80003es2lan) 2450 adapter->hw.fc.pause_time = 0xFFFF; 2451 break; 2452 } 2453 2454 /* Issue a global reset */ 2455 e1000_reset_hw(&adapter->hw); 2456 if (adapter->hw.mac.type >= e1000_82544) 2457 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2458 em_disable_aspm(adapter); 2459 2460 if (e1000_init_hw(&adapter->hw) < 0) { 2461 device_printf(dev, "Hardware Initialization Failed\n"); 2462 return (EIO); 2463 } 2464 2465 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 2466 e1000_get_phy_info(&adapter->hw); 2467 e1000_check_for_link(&adapter->hw); 2468 2469 return (0); 2470 } 2471 2472 static void 2473 em_setup_ifp(struct adapter *adapter) 2474 { 2475 struct ifnet *ifp = &adapter->arpcom.ac_if; 2476 2477 if_initname(ifp, device_get_name(adapter->dev), 2478 device_get_unit(adapter->dev)); 2479 ifp->if_softc = adapter; 2480 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2481 ifp->if_init = em_init; 2482 ifp->if_ioctl = em_ioctl; 2483 ifp->if_start = em_start; 2484 #ifdef IFPOLL_ENABLE 2485 ifp->if_npoll = em_npoll; 2486 #endif 2487 ifp->if_watchdog = em_watchdog; 2488 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1); 2489 ifq_set_ready(&ifp->if_snd); 2490 2491 ether_ifattach(ifp, adapter->hw.mac.addr, NULL); 2492 2493 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2494 if (adapter->hw.mac.type >= e1000_82543) 2495 ifp->if_capabilities |= IFCAP_HWCSUM; 2496 if (adapter->flags & EM_FLAG_TSO) 2497 ifp->if_capabilities |= IFCAP_TSO; 2498 ifp->if_capenable = ifp->if_capabilities; 2499 2500 if (ifp->if_capenable & IFCAP_TXCSUM) 2501 ifp->if_hwassist |= EM_CSUM_FEATURES; 2502 if (ifp->if_capenable & IFCAP_TSO) 2503 ifp->if_hwassist |= CSUM_TSO; 2504 2505 /* 2506 * Tell the upper layer(s) we support long frames. 2507 */ 2508 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2509 2510 /* 2511 * Specify the media types supported by this adapter and register 2512 * callbacks to update media and link information 2513 */ 2514 ifmedia_init(&adapter->media, IFM_IMASK, 2515 em_media_change, em_media_status); 2516 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2517 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2518 u_char fiber_type = IFM_1000_SX; /* default type */ 2519 2520 if (adapter->hw.mac.type == e1000_82545) 2521 fiber_type = IFM_1000_LX; 2522 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2523 0, NULL); 2524 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2525 } else { 2526 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2527 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2528 0, NULL); 2529 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2530 0, NULL); 2531 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2532 0, NULL); 2533 if (adapter->hw.phy.type != e1000_phy_ife) { 2534 ifmedia_add(&adapter->media, 2535 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2536 ifmedia_add(&adapter->media, 2537 IFM_ETHER | IFM_1000_T, 0, NULL); 2538 } 2539 } 2540 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2541 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2542 } 2543 2544 2545 /* 2546 * Workaround for SmartSpeed on 82541 and 82547 controllers 2547 */ 2548 static void 2549 em_smartspeed(struct adapter *adapter) 2550 { 2551 uint16_t phy_tmp; 2552 2553 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp || 2554 adapter->hw.mac.autoneg == 0 || 2555 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2556 return; 2557 2558 if (adapter->smartspeed == 0) { 2559 /* 2560 * If Master/Slave config fault is asserted twice, 2561 * we assume back-to-back 2562 */ 2563 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2564 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2565 return; 2566 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2567 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2568 e1000_read_phy_reg(&adapter->hw, 2569 PHY_1000T_CTRL, &phy_tmp); 2570 if (phy_tmp & CR_1000T_MS_ENABLE) { 2571 phy_tmp &= ~CR_1000T_MS_ENABLE; 2572 e1000_write_phy_reg(&adapter->hw, 2573 PHY_1000T_CTRL, phy_tmp); 2574 adapter->smartspeed++; 2575 if (adapter->hw.mac.autoneg && 2576 !e1000_phy_setup_autoneg(&adapter->hw) && 2577 !e1000_read_phy_reg(&adapter->hw, 2578 PHY_CONTROL, &phy_tmp)) { 2579 phy_tmp |= MII_CR_AUTO_NEG_EN | 2580 MII_CR_RESTART_AUTO_NEG; 2581 e1000_write_phy_reg(&adapter->hw, 2582 PHY_CONTROL, phy_tmp); 2583 } 2584 } 2585 } 2586 return; 2587 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2588 /* If still no link, perhaps using 2/3 pair cable */ 2589 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2590 phy_tmp |= CR_1000T_MS_ENABLE; 2591 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2592 if (adapter->hw.mac.autoneg && 2593 !e1000_phy_setup_autoneg(&adapter->hw) && 2594 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2595 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2596 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2597 } 2598 } 2599 2600 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2601 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2602 adapter->smartspeed = 0; 2603 } 2604 2605 static int 2606 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2607 struct em_dma_alloc *dma) 2608 { 2609 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag, 2610 EM_DBA_ALIGN, size, BUS_DMA_WAITOK, 2611 &dma->dma_tag, &dma->dma_map, 2612 &dma->dma_paddr); 2613 if (dma->dma_vaddr == NULL) 2614 return ENOMEM; 2615 else 2616 return 0; 2617 } 2618 2619 static void 2620 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2621 { 2622 if (dma->dma_tag == NULL) 2623 return; 2624 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2625 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2626 bus_dma_tag_destroy(dma->dma_tag); 2627 } 2628 2629 static int 2630 em_create_tx_ring(struct adapter *adapter) 2631 { 2632 device_t dev = adapter->dev; 2633 struct em_buffer *tx_buffer; 2634 int error, i; 2635 2636 adapter->tx_buffer_area = 2637 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc, 2638 M_DEVBUF, M_WAITOK | M_ZERO); 2639 2640 /* 2641 * Create DMA tags for tx buffers 2642 */ 2643 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 2644 1, 0, /* alignment, bounds */ 2645 BUS_SPACE_MAXADDR, /* lowaddr */ 2646 BUS_SPACE_MAXADDR, /* highaddr */ 2647 NULL, NULL, /* filter, filterarg */ 2648 EM_TSO_SIZE, /* maxsize */ 2649 EM_MAX_SCATTER, /* nsegments */ 2650 PAGE_SIZE, /* maxsegsize */ 2651 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2652 BUS_DMA_ONEBPAGE, /* flags */ 2653 &adapter->txtag); 2654 if (error) { 2655 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2656 kfree(adapter->tx_buffer_area, M_DEVBUF); 2657 adapter->tx_buffer_area = NULL; 2658 return error; 2659 } 2660 2661 /* 2662 * Create DMA maps for tx buffers 2663 */ 2664 for (i = 0; i < adapter->num_tx_desc; i++) { 2665 tx_buffer = &adapter->tx_buffer_area[i]; 2666 2667 error = bus_dmamap_create(adapter->txtag, 2668 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2669 &tx_buffer->map); 2670 if (error) { 2671 device_printf(dev, "Unable to create TX DMA map\n"); 2672 em_destroy_tx_ring(adapter, i); 2673 return error; 2674 } 2675 } 2676 return (0); 2677 } 2678 2679 static void 2680 em_init_tx_ring(struct adapter *adapter) 2681 { 2682 /* Clear the old ring contents */ 2683 bzero(adapter->tx_desc_base, 2684 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 2685 2686 /* Reset state */ 2687 adapter->next_avail_tx_desc = 0; 2688 adapter->next_tx_to_clean = 0; 2689 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2690 } 2691 2692 static void 2693 em_init_tx_unit(struct adapter *adapter) 2694 { 2695 uint32_t tctl, tarc, tipg = 0; 2696 uint64_t bus_addr; 2697 2698 /* Setup the Base and Length of the Tx Descriptor Ring */ 2699 bus_addr = adapter->txdma.dma_paddr; 2700 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 2701 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 2702 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 2703 (uint32_t)(bus_addr >> 32)); 2704 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 2705 (uint32_t)bus_addr); 2706 /* Setup the HW Tx Head and Tail descriptor pointers */ 2707 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 2708 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 2709 2710 /* Set the default values for the Tx Inter Packet Gap timer */ 2711 switch (adapter->hw.mac.type) { 2712 case e1000_82542: 2713 tipg = DEFAULT_82542_TIPG_IPGT; 2714 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2715 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2716 break; 2717 2718 case e1000_80003es2lan: 2719 tipg = DEFAULT_82543_TIPG_IPGR1; 2720 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2721 E1000_TIPG_IPGR2_SHIFT; 2722 break; 2723 2724 default: 2725 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2726 adapter->hw.phy.media_type == 2727 e1000_media_type_internal_serdes) 2728 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2729 else 2730 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2731 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2732 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2733 break; 2734 } 2735 2736 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2737 2738 /* NOTE: 0 is not allowed for TIDV */ 2739 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1); 2740 if(adapter->hw.mac.type >= e1000_82540) 2741 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0); 2742 2743 if (adapter->hw.mac.type == e1000_82571 || 2744 adapter->hw.mac.type == e1000_82572) { 2745 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2746 tarc |= SPEED_MODE_BIT; 2747 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2748 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2749 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2750 tarc |= 1; 2751 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2752 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2753 tarc |= 1; 2754 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2755 } 2756 2757 /* Program the Transmit Control Register */ 2758 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2759 tctl &= ~E1000_TCTL_CT; 2760 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2761 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2762 2763 if (adapter->hw.mac.type >= e1000_82571) 2764 tctl |= E1000_TCTL_MULR; 2765 2766 /* This write will effectively turn on the transmit unit. */ 2767 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2768 2769 if (adapter->hw.mac.type == e1000_82571 || 2770 adapter->hw.mac.type == e1000_82572 || 2771 adapter->hw.mac.type == e1000_80003es2lan) { 2772 /* Bit 28 of TARC1 must be cleared when MULR is enabled */ 2773 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2774 tarc &= ~(1 << 28); 2775 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2776 } 2777 } 2778 2779 static void 2780 em_destroy_tx_ring(struct adapter *adapter, int ndesc) 2781 { 2782 struct em_buffer *tx_buffer; 2783 int i; 2784 2785 if (adapter->tx_buffer_area == NULL) 2786 return; 2787 2788 for (i = 0; i < ndesc; i++) { 2789 tx_buffer = &adapter->tx_buffer_area[i]; 2790 2791 KKASSERT(tx_buffer->m_head == NULL); 2792 bus_dmamap_destroy(adapter->txtag, tx_buffer->map); 2793 } 2794 bus_dma_tag_destroy(adapter->txtag); 2795 2796 kfree(adapter->tx_buffer_area, M_DEVBUF); 2797 adapter->tx_buffer_area = NULL; 2798 } 2799 2800 /* 2801 * The offload context needs to be set when we transfer the first 2802 * packet of a particular protocol (TCP/UDP). This routine has been 2803 * enhanced to deal with inserted VLAN headers. 2804 * 2805 * If the new packet's ether header length, ip header length and 2806 * csum offloading type are same as the previous packet, we should 2807 * avoid allocating a new csum context descriptor; mainly to take 2808 * advantage of the pipeline effect of the TX data read request. 2809 * 2810 * This function returns number of TX descrptors allocated for 2811 * csum context. 2812 */ 2813 static int 2814 em_txcsum(struct adapter *adapter, struct mbuf *mp, 2815 uint32_t *txd_upper, uint32_t *txd_lower) 2816 { 2817 struct e1000_context_desc *TXD; 2818 int curr_txd, ehdrlen, csum_flags; 2819 uint32_t cmd, hdr_len, ip_hlen; 2820 2821 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES; 2822 ip_hlen = mp->m_pkthdr.csum_iphlen; 2823 ehdrlen = mp->m_pkthdr.csum_lhlen; 2824 2825 if (adapter->csum_lhlen == ehdrlen && 2826 adapter->csum_iphlen == ip_hlen && 2827 adapter->csum_flags == csum_flags) { 2828 /* 2829 * Same csum offload context as the previous packets; 2830 * just return. 2831 */ 2832 *txd_upper = adapter->csum_txd_upper; 2833 *txd_lower = adapter->csum_txd_lower; 2834 return 0; 2835 } 2836 2837 /* 2838 * Setup a new csum offload context. 2839 */ 2840 2841 curr_txd = adapter->next_avail_tx_desc; 2842 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 2843 2844 cmd = 0; 2845 2846 /* Setup of IP header checksum. */ 2847 if (csum_flags & CSUM_IP) { 2848 /* 2849 * Start offset for header checksum calculation. 2850 * End offset for header checksum calculation. 2851 * Offset of place to put the checksum. 2852 */ 2853 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2854 TXD->lower_setup.ip_fields.ipcse = 2855 htole16(ehdrlen + ip_hlen - 1); 2856 TXD->lower_setup.ip_fields.ipcso = 2857 ehdrlen + offsetof(struct ip, ip_sum); 2858 cmd |= E1000_TXD_CMD_IP; 2859 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2860 } 2861 hdr_len = ehdrlen + ip_hlen; 2862 2863 if (csum_flags & CSUM_TCP) { 2864 /* 2865 * Start offset for payload checksum calculation. 2866 * End offset for payload checksum calculation. 2867 * Offset of place to put the checksum. 2868 */ 2869 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2870 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2871 TXD->upper_setup.tcp_fields.tucso = 2872 hdr_len + offsetof(struct tcphdr, th_sum); 2873 cmd |= E1000_TXD_CMD_TCP; 2874 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2875 } else if (csum_flags & CSUM_UDP) { 2876 /* 2877 * Start offset for header checksum calculation. 2878 * End offset for header checksum calculation. 2879 * Offset of place to put the checksum. 2880 */ 2881 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2882 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2883 TXD->upper_setup.tcp_fields.tucso = 2884 hdr_len + offsetof(struct udphdr, uh_sum); 2885 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2886 } 2887 2888 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2889 E1000_TXD_DTYP_D; /* Data descr */ 2890 2891 /* Save the information for this csum offloading context */ 2892 adapter->csum_lhlen = ehdrlen; 2893 adapter->csum_iphlen = ip_hlen; 2894 adapter->csum_flags = csum_flags; 2895 adapter->csum_txd_upper = *txd_upper; 2896 adapter->csum_txd_lower = *txd_lower; 2897 2898 TXD->tcp_seg_setup.data = htole32(0); 2899 TXD->cmd_and_length = 2900 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2901 2902 if (++curr_txd == adapter->num_tx_desc) 2903 curr_txd = 0; 2904 2905 KKASSERT(adapter->num_tx_desc_avail > 0); 2906 adapter->num_tx_desc_avail--; 2907 2908 adapter->next_avail_tx_desc = curr_txd; 2909 return 1; 2910 } 2911 2912 static void 2913 em_txeof(struct adapter *adapter) 2914 { 2915 struct ifnet *ifp = &adapter->arpcom.ac_if; 2916 struct em_buffer *tx_buffer; 2917 int first, num_avail; 2918 2919 if (adapter->tx_dd_head == adapter->tx_dd_tail) 2920 return; 2921 2922 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2923 return; 2924 2925 num_avail = adapter->num_tx_desc_avail; 2926 first = adapter->next_tx_to_clean; 2927 2928 while (adapter->tx_dd_head != adapter->tx_dd_tail) { 2929 struct e1000_tx_desc *tx_desc; 2930 int dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2931 2932 tx_desc = &adapter->tx_desc_base[dd_idx]; 2933 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2934 EM_INC_TXDD_IDX(adapter->tx_dd_head); 2935 2936 if (++dd_idx == adapter->num_tx_desc) 2937 dd_idx = 0; 2938 2939 while (first != dd_idx) { 2940 logif(pkt_txclean); 2941 2942 num_avail++; 2943 2944 tx_buffer = &adapter->tx_buffer_area[first]; 2945 if (tx_buffer->m_head) { 2946 IFNET_STAT_INC(ifp, opackets, 1); 2947 bus_dmamap_unload(adapter->txtag, 2948 tx_buffer->map); 2949 m_freem(tx_buffer->m_head); 2950 tx_buffer->m_head = NULL; 2951 } 2952 2953 if (++first == adapter->num_tx_desc) 2954 first = 0; 2955 } 2956 } else { 2957 break; 2958 } 2959 } 2960 adapter->next_tx_to_clean = first; 2961 adapter->num_tx_desc_avail = num_avail; 2962 2963 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 2964 adapter->tx_dd_head = 0; 2965 adapter->tx_dd_tail = 0; 2966 } 2967 2968 if (!EM_IS_OACTIVE(adapter)) { 2969 ifq_clr_oactive(&ifp->if_snd); 2970 2971 /* All clean, turn off the timer */ 2972 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2973 ifp->if_timer = 0; 2974 } 2975 } 2976 2977 static void 2978 em_tx_collect(struct adapter *adapter) 2979 { 2980 struct ifnet *ifp = &adapter->arpcom.ac_if; 2981 struct em_buffer *tx_buffer; 2982 int tdh, first, num_avail, dd_idx = -1; 2983 2984 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2985 return; 2986 2987 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0)); 2988 if (tdh == adapter->next_tx_to_clean) 2989 return; 2990 2991 if (adapter->tx_dd_head != adapter->tx_dd_tail) 2992 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2993 2994 num_avail = adapter->num_tx_desc_avail; 2995 first = adapter->next_tx_to_clean; 2996 2997 while (first != tdh) { 2998 logif(pkt_txclean); 2999 3000 num_avail++; 3001 3002 tx_buffer = &adapter->tx_buffer_area[first]; 3003 if (tx_buffer->m_head) { 3004 IFNET_STAT_INC(ifp, opackets, 1); 3005 bus_dmamap_unload(adapter->txtag, 3006 tx_buffer->map); 3007 m_freem(tx_buffer->m_head); 3008 tx_buffer->m_head = NULL; 3009 } 3010 3011 if (first == dd_idx) { 3012 EM_INC_TXDD_IDX(adapter->tx_dd_head); 3013 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 3014 adapter->tx_dd_head = 0; 3015 adapter->tx_dd_tail = 0; 3016 dd_idx = -1; 3017 } else { 3018 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3019 } 3020 } 3021 3022 if (++first == adapter->num_tx_desc) 3023 first = 0; 3024 } 3025 adapter->next_tx_to_clean = first; 3026 adapter->num_tx_desc_avail = num_avail; 3027 3028 if (!EM_IS_OACTIVE(adapter)) { 3029 ifq_clr_oactive(&ifp->if_snd); 3030 3031 /* All clean, turn off the timer */ 3032 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3033 ifp->if_timer = 0; 3034 } 3035 } 3036 3037 /* 3038 * When Link is lost sometimes there is work still in the TX ring 3039 * which will result in a watchdog, rather than allow that do an 3040 * attempted cleanup and then reinit here. Note that this has been 3041 * seens mostly with fiber adapters. 3042 */ 3043 static void 3044 em_tx_purge(struct adapter *adapter) 3045 { 3046 struct ifnet *ifp = &adapter->arpcom.ac_if; 3047 3048 if (!adapter->link_active && ifp->if_timer) { 3049 em_tx_collect(adapter); 3050 if (ifp->if_timer) { 3051 if_printf(ifp, "Link lost, TX pending, reinit\n"); 3052 ifp->if_timer = 0; 3053 em_init(adapter); 3054 } 3055 } 3056 } 3057 3058 static int 3059 em_newbuf(struct adapter *adapter, int i, int init) 3060 { 3061 struct mbuf *m; 3062 bus_dma_segment_t seg; 3063 bus_dmamap_t map; 3064 struct em_buffer *rx_buffer; 3065 int error, nseg; 3066 3067 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 3068 if (m == NULL) { 3069 adapter->mbuf_cluster_failed++; 3070 if (init) { 3071 if_printf(&adapter->arpcom.ac_if, 3072 "Unable to allocate RX mbuf\n"); 3073 } 3074 return (ENOBUFS); 3075 } 3076 m->m_len = m->m_pkthdr.len = MCLBYTES; 3077 3078 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN) 3079 m_adj(m, ETHER_ALIGN); 3080 3081 error = bus_dmamap_load_mbuf_segment(adapter->rxtag, 3082 adapter->rx_sparemap, m, 3083 &seg, 1, &nseg, BUS_DMA_NOWAIT); 3084 if (error) { 3085 m_freem(m); 3086 if (init) { 3087 if_printf(&adapter->arpcom.ac_if, 3088 "Unable to load RX mbuf\n"); 3089 } 3090 return (error); 3091 } 3092 3093 rx_buffer = &adapter->rx_buffer_area[i]; 3094 if (rx_buffer->m_head != NULL) 3095 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 3096 3097 map = rx_buffer->map; 3098 rx_buffer->map = adapter->rx_sparemap; 3099 adapter->rx_sparemap = map; 3100 3101 rx_buffer->m_head = m; 3102 3103 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr); 3104 return (0); 3105 } 3106 3107 static int 3108 em_create_rx_ring(struct adapter *adapter) 3109 { 3110 device_t dev = adapter->dev; 3111 struct em_buffer *rx_buffer; 3112 int i, error; 3113 3114 adapter->rx_buffer_area = 3115 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc, 3116 M_DEVBUF, M_WAITOK | M_ZERO); 3117 3118 /* 3119 * Create DMA tag for rx buffers 3120 */ 3121 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 3122 1, 0, /* alignment, bounds */ 3123 BUS_SPACE_MAXADDR, /* lowaddr */ 3124 BUS_SPACE_MAXADDR, /* highaddr */ 3125 NULL, NULL, /* filter, filterarg */ 3126 MCLBYTES, /* maxsize */ 3127 1, /* nsegments */ 3128 MCLBYTES, /* maxsegsize */ 3129 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 3130 &adapter->rxtag); 3131 if (error) { 3132 device_printf(dev, "Unable to allocate RX DMA tag\n"); 3133 kfree(adapter->rx_buffer_area, M_DEVBUF); 3134 adapter->rx_buffer_area = NULL; 3135 return error; 3136 } 3137 3138 /* 3139 * Create spare DMA map for rx buffers 3140 */ 3141 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3142 &adapter->rx_sparemap); 3143 if (error) { 3144 device_printf(dev, "Unable to create spare RX DMA map\n"); 3145 bus_dma_tag_destroy(adapter->rxtag); 3146 kfree(adapter->rx_buffer_area, M_DEVBUF); 3147 adapter->rx_buffer_area = NULL; 3148 return error; 3149 } 3150 3151 /* 3152 * Create DMA maps for rx buffers 3153 */ 3154 for (i = 0; i < adapter->num_rx_desc; i++) { 3155 rx_buffer = &adapter->rx_buffer_area[i]; 3156 3157 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3158 &rx_buffer->map); 3159 if (error) { 3160 device_printf(dev, "Unable to create RX DMA map\n"); 3161 em_destroy_rx_ring(adapter, i); 3162 return error; 3163 } 3164 } 3165 return (0); 3166 } 3167 3168 static int 3169 em_init_rx_ring(struct adapter *adapter) 3170 { 3171 int i, error; 3172 3173 /* Reset descriptor ring */ 3174 bzero(adapter->rx_desc_base, 3175 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 3176 3177 /* Allocate new ones. */ 3178 for (i = 0; i < adapter->num_rx_desc; i++) { 3179 error = em_newbuf(adapter, i, 1); 3180 if (error) 3181 return (error); 3182 } 3183 3184 /* Setup our descriptor pointers */ 3185 adapter->next_rx_desc_to_check = 0; 3186 3187 return (0); 3188 } 3189 3190 static void 3191 em_init_rx_unit(struct adapter *adapter) 3192 { 3193 struct ifnet *ifp = &adapter->arpcom.ac_if; 3194 uint64_t bus_addr; 3195 uint32_t rctl; 3196 3197 /* 3198 * Make sure receives are disabled while setting 3199 * up the descriptor ring 3200 */ 3201 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3202 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3203 3204 if (adapter->hw.mac.type >= e1000_82540) { 3205 uint32_t itr; 3206 3207 /* 3208 * Set the interrupt throttling rate. Value is calculated 3209 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 3210 */ 3211 if (adapter->int_throttle_ceil) 3212 itr = 1000000000 / 256 / adapter->int_throttle_ceil; 3213 else 3214 itr = 0; 3215 em_set_itr(adapter, itr); 3216 } 3217 3218 /* Disable accelerated ackknowledge */ 3219 if (adapter->hw.mac.type == e1000_82574) { 3220 E1000_WRITE_REG(&adapter->hw, 3221 E1000_RFCTL, E1000_RFCTL_ACK_DIS); 3222 } 3223 3224 /* Receive Checksum Offload for TCP and UDP */ 3225 if (ifp->if_capenable & IFCAP_RXCSUM) { 3226 uint32_t rxcsum; 3227 3228 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 3229 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3230 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum); 3231 } 3232 3233 /* 3234 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3235 * long latencies are observed, like Lenovo X60. This 3236 * change eliminates the problem, but since having positive 3237 * values in RDTR is a known source of problems on other 3238 * platforms another solution is being sought. 3239 */ 3240 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) { 3241 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573); 3242 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573); 3243 } 3244 3245 /* 3246 * Setup the Base and Length of the Rx Descriptor Ring 3247 */ 3248 bus_addr = adapter->rxdma.dma_paddr; 3249 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 3250 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 3251 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 3252 (uint32_t)(bus_addr >> 32)); 3253 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 3254 (uint32_t)bus_addr); 3255 3256 /* 3257 * Setup the HW Rx Head and Tail Descriptor Pointers 3258 */ 3259 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 3260 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 3261 3262 /* Set PTHRESH for improved jumbo performance */ 3263 if (((adapter->hw.mac.type == e1000_ich9lan) || 3264 (adapter->hw.mac.type == e1000_pch2lan) || 3265 (adapter->hw.mac.type == e1000_ich10lan)) && 3266 (ifp->if_mtu > ETHERMTU)) { 3267 uint32_t rxdctl; 3268 3269 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0)); 3270 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3); 3271 } 3272 3273 if (adapter->hw.mac.type == e1000_pch2lan) { 3274 if (ifp->if_mtu > ETHERMTU) 3275 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE); 3276 else 3277 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE); 3278 } 3279 3280 /* Setup the Receive Control Register */ 3281 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3282 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3283 E1000_RCTL_RDMTS_HALF | 3284 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3285 3286 /* Make sure VLAN Filters are off */ 3287 rctl &= ~E1000_RCTL_VFE; 3288 3289 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 3290 rctl |= E1000_RCTL_SBP; 3291 else 3292 rctl &= ~E1000_RCTL_SBP; 3293 3294 switch (adapter->rx_buffer_len) { 3295 default: 3296 case 2048: 3297 rctl |= E1000_RCTL_SZ_2048; 3298 break; 3299 3300 case 4096: 3301 rctl |= E1000_RCTL_SZ_4096 | 3302 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3303 break; 3304 3305 case 8192: 3306 rctl |= E1000_RCTL_SZ_8192 | 3307 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3308 break; 3309 3310 case 16384: 3311 rctl |= E1000_RCTL_SZ_16384 | 3312 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3313 break; 3314 } 3315 3316 if (ifp->if_mtu > ETHERMTU) 3317 rctl |= E1000_RCTL_LPE; 3318 else 3319 rctl &= ~E1000_RCTL_LPE; 3320 3321 /* Enable Receives */ 3322 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3323 } 3324 3325 static void 3326 em_destroy_rx_ring(struct adapter *adapter, int ndesc) 3327 { 3328 struct em_buffer *rx_buffer; 3329 int i; 3330 3331 if (adapter->rx_buffer_area == NULL) 3332 return; 3333 3334 for (i = 0; i < ndesc; i++) { 3335 rx_buffer = &adapter->rx_buffer_area[i]; 3336 3337 KKASSERT(rx_buffer->m_head == NULL); 3338 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map); 3339 } 3340 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 3341 bus_dma_tag_destroy(adapter->rxtag); 3342 3343 kfree(adapter->rx_buffer_area, M_DEVBUF); 3344 adapter->rx_buffer_area = NULL; 3345 } 3346 3347 static void 3348 em_rxeof(struct adapter *adapter, int count) 3349 { 3350 struct ifnet *ifp = &adapter->arpcom.ac_if; 3351 uint8_t status, accept_frame = 0, eop = 0; 3352 uint16_t len, desc_len, prev_len_adj; 3353 struct e1000_rx_desc *current_desc; 3354 struct mbuf *mp; 3355 int i; 3356 3357 i = adapter->next_rx_desc_to_check; 3358 current_desc = &adapter->rx_desc_base[i]; 3359 3360 if (!(current_desc->status & E1000_RXD_STAT_DD)) 3361 return; 3362 3363 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) { 3364 struct mbuf *m = NULL; 3365 3366 logif(pkt_receive); 3367 3368 mp = adapter->rx_buffer_area[i].m_head; 3369 3370 /* 3371 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3372 * needs to access the last received byte in the mbuf. 3373 */ 3374 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3375 BUS_DMASYNC_POSTREAD); 3376 3377 accept_frame = 1; 3378 prev_len_adj = 0; 3379 desc_len = le16toh(current_desc->length); 3380 status = current_desc->status; 3381 if (status & E1000_RXD_STAT_EOP) { 3382 count--; 3383 eop = 1; 3384 if (desc_len < ETHER_CRC_LEN) { 3385 len = 0; 3386 prev_len_adj = ETHER_CRC_LEN - desc_len; 3387 } else { 3388 len = desc_len - ETHER_CRC_LEN; 3389 } 3390 } else { 3391 eop = 0; 3392 len = desc_len; 3393 } 3394 3395 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3396 uint8_t last_byte; 3397 uint32_t pkt_len = desc_len; 3398 3399 if (adapter->fmp != NULL) 3400 pkt_len += adapter->fmp->m_pkthdr.len; 3401 3402 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3403 if (TBI_ACCEPT(&adapter->hw, status, 3404 current_desc->errors, pkt_len, last_byte, 3405 adapter->min_frame_size, adapter->max_frame_size)) { 3406 e1000_tbi_adjust_stats_82543(&adapter->hw, 3407 &adapter->stats, pkt_len, 3408 adapter->hw.mac.addr, 3409 adapter->max_frame_size); 3410 if (len > 0) 3411 len--; 3412 } else { 3413 accept_frame = 0; 3414 } 3415 } 3416 3417 if (accept_frame) { 3418 if (em_newbuf(adapter, i, 0) != 0) { 3419 IFNET_STAT_INC(ifp, iqdrops, 1); 3420 goto discard; 3421 } 3422 3423 /* Assign correct length to the current fragment */ 3424 mp->m_len = len; 3425 3426 if (adapter->fmp == NULL) { 3427 mp->m_pkthdr.len = len; 3428 adapter->fmp = mp; /* Store the first mbuf */ 3429 adapter->lmp = mp; 3430 } else { 3431 /* 3432 * Chain mbuf's together 3433 */ 3434 3435 /* 3436 * Adjust length of previous mbuf in chain if 3437 * we received less than 4 bytes in the last 3438 * descriptor. 3439 */ 3440 if (prev_len_adj > 0) { 3441 adapter->lmp->m_len -= prev_len_adj; 3442 adapter->fmp->m_pkthdr.len -= 3443 prev_len_adj; 3444 } 3445 adapter->lmp->m_next = mp; 3446 adapter->lmp = adapter->lmp->m_next; 3447 adapter->fmp->m_pkthdr.len += len; 3448 } 3449 3450 if (eop) { 3451 adapter->fmp->m_pkthdr.rcvif = ifp; 3452 IFNET_STAT_INC(ifp, ipackets, 1); 3453 3454 if (ifp->if_capenable & IFCAP_RXCSUM) { 3455 em_rxcsum(adapter, current_desc, 3456 adapter->fmp); 3457 } 3458 3459 if (status & E1000_RXD_STAT_VP) { 3460 adapter->fmp->m_pkthdr.ether_vlantag = 3461 (le16toh(current_desc->special) & 3462 E1000_RXD_SPC_VLAN_MASK); 3463 adapter->fmp->m_flags |= M_VLANTAG; 3464 } 3465 m = adapter->fmp; 3466 adapter->fmp = NULL; 3467 adapter->lmp = NULL; 3468 } 3469 } else { 3470 IFNET_STAT_INC(ifp, ierrors, 1); 3471 discard: 3472 #ifdef foo 3473 /* Reuse loaded DMA map and just update mbuf chain */ 3474 mp = adapter->rx_buffer_area[i].m_head; 3475 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 3476 mp->m_data = mp->m_ext.ext_buf; 3477 mp->m_next = NULL; 3478 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 3479 m_adj(mp, ETHER_ALIGN); 3480 #endif 3481 if (adapter->fmp != NULL) { 3482 m_freem(adapter->fmp); 3483 adapter->fmp = NULL; 3484 adapter->lmp = NULL; 3485 } 3486 m = NULL; 3487 } 3488 3489 /* Zero out the receive descriptors status. */ 3490 current_desc->status = 0; 3491 3492 if (m != NULL) 3493 ifp->if_input(ifp, m); 3494 3495 /* Advance our pointers to the next descriptor. */ 3496 if (++i == adapter->num_rx_desc) 3497 i = 0; 3498 current_desc = &adapter->rx_desc_base[i]; 3499 } 3500 adapter->next_rx_desc_to_check = i; 3501 3502 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3503 if (--i < 0) 3504 i = adapter->num_rx_desc - 1; 3505 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 3506 } 3507 3508 static void 3509 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc, 3510 struct mbuf *mp) 3511 { 3512 /* 82543 or newer only */ 3513 if (adapter->hw.mac.type < e1000_82543 || 3514 /* Ignore Checksum bit is set */ 3515 (rx_desc->status & E1000_RXD_STAT_IXSM)) 3516 return; 3517 3518 if ((rx_desc->status & E1000_RXD_STAT_IPCS) && 3519 !(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3520 /* IP Checksum Good */ 3521 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 3522 } 3523 3524 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) && 3525 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3526 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3527 CSUM_PSEUDO_HDR | 3528 CSUM_FRAG_NOT_CHECKED; 3529 mp->m_pkthdr.csum_data = htons(0xffff); 3530 } 3531 } 3532 3533 static void 3534 em_enable_intr(struct adapter *adapter) 3535 { 3536 uint32_t ims_mask = IMS_ENABLE_MASK; 3537 3538 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer); 3539 3540 #if 0 3541 /* XXX MSIX */ 3542 if (adapter->hw.mac.type == e1000_82574) { 3543 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK); 3544 ims_mask |= EM_MSIX_MASK; 3545 } 3546 #endif 3547 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask); 3548 } 3549 3550 static void 3551 em_disable_intr(struct adapter *adapter) 3552 { 3553 uint32_t clear = 0xffffffff; 3554 3555 /* 3556 * The first version of 82542 had an errata where when link was forced 3557 * it would stay up even up even if the cable was disconnected. 3558 * Sequence errors were used to detect the disconnect and then the 3559 * driver would unforce the link. This code in the in the ISR. For 3560 * this to work correctly the Sequence error interrupt had to be 3561 * enabled all the time. 3562 */ 3563 if (adapter->hw.mac.type == e1000_82542 && 3564 adapter->hw.revision_id == E1000_REVISION_2) 3565 clear &= ~E1000_ICR_RXSEQ; 3566 else if (adapter->hw.mac.type == e1000_82574) 3567 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0); 3568 3569 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear); 3570 3571 adapter->npoll.ifpc_stcount = 0; 3572 3573 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer); 3574 } 3575 3576 /* 3577 * Bit of a misnomer, what this really means is 3578 * to enable OS management of the system... aka 3579 * to disable special hardware management features 3580 */ 3581 static void 3582 em_get_mgmt(struct adapter *adapter) 3583 { 3584 /* A shared code workaround */ 3585 #define E1000_82542_MANC2H E1000_MANC2H 3586 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3587 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3588 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3589 3590 /* disable hardware interception of ARP */ 3591 manc &= ~(E1000_MANC_ARP_EN); 3592 3593 /* enable receiving management packets to the host */ 3594 if (adapter->hw.mac.type >= e1000_82571) { 3595 manc |= E1000_MANC_EN_MNG2HOST; 3596 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3597 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3598 manc2h |= E1000_MNG2HOST_PORT_623; 3599 manc2h |= E1000_MNG2HOST_PORT_664; 3600 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3601 } 3602 3603 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3604 } 3605 } 3606 3607 /* 3608 * Give control back to hardware management 3609 * controller if there is one. 3610 */ 3611 static void 3612 em_rel_mgmt(struct adapter *adapter) 3613 { 3614 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3615 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3616 3617 /* re-enable hardware interception of ARP */ 3618 manc |= E1000_MANC_ARP_EN; 3619 3620 if (adapter->hw.mac.type >= e1000_82571) 3621 manc &= ~E1000_MANC_EN_MNG2HOST; 3622 3623 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3624 } 3625 } 3626 3627 /* 3628 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3629 * For ASF and Pass Through versions of f/w this means that 3630 * the driver is loaded. For AMT version (only with 82573) 3631 * of the f/w this means that the network i/f is open. 3632 */ 3633 static void 3634 em_get_hw_control(struct adapter *adapter) 3635 { 3636 /* Let firmware know the driver has taken over */ 3637 if (adapter->hw.mac.type == e1000_82573) { 3638 uint32_t swsm; 3639 3640 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3641 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3642 swsm | E1000_SWSM_DRV_LOAD); 3643 } else { 3644 uint32_t ctrl_ext; 3645 3646 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3647 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3648 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3649 } 3650 adapter->flags |= EM_FLAG_HW_CTRL; 3651 } 3652 3653 /* 3654 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3655 * For ASF and Pass Through versions of f/w this means that the 3656 * driver is no longer loaded. For AMT version (only with 82573) 3657 * of the f/w this means that the network i/f is closed. 3658 */ 3659 static void 3660 em_rel_hw_control(struct adapter *adapter) 3661 { 3662 if ((adapter->flags & EM_FLAG_HW_CTRL) == 0) 3663 return; 3664 adapter->flags &= ~EM_FLAG_HW_CTRL; 3665 3666 /* Let firmware taken over control of h/w */ 3667 if (adapter->hw.mac.type == e1000_82573) { 3668 uint32_t swsm; 3669 3670 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3671 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3672 swsm & ~E1000_SWSM_DRV_LOAD); 3673 } else { 3674 uint32_t ctrl_ext; 3675 3676 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3677 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3678 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3679 } 3680 } 3681 3682 static int 3683 em_is_valid_eaddr(const uint8_t *addr) 3684 { 3685 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3686 3687 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3688 return (FALSE); 3689 3690 return (TRUE); 3691 } 3692 3693 /* 3694 * Enable PCI Wake On Lan capability 3695 */ 3696 void 3697 em_enable_wol(device_t dev) 3698 { 3699 uint16_t cap, status; 3700 uint8_t id; 3701 3702 /* First find the capabilities pointer*/ 3703 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3704 3705 /* Read the PM Capabilities */ 3706 id = pci_read_config(dev, cap, 1); 3707 if (id != PCIY_PMG) /* Something wrong */ 3708 return; 3709 3710 /* 3711 * OK, we have the power capabilities, 3712 * so now get the status register 3713 */ 3714 cap += PCIR_POWER_STATUS; 3715 status = pci_read_config(dev, cap, 2); 3716 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3717 pci_write_config(dev, cap, status, 2); 3718 } 3719 3720 3721 /* 3722 * 82544 Coexistence issue workaround. 3723 * There are 2 issues. 3724 * 1. Transmit Hang issue. 3725 * To detect this issue, following equation can be used... 3726 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3727 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3728 * 3729 * 2. DAC issue. 3730 * To detect this issue, following equation can be used... 3731 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3732 * If SUM[3:0] is in between 9 to c, we will have this issue. 3733 * 3734 * WORKAROUND: 3735 * Make sure we do not have ending address 3736 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3737 */ 3738 static uint32_t 3739 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array) 3740 { 3741 uint32_t safe_terminator; 3742 3743 /* 3744 * Since issue is sensitive to length and address. 3745 * Let us first check the address... 3746 */ 3747 if (length <= 4) { 3748 desc_array->descriptor[0].address = address; 3749 desc_array->descriptor[0].length = length; 3750 desc_array->elements = 1; 3751 return (desc_array->elements); 3752 } 3753 3754 safe_terminator = 3755 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3756 3757 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3758 if (safe_terminator == 0 || 3759 (safe_terminator > 4 && safe_terminator < 9) || 3760 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 3761 desc_array->descriptor[0].address = address; 3762 desc_array->descriptor[0].length = length; 3763 desc_array->elements = 1; 3764 return (desc_array->elements); 3765 } 3766 3767 desc_array->descriptor[0].address = address; 3768 desc_array->descriptor[0].length = length - 4; 3769 desc_array->descriptor[1].address = address + (length - 4); 3770 desc_array->descriptor[1].length = 4; 3771 desc_array->elements = 2; 3772 return (desc_array->elements); 3773 } 3774 3775 static void 3776 em_update_stats(struct adapter *adapter) 3777 { 3778 struct ifnet *ifp = &adapter->arpcom.ac_if; 3779 3780 if (adapter->hw.phy.media_type == e1000_media_type_copper || 3781 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3782 adapter->stats.symerrs += 3783 E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3784 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3785 } 3786 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3787 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3788 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3789 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3790 3791 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3792 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3793 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3794 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3795 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3796 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3797 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3798 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3799 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3800 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3801 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3802 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3803 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3804 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3805 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3806 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3807 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3808 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3809 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3810 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3811 3812 /* For the 64-bit byte counters the low dword must be read first. */ 3813 /* Both registers clear on the read of the high dword */ 3814 3815 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 3816 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 3817 3818 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3819 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3820 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3821 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3822 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3823 3824 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3825 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3826 3827 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3828 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3829 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3830 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3831 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3832 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3833 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3834 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3835 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3836 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3837 3838 if (adapter->hw.mac.type >= e1000_82543) { 3839 adapter->stats.algnerrc += 3840 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3841 adapter->stats.rxerrc += 3842 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3843 adapter->stats.tncrs += 3844 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3845 adapter->stats.cexterr += 3846 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3847 adapter->stats.tsctc += 3848 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3849 adapter->stats.tsctfc += 3850 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3851 } 3852 3853 IFNET_STAT_SET(ifp, collisions, adapter->stats.colc); 3854 3855 /* Rx Errors */ 3856 IFNET_STAT_SET(ifp, ierrors, 3857 adapter->dropped_pkts + adapter->stats.rxerrc + 3858 adapter->stats.crcerrs + adapter->stats.algnerrc + 3859 adapter->stats.ruc + adapter->stats.roc + 3860 adapter->stats.mpc + adapter->stats.cexterr); 3861 3862 /* Tx Errors */ 3863 IFNET_STAT_SET(ifp, oerrors, 3864 adapter->stats.ecol + adapter->stats.latecol + 3865 adapter->watchdog_events); 3866 } 3867 3868 static void 3869 em_print_debug_info(struct adapter *adapter) 3870 { 3871 device_t dev = adapter->dev; 3872 uint8_t *hw_addr = adapter->hw.hw_addr; 3873 3874 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3875 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3876 E1000_READ_REG(&adapter->hw, E1000_CTRL), 3877 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 3878 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3879 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3880 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 3881 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3882 adapter->hw.fc.high_water, 3883 adapter->hw.fc.low_water); 3884 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3885 E1000_READ_REG(&adapter->hw, E1000_TIDV), 3886 E1000_READ_REG(&adapter->hw, E1000_TADV)); 3887 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3888 E1000_READ_REG(&adapter->hw, E1000_RDTR), 3889 E1000_READ_REG(&adapter->hw, E1000_RADV)); 3890 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3891 (long long)adapter->tx_fifo_wrk_cnt, 3892 (long long)adapter->tx_fifo_reset_cnt); 3893 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3894 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 3895 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 3896 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3897 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 3898 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 3899 device_printf(dev, "Num Tx descriptors avail = %d\n", 3900 adapter->num_tx_desc_avail); 3901 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3902 adapter->no_tx_desc_avail1); 3903 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3904 adapter->no_tx_desc_avail2); 3905 device_printf(dev, "Std mbuf failed = %ld\n", 3906 adapter->mbuf_alloc_failed); 3907 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3908 adapter->mbuf_cluster_failed); 3909 device_printf(dev, "Driver dropped packets = %ld\n", 3910 adapter->dropped_pkts); 3911 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3912 adapter->no_tx_dma_setup); 3913 } 3914 3915 static void 3916 em_print_hw_stats(struct adapter *adapter) 3917 { 3918 device_t dev = adapter->dev; 3919 3920 device_printf(dev, "Excessive collisions = %lld\n", 3921 (long long)adapter->stats.ecol); 3922 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3923 device_printf(dev, "Symbol errors = %lld\n", 3924 (long long)adapter->stats.symerrs); 3925 #endif 3926 device_printf(dev, "Sequence errors = %lld\n", 3927 (long long)adapter->stats.sec); 3928 device_printf(dev, "Defer count = %lld\n", 3929 (long long)adapter->stats.dc); 3930 device_printf(dev, "Missed Packets = %lld\n", 3931 (long long)adapter->stats.mpc); 3932 device_printf(dev, "Receive No Buffers = %lld\n", 3933 (long long)adapter->stats.rnbc); 3934 /* RLEC is inaccurate on some hardware, calculate our own. */ 3935 device_printf(dev, "Receive Length Errors = %lld\n", 3936 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 3937 device_printf(dev, "Receive errors = %lld\n", 3938 (long long)adapter->stats.rxerrc); 3939 device_printf(dev, "Crc errors = %lld\n", 3940 (long long)adapter->stats.crcerrs); 3941 device_printf(dev, "Alignment errors = %lld\n", 3942 (long long)adapter->stats.algnerrc); 3943 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3944 (long long)adapter->stats.cexterr); 3945 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 3946 device_printf(dev, "watchdog timeouts = %ld\n", 3947 adapter->watchdog_events); 3948 device_printf(dev, "XON Rcvd = %lld\n", 3949 (long long)adapter->stats.xonrxc); 3950 device_printf(dev, "XON Xmtd = %lld\n", 3951 (long long)adapter->stats.xontxc); 3952 device_printf(dev, "XOFF Rcvd = %lld\n", 3953 (long long)adapter->stats.xoffrxc); 3954 device_printf(dev, "XOFF Xmtd = %lld\n", 3955 (long long)adapter->stats.xofftxc); 3956 device_printf(dev, "Good Packets Rcvd = %lld\n", 3957 (long long)adapter->stats.gprc); 3958 device_printf(dev, "Good Packets Xmtd = %lld\n", 3959 (long long)adapter->stats.gptc); 3960 } 3961 3962 static void 3963 em_print_nvm_info(struct adapter *adapter) 3964 { 3965 uint16_t eeprom_data; 3966 int i, j, row = 0; 3967 3968 /* Its a bit crude, but it gets the job done */ 3969 kprintf("\nInterface EEPROM Dump:\n"); 3970 kprintf("Offset\n0x0000 "); 3971 for (i = 0, j = 0; i < 32; i++, j++) { 3972 if (j == 8) { /* Make the offset block */ 3973 j = 0; ++row; 3974 kprintf("\n0x00%x0 ",row); 3975 } 3976 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 3977 kprintf("%04x ", eeprom_data); 3978 } 3979 kprintf("\n"); 3980 } 3981 3982 static int 3983 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3984 { 3985 struct adapter *adapter; 3986 struct ifnet *ifp; 3987 int error, result; 3988 3989 result = -1; 3990 error = sysctl_handle_int(oidp, &result, 0, req); 3991 if (error || !req->newptr) 3992 return (error); 3993 3994 adapter = (struct adapter *)arg1; 3995 ifp = &adapter->arpcom.ac_if; 3996 3997 lwkt_serialize_enter(ifp->if_serializer); 3998 3999 if (result == 1) 4000 em_print_debug_info(adapter); 4001 4002 /* 4003 * This value will cause a hex dump of the 4004 * first 32 16-bit words of the EEPROM to 4005 * the screen. 4006 */ 4007 if (result == 2) 4008 em_print_nvm_info(adapter); 4009 4010 lwkt_serialize_exit(ifp->if_serializer); 4011 4012 return (error); 4013 } 4014 4015 static int 4016 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 4017 { 4018 int error, result; 4019 4020 result = -1; 4021 error = sysctl_handle_int(oidp, &result, 0, req); 4022 if (error || !req->newptr) 4023 return (error); 4024 4025 if (result == 1) { 4026 struct adapter *adapter = (struct adapter *)arg1; 4027 struct ifnet *ifp = &adapter->arpcom.ac_if; 4028 4029 lwkt_serialize_enter(ifp->if_serializer); 4030 em_print_hw_stats(adapter); 4031 lwkt_serialize_exit(ifp->if_serializer); 4032 } 4033 return (error); 4034 } 4035 4036 static void 4037 em_add_sysctl(struct adapter *adapter) 4038 { 4039 sysctl_ctx_init(&adapter->sysctl_ctx); 4040 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx, 4041 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 4042 device_get_nameunit(adapter->dev), 4043 CTLFLAG_RD, 0, ""); 4044 if (adapter->sysctl_tree == NULL) { 4045 device_printf(adapter->dev, "can't add sysctl node\n"); 4046 } else { 4047 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4048 SYSCTL_CHILDREN(adapter->sysctl_tree), 4049 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4050 em_sysctl_debug_info, "I", "Debug Information"); 4051 4052 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4053 SYSCTL_CHILDREN(adapter->sysctl_tree), 4054 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4055 em_sysctl_stats, "I", "Statistics"); 4056 4057 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4058 SYSCTL_CHILDREN(adapter->sysctl_tree), 4059 OID_AUTO, "rxd", CTLFLAG_RD, 4060 &adapter->num_rx_desc, 0, NULL); 4061 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4062 SYSCTL_CHILDREN(adapter->sysctl_tree), 4063 OID_AUTO, "txd", CTLFLAG_RD, 4064 &adapter->num_tx_desc, 0, NULL); 4065 4066 if (adapter->hw.mac.type >= e1000_82540) { 4067 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4068 SYSCTL_CHILDREN(adapter->sysctl_tree), 4069 OID_AUTO, "int_throttle_ceil", 4070 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4071 em_sysctl_int_throttle, "I", 4072 "interrupt throttling rate"); 4073 } 4074 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4075 SYSCTL_CHILDREN(adapter->sysctl_tree), 4076 OID_AUTO, "int_tx_nsegs", 4077 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4078 em_sysctl_int_tx_nsegs, "I", 4079 "# segments per TX interrupt"); 4080 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4081 SYSCTL_CHILDREN(adapter->sysctl_tree), 4082 OID_AUTO, "wreg_tx_nsegs", CTLFLAG_RW, 4083 &adapter->tx_wreg_nsegs, 0, 4084 "# segments before write to hardware register"); 4085 } 4086 } 4087 4088 static int 4089 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 4090 { 4091 struct adapter *adapter = (void *)arg1; 4092 struct ifnet *ifp = &adapter->arpcom.ac_if; 4093 int error, throttle; 4094 4095 throttle = adapter->int_throttle_ceil; 4096 error = sysctl_handle_int(oidp, &throttle, 0, req); 4097 if (error || req->newptr == NULL) 4098 return error; 4099 if (throttle < 0 || throttle > 1000000000 / 256) 4100 return EINVAL; 4101 4102 if (throttle) { 4103 /* 4104 * Set the interrupt throttling rate in 256ns increments, 4105 * recalculate sysctl value assignment to get exact frequency. 4106 */ 4107 throttle = 1000000000 / 256 / throttle; 4108 4109 /* Upper 16bits of ITR is reserved and should be zero */ 4110 if (throttle & 0xffff0000) 4111 return EINVAL; 4112 } 4113 4114 lwkt_serialize_enter(ifp->if_serializer); 4115 4116 if (throttle) 4117 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 4118 else 4119 adapter->int_throttle_ceil = 0; 4120 4121 if (ifp->if_flags & IFF_RUNNING) 4122 em_set_itr(adapter, throttle); 4123 4124 lwkt_serialize_exit(ifp->if_serializer); 4125 4126 if (bootverbose) { 4127 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 4128 adapter->int_throttle_ceil); 4129 } 4130 return 0; 4131 } 4132 4133 static int 4134 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 4135 { 4136 struct adapter *adapter = (void *)arg1; 4137 struct ifnet *ifp = &adapter->arpcom.ac_if; 4138 int error, segs; 4139 4140 segs = adapter->tx_int_nsegs; 4141 error = sysctl_handle_int(oidp, &segs, 0, req); 4142 if (error || req->newptr == NULL) 4143 return error; 4144 if (segs <= 0) 4145 return EINVAL; 4146 4147 lwkt_serialize_enter(ifp->if_serializer); 4148 4149 /* 4150 * Don't allow int_tx_nsegs to become: 4151 * o Less the oact_tx_desc 4152 * o Too large that no TX desc will cause TX interrupt to 4153 * be generated (OACTIVE will never recover) 4154 * o Too small that will cause tx_dd[] overflow 4155 */ 4156 if (segs < adapter->oact_tx_desc || 4157 segs >= adapter->num_tx_desc - adapter->oact_tx_desc || 4158 segs < adapter->num_tx_desc / EM_TXDD_SAFE) { 4159 error = EINVAL; 4160 } else { 4161 error = 0; 4162 adapter->tx_int_nsegs = segs; 4163 } 4164 4165 lwkt_serialize_exit(ifp->if_serializer); 4166 4167 return error; 4168 } 4169 4170 static void 4171 em_set_itr(struct adapter *adapter, uint32_t itr) 4172 { 4173 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr); 4174 if (adapter->hw.mac.type == e1000_82574) { 4175 int i; 4176 4177 /* 4178 * When using MSIX interrupts we need to 4179 * throttle using the EITR register 4180 */ 4181 for (i = 0; i < 4; ++i) { 4182 E1000_WRITE_REG(&adapter->hw, 4183 E1000_EITR_82574(i), itr); 4184 } 4185 } 4186 } 4187 4188 static void 4189 em_disable_aspm(struct adapter *adapter) 4190 { 4191 uint16_t link_cap, link_ctrl, disable; 4192 uint8_t pcie_ptr, reg; 4193 device_t dev = adapter->dev; 4194 4195 switch (adapter->hw.mac.type) { 4196 case e1000_82571: 4197 case e1000_82572: 4198 case e1000_82573: 4199 /* 4200 * 82573 specification update 4201 * errata #8 disable L0s 4202 * errata #41 disable L1 4203 * 4204 * 82571/82572 specification update 4205 # errata #13 disable L1 4206 * errata #68 disable L0s 4207 */ 4208 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 4209 break; 4210 4211 case e1000_82574: 4212 case e1000_82583: 4213 /* 4214 * 82574 specification update errata #20 4215 * 82583 specification update errata #9 4216 * 4217 * There is no need to disable L1 4218 */ 4219 disable = PCIEM_LNKCTL_ASPM_L0S; 4220 break; 4221 4222 default: 4223 return; 4224 } 4225 4226 pcie_ptr = pci_get_pciecap_ptr(dev); 4227 if (pcie_ptr == 0) 4228 return; 4229 4230 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 4231 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 4232 return; 4233 4234 if (bootverbose) { 4235 if_printf(&adapter->arpcom.ac_if, 4236 "disable ASPM %#02x\n", disable); 4237 } 4238 4239 reg = pcie_ptr + PCIER_LINKCTRL; 4240 link_ctrl = pci_read_config(dev, reg, 2); 4241 link_ctrl &= ~disable; 4242 pci_write_config(dev, reg, link_ctrl, 2); 4243 } 4244 4245 static int 4246 em_tso_pullup(struct adapter *adapter, struct mbuf **mp) 4247 { 4248 int iphlen, hoff, thoff, ex = 0; 4249 struct mbuf *m; 4250 struct ip *ip; 4251 4252 m = *mp; 4253 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 4254 4255 iphlen = m->m_pkthdr.csum_iphlen; 4256 thoff = m->m_pkthdr.csum_thlen; 4257 hoff = m->m_pkthdr.csum_lhlen; 4258 4259 KASSERT(iphlen > 0, ("invalid ip hlen")); 4260 KASSERT(thoff > 0, ("invalid tcp hlen")); 4261 KASSERT(hoff > 0, ("invalid ether hlen")); 4262 4263 if (adapter->flags & EM_FLAG_TSO_PULLEX) 4264 ex = 4; 4265 4266 if (m->m_len < hoff + iphlen + thoff + ex) { 4267 m = m_pullup(m, hoff + iphlen + thoff + ex); 4268 if (m == NULL) { 4269 *mp = NULL; 4270 return ENOBUFS; 4271 } 4272 *mp = m; 4273 } 4274 ip = mtodoff(m, struct ip *, hoff); 4275 ip->ip_len = 0; 4276 4277 return 0; 4278 } 4279 4280 static int 4281 em_tso_setup(struct adapter *adapter, struct mbuf *mp, 4282 uint32_t *txd_upper, uint32_t *txd_lower) 4283 { 4284 struct e1000_context_desc *TXD; 4285 int hoff, iphlen, thoff, hlen; 4286 int mss, pktlen, curr_txd; 4287 4288 iphlen = mp->m_pkthdr.csum_iphlen; 4289 thoff = mp->m_pkthdr.csum_thlen; 4290 hoff = mp->m_pkthdr.csum_lhlen; 4291 mss = mp->m_pkthdr.tso_segsz; 4292 pktlen = mp->m_pkthdr.len; 4293 4294 if (adapter->csum_flags == CSUM_TSO && 4295 adapter->csum_iphlen == iphlen && 4296 adapter->csum_lhlen == hoff && 4297 adapter->csum_thlen == thoff && 4298 adapter->csum_mss == mss && 4299 adapter->csum_pktlen == pktlen) { 4300 *txd_upper = adapter->csum_txd_upper; 4301 *txd_lower = adapter->csum_txd_lower; 4302 return 0; 4303 } 4304 hlen = hoff + iphlen + thoff; 4305 4306 /* 4307 * Setup a new TSO context. 4308 */ 4309 4310 curr_txd = adapter->next_avail_tx_desc; 4311 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 4312 4313 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 4314 E1000_TXD_DTYP_D | /* Data descr type */ 4315 E1000_TXD_CMD_TSE; /* Do TSE on this packet */ 4316 4317 /* IP and/or TCP header checksum calculation and insertion. */ 4318 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 4319 4320 /* 4321 * Start offset for header checksum calculation. 4322 * End offset for header checksum calculation. 4323 * Offset of place put the checksum. 4324 */ 4325 TXD->lower_setup.ip_fields.ipcss = hoff; 4326 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1); 4327 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum); 4328 4329 /* 4330 * Start offset for payload checksum calculation. 4331 * End offset for payload checksum calculation. 4332 * Offset of place to put the checksum. 4333 */ 4334 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen; 4335 TXD->upper_setup.tcp_fields.tucse = 0; 4336 TXD->upper_setup.tcp_fields.tucso = 4337 hoff + iphlen + offsetof(struct tcphdr, th_sum); 4338 4339 /* 4340 * Payload size per packet w/o any headers. 4341 * Length of all headers up to payload. 4342 */ 4343 TXD->tcp_seg_setup.fields.mss = htole16(mss); 4344 TXD->tcp_seg_setup.fields.hdr_len = hlen; 4345 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS | 4346 E1000_TXD_CMD_DEXT | /* Extended descr */ 4347 E1000_TXD_CMD_TSE | /* TSE context */ 4348 E1000_TXD_CMD_IP | /* Do IP csum */ 4349 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 4350 (pktlen - hlen)); /* Total len */ 4351 4352 /* Save the information for this TSO context */ 4353 adapter->csum_flags = CSUM_TSO; 4354 adapter->csum_lhlen = hoff; 4355 adapter->csum_iphlen = iphlen; 4356 adapter->csum_thlen = thoff; 4357 adapter->csum_mss = mss; 4358 adapter->csum_pktlen = pktlen; 4359 adapter->csum_txd_upper = *txd_upper; 4360 adapter->csum_txd_lower = *txd_lower; 4361 4362 if (++curr_txd == adapter->num_tx_desc) 4363 curr_txd = 0; 4364 4365 KKASSERT(adapter->num_tx_desc_avail > 0); 4366 adapter->num_tx_desc_avail--; 4367 4368 adapter->next_avail_tx_desc = curr_txd; 4369 return 1; 4370 } 4371