1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 */ 67 /* 68 * SERIALIZATION API RULES: 69 * 70 * - If the driver uses the same serializer for the interrupt as for the 71 * ifnet, most of the serialization will be done automatically for the 72 * driver. 73 * 74 * - ifmedia entry points will be serialized by the ifmedia code using the 75 * ifnet serializer. 76 * 77 * - if_* entry points except for if_input will be serialized by the IF 78 * and protocol layers. 79 * 80 * - The device driver must be sure to serialize access from timeout code 81 * installed by the device driver. 82 * 83 * - The device driver typically holds the serializer at the time it wishes 84 * to call if_input. 85 * 86 * - We must call lwkt_serialize_handler_enable() prior to enabling the 87 * hardware interrupt and lwkt_serialize_handler_disable() after disabling 88 * the hardware interrupt in order to avoid handler execution races from 89 * scheduled interrupt threads. 90 * 91 * NOTE! Since callers into the device driver hold the ifnet serializer, 92 * the device driver may be holding a serializer at the time it calls 93 * if_input even if it is not serializer-aware. 94 */ 95 96 #include "opt_ifpoll.h" 97 98 #include <sys/param.h> 99 #include <sys/bus.h> 100 #include <sys/endian.h> 101 #include <sys/interrupt.h> 102 #include <sys/kernel.h> 103 #include <sys/ktr.h> 104 #include <sys/malloc.h> 105 #include <sys/mbuf.h> 106 #include <sys/proc.h> 107 #include <sys/rman.h> 108 #include <sys/serialize.h> 109 #include <sys/socket.h> 110 #include <sys/sockio.h> 111 #include <sys/sysctl.h> 112 #include <sys/systm.h> 113 114 #include <net/bpf.h> 115 #include <net/ethernet.h> 116 #include <net/if.h> 117 #include <net/if_arp.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/if_poll.h> 121 #include <net/ifq_var.h> 122 #include <net/vlan/if_vlan_var.h> 123 #include <net/vlan/if_vlan_ether.h> 124 125 #include <netinet/ip.h> 126 #include <netinet/tcp.h> 127 #include <netinet/udp.h> 128 129 #include <bus/pci/pcivar.h> 130 #include <bus/pci/pcireg.h> 131 132 #include <dev/netif/ig_hal/e1000_api.h> 133 #include <dev/netif/ig_hal/e1000_82571.h> 134 #include <dev/netif/em/if_em.h> 135 136 #define EM_NAME "Intel(R) PRO/1000 Network Connection " 137 #define EM_VER " 7.2.4" 138 139 #define _EM_DEVICE(id, ret) \ 140 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER } 141 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100) 142 #define EM_DEVICE(id) _EM_DEVICE(id, 0) 143 #define EM_DEVICE_NULL { 0, 0, 0, NULL } 144 145 static const struct em_vendor_info em_vendor_info_array[] = { 146 EM_DEVICE(82540EM), 147 EM_DEVICE(82540EM_LOM), 148 EM_DEVICE(82540EP), 149 EM_DEVICE(82540EP_LOM), 150 EM_DEVICE(82540EP_LP), 151 152 EM_DEVICE(82541EI), 153 EM_DEVICE(82541ER), 154 EM_DEVICE(82541ER_LOM), 155 EM_DEVICE(82541EI_MOBILE), 156 EM_DEVICE(82541GI), 157 EM_DEVICE(82541GI_LF), 158 EM_DEVICE(82541GI_MOBILE), 159 160 EM_DEVICE(82542), 161 162 EM_DEVICE(82543GC_FIBER), 163 EM_DEVICE(82543GC_COPPER), 164 165 EM_DEVICE(82544EI_COPPER), 166 EM_DEVICE(82544EI_FIBER), 167 EM_DEVICE(82544GC_COPPER), 168 EM_DEVICE(82544GC_LOM), 169 170 EM_DEVICE(82545EM_COPPER), 171 EM_DEVICE(82545EM_FIBER), 172 EM_DEVICE(82545GM_COPPER), 173 EM_DEVICE(82545GM_FIBER), 174 EM_DEVICE(82545GM_SERDES), 175 176 EM_DEVICE(82546EB_COPPER), 177 EM_DEVICE(82546EB_FIBER), 178 EM_DEVICE(82546EB_QUAD_COPPER), 179 EM_DEVICE(82546GB_COPPER), 180 EM_DEVICE(82546GB_FIBER), 181 EM_DEVICE(82546GB_SERDES), 182 EM_DEVICE(82546GB_PCIE), 183 EM_DEVICE(82546GB_QUAD_COPPER), 184 EM_DEVICE(82546GB_QUAD_COPPER_KSP3), 185 186 EM_DEVICE(82547EI), 187 EM_DEVICE(82547EI_MOBILE), 188 EM_DEVICE(82547GI), 189 190 EM_EMX_DEVICE(82571EB_COPPER), 191 EM_EMX_DEVICE(82571EB_FIBER), 192 EM_EMX_DEVICE(82571EB_SERDES), 193 EM_EMX_DEVICE(82571EB_SERDES_DUAL), 194 EM_EMX_DEVICE(82571EB_SERDES_QUAD), 195 EM_EMX_DEVICE(82571EB_QUAD_COPPER), 196 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP), 197 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP), 198 EM_EMX_DEVICE(82571EB_QUAD_FIBER), 199 EM_EMX_DEVICE(82571PT_QUAD_COPPER), 200 201 EM_EMX_DEVICE(82572EI_COPPER), 202 EM_EMX_DEVICE(82572EI_FIBER), 203 EM_EMX_DEVICE(82572EI_SERDES), 204 EM_EMX_DEVICE(82572EI), 205 206 EM_EMX_DEVICE(82573E), 207 EM_EMX_DEVICE(82573E_IAMT), 208 EM_EMX_DEVICE(82573L), 209 210 EM_DEVICE(82583V), 211 212 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT), 213 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT), 214 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT), 215 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT), 216 217 EM_DEVICE(ICH8_IGP_M_AMT), 218 EM_DEVICE(ICH8_IGP_AMT), 219 EM_DEVICE(ICH8_IGP_C), 220 EM_DEVICE(ICH8_IFE), 221 EM_DEVICE(ICH8_IFE_GT), 222 EM_DEVICE(ICH8_IFE_G), 223 EM_DEVICE(ICH8_IGP_M), 224 EM_DEVICE(ICH8_82567V_3), 225 226 EM_DEVICE(ICH9_IGP_M_AMT), 227 EM_DEVICE(ICH9_IGP_AMT), 228 EM_DEVICE(ICH9_IGP_C), 229 EM_DEVICE(ICH9_IGP_M), 230 EM_DEVICE(ICH9_IGP_M_V), 231 EM_DEVICE(ICH9_IFE), 232 EM_DEVICE(ICH9_IFE_GT), 233 EM_DEVICE(ICH9_IFE_G), 234 EM_DEVICE(ICH9_BM), 235 236 EM_EMX_DEVICE(82574L), 237 EM_EMX_DEVICE(82574LA), 238 239 EM_DEVICE(ICH10_R_BM_LM), 240 EM_DEVICE(ICH10_R_BM_LF), 241 EM_DEVICE(ICH10_R_BM_V), 242 EM_DEVICE(ICH10_D_BM_LM), 243 EM_DEVICE(ICH10_D_BM_LF), 244 EM_DEVICE(ICH10_D_BM_V), 245 246 EM_DEVICE(PCH_M_HV_LM), 247 EM_DEVICE(PCH_M_HV_LC), 248 EM_DEVICE(PCH_D_HV_DM), 249 EM_DEVICE(PCH_D_HV_DC), 250 251 EM_DEVICE(PCH2_LV_LM), 252 EM_DEVICE(PCH2_LV_V), 253 254 /* required last entry */ 255 EM_DEVICE_NULL 256 }; 257 258 static int em_probe(device_t); 259 static int em_attach(device_t); 260 static int em_detach(device_t); 261 static int em_shutdown(device_t); 262 static int em_suspend(device_t); 263 static int em_resume(device_t); 264 265 static void em_init(void *); 266 static void em_stop(struct adapter *); 267 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 268 static void em_start(struct ifnet *); 269 #ifdef IFPOLL_ENABLE 270 static void em_npoll(struct ifnet *, struct ifpoll_info *); 271 static void em_npoll_compat(struct ifnet *, void *, int); 272 #endif 273 static void em_watchdog(struct ifnet *); 274 static void em_media_status(struct ifnet *, struct ifmediareq *); 275 static int em_media_change(struct ifnet *); 276 static void em_timer(void *); 277 278 static void em_intr(void *); 279 static void em_intr_mask(void *); 280 static void em_intr_body(struct adapter *, boolean_t); 281 static void em_rxeof(struct adapter *, int); 282 static void em_txeof(struct adapter *); 283 static void em_tx_collect(struct adapter *); 284 static void em_tx_purge(struct adapter *); 285 static void em_enable_intr(struct adapter *); 286 static void em_disable_intr(struct adapter *); 287 288 static int em_dma_malloc(struct adapter *, bus_size_t, 289 struct em_dma_alloc *); 290 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 291 static void em_init_tx_ring(struct adapter *); 292 static int em_init_rx_ring(struct adapter *); 293 static int em_create_tx_ring(struct adapter *); 294 static int em_create_rx_ring(struct adapter *); 295 static void em_destroy_tx_ring(struct adapter *, int); 296 static void em_destroy_rx_ring(struct adapter *, int); 297 static int em_newbuf(struct adapter *, int, int); 298 static int em_encap(struct adapter *, struct mbuf **, int *, int *); 299 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *, 300 struct mbuf *); 301 static int em_txcsum(struct adapter *, struct mbuf *, 302 uint32_t *, uint32_t *); 303 static int em_tso_pullup(struct adapter *, struct mbuf **); 304 static int em_tso_setup(struct adapter *, struct mbuf *, 305 uint32_t *, uint32_t *); 306 307 static int em_get_hw_info(struct adapter *); 308 static int em_is_valid_eaddr(const uint8_t *); 309 static int em_alloc_pci_res(struct adapter *); 310 static void em_free_pci_res(struct adapter *); 311 static int em_reset(struct adapter *); 312 static void em_setup_ifp(struct adapter *); 313 static void em_init_tx_unit(struct adapter *); 314 static void em_init_rx_unit(struct adapter *); 315 static void em_update_stats(struct adapter *); 316 static void em_set_promisc(struct adapter *); 317 static void em_disable_promisc(struct adapter *); 318 static void em_set_multi(struct adapter *); 319 static void em_update_link_status(struct adapter *); 320 static void em_smartspeed(struct adapter *); 321 static void em_set_itr(struct adapter *, uint32_t); 322 static void em_disable_aspm(struct adapter *); 323 324 /* Hardware workarounds */ 325 static int em_82547_fifo_workaround(struct adapter *, int); 326 static void em_82547_update_fifo_head(struct adapter *, int); 327 static int em_82547_tx_fifo_reset(struct adapter *); 328 static void em_82547_move_tail(void *); 329 static void em_82547_move_tail_serialized(struct adapter *); 330 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY); 331 332 static void em_print_debug_info(struct adapter *); 333 static void em_print_nvm_info(struct adapter *); 334 static void em_print_hw_stats(struct adapter *); 335 336 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 337 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 338 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 339 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 340 static void em_add_sysctl(struct adapter *adapter); 341 342 /* Management and WOL Support */ 343 static void em_get_mgmt(struct adapter *); 344 static void em_rel_mgmt(struct adapter *); 345 static void em_get_hw_control(struct adapter *); 346 static void em_rel_hw_control(struct adapter *); 347 static void em_enable_wol(device_t); 348 349 static device_method_t em_methods[] = { 350 /* Device interface */ 351 DEVMETHOD(device_probe, em_probe), 352 DEVMETHOD(device_attach, em_attach), 353 DEVMETHOD(device_detach, em_detach), 354 DEVMETHOD(device_shutdown, em_shutdown), 355 DEVMETHOD(device_suspend, em_suspend), 356 DEVMETHOD(device_resume, em_resume), 357 { 0, 0 } 358 }; 359 360 static driver_t em_driver = { 361 "em", 362 em_methods, 363 sizeof(struct adapter), 364 }; 365 366 static devclass_t em_devclass; 367 368 DECLARE_DUMMY_MODULE(if_em); 369 MODULE_DEPEND(em, ig_hal, 1, 1, 1); 370 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL); 371 372 /* 373 * Tunables 374 */ 375 static int em_int_throttle_ceil = EM_DEFAULT_ITR; 376 static int em_rxd = EM_DEFAULT_RXD; 377 static int em_txd = EM_DEFAULT_TXD; 378 static int em_smart_pwr_down = 0; 379 380 /* Controls whether promiscuous also shows bad packets */ 381 static int em_debug_sbp = FALSE; 382 383 static int em_82573_workaround = 1; 384 static int em_msi_enable = 1; 385 386 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil); 387 TUNABLE_INT("hw.em.rxd", &em_rxd); 388 TUNABLE_INT("hw.em.txd", &em_txd); 389 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 390 TUNABLE_INT("hw.em.sbp", &em_debug_sbp); 391 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround); 392 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable); 393 394 /* Global used in WOL setup with multiport cards */ 395 static int em_global_quad_port_a = 0; 396 397 /* Set this to one to display debug statistics */ 398 static int em_display_debug_stats = 0; 399 400 #if !defined(KTR_IF_EM) 401 #define KTR_IF_EM KTR_ALL 402 #endif 403 KTR_INFO_MASTER(if_em); 404 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin"); 405 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end"); 406 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet"); 407 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet"); 408 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean"); 409 #define logif(name) KTR_LOG(if_em_ ## name) 410 411 static int 412 em_probe(device_t dev) 413 { 414 const struct em_vendor_info *ent; 415 uint16_t vid, did; 416 417 vid = pci_get_vendor(dev); 418 did = pci_get_device(dev); 419 420 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) { 421 if (vid == ent->vendor_id && did == ent->device_id) { 422 device_set_desc(dev, ent->desc); 423 device_set_async_attach(dev, TRUE); 424 return (ent->ret); 425 } 426 } 427 return (ENXIO); 428 } 429 430 static int 431 em_attach(device_t dev) 432 { 433 struct adapter *adapter = device_get_softc(dev); 434 struct ifnet *ifp = &adapter->arpcom.ac_if; 435 int tsize, rsize; 436 int error = 0; 437 uint16_t eeprom_data, device_id, apme_mask; 438 driver_intr_t *intr_func; 439 440 adapter->dev = adapter->osdep.dev = dev; 441 442 callout_init_mp(&adapter->timer); 443 callout_init_mp(&adapter->tx_fifo_timer); 444 445 /* Determine hardware and mac info */ 446 error = em_get_hw_info(adapter); 447 if (error) { 448 device_printf(dev, "Identify hardware failed\n"); 449 goto fail; 450 } 451 452 /* Setup PCI resources */ 453 error = em_alloc_pci_res(adapter); 454 if (error) { 455 device_printf(dev, "Allocation of PCI resources failed\n"); 456 goto fail; 457 } 458 459 /* 460 * For ICH8 and family we need to map the flash memory, 461 * and this must happen after the MAC is identified. 462 */ 463 if (adapter->hw.mac.type == e1000_ich8lan || 464 adapter->hw.mac.type == e1000_ich9lan || 465 adapter->hw.mac.type == e1000_ich10lan || 466 adapter->hw.mac.type == e1000_pchlan || 467 adapter->hw.mac.type == e1000_pch2lan) { 468 adapter->flash_rid = EM_BAR_FLASH; 469 470 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 471 &adapter->flash_rid, RF_ACTIVE); 472 if (adapter->flash == NULL) { 473 device_printf(dev, "Mapping of Flash failed\n"); 474 error = ENXIO; 475 goto fail; 476 } 477 adapter->osdep.flash_bus_space_tag = 478 rman_get_bustag(adapter->flash); 479 adapter->osdep.flash_bus_space_handle = 480 rman_get_bushandle(adapter->flash); 481 482 /* 483 * This is used in the shared code 484 * XXX this goof is actually not used. 485 */ 486 adapter->hw.flash_address = (uint8_t *)adapter->flash; 487 } 488 489 switch (adapter->hw.mac.type) { 490 case e1000_82571: 491 case e1000_82572: 492 /* 493 * Pullup extra 4bytes into the first data segment, see: 494 * 82571/82572 specification update errata #7 495 * 496 * NOTE: 497 * 4bytes instead of 2bytes, which are mentioned in the 498 * errata, are pulled; mainly to keep rest of the data 499 * properly aligned. 500 */ 501 adapter->flags |= EM_FLAG_TSO_PULLEX; 502 /* FALL THROUGH */ 503 504 case e1000_82573: 505 case e1000_82574: 506 case e1000_80003es2lan: 507 adapter->flags |= EM_FLAG_TSO; 508 break; 509 510 default: 511 break; 512 } 513 514 /* Do Shared Code initialization */ 515 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 516 device_printf(dev, "Setup of Shared code failed\n"); 517 error = ENXIO; 518 goto fail; 519 } 520 521 e1000_get_bus_info(&adapter->hw); 522 523 /* 524 * Validate number of transmit and receive descriptors. It 525 * must not exceed hardware maximum, and must be multiple 526 * of E1000_DBA_ALIGN. 527 */ 528 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 || 529 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 530 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 531 em_txd < EM_MIN_TXD) { 532 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 533 EM_DEFAULT_TXD, em_txd); 534 adapter->num_tx_desc = EM_DEFAULT_TXD; 535 } else { 536 adapter->num_tx_desc = em_txd; 537 } 538 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 || 539 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 540 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 541 em_rxd < EM_MIN_RXD) { 542 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 543 EM_DEFAULT_RXD, em_rxd); 544 adapter->num_rx_desc = EM_DEFAULT_RXD; 545 } else { 546 adapter->num_rx_desc = em_rxd; 547 } 548 549 adapter->hw.mac.autoneg = DO_AUTO_NEG; 550 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 551 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 552 adapter->rx_buffer_len = MCLBYTES; 553 554 /* 555 * Interrupt throttle rate 556 */ 557 if (em_int_throttle_ceil == 0) { 558 adapter->int_throttle_ceil = 0; 559 } else { 560 int throttle = em_int_throttle_ceil; 561 562 if (throttle < 0) 563 throttle = EM_DEFAULT_ITR; 564 565 /* Recalculate the tunable value to get the exact frequency. */ 566 throttle = 1000000000 / 256 / throttle; 567 568 /* Upper 16bits of ITR is reserved and should be zero */ 569 if (throttle & 0xffff0000) 570 throttle = 1000000000 / 256 / EM_DEFAULT_ITR; 571 572 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 573 } 574 575 e1000_init_script_state_82541(&adapter->hw, TRUE); 576 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 577 578 /* Copper options */ 579 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 580 adapter->hw.phy.mdix = AUTO_ALL_MODES; 581 adapter->hw.phy.disable_polarity_correction = FALSE; 582 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 583 } 584 585 /* Set the frame limits assuming standard ethernet sized frames. */ 586 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 587 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN; 588 589 /* This controls when hardware reports transmit completion status. */ 590 adapter->hw.mac.report_tx_early = 1; 591 592 /* 593 * Create top level busdma tag 594 */ 595 error = bus_dma_tag_create(NULL, 1, 0, 596 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 597 NULL, NULL, 598 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 599 0, &adapter->parent_dtag); 600 if (error) { 601 device_printf(dev, "could not create top level DMA tag\n"); 602 goto fail; 603 } 604 605 /* 606 * Allocate Transmit Descriptor ring 607 */ 608 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 609 EM_DBA_ALIGN); 610 error = em_dma_malloc(adapter, tsize, &adapter->txdma); 611 if (error) { 612 device_printf(dev, "Unable to allocate tx_desc memory\n"); 613 goto fail; 614 } 615 adapter->tx_desc_base = adapter->txdma.dma_vaddr; 616 617 /* 618 * Allocate Receive Descriptor ring 619 */ 620 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 621 EM_DBA_ALIGN); 622 error = em_dma_malloc(adapter, rsize, &adapter->rxdma); 623 if (error) { 624 device_printf(dev, "Unable to allocate rx_desc memory\n"); 625 goto fail; 626 } 627 adapter->rx_desc_base = adapter->rxdma.dma_vaddr; 628 629 /* Allocate multicast array memory. */ 630 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES, 631 M_DEVBUF, M_WAITOK); 632 633 /* Indicate SOL/IDER usage */ 634 if (e1000_check_reset_block(&adapter->hw)) { 635 device_printf(dev, 636 "PHY reset is blocked due to SOL/IDER session.\n"); 637 } 638 639 /* 640 * Start from a known state, this is important in reading the 641 * nvm and mac from that. 642 */ 643 e1000_reset_hw(&adapter->hw); 644 645 /* Make sure we have a good EEPROM before we read from it */ 646 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 647 /* 648 * Some PCI-E parts fail the first check due to 649 * the link being in sleep state, call it again, 650 * if it fails a second time its a real issue. 651 */ 652 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 653 device_printf(dev, 654 "The EEPROM Checksum Is Not Valid\n"); 655 error = EIO; 656 goto fail; 657 } 658 } 659 660 /* Copy the permanent MAC address out of the EEPROM */ 661 if (e1000_read_mac_addr(&adapter->hw) < 0) { 662 device_printf(dev, "EEPROM read error while reading MAC" 663 " address\n"); 664 error = EIO; 665 goto fail; 666 } 667 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) { 668 device_printf(dev, "Invalid MAC address\n"); 669 error = EIO; 670 goto fail; 671 } 672 673 /* Allocate transmit descriptors and buffers */ 674 error = em_create_tx_ring(adapter); 675 if (error) { 676 device_printf(dev, "Could not setup transmit structures\n"); 677 goto fail; 678 } 679 680 /* Allocate receive descriptors and buffers */ 681 error = em_create_rx_ring(adapter); 682 if (error) { 683 device_printf(dev, "Could not setup receive structures\n"); 684 goto fail; 685 } 686 687 /* Manually turn off all interrupts */ 688 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 689 690 /* Determine if we have to control management hardware */ 691 if (e1000_enable_mng_pass_thru(&adapter->hw)) 692 adapter->flags |= EM_FLAG_HAS_MGMT; 693 694 /* 695 * Setup Wake-on-Lan 696 */ 697 apme_mask = EM_EEPROM_APME; 698 eeprom_data = 0; 699 switch (adapter->hw.mac.type) { 700 case e1000_82542: 701 case e1000_82543: 702 break; 703 704 case e1000_82573: 705 case e1000_82583: 706 adapter->flags |= EM_FLAG_HAS_AMT; 707 /* FALL THROUGH */ 708 709 case e1000_82546: 710 case e1000_82546_rev_3: 711 case e1000_82571: 712 case e1000_82572: 713 case e1000_80003es2lan: 714 if (adapter->hw.bus.func == 1) { 715 e1000_read_nvm(&adapter->hw, 716 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 717 } else { 718 e1000_read_nvm(&adapter->hw, 719 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 720 } 721 break; 722 723 case e1000_ich8lan: 724 case e1000_ich9lan: 725 case e1000_ich10lan: 726 case e1000_pchlan: 727 case e1000_pch2lan: 728 apme_mask = E1000_WUC_APME; 729 adapter->flags |= EM_FLAG_HAS_AMT; 730 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 731 break; 732 733 default: 734 e1000_read_nvm(&adapter->hw, 735 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 736 break; 737 } 738 if (eeprom_data & apme_mask) 739 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 740 741 /* 742 * We have the eeprom settings, now apply the special cases 743 * where the eeprom may be wrong or the board won't support 744 * wake on lan on a particular port 745 */ 746 device_id = pci_get_device(dev); 747 switch (device_id) { 748 case E1000_DEV_ID_82546GB_PCIE: 749 adapter->wol = 0; 750 break; 751 752 case E1000_DEV_ID_82546EB_FIBER: 753 case E1000_DEV_ID_82546GB_FIBER: 754 case E1000_DEV_ID_82571EB_FIBER: 755 /* 756 * Wake events only supported on port A for dual fiber 757 * regardless of eeprom setting 758 */ 759 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 760 E1000_STATUS_FUNC_1) 761 adapter->wol = 0; 762 break; 763 764 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 765 case E1000_DEV_ID_82571EB_QUAD_COPPER: 766 case E1000_DEV_ID_82571EB_QUAD_FIBER: 767 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 768 /* if quad port adapter, disable WoL on all but port A */ 769 if (em_global_quad_port_a != 0) 770 adapter->wol = 0; 771 /* Reset for multiple quad port adapters */ 772 if (++em_global_quad_port_a == 4) 773 em_global_quad_port_a = 0; 774 break; 775 } 776 777 /* XXX disable wol */ 778 adapter->wol = 0; 779 780 /* Setup OS specific network interface */ 781 em_setup_ifp(adapter); 782 783 /* Add sysctl tree, must after em_setup_ifp() */ 784 em_add_sysctl(adapter); 785 786 #ifdef IFPOLL_ENABLE 787 /* Polling setup */ 788 ifpoll_compat_setup(&adapter->npoll, 789 &adapter->sysctl_ctx, adapter->sysctl_tree, device_get_unit(dev), 790 ifp->if_serializer); 791 #endif 792 793 /* Reset the hardware */ 794 error = em_reset(adapter); 795 if (error) { 796 device_printf(dev, "Unable to reset the hardware\n"); 797 goto fail; 798 } 799 800 /* Initialize statistics */ 801 em_update_stats(adapter); 802 803 adapter->hw.mac.get_link_status = 1; 804 em_update_link_status(adapter); 805 806 /* Do we need workaround for 82544 PCI-X adapter? */ 807 if (adapter->hw.bus.type == e1000_bus_type_pcix && 808 adapter->hw.mac.type == e1000_82544) 809 adapter->pcix_82544 = TRUE; 810 else 811 adapter->pcix_82544 = FALSE; 812 813 if (adapter->pcix_82544) { 814 /* 815 * 82544 on PCI-X may split one TX segment 816 * into two TX descs, so we double its number 817 * of spare TX desc here. 818 */ 819 adapter->spare_tx_desc = 2 * EM_TX_SPARE; 820 } else { 821 adapter->spare_tx_desc = EM_TX_SPARE; 822 } 823 if (adapter->flags & EM_FLAG_TSO) 824 adapter->spare_tx_desc = EM_TX_SPARE_TSO; 825 adapter->tx_wreg_nsegs = 8; 826 827 /* 828 * Keep following relationship between spare_tx_desc, oact_tx_desc 829 * and tx_int_nsegs: 830 * (spare_tx_desc + EM_TX_RESERVED) <= 831 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs 832 */ 833 adapter->oact_tx_desc = adapter->num_tx_desc / 8; 834 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX) 835 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX; 836 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED) 837 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED; 838 839 adapter->tx_int_nsegs = adapter->num_tx_desc / 16; 840 if (adapter->tx_int_nsegs < adapter->oact_tx_desc) 841 adapter->tx_int_nsegs = adapter->oact_tx_desc; 842 843 /* Non-AMT based hardware can now take control from firmware */ 844 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 845 EM_FLAG_HAS_MGMT && adapter->hw.mac.type >= e1000_82571) 846 em_get_hw_control(adapter); 847 848 /* 849 * Missing Interrupt Following ICR read: 850 * 851 * 82571/82572 specification update errata #76 852 * 82573 specification update errata #31 853 * 82574 specification update errata #12 854 * 82583 specification update errata #4 855 */ 856 intr_func = em_intr; 857 if ((adapter->flags & EM_FLAG_SHARED_INTR) && 858 (adapter->hw.mac.type == e1000_82571 || 859 adapter->hw.mac.type == e1000_82572 || 860 adapter->hw.mac.type == e1000_82573 || 861 adapter->hw.mac.type == e1000_82574 || 862 adapter->hw.mac.type == e1000_82583)) 863 intr_func = em_intr_mask; 864 865 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE, 866 intr_func, adapter, &adapter->intr_tag, 867 ifp->if_serializer); 868 if (error) { 869 device_printf(dev, "Failed to register interrupt handler"); 870 ether_ifdetach(&adapter->arpcom.ac_if); 871 goto fail; 872 } 873 874 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 875 return (0); 876 fail: 877 em_detach(dev); 878 return (error); 879 } 880 881 static int 882 em_detach(device_t dev) 883 { 884 struct adapter *adapter = device_get_softc(dev); 885 886 if (device_is_attached(dev)) { 887 struct ifnet *ifp = &adapter->arpcom.ac_if; 888 889 lwkt_serialize_enter(ifp->if_serializer); 890 891 em_stop(adapter); 892 893 e1000_phy_hw_reset(&adapter->hw); 894 895 em_rel_mgmt(adapter); 896 em_rel_hw_control(adapter); 897 898 if (adapter->wol) { 899 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 900 E1000_WUC_PME_EN); 901 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 902 em_enable_wol(dev); 903 } 904 905 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag); 906 907 lwkt_serialize_exit(ifp->if_serializer); 908 909 ether_ifdetach(ifp); 910 } else if (adapter->memory != NULL) { 911 em_rel_hw_control(adapter); 912 } 913 bus_generic_detach(dev); 914 915 em_free_pci_res(adapter); 916 917 em_destroy_tx_ring(adapter, adapter->num_tx_desc); 918 em_destroy_rx_ring(adapter, adapter->num_rx_desc); 919 920 /* Free Transmit Descriptor ring */ 921 if (adapter->tx_desc_base) 922 em_dma_free(adapter, &adapter->txdma); 923 924 /* Free Receive Descriptor ring */ 925 if (adapter->rx_desc_base) 926 em_dma_free(adapter, &adapter->rxdma); 927 928 /* Free top level busdma tag */ 929 if (adapter->parent_dtag != NULL) 930 bus_dma_tag_destroy(adapter->parent_dtag); 931 932 /* Free sysctl tree */ 933 if (adapter->sysctl_tree != NULL) 934 sysctl_ctx_free(&adapter->sysctl_ctx); 935 936 if (adapter->mta != NULL) 937 kfree(adapter->mta, M_DEVBUF); 938 939 return (0); 940 } 941 942 static int 943 em_shutdown(device_t dev) 944 { 945 return em_suspend(dev); 946 } 947 948 static int 949 em_suspend(device_t dev) 950 { 951 struct adapter *adapter = device_get_softc(dev); 952 struct ifnet *ifp = &adapter->arpcom.ac_if; 953 954 lwkt_serialize_enter(ifp->if_serializer); 955 956 em_stop(adapter); 957 958 em_rel_mgmt(adapter); 959 em_rel_hw_control(adapter); 960 961 if (adapter->wol) { 962 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 963 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 964 em_enable_wol(dev); 965 } 966 967 lwkt_serialize_exit(ifp->if_serializer); 968 969 return bus_generic_suspend(dev); 970 } 971 972 static int 973 em_resume(device_t dev) 974 { 975 struct adapter *adapter = device_get_softc(dev); 976 struct ifnet *ifp = &adapter->arpcom.ac_if; 977 978 lwkt_serialize_enter(ifp->if_serializer); 979 980 em_init(adapter); 981 em_get_mgmt(adapter); 982 if_devstart(ifp); 983 984 lwkt_serialize_exit(ifp->if_serializer); 985 986 return bus_generic_resume(dev); 987 } 988 989 static void 990 em_start(struct ifnet *ifp) 991 { 992 struct adapter *adapter = ifp->if_softc; 993 struct mbuf *m_head; 994 int idx = -1, nsegs = 0; 995 996 ASSERT_SERIALIZED(ifp->if_serializer); 997 998 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 999 return; 1000 1001 if (!adapter->link_active) { 1002 ifq_purge(&ifp->if_snd); 1003 return; 1004 } 1005 1006 while (!ifq_is_empty(&ifp->if_snd)) { 1007 /* Now do we at least have a minimal? */ 1008 if (EM_IS_OACTIVE(adapter)) { 1009 em_tx_collect(adapter); 1010 if (EM_IS_OACTIVE(adapter)) { 1011 ifq_set_oactive(&ifp->if_snd); 1012 adapter->no_tx_desc_avail1++; 1013 break; 1014 } 1015 } 1016 1017 logif(pkt_txqueue); 1018 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1019 if (m_head == NULL) 1020 break; 1021 1022 if (em_encap(adapter, &m_head, &nsegs, &idx)) { 1023 ifp->if_oerrors++; 1024 em_tx_collect(adapter); 1025 continue; 1026 } 1027 1028 if (nsegs >= adapter->tx_wreg_nsegs && idx >= 0) { 1029 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1030 nsegs = 0; 1031 idx = -1; 1032 } 1033 1034 /* Send a copy of the frame to the BPF listener */ 1035 ETHER_BPF_MTAP(ifp, m_head); 1036 1037 /* Set timeout in case hardware has problems transmitting. */ 1038 ifp->if_timer = EM_TX_TIMEOUT; 1039 } 1040 if (idx >= 0) 1041 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1042 } 1043 1044 static int 1045 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1046 { 1047 struct adapter *adapter = ifp->if_softc; 1048 struct ifreq *ifr = (struct ifreq *)data; 1049 uint16_t eeprom_data = 0; 1050 int max_frame_size, mask, reinit; 1051 int error = 0; 1052 1053 ASSERT_SERIALIZED(ifp->if_serializer); 1054 1055 switch (command) { 1056 case SIOCSIFMTU: 1057 switch (adapter->hw.mac.type) { 1058 case e1000_82573: 1059 /* 1060 * 82573 only supports jumbo frames 1061 * if ASPM is disabled. 1062 */ 1063 e1000_read_nvm(&adapter->hw, 1064 NVM_INIT_3GIO_3, 1, &eeprom_data); 1065 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1066 max_frame_size = ETHER_MAX_LEN; 1067 break; 1068 } 1069 /* FALL THROUGH */ 1070 1071 /* Limit Jumbo Frame size */ 1072 case e1000_82571: 1073 case e1000_82572: 1074 case e1000_ich9lan: 1075 case e1000_ich10lan: 1076 case e1000_pch2lan: 1077 case e1000_82574: 1078 case e1000_82583: 1079 case e1000_80003es2lan: 1080 max_frame_size = 9234; 1081 break; 1082 1083 case e1000_pchlan: 1084 max_frame_size = 4096; 1085 break; 1086 1087 /* Adapters that do not support jumbo frames */ 1088 case e1000_82542: 1089 case e1000_ich8lan: 1090 max_frame_size = ETHER_MAX_LEN; 1091 break; 1092 1093 default: 1094 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1095 break; 1096 } 1097 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1098 ETHER_CRC_LEN) { 1099 error = EINVAL; 1100 break; 1101 } 1102 1103 ifp->if_mtu = ifr->ifr_mtu; 1104 adapter->max_frame_size = 1105 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1106 1107 if (ifp->if_flags & IFF_RUNNING) 1108 em_init(adapter); 1109 break; 1110 1111 case SIOCSIFFLAGS: 1112 if (ifp->if_flags & IFF_UP) { 1113 if ((ifp->if_flags & IFF_RUNNING)) { 1114 if ((ifp->if_flags ^ adapter->if_flags) & 1115 (IFF_PROMISC | IFF_ALLMULTI)) { 1116 em_disable_promisc(adapter); 1117 em_set_promisc(adapter); 1118 } 1119 } else { 1120 em_init(adapter); 1121 } 1122 } else if (ifp->if_flags & IFF_RUNNING) { 1123 em_stop(adapter); 1124 } 1125 adapter->if_flags = ifp->if_flags; 1126 break; 1127 1128 case SIOCADDMULTI: 1129 case SIOCDELMULTI: 1130 if (ifp->if_flags & IFF_RUNNING) { 1131 em_disable_intr(adapter); 1132 em_set_multi(adapter); 1133 if (adapter->hw.mac.type == e1000_82542 && 1134 adapter->hw.revision_id == E1000_REVISION_2) 1135 em_init_rx_unit(adapter); 1136 #ifdef IFPOLL_ENABLE 1137 if (!(ifp->if_flags & IFF_NPOLLING)) 1138 #endif 1139 em_enable_intr(adapter); 1140 } 1141 break; 1142 1143 case SIOCSIFMEDIA: 1144 /* Check SOL/IDER usage */ 1145 if (e1000_check_reset_block(&adapter->hw)) { 1146 device_printf(adapter->dev, "Media change is" 1147 " blocked due to SOL/IDER session.\n"); 1148 break; 1149 } 1150 /* FALL THROUGH */ 1151 1152 case SIOCGIFMEDIA: 1153 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1154 break; 1155 1156 case SIOCSIFCAP: 1157 reinit = 0; 1158 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1159 if (mask & IFCAP_RXCSUM) { 1160 ifp->if_capenable ^= IFCAP_RXCSUM; 1161 reinit = 1; 1162 } 1163 if (mask & IFCAP_TXCSUM) { 1164 ifp->if_capenable ^= IFCAP_TXCSUM; 1165 if (ifp->if_capenable & IFCAP_TXCSUM) 1166 ifp->if_hwassist |= EM_CSUM_FEATURES; 1167 else 1168 ifp->if_hwassist &= ~EM_CSUM_FEATURES; 1169 } 1170 if (mask & IFCAP_TSO) { 1171 ifp->if_capenable ^= IFCAP_TSO; 1172 if (ifp->if_capenable & IFCAP_TSO) 1173 ifp->if_hwassist |= CSUM_TSO; 1174 else 1175 ifp->if_hwassist &= ~CSUM_TSO; 1176 } 1177 if (mask & IFCAP_VLAN_HWTAGGING) { 1178 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1179 reinit = 1; 1180 } 1181 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1182 em_init(adapter); 1183 break; 1184 1185 default: 1186 error = ether_ioctl(ifp, command, data); 1187 break; 1188 } 1189 return (error); 1190 } 1191 1192 static void 1193 em_watchdog(struct ifnet *ifp) 1194 { 1195 struct adapter *adapter = ifp->if_softc; 1196 1197 ASSERT_SERIALIZED(ifp->if_serializer); 1198 1199 /* 1200 * The timer is set to 5 every time start queues a packet. 1201 * Then txeof keeps resetting it as long as it cleans at 1202 * least one descriptor. 1203 * Finally, anytime all descriptors are clean the timer is 1204 * set to 0. 1205 */ 1206 1207 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1208 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) { 1209 /* 1210 * If we reach here, all TX jobs are completed and 1211 * the TX engine should have been idled for some time. 1212 * We don't need to call if_devstart() here. 1213 */ 1214 ifq_clr_oactive(&ifp->if_snd); 1215 ifp->if_timer = 0; 1216 return; 1217 } 1218 1219 /* 1220 * If we are in this routine because of pause frames, then 1221 * don't reset the hardware. 1222 */ 1223 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1224 E1000_STATUS_TXOFF) { 1225 ifp->if_timer = EM_TX_TIMEOUT; 1226 return; 1227 } 1228 1229 if (e1000_check_for_link(&adapter->hw) == 0) 1230 if_printf(ifp, "watchdog timeout -- resetting\n"); 1231 1232 ifp->if_oerrors++; 1233 adapter->watchdog_events++; 1234 1235 em_init(adapter); 1236 1237 if (!ifq_is_empty(&ifp->if_snd)) 1238 if_devstart(ifp); 1239 } 1240 1241 static void 1242 em_init(void *xsc) 1243 { 1244 struct adapter *adapter = xsc; 1245 struct ifnet *ifp = &adapter->arpcom.ac_if; 1246 device_t dev = adapter->dev; 1247 uint32_t pba; 1248 1249 ASSERT_SERIALIZED(ifp->if_serializer); 1250 1251 em_stop(adapter); 1252 1253 /* 1254 * Packet Buffer Allocation (PBA) 1255 * Writing PBA sets the receive portion of the buffer 1256 * the remainder is used for the transmit buffer. 1257 * 1258 * Devices before the 82547 had a Packet Buffer of 64K. 1259 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 1260 * After the 82547 the buffer was reduced to 40K. 1261 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 1262 * Note: default does not leave enough room for Jumbo Frame >10k. 1263 */ 1264 switch (adapter->hw.mac.type) { 1265 case e1000_82547: 1266 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 1267 if (adapter->max_frame_size > 8192) 1268 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1269 else 1270 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1271 adapter->tx_fifo_head = 0; 1272 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 1273 adapter->tx_fifo_size = 1274 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 1275 break; 1276 1277 /* Total Packet Buffer on these is 48K */ 1278 case e1000_82571: 1279 case e1000_82572: 1280 case e1000_80003es2lan: 1281 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1282 break; 1283 1284 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1285 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1286 break; 1287 1288 case e1000_82574: 1289 case e1000_82583: 1290 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1291 break; 1292 1293 case e1000_ich8lan: 1294 pba = E1000_PBA_8K; 1295 break; 1296 1297 case e1000_ich9lan: 1298 case e1000_ich10lan: 1299 #define E1000_PBA_10K 0x000A 1300 pba = E1000_PBA_10K; 1301 break; 1302 1303 case e1000_pchlan: 1304 case e1000_pch2lan: 1305 pba = E1000_PBA_26K; 1306 break; 1307 1308 default: 1309 /* Devices before 82547 had a Packet Buffer of 64K. */ 1310 if (adapter->max_frame_size > 8192) 1311 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1312 else 1313 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1314 } 1315 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 1316 1317 /* Get the latest mac address, User can use a LAA */ 1318 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN); 1319 1320 /* Put the address into the Receive Address Array */ 1321 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1322 1323 /* 1324 * With the 82571 adapter, RAR[0] may be overwritten 1325 * when the other port is reset, we make a duplicate 1326 * in RAR[14] for that eventuality, this assures 1327 * the interface continues to function. 1328 */ 1329 if (adapter->hw.mac.type == e1000_82571) { 1330 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1331 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1332 E1000_RAR_ENTRIES - 1); 1333 } 1334 1335 /* Reset the hardware */ 1336 if (em_reset(adapter)) { 1337 device_printf(dev, "Unable to reset the hardware\n"); 1338 /* XXX em_stop()? */ 1339 return; 1340 } 1341 em_update_link_status(adapter); 1342 1343 /* Setup VLAN support, basic and offload if available */ 1344 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1345 1346 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1347 uint32_t ctrl; 1348 1349 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1350 ctrl |= E1000_CTRL_VME; 1351 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1352 } 1353 1354 /* Configure for OS presence */ 1355 em_get_mgmt(adapter); 1356 1357 /* Prepare transmit descriptors and buffers */ 1358 em_init_tx_ring(adapter); 1359 em_init_tx_unit(adapter); 1360 1361 /* Setup Multicast table */ 1362 em_set_multi(adapter); 1363 1364 /* Prepare receive descriptors and buffers */ 1365 if (em_init_rx_ring(adapter)) { 1366 device_printf(dev, "Could not setup receive structures\n"); 1367 em_stop(adapter); 1368 return; 1369 } 1370 em_init_rx_unit(adapter); 1371 1372 /* Don't lose promiscuous settings */ 1373 em_set_promisc(adapter); 1374 1375 ifp->if_flags |= IFF_RUNNING; 1376 ifq_clr_oactive(&ifp->if_snd); 1377 1378 callout_reset(&adapter->timer, hz, em_timer, adapter); 1379 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1380 1381 /* MSI/X configuration for 82574 */ 1382 if (adapter->hw.mac.type == e1000_82574) { 1383 int tmp; 1384 1385 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1386 tmp |= E1000_CTRL_EXT_PBA_CLR; 1387 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1388 /* 1389 * XXX MSIX 1390 * Set the IVAR - interrupt vector routing. 1391 * Each nibble represents a vector, high bit 1392 * is enable, other 3 bits are the MSIX table 1393 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1394 * Link (other) to 2, hence the magic number. 1395 */ 1396 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); 1397 } 1398 1399 #ifdef IFPOLL_ENABLE 1400 /* 1401 * Only enable interrupts if we are not polling, make sure 1402 * they are off otherwise. 1403 */ 1404 if (ifp->if_flags & IFF_NPOLLING) 1405 em_disable_intr(adapter); 1406 else 1407 #endif /* IFPOLL_ENABLE */ 1408 em_enable_intr(adapter); 1409 1410 /* AMT based hardware can now take control from firmware */ 1411 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 1412 (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT) && 1413 adapter->hw.mac.type >= e1000_82571) 1414 em_get_hw_control(adapter); 1415 1416 /* Don't reset the phy next time init gets called */ 1417 adapter->hw.phy.reset_disable = TRUE; 1418 } 1419 1420 #ifdef IFPOLL_ENABLE 1421 1422 static void 1423 em_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 1424 { 1425 struct adapter *adapter = ifp->if_softc; 1426 1427 ASSERT_SERIALIZED(ifp->if_serializer); 1428 1429 if (adapter->npoll.ifpc_stcount-- == 0) { 1430 uint32_t reg_icr; 1431 1432 adapter->npoll.ifpc_stcount = adapter->npoll.ifpc_stfrac; 1433 1434 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1435 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1436 callout_stop(&adapter->timer); 1437 adapter->hw.mac.get_link_status = 1; 1438 em_update_link_status(adapter); 1439 callout_reset(&adapter->timer, hz, em_timer, adapter); 1440 } 1441 } 1442 1443 em_rxeof(adapter, count); 1444 em_txeof(adapter); 1445 1446 if (!ifq_is_empty(&ifp->if_snd)) 1447 if_devstart(ifp); 1448 } 1449 1450 static void 1451 em_npoll(struct ifnet *ifp, struct ifpoll_info *info) 1452 { 1453 struct adapter *adapter = ifp->if_softc; 1454 1455 ASSERT_SERIALIZED(ifp->if_serializer); 1456 1457 if (info != NULL) { 1458 int cpuid = adapter->npoll.ifpc_cpuid; 1459 1460 info->ifpi_rx[cpuid].poll_func = em_npoll_compat; 1461 info->ifpi_rx[cpuid].arg = NULL; 1462 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 1463 1464 if (ifp->if_flags & IFF_RUNNING) 1465 em_disable_intr(adapter); 1466 ifq_set_cpuid(&ifp->if_snd, cpuid); 1467 } else { 1468 if (ifp->if_flags & IFF_RUNNING) 1469 em_enable_intr(adapter); 1470 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 1471 } 1472 } 1473 1474 #endif /* IFPOLL_ENABLE */ 1475 1476 static void 1477 em_intr(void *xsc) 1478 { 1479 em_intr_body(xsc, TRUE); 1480 } 1481 1482 static void 1483 em_intr_body(struct adapter *adapter, boolean_t chk_asserted) 1484 { 1485 struct ifnet *ifp = &adapter->arpcom.ac_if; 1486 uint32_t reg_icr; 1487 1488 logif(intr_beg); 1489 ASSERT_SERIALIZED(ifp->if_serializer); 1490 1491 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1492 1493 if (chk_asserted && 1494 ((adapter->hw.mac.type >= e1000_82571 && 1495 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1496 reg_icr == 0)) { 1497 logif(intr_end); 1498 return; 1499 } 1500 1501 /* 1502 * XXX: some laptops trigger several spurious interrupts 1503 * on em(4) when in the resume cycle. The ICR register 1504 * reports all-ones value in this case. Processing such 1505 * interrupts would lead to a freeze. I don't know why. 1506 */ 1507 if (reg_icr == 0xffffffff) { 1508 logif(intr_end); 1509 return; 1510 } 1511 1512 if (ifp->if_flags & IFF_RUNNING) { 1513 if (reg_icr & 1514 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) 1515 em_rxeof(adapter, -1); 1516 if (reg_icr & E1000_ICR_TXDW) { 1517 em_txeof(adapter); 1518 if (!ifq_is_empty(&ifp->if_snd)) 1519 if_devstart(ifp); 1520 } 1521 } 1522 1523 /* Link status change */ 1524 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1525 callout_stop(&adapter->timer); 1526 adapter->hw.mac.get_link_status = 1; 1527 em_update_link_status(adapter); 1528 1529 /* Deal with TX cruft when link lost */ 1530 em_tx_purge(adapter); 1531 1532 callout_reset(&adapter->timer, hz, em_timer, adapter); 1533 } 1534 1535 if (reg_icr & E1000_ICR_RXO) 1536 adapter->rx_overruns++; 1537 1538 logif(intr_end); 1539 } 1540 1541 static void 1542 em_intr_mask(void *xsc) 1543 { 1544 struct adapter *adapter = xsc; 1545 1546 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 1547 /* 1548 * NOTE: 1549 * ICR.INT_ASSERTED bit will never be set if IMS is 0, 1550 * so don't check it. 1551 */ 1552 em_intr_body(adapter, FALSE); 1553 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK); 1554 } 1555 1556 static void 1557 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1558 { 1559 struct adapter *adapter = ifp->if_softc; 1560 u_char fiber_type = IFM_1000_SX; 1561 1562 ASSERT_SERIALIZED(ifp->if_serializer); 1563 1564 em_update_link_status(adapter); 1565 1566 ifmr->ifm_status = IFM_AVALID; 1567 ifmr->ifm_active = IFM_ETHER; 1568 1569 if (!adapter->link_active) 1570 return; 1571 1572 ifmr->ifm_status |= IFM_ACTIVE; 1573 1574 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 1575 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 1576 if (adapter->hw.mac.type == e1000_82545) 1577 fiber_type = IFM_1000_LX; 1578 ifmr->ifm_active |= fiber_type | IFM_FDX; 1579 } else { 1580 switch (adapter->link_speed) { 1581 case 10: 1582 ifmr->ifm_active |= IFM_10_T; 1583 break; 1584 case 100: 1585 ifmr->ifm_active |= IFM_100_TX; 1586 break; 1587 1588 case 1000: 1589 ifmr->ifm_active |= IFM_1000_T; 1590 break; 1591 } 1592 if (adapter->link_duplex == FULL_DUPLEX) 1593 ifmr->ifm_active |= IFM_FDX; 1594 else 1595 ifmr->ifm_active |= IFM_HDX; 1596 } 1597 } 1598 1599 static int 1600 em_media_change(struct ifnet *ifp) 1601 { 1602 struct adapter *adapter = ifp->if_softc; 1603 struct ifmedia *ifm = &adapter->media; 1604 1605 ASSERT_SERIALIZED(ifp->if_serializer); 1606 1607 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1608 return (EINVAL); 1609 1610 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1611 case IFM_AUTO: 1612 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1613 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1614 break; 1615 1616 case IFM_1000_LX: 1617 case IFM_1000_SX: 1618 case IFM_1000_T: 1619 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1620 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1621 break; 1622 1623 case IFM_100_TX: 1624 adapter->hw.mac.autoneg = FALSE; 1625 adapter->hw.phy.autoneg_advertised = 0; 1626 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1627 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1628 else 1629 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1630 break; 1631 1632 case IFM_10_T: 1633 adapter->hw.mac.autoneg = FALSE; 1634 adapter->hw.phy.autoneg_advertised = 0; 1635 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1636 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1637 else 1638 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1639 break; 1640 1641 default: 1642 if_printf(ifp, "Unsupported media type\n"); 1643 break; 1644 } 1645 1646 /* 1647 * As the speed/duplex settings my have changed we need to 1648 * reset the PHY. 1649 */ 1650 adapter->hw.phy.reset_disable = FALSE; 1651 1652 em_init(adapter); 1653 1654 return (0); 1655 } 1656 1657 static int 1658 em_encap(struct adapter *adapter, struct mbuf **m_headp, 1659 int *segs_used, int *idx) 1660 { 1661 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1662 bus_dmamap_t map; 1663 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1664 struct e1000_tx_desc *ctxd = NULL; 1665 struct mbuf *m_head = *m_headp; 1666 uint32_t txd_upper, txd_lower, txd_used, cmd = 0; 1667 int maxsegs, nsegs, i, j, first, last = 0, error; 1668 1669 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1670 error = em_tso_pullup(adapter, m_headp); 1671 if (error) 1672 return error; 1673 m_head = *m_headp; 1674 } 1675 1676 txd_upper = txd_lower = 0; 1677 txd_used = 0; 1678 1679 /* 1680 * Capture the first descriptor index, this descriptor 1681 * will have the index of the EOP which is the only one 1682 * that now gets a DONE bit writeback. 1683 */ 1684 first = adapter->next_avail_tx_desc; 1685 tx_buffer = &adapter->tx_buffer_area[first]; 1686 tx_buffer_mapped = tx_buffer; 1687 map = tx_buffer->map; 1688 1689 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED; 1690 KASSERT(maxsegs >= adapter->spare_tx_desc, 1691 ("not enough spare TX desc")); 1692 if (adapter->pcix_82544) { 1693 /* Half it; see the comment in em_attach() */ 1694 maxsegs >>= 1; 1695 } 1696 if (maxsegs > EM_MAX_SCATTER) 1697 maxsegs = EM_MAX_SCATTER; 1698 1699 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp, 1700 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1701 if (error) { 1702 if (error == ENOBUFS) 1703 adapter->mbuf_alloc_failed++; 1704 else 1705 adapter->no_tx_dma_setup++; 1706 1707 m_freem(*m_headp); 1708 *m_headp = NULL; 1709 return error; 1710 } 1711 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1712 1713 m_head = *m_headp; 1714 adapter->tx_nsegs += nsegs; 1715 *segs_used += nsegs; 1716 1717 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1718 /* TSO will consume one TX desc */ 1719 i = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower); 1720 adapter->tx_nsegs += i; 1721 *segs_used += i; 1722 } else if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) { 1723 /* TX csum offloading will consume one TX desc */ 1724 i = em_txcsum(adapter, m_head, &txd_upper, &txd_lower); 1725 adapter->tx_nsegs += i; 1726 *segs_used += i; 1727 } 1728 i = adapter->next_avail_tx_desc; 1729 1730 /* Set up our transmit descriptors */ 1731 for (j = 0; j < nsegs; j++) { 1732 /* If adapter is 82544 and on PCIX bus */ 1733 if(adapter->pcix_82544) { 1734 DESC_ARRAY desc_array; 1735 uint32_t array_elements, counter; 1736 1737 /* 1738 * Check the Address and Length combination and 1739 * split the data accordingly 1740 */ 1741 array_elements = em_82544_fill_desc(segs[j].ds_addr, 1742 segs[j].ds_len, &desc_array); 1743 for (counter = 0; counter < array_elements; counter++) { 1744 KKASSERT(txd_used < adapter->num_tx_desc_avail); 1745 1746 tx_buffer = &adapter->tx_buffer_area[i]; 1747 ctxd = &adapter->tx_desc_base[i]; 1748 1749 ctxd->buffer_addr = htole64( 1750 desc_array.descriptor[counter].address); 1751 ctxd->lower.data = htole32( 1752 E1000_TXD_CMD_IFCS | txd_lower | 1753 desc_array.descriptor[counter].length); 1754 ctxd->upper.data = htole32(txd_upper); 1755 1756 last = i; 1757 if (++i == adapter->num_tx_desc) 1758 i = 0; 1759 1760 txd_used++; 1761 } 1762 } else { 1763 tx_buffer = &adapter->tx_buffer_area[i]; 1764 ctxd = &adapter->tx_desc_base[i]; 1765 1766 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1767 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1768 txd_lower | segs[j].ds_len); 1769 ctxd->upper.data = htole32(txd_upper); 1770 1771 last = i; 1772 if (++i == adapter->num_tx_desc) 1773 i = 0; 1774 } 1775 } 1776 1777 adapter->next_avail_tx_desc = i; 1778 if (adapter->pcix_82544) { 1779 KKASSERT(adapter->num_tx_desc_avail > txd_used); 1780 adapter->num_tx_desc_avail -= txd_used; 1781 } else { 1782 KKASSERT(adapter->num_tx_desc_avail > nsegs); 1783 adapter->num_tx_desc_avail -= nsegs; 1784 } 1785 1786 /* Handle VLAN tag */ 1787 if (m_head->m_flags & M_VLANTAG) { 1788 /* Set the vlan id. */ 1789 ctxd->upper.fields.special = 1790 htole16(m_head->m_pkthdr.ether_vlantag); 1791 1792 /* Tell hardware to add tag */ 1793 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1794 } 1795 1796 tx_buffer->m_head = m_head; 1797 tx_buffer_mapped->map = tx_buffer->map; 1798 tx_buffer->map = map; 1799 1800 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) { 1801 adapter->tx_nsegs = 0; 1802 1803 /* 1804 * Report Status (RS) is turned on 1805 * every tx_int_nsegs descriptors. 1806 */ 1807 cmd = E1000_TXD_CMD_RS; 1808 1809 /* 1810 * Keep track of the descriptor, which will 1811 * be written back by hardware. 1812 */ 1813 adapter->tx_dd[adapter->tx_dd_tail] = last; 1814 EM_INC_TXDD_IDX(adapter->tx_dd_tail); 1815 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head); 1816 } 1817 1818 /* 1819 * Last Descriptor of Packet needs End Of Packet (EOP) 1820 */ 1821 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1822 1823 if (adapter->hw.mac.type == e1000_82547) { 1824 /* 1825 * Advance the Transmit Descriptor Tail (TDT), this tells the 1826 * E1000 that this frame is available to transmit. 1827 */ 1828 if (adapter->link_duplex == HALF_DUPLEX) { 1829 em_82547_move_tail_serialized(adapter); 1830 } else { 1831 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 1832 em_82547_update_fifo_head(adapter, 1833 m_head->m_pkthdr.len); 1834 } 1835 } else { 1836 /* 1837 * Defer TDT updating, until enough descriptors are setup 1838 */ 1839 *idx = i; 1840 } 1841 return (0); 1842 } 1843 1844 /* 1845 * 82547 workaround to avoid controller hang in half-duplex environment. 1846 * The workaround is to avoid queuing a large packet that would span 1847 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1848 * in this case. We do that only when FIFO is quiescent. 1849 */ 1850 static void 1851 em_82547_move_tail_serialized(struct adapter *adapter) 1852 { 1853 struct e1000_tx_desc *tx_desc; 1854 uint16_t hw_tdt, sw_tdt, length = 0; 1855 bool eop = 0; 1856 1857 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer); 1858 1859 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 1860 sw_tdt = adapter->next_avail_tx_desc; 1861 1862 while (hw_tdt != sw_tdt) { 1863 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1864 length += tx_desc->lower.flags.length; 1865 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1866 if (++hw_tdt == adapter->num_tx_desc) 1867 hw_tdt = 0; 1868 1869 if (eop) { 1870 if (em_82547_fifo_workaround(adapter, length)) { 1871 adapter->tx_fifo_wrk_cnt++; 1872 callout_reset(&adapter->tx_fifo_timer, 1, 1873 em_82547_move_tail, adapter); 1874 break; 1875 } 1876 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 1877 em_82547_update_fifo_head(adapter, length); 1878 length = 0; 1879 } 1880 } 1881 } 1882 1883 static void 1884 em_82547_move_tail(void *xsc) 1885 { 1886 struct adapter *adapter = xsc; 1887 struct ifnet *ifp = &adapter->arpcom.ac_if; 1888 1889 lwkt_serialize_enter(ifp->if_serializer); 1890 em_82547_move_tail_serialized(adapter); 1891 lwkt_serialize_exit(ifp->if_serializer); 1892 } 1893 1894 static int 1895 em_82547_fifo_workaround(struct adapter *adapter, int len) 1896 { 1897 int fifo_space, fifo_pkt_len; 1898 1899 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1900 1901 if (adapter->link_duplex == HALF_DUPLEX) { 1902 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 1903 1904 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1905 if (em_82547_tx_fifo_reset(adapter)) 1906 return (0); 1907 else 1908 return (1); 1909 } 1910 } 1911 return (0); 1912 } 1913 1914 static void 1915 em_82547_update_fifo_head(struct adapter *adapter, int len) 1916 { 1917 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1918 1919 /* tx_fifo_head is always 16 byte aligned */ 1920 adapter->tx_fifo_head += fifo_pkt_len; 1921 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) 1922 adapter->tx_fifo_head -= adapter->tx_fifo_size; 1923 } 1924 1925 static int 1926 em_82547_tx_fifo_reset(struct adapter *adapter) 1927 { 1928 uint32_t tctl; 1929 1930 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1931 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 1932 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 1933 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 1934 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 1935 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 1936 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 1937 /* Disable TX unit */ 1938 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 1939 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 1940 tctl & ~E1000_TCTL_EN); 1941 1942 /* Reset FIFO pointers */ 1943 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 1944 adapter->tx_head_addr); 1945 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 1946 adapter->tx_head_addr); 1947 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 1948 adapter->tx_head_addr); 1949 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 1950 adapter->tx_head_addr); 1951 1952 /* Re-enable TX unit */ 1953 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 1954 E1000_WRITE_FLUSH(&adapter->hw); 1955 1956 adapter->tx_fifo_head = 0; 1957 adapter->tx_fifo_reset_cnt++; 1958 1959 return (TRUE); 1960 } else { 1961 return (FALSE); 1962 } 1963 } 1964 1965 static void 1966 em_set_promisc(struct adapter *adapter) 1967 { 1968 struct ifnet *ifp = &adapter->arpcom.ac_if; 1969 uint32_t reg_rctl; 1970 1971 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1972 1973 if (ifp->if_flags & IFF_PROMISC) { 1974 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1975 /* Turn this on if you want to see bad packets */ 1976 if (em_debug_sbp) 1977 reg_rctl |= E1000_RCTL_SBP; 1978 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1979 } else if (ifp->if_flags & IFF_ALLMULTI) { 1980 reg_rctl |= E1000_RCTL_MPE; 1981 reg_rctl &= ~E1000_RCTL_UPE; 1982 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1983 } 1984 } 1985 1986 static void 1987 em_disable_promisc(struct adapter *adapter) 1988 { 1989 uint32_t reg_rctl; 1990 1991 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1992 1993 reg_rctl &= ~E1000_RCTL_UPE; 1994 reg_rctl &= ~E1000_RCTL_MPE; 1995 reg_rctl &= ~E1000_RCTL_SBP; 1996 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1997 } 1998 1999 static void 2000 em_set_multi(struct adapter *adapter) 2001 { 2002 struct ifnet *ifp = &adapter->arpcom.ac_if; 2003 struct ifmultiaddr *ifma; 2004 uint32_t reg_rctl = 0; 2005 uint8_t *mta; 2006 int mcnt = 0; 2007 2008 mta = adapter->mta; 2009 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 2010 2011 if (adapter->hw.mac.type == e1000_82542 && 2012 adapter->hw.revision_id == E1000_REVISION_2) { 2013 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2014 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2015 e1000_pci_clear_mwi(&adapter->hw); 2016 reg_rctl |= E1000_RCTL_RST; 2017 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2018 msec_delay(5); 2019 } 2020 2021 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2022 if (ifma->ifma_addr->sa_family != AF_LINK) 2023 continue; 2024 2025 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 2026 break; 2027 2028 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2029 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 2030 mcnt++; 2031 } 2032 2033 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 2034 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2035 reg_rctl |= E1000_RCTL_MPE; 2036 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2037 } else { 2038 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 2039 } 2040 2041 if (adapter->hw.mac.type == e1000_82542 && 2042 adapter->hw.revision_id == E1000_REVISION_2) { 2043 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2044 reg_rctl &= ~E1000_RCTL_RST; 2045 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2046 msec_delay(5); 2047 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2048 e1000_pci_set_mwi(&adapter->hw); 2049 } 2050 } 2051 2052 /* 2053 * This routine checks for link status and updates statistics. 2054 */ 2055 static void 2056 em_timer(void *xsc) 2057 { 2058 struct adapter *adapter = xsc; 2059 struct ifnet *ifp = &adapter->arpcom.ac_if; 2060 2061 lwkt_serialize_enter(ifp->if_serializer); 2062 2063 em_update_link_status(adapter); 2064 em_update_stats(adapter); 2065 2066 /* Reset LAA into RAR[0] on 82571 */ 2067 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 2068 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 2069 2070 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 2071 em_print_hw_stats(adapter); 2072 2073 em_smartspeed(adapter); 2074 2075 callout_reset(&adapter->timer, hz, em_timer, adapter); 2076 2077 lwkt_serialize_exit(ifp->if_serializer); 2078 } 2079 2080 static void 2081 em_update_link_status(struct adapter *adapter) 2082 { 2083 struct e1000_hw *hw = &adapter->hw; 2084 struct ifnet *ifp = &adapter->arpcom.ac_if; 2085 device_t dev = adapter->dev; 2086 uint32_t link_check = 0; 2087 2088 /* Get the cached link value or read phy for real */ 2089 switch (hw->phy.media_type) { 2090 case e1000_media_type_copper: 2091 if (hw->mac.get_link_status) { 2092 /* Do the work to read phy */ 2093 e1000_check_for_link(hw); 2094 link_check = !hw->mac.get_link_status; 2095 if (link_check) /* ESB2 fix */ 2096 e1000_cfg_on_link_up(hw); 2097 } else { 2098 link_check = TRUE; 2099 } 2100 break; 2101 2102 case e1000_media_type_fiber: 2103 e1000_check_for_link(hw); 2104 link_check = 2105 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 2106 break; 2107 2108 case e1000_media_type_internal_serdes: 2109 e1000_check_for_link(hw); 2110 link_check = adapter->hw.mac.serdes_has_link; 2111 break; 2112 2113 case e1000_media_type_unknown: 2114 default: 2115 break; 2116 } 2117 2118 /* Now check for a transition */ 2119 if (link_check && adapter->link_active == 0) { 2120 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 2121 &adapter->link_duplex); 2122 2123 /* 2124 * Check if we should enable/disable SPEED_MODE bit on 2125 * 82571/82572 2126 */ 2127 if (adapter->link_speed != SPEED_1000 && 2128 (hw->mac.type == e1000_82571 || 2129 hw->mac.type == e1000_82572)) { 2130 int tarc0; 2131 2132 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2133 tarc0 &= ~SPEED_MODE_BIT; 2134 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2135 } 2136 if (bootverbose) { 2137 device_printf(dev, "Link is up %d Mbps %s\n", 2138 adapter->link_speed, 2139 ((adapter->link_duplex == FULL_DUPLEX) ? 2140 "Full Duplex" : "Half Duplex")); 2141 } 2142 adapter->link_active = 1; 2143 adapter->smartspeed = 0; 2144 ifp->if_baudrate = adapter->link_speed * 1000000; 2145 ifp->if_link_state = LINK_STATE_UP; 2146 if_link_state_change(ifp); 2147 } else if (!link_check && adapter->link_active == 1) { 2148 ifp->if_baudrate = adapter->link_speed = 0; 2149 adapter->link_duplex = 0; 2150 if (bootverbose) 2151 device_printf(dev, "Link is Down\n"); 2152 adapter->link_active = 0; 2153 #if 0 2154 /* Link down, disable watchdog */ 2155 if->if_timer = 0; 2156 #endif 2157 ifp->if_link_state = LINK_STATE_DOWN; 2158 if_link_state_change(ifp); 2159 } 2160 } 2161 2162 static void 2163 em_stop(struct adapter *adapter) 2164 { 2165 struct ifnet *ifp = &adapter->arpcom.ac_if; 2166 int i; 2167 2168 ASSERT_SERIALIZED(ifp->if_serializer); 2169 2170 em_disable_intr(adapter); 2171 2172 callout_stop(&adapter->timer); 2173 callout_stop(&adapter->tx_fifo_timer); 2174 2175 ifp->if_flags &= ~IFF_RUNNING; 2176 ifq_clr_oactive(&ifp->if_snd); 2177 ifp->if_timer = 0; 2178 2179 e1000_reset_hw(&adapter->hw); 2180 if (adapter->hw.mac.type >= e1000_82544) 2181 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2182 2183 for (i = 0; i < adapter->num_tx_desc; i++) { 2184 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i]; 2185 2186 if (tx_buffer->m_head != NULL) { 2187 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 2188 m_freem(tx_buffer->m_head); 2189 tx_buffer->m_head = NULL; 2190 } 2191 } 2192 2193 for (i = 0; i < adapter->num_rx_desc; i++) { 2194 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i]; 2195 2196 if (rx_buffer->m_head != NULL) { 2197 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 2198 m_freem(rx_buffer->m_head); 2199 rx_buffer->m_head = NULL; 2200 } 2201 } 2202 2203 if (adapter->fmp != NULL) 2204 m_freem(adapter->fmp); 2205 adapter->fmp = NULL; 2206 adapter->lmp = NULL; 2207 2208 adapter->csum_flags = 0; 2209 adapter->csum_lhlen = 0; 2210 adapter->csum_iphlen = 0; 2211 adapter->csum_thlen = 0; 2212 adapter->csum_mss = 0; 2213 adapter->csum_pktlen = 0; 2214 2215 adapter->tx_dd_head = 0; 2216 adapter->tx_dd_tail = 0; 2217 adapter->tx_nsegs = 0; 2218 } 2219 2220 static int 2221 em_get_hw_info(struct adapter *adapter) 2222 { 2223 device_t dev = adapter->dev; 2224 2225 /* Save off the information about this board */ 2226 adapter->hw.vendor_id = pci_get_vendor(dev); 2227 adapter->hw.device_id = pci_get_device(dev); 2228 adapter->hw.revision_id = pci_get_revid(dev); 2229 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev); 2230 adapter->hw.subsystem_device_id = pci_get_subdevice(dev); 2231 2232 /* Do Shared Code Init and Setup */ 2233 if (e1000_set_mac_type(&adapter->hw)) 2234 return ENXIO; 2235 return 0; 2236 } 2237 2238 static int 2239 em_alloc_pci_res(struct adapter *adapter) 2240 { 2241 device_t dev = adapter->dev; 2242 u_int intr_flags; 2243 int val, rid, msi_enable; 2244 2245 /* Enable bus mastering */ 2246 pci_enable_busmaster(dev); 2247 2248 adapter->memory_rid = EM_BAR_MEM; 2249 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2250 &adapter->memory_rid, RF_ACTIVE); 2251 if (adapter->memory == NULL) { 2252 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2253 return (ENXIO); 2254 } 2255 adapter->osdep.mem_bus_space_tag = 2256 rman_get_bustag(adapter->memory); 2257 adapter->osdep.mem_bus_space_handle = 2258 rman_get_bushandle(adapter->memory); 2259 2260 /* XXX This is quite goofy, it is not actually used */ 2261 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2262 2263 /* Only older adapters use IO mapping */ 2264 if (adapter->hw.mac.type > e1000_82543 && 2265 adapter->hw.mac.type < e1000_82571) { 2266 /* Figure our where our IO BAR is ? */ 2267 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) { 2268 val = pci_read_config(dev, rid, 4); 2269 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2270 adapter->io_rid = rid; 2271 break; 2272 } 2273 rid += 4; 2274 /* check for 64bit BAR */ 2275 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2276 rid += 4; 2277 } 2278 if (rid >= PCIR_CARDBUSCIS) { 2279 device_printf(dev, "Unable to locate IO BAR\n"); 2280 return (ENXIO); 2281 } 2282 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2283 &adapter->io_rid, RF_ACTIVE); 2284 if (adapter->ioport == NULL) { 2285 device_printf(dev, "Unable to allocate bus resource: " 2286 "ioport\n"); 2287 return (ENXIO); 2288 } 2289 adapter->hw.io_base = 0; 2290 adapter->osdep.io_bus_space_tag = 2291 rman_get_bustag(adapter->ioport); 2292 adapter->osdep.io_bus_space_handle = 2293 rman_get_bushandle(adapter->ioport); 2294 } 2295 2296 /* 2297 * Don't enable MSI-X on 82574, see: 2298 * 82574 specification update errata #15 2299 * 2300 * Don't enable MSI on PCI/PCI-X chips, see: 2301 * 82540 specification update errata #6 2302 * 82545 specification update errata #4 2303 * 2304 * Don't enable MSI on 82571/82572, see: 2305 * 82571/82572 specification update errata #63 2306 */ 2307 msi_enable = em_msi_enable; 2308 if (msi_enable && 2309 (!pci_is_pcie(dev) || 2310 adapter->hw.mac.type == e1000_82571 || 2311 adapter->hw.mac.type == e1000_82572)) 2312 msi_enable = 0; 2313 2314 adapter->intr_type = pci_alloc_1intr(dev, msi_enable, 2315 &adapter->intr_rid, &intr_flags); 2316 2317 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) { 2318 int unshared; 2319 2320 unshared = device_getenv_int(dev, "irq.unshared", 0); 2321 if (!unshared) { 2322 adapter->flags |= EM_FLAG_SHARED_INTR; 2323 if (bootverbose) 2324 device_printf(dev, "IRQ shared\n"); 2325 } else { 2326 intr_flags &= ~RF_SHAREABLE; 2327 if (bootverbose) 2328 device_printf(dev, "IRQ unshared\n"); 2329 } 2330 } 2331 2332 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 2333 &adapter->intr_rid, intr_flags); 2334 if (adapter->intr_res == NULL) { 2335 device_printf(dev, "Unable to allocate bus resource: " 2336 "interrupt\n"); 2337 return (ENXIO); 2338 } 2339 2340 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2341 adapter->hw.back = &adapter->osdep; 2342 return (0); 2343 } 2344 2345 static void 2346 em_free_pci_res(struct adapter *adapter) 2347 { 2348 device_t dev = adapter->dev; 2349 2350 if (adapter->intr_res != NULL) { 2351 bus_release_resource(dev, SYS_RES_IRQ, 2352 adapter->intr_rid, adapter->intr_res); 2353 } 2354 2355 if (adapter->intr_type == PCI_INTR_TYPE_MSI) 2356 pci_release_msi(dev); 2357 2358 if (adapter->memory != NULL) { 2359 bus_release_resource(dev, SYS_RES_MEMORY, 2360 adapter->memory_rid, adapter->memory); 2361 } 2362 2363 if (adapter->flash != NULL) { 2364 bus_release_resource(dev, SYS_RES_MEMORY, 2365 adapter->flash_rid, adapter->flash); 2366 } 2367 2368 if (adapter->ioport != NULL) { 2369 bus_release_resource(dev, SYS_RES_IOPORT, 2370 adapter->io_rid, adapter->ioport); 2371 } 2372 } 2373 2374 static int 2375 em_reset(struct adapter *adapter) 2376 { 2377 device_t dev = adapter->dev; 2378 uint16_t rx_buffer_size; 2379 2380 /* When hardware is reset, fifo_head is also reset */ 2381 adapter->tx_fifo_head = 0; 2382 2383 /* Set up smart power down as default off on newer adapters. */ 2384 if (!em_smart_pwr_down && 2385 (adapter->hw.mac.type == e1000_82571 || 2386 adapter->hw.mac.type == e1000_82572)) { 2387 uint16_t phy_tmp = 0; 2388 2389 /* Speed up time to link by disabling smart power down. */ 2390 e1000_read_phy_reg(&adapter->hw, 2391 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2392 phy_tmp &= ~IGP02E1000_PM_SPD; 2393 e1000_write_phy_reg(&adapter->hw, 2394 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2395 } 2396 2397 /* 2398 * These parameters control the automatic generation (Tx) and 2399 * response (Rx) to Ethernet PAUSE frames. 2400 * - High water mark should allow for at least two frames to be 2401 * received after sending an XOFF. 2402 * - Low water mark works best when it is very near the high water mark. 2403 * This allows the receiver to restart by sending XON when it has 2404 * drained a bit. Here we use an arbitary value of 1500 which will 2405 * restart after one full frame is pulled from the buffer. There 2406 * could be several smaller frames in the buffer and if so they will 2407 * not trigger the XON until their total number reduces the buffer 2408 * by 1500. 2409 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2410 */ 2411 rx_buffer_size = 2412 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10; 2413 2414 adapter->hw.fc.high_water = rx_buffer_size - 2415 roundup2(adapter->max_frame_size, 1024); 2416 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 2417 2418 if (adapter->hw.mac.type == e1000_80003es2lan) 2419 adapter->hw.fc.pause_time = 0xFFFF; 2420 else 2421 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 2422 2423 adapter->hw.fc.send_xon = TRUE; 2424 2425 adapter->hw.fc.requested_mode = e1000_fc_full; 2426 2427 /* Workaround: no TX flow ctrl for PCH */ 2428 if (adapter->hw.mac.type == e1000_pchlan) 2429 adapter->hw.fc.requested_mode = e1000_fc_rx_pause; 2430 2431 /* Override - settings for PCH2LAN, ya its magic :) */ 2432 if (adapter->hw.mac.type == e1000_pch2lan) { 2433 adapter->hw.fc.high_water = 0x5C20; 2434 adapter->hw.fc.low_water = 0x5048; 2435 adapter->hw.fc.pause_time = 0x0650; 2436 adapter->hw.fc.refresh_time = 0x0400; 2437 2438 /* Jumbos need adjusted PBA */ 2439 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) 2440 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12); 2441 else 2442 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26); 2443 } 2444 2445 /* Issue a global reset */ 2446 e1000_reset_hw(&adapter->hw); 2447 if (adapter->hw.mac.type >= e1000_82544) 2448 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2449 em_disable_aspm(adapter); 2450 2451 if (e1000_init_hw(&adapter->hw) < 0) { 2452 device_printf(dev, "Hardware Initialization Failed\n"); 2453 return (EIO); 2454 } 2455 2456 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 2457 e1000_get_phy_info(&adapter->hw); 2458 e1000_check_for_link(&adapter->hw); 2459 2460 return (0); 2461 } 2462 2463 static void 2464 em_setup_ifp(struct adapter *adapter) 2465 { 2466 struct ifnet *ifp = &adapter->arpcom.ac_if; 2467 2468 if_initname(ifp, device_get_name(adapter->dev), 2469 device_get_unit(adapter->dev)); 2470 ifp->if_softc = adapter; 2471 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2472 ifp->if_init = em_init; 2473 ifp->if_ioctl = em_ioctl; 2474 ifp->if_start = em_start; 2475 #ifdef IFPOLL_ENABLE 2476 ifp->if_npoll = em_npoll; 2477 #endif 2478 ifp->if_watchdog = em_watchdog; 2479 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1); 2480 ifq_set_ready(&ifp->if_snd); 2481 2482 ether_ifattach(ifp, adapter->hw.mac.addr, NULL); 2483 2484 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2485 if (adapter->hw.mac.type >= e1000_82543) 2486 ifp->if_capabilities |= IFCAP_HWCSUM; 2487 if (adapter->flags & EM_FLAG_TSO) 2488 ifp->if_capabilities |= IFCAP_TSO; 2489 ifp->if_capenable = ifp->if_capabilities; 2490 2491 if (ifp->if_capenable & IFCAP_TXCSUM) 2492 ifp->if_hwassist |= EM_CSUM_FEATURES; 2493 if (ifp->if_capenable & IFCAP_TSO) 2494 ifp->if_hwassist |= CSUM_TSO; 2495 2496 /* 2497 * Tell the upper layer(s) we support long frames. 2498 */ 2499 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2500 2501 /* 2502 * Specify the media types supported by this adapter and register 2503 * callbacks to update media and link information 2504 */ 2505 ifmedia_init(&adapter->media, IFM_IMASK, 2506 em_media_change, em_media_status); 2507 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2508 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2509 u_char fiber_type = IFM_1000_SX; /* default type */ 2510 2511 if (adapter->hw.mac.type == e1000_82545) 2512 fiber_type = IFM_1000_LX; 2513 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2514 0, NULL); 2515 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2516 } else { 2517 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2518 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2519 0, NULL); 2520 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2521 0, NULL); 2522 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2523 0, NULL); 2524 if (adapter->hw.phy.type != e1000_phy_ife) { 2525 ifmedia_add(&adapter->media, 2526 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2527 ifmedia_add(&adapter->media, 2528 IFM_ETHER | IFM_1000_T, 0, NULL); 2529 } 2530 } 2531 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2532 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2533 } 2534 2535 2536 /* 2537 * Workaround for SmartSpeed on 82541 and 82547 controllers 2538 */ 2539 static void 2540 em_smartspeed(struct adapter *adapter) 2541 { 2542 uint16_t phy_tmp; 2543 2544 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp || 2545 adapter->hw.mac.autoneg == 0 || 2546 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2547 return; 2548 2549 if (adapter->smartspeed == 0) { 2550 /* 2551 * If Master/Slave config fault is asserted twice, 2552 * we assume back-to-back 2553 */ 2554 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2555 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2556 return; 2557 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2558 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2559 e1000_read_phy_reg(&adapter->hw, 2560 PHY_1000T_CTRL, &phy_tmp); 2561 if (phy_tmp & CR_1000T_MS_ENABLE) { 2562 phy_tmp &= ~CR_1000T_MS_ENABLE; 2563 e1000_write_phy_reg(&adapter->hw, 2564 PHY_1000T_CTRL, phy_tmp); 2565 adapter->smartspeed++; 2566 if (adapter->hw.mac.autoneg && 2567 !e1000_phy_setup_autoneg(&adapter->hw) && 2568 !e1000_read_phy_reg(&adapter->hw, 2569 PHY_CONTROL, &phy_tmp)) { 2570 phy_tmp |= MII_CR_AUTO_NEG_EN | 2571 MII_CR_RESTART_AUTO_NEG; 2572 e1000_write_phy_reg(&adapter->hw, 2573 PHY_CONTROL, phy_tmp); 2574 } 2575 } 2576 } 2577 return; 2578 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2579 /* If still no link, perhaps using 2/3 pair cable */ 2580 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2581 phy_tmp |= CR_1000T_MS_ENABLE; 2582 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2583 if (adapter->hw.mac.autoneg && 2584 !e1000_phy_setup_autoneg(&adapter->hw) && 2585 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2586 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2587 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2588 } 2589 } 2590 2591 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2592 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2593 adapter->smartspeed = 0; 2594 } 2595 2596 static int 2597 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2598 struct em_dma_alloc *dma) 2599 { 2600 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag, 2601 EM_DBA_ALIGN, size, BUS_DMA_WAITOK, 2602 &dma->dma_tag, &dma->dma_map, 2603 &dma->dma_paddr); 2604 if (dma->dma_vaddr == NULL) 2605 return ENOMEM; 2606 else 2607 return 0; 2608 } 2609 2610 static void 2611 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2612 { 2613 if (dma->dma_tag == NULL) 2614 return; 2615 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2616 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2617 bus_dma_tag_destroy(dma->dma_tag); 2618 } 2619 2620 static int 2621 em_create_tx_ring(struct adapter *adapter) 2622 { 2623 device_t dev = adapter->dev; 2624 struct em_buffer *tx_buffer; 2625 int error, i; 2626 2627 adapter->tx_buffer_area = 2628 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc, 2629 M_DEVBUF, M_WAITOK | M_ZERO); 2630 2631 /* 2632 * Create DMA tags for tx buffers 2633 */ 2634 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 2635 1, 0, /* alignment, bounds */ 2636 BUS_SPACE_MAXADDR, /* lowaddr */ 2637 BUS_SPACE_MAXADDR, /* highaddr */ 2638 NULL, NULL, /* filter, filterarg */ 2639 EM_TSO_SIZE, /* maxsize */ 2640 EM_MAX_SCATTER, /* nsegments */ 2641 PAGE_SIZE, /* maxsegsize */ 2642 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2643 BUS_DMA_ONEBPAGE, /* flags */ 2644 &adapter->txtag); 2645 if (error) { 2646 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2647 kfree(adapter->tx_buffer_area, M_DEVBUF); 2648 adapter->tx_buffer_area = NULL; 2649 return error; 2650 } 2651 2652 /* 2653 * Create DMA maps for tx buffers 2654 */ 2655 for (i = 0; i < adapter->num_tx_desc; i++) { 2656 tx_buffer = &adapter->tx_buffer_area[i]; 2657 2658 error = bus_dmamap_create(adapter->txtag, 2659 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2660 &tx_buffer->map); 2661 if (error) { 2662 device_printf(dev, "Unable to create TX DMA map\n"); 2663 em_destroy_tx_ring(adapter, i); 2664 return error; 2665 } 2666 } 2667 return (0); 2668 } 2669 2670 static void 2671 em_init_tx_ring(struct adapter *adapter) 2672 { 2673 /* Clear the old ring contents */ 2674 bzero(adapter->tx_desc_base, 2675 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 2676 2677 /* Reset state */ 2678 adapter->next_avail_tx_desc = 0; 2679 adapter->next_tx_to_clean = 0; 2680 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2681 } 2682 2683 static void 2684 em_init_tx_unit(struct adapter *adapter) 2685 { 2686 uint32_t tctl, tarc, tipg = 0; 2687 uint64_t bus_addr; 2688 2689 /* Setup the Base and Length of the Tx Descriptor Ring */ 2690 bus_addr = adapter->txdma.dma_paddr; 2691 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 2692 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 2693 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 2694 (uint32_t)(bus_addr >> 32)); 2695 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 2696 (uint32_t)bus_addr); 2697 /* Setup the HW Tx Head and Tail descriptor pointers */ 2698 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 2699 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 2700 2701 /* Set the default values for the Tx Inter Packet Gap timer */ 2702 switch (adapter->hw.mac.type) { 2703 case e1000_82542: 2704 tipg = DEFAULT_82542_TIPG_IPGT; 2705 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2706 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2707 break; 2708 2709 case e1000_80003es2lan: 2710 tipg = DEFAULT_82543_TIPG_IPGR1; 2711 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2712 E1000_TIPG_IPGR2_SHIFT; 2713 break; 2714 2715 default: 2716 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2717 adapter->hw.phy.media_type == 2718 e1000_media_type_internal_serdes) 2719 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2720 else 2721 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2722 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2723 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2724 break; 2725 } 2726 2727 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2728 2729 /* NOTE: 0 is not allowed for TIDV */ 2730 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1); 2731 if(adapter->hw.mac.type >= e1000_82540) 2732 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0); 2733 2734 if (adapter->hw.mac.type == e1000_82571 || 2735 adapter->hw.mac.type == e1000_82572) { 2736 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2737 tarc |= SPEED_MODE_BIT; 2738 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2739 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2740 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2741 tarc |= 1; 2742 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2743 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2744 tarc |= 1; 2745 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2746 } 2747 2748 /* Program the Transmit Control Register */ 2749 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2750 tctl &= ~E1000_TCTL_CT; 2751 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2752 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2753 2754 if (adapter->hw.mac.type >= e1000_82571) 2755 tctl |= E1000_TCTL_MULR; 2756 2757 /* This write will effectively turn on the transmit unit. */ 2758 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2759 } 2760 2761 static void 2762 em_destroy_tx_ring(struct adapter *adapter, int ndesc) 2763 { 2764 struct em_buffer *tx_buffer; 2765 int i; 2766 2767 if (adapter->tx_buffer_area == NULL) 2768 return; 2769 2770 for (i = 0; i < ndesc; i++) { 2771 tx_buffer = &adapter->tx_buffer_area[i]; 2772 2773 KKASSERT(tx_buffer->m_head == NULL); 2774 bus_dmamap_destroy(adapter->txtag, tx_buffer->map); 2775 } 2776 bus_dma_tag_destroy(adapter->txtag); 2777 2778 kfree(adapter->tx_buffer_area, M_DEVBUF); 2779 adapter->tx_buffer_area = NULL; 2780 } 2781 2782 /* 2783 * The offload context needs to be set when we transfer the first 2784 * packet of a particular protocol (TCP/UDP). This routine has been 2785 * enhanced to deal with inserted VLAN headers. 2786 * 2787 * If the new packet's ether header length, ip header length and 2788 * csum offloading type are same as the previous packet, we should 2789 * avoid allocating a new csum context descriptor; mainly to take 2790 * advantage of the pipeline effect of the TX data read request. 2791 * 2792 * This function returns number of TX descrptors allocated for 2793 * csum context. 2794 */ 2795 static int 2796 em_txcsum(struct adapter *adapter, struct mbuf *mp, 2797 uint32_t *txd_upper, uint32_t *txd_lower) 2798 { 2799 struct e1000_context_desc *TXD; 2800 int curr_txd, ehdrlen, csum_flags; 2801 uint32_t cmd, hdr_len, ip_hlen; 2802 2803 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES; 2804 ip_hlen = mp->m_pkthdr.csum_iphlen; 2805 ehdrlen = mp->m_pkthdr.csum_lhlen; 2806 2807 if (adapter->csum_lhlen == ehdrlen && 2808 adapter->csum_iphlen == ip_hlen && 2809 adapter->csum_flags == csum_flags) { 2810 /* 2811 * Same csum offload context as the previous packets; 2812 * just return. 2813 */ 2814 *txd_upper = adapter->csum_txd_upper; 2815 *txd_lower = adapter->csum_txd_lower; 2816 return 0; 2817 } 2818 2819 /* 2820 * Setup a new csum offload context. 2821 */ 2822 2823 curr_txd = adapter->next_avail_tx_desc; 2824 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 2825 2826 cmd = 0; 2827 2828 /* Setup of IP header checksum. */ 2829 if (csum_flags & CSUM_IP) { 2830 /* 2831 * Start offset for header checksum calculation. 2832 * End offset for header checksum calculation. 2833 * Offset of place to put the checksum. 2834 */ 2835 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2836 TXD->lower_setup.ip_fields.ipcse = 2837 htole16(ehdrlen + ip_hlen - 1); 2838 TXD->lower_setup.ip_fields.ipcso = 2839 ehdrlen + offsetof(struct ip, ip_sum); 2840 cmd |= E1000_TXD_CMD_IP; 2841 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2842 } 2843 hdr_len = ehdrlen + ip_hlen; 2844 2845 if (csum_flags & CSUM_TCP) { 2846 /* 2847 * Start offset for payload checksum calculation. 2848 * End offset for payload checksum calculation. 2849 * Offset of place to put the checksum. 2850 */ 2851 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2852 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2853 TXD->upper_setup.tcp_fields.tucso = 2854 hdr_len + offsetof(struct tcphdr, th_sum); 2855 cmd |= E1000_TXD_CMD_TCP; 2856 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2857 } else if (csum_flags & CSUM_UDP) { 2858 /* 2859 * Start offset for header checksum calculation. 2860 * End offset for header checksum calculation. 2861 * Offset of place to put the checksum. 2862 */ 2863 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2864 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2865 TXD->upper_setup.tcp_fields.tucso = 2866 hdr_len + offsetof(struct udphdr, uh_sum); 2867 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2868 } 2869 2870 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2871 E1000_TXD_DTYP_D; /* Data descr */ 2872 2873 /* Save the information for this csum offloading context */ 2874 adapter->csum_lhlen = ehdrlen; 2875 adapter->csum_iphlen = ip_hlen; 2876 adapter->csum_flags = csum_flags; 2877 adapter->csum_txd_upper = *txd_upper; 2878 adapter->csum_txd_lower = *txd_lower; 2879 2880 TXD->tcp_seg_setup.data = htole32(0); 2881 TXD->cmd_and_length = 2882 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2883 2884 if (++curr_txd == adapter->num_tx_desc) 2885 curr_txd = 0; 2886 2887 KKASSERT(adapter->num_tx_desc_avail > 0); 2888 adapter->num_tx_desc_avail--; 2889 2890 adapter->next_avail_tx_desc = curr_txd; 2891 return 1; 2892 } 2893 2894 static void 2895 em_txeof(struct adapter *adapter) 2896 { 2897 struct ifnet *ifp = &adapter->arpcom.ac_if; 2898 struct em_buffer *tx_buffer; 2899 int first, num_avail; 2900 2901 if (adapter->tx_dd_head == adapter->tx_dd_tail) 2902 return; 2903 2904 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2905 return; 2906 2907 num_avail = adapter->num_tx_desc_avail; 2908 first = adapter->next_tx_to_clean; 2909 2910 while (adapter->tx_dd_head != adapter->tx_dd_tail) { 2911 struct e1000_tx_desc *tx_desc; 2912 int dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2913 2914 tx_desc = &adapter->tx_desc_base[dd_idx]; 2915 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2916 EM_INC_TXDD_IDX(adapter->tx_dd_head); 2917 2918 if (++dd_idx == adapter->num_tx_desc) 2919 dd_idx = 0; 2920 2921 while (first != dd_idx) { 2922 logif(pkt_txclean); 2923 2924 num_avail++; 2925 2926 tx_buffer = &adapter->tx_buffer_area[first]; 2927 if (tx_buffer->m_head) { 2928 ifp->if_opackets++; 2929 bus_dmamap_unload(adapter->txtag, 2930 tx_buffer->map); 2931 m_freem(tx_buffer->m_head); 2932 tx_buffer->m_head = NULL; 2933 } 2934 2935 if (++first == adapter->num_tx_desc) 2936 first = 0; 2937 } 2938 } else { 2939 break; 2940 } 2941 } 2942 adapter->next_tx_to_clean = first; 2943 adapter->num_tx_desc_avail = num_avail; 2944 2945 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 2946 adapter->tx_dd_head = 0; 2947 adapter->tx_dd_tail = 0; 2948 } 2949 2950 if (!EM_IS_OACTIVE(adapter)) { 2951 ifq_clr_oactive(&ifp->if_snd); 2952 2953 /* All clean, turn off the timer */ 2954 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2955 ifp->if_timer = 0; 2956 } 2957 } 2958 2959 static void 2960 em_tx_collect(struct adapter *adapter) 2961 { 2962 struct ifnet *ifp = &adapter->arpcom.ac_if; 2963 struct em_buffer *tx_buffer; 2964 int tdh, first, num_avail, dd_idx = -1; 2965 2966 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2967 return; 2968 2969 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0)); 2970 if (tdh == adapter->next_tx_to_clean) 2971 return; 2972 2973 if (adapter->tx_dd_head != adapter->tx_dd_tail) 2974 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2975 2976 num_avail = adapter->num_tx_desc_avail; 2977 first = adapter->next_tx_to_clean; 2978 2979 while (first != tdh) { 2980 logif(pkt_txclean); 2981 2982 num_avail++; 2983 2984 tx_buffer = &adapter->tx_buffer_area[first]; 2985 if (tx_buffer->m_head) { 2986 ifp->if_opackets++; 2987 bus_dmamap_unload(adapter->txtag, 2988 tx_buffer->map); 2989 m_freem(tx_buffer->m_head); 2990 tx_buffer->m_head = NULL; 2991 } 2992 2993 if (first == dd_idx) { 2994 EM_INC_TXDD_IDX(adapter->tx_dd_head); 2995 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 2996 adapter->tx_dd_head = 0; 2997 adapter->tx_dd_tail = 0; 2998 dd_idx = -1; 2999 } else { 3000 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3001 } 3002 } 3003 3004 if (++first == adapter->num_tx_desc) 3005 first = 0; 3006 } 3007 adapter->next_tx_to_clean = first; 3008 adapter->num_tx_desc_avail = num_avail; 3009 3010 if (!EM_IS_OACTIVE(adapter)) { 3011 ifq_clr_oactive(&ifp->if_snd); 3012 3013 /* All clean, turn off the timer */ 3014 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3015 ifp->if_timer = 0; 3016 } 3017 } 3018 3019 /* 3020 * When Link is lost sometimes there is work still in the TX ring 3021 * which will result in a watchdog, rather than allow that do an 3022 * attempted cleanup and then reinit here. Note that this has been 3023 * seens mostly with fiber adapters. 3024 */ 3025 static void 3026 em_tx_purge(struct adapter *adapter) 3027 { 3028 struct ifnet *ifp = &adapter->arpcom.ac_if; 3029 3030 if (!adapter->link_active && ifp->if_timer) { 3031 em_tx_collect(adapter); 3032 if (ifp->if_timer) { 3033 if_printf(ifp, "Link lost, TX pending, reinit\n"); 3034 ifp->if_timer = 0; 3035 em_init(adapter); 3036 } 3037 } 3038 } 3039 3040 static int 3041 em_newbuf(struct adapter *adapter, int i, int init) 3042 { 3043 struct mbuf *m; 3044 bus_dma_segment_t seg; 3045 bus_dmamap_t map; 3046 struct em_buffer *rx_buffer; 3047 int error, nseg; 3048 3049 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 3050 if (m == NULL) { 3051 adapter->mbuf_cluster_failed++; 3052 if (init) { 3053 if_printf(&adapter->arpcom.ac_if, 3054 "Unable to allocate RX mbuf\n"); 3055 } 3056 return (ENOBUFS); 3057 } 3058 m->m_len = m->m_pkthdr.len = MCLBYTES; 3059 3060 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN) 3061 m_adj(m, ETHER_ALIGN); 3062 3063 error = bus_dmamap_load_mbuf_segment(adapter->rxtag, 3064 adapter->rx_sparemap, m, 3065 &seg, 1, &nseg, BUS_DMA_NOWAIT); 3066 if (error) { 3067 m_freem(m); 3068 if (init) { 3069 if_printf(&adapter->arpcom.ac_if, 3070 "Unable to load RX mbuf\n"); 3071 } 3072 return (error); 3073 } 3074 3075 rx_buffer = &adapter->rx_buffer_area[i]; 3076 if (rx_buffer->m_head != NULL) 3077 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 3078 3079 map = rx_buffer->map; 3080 rx_buffer->map = adapter->rx_sparemap; 3081 adapter->rx_sparemap = map; 3082 3083 rx_buffer->m_head = m; 3084 3085 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr); 3086 return (0); 3087 } 3088 3089 static int 3090 em_create_rx_ring(struct adapter *adapter) 3091 { 3092 device_t dev = adapter->dev; 3093 struct em_buffer *rx_buffer; 3094 int i, error; 3095 3096 adapter->rx_buffer_area = 3097 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc, 3098 M_DEVBUF, M_WAITOK | M_ZERO); 3099 3100 /* 3101 * Create DMA tag for rx buffers 3102 */ 3103 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 3104 1, 0, /* alignment, bounds */ 3105 BUS_SPACE_MAXADDR, /* lowaddr */ 3106 BUS_SPACE_MAXADDR, /* highaddr */ 3107 NULL, NULL, /* filter, filterarg */ 3108 MCLBYTES, /* maxsize */ 3109 1, /* nsegments */ 3110 MCLBYTES, /* maxsegsize */ 3111 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 3112 &adapter->rxtag); 3113 if (error) { 3114 device_printf(dev, "Unable to allocate RX DMA tag\n"); 3115 kfree(adapter->rx_buffer_area, M_DEVBUF); 3116 adapter->rx_buffer_area = NULL; 3117 return error; 3118 } 3119 3120 /* 3121 * Create spare DMA map for rx buffers 3122 */ 3123 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3124 &adapter->rx_sparemap); 3125 if (error) { 3126 device_printf(dev, "Unable to create spare RX DMA map\n"); 3127 bus_dma_tag_destroy(adapter->rxtag); 3128 kfree(adapter->rx_buffer_area, M_DEVBUF); 3129 adapter->rx_buffer_area = NULL; 3130 return error; 3131 } 3132 3133 /* 3134 * Create DMA maps for rx buffers 3135 */ 3136 for (i = 0; i < adapter->num_rx_desc; i++) { 3137 rx_buffer = &adapter->rx_buffer_area[i]; 3138 3139 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3140 &rx_buffer->map); 3141 if (error) { 3142 device_printf(dev, "Unable to create RX DMA map\n"); 3143 em_destroy_rx_ring(adapter, i); 3144 return error; 3145 } 3146 } 3147 return (0); 3148 } 3149 3150 static int 3151 em_init_rx_ring(struct adapter *adapter) 3152 { 3153 int i, error; 3154 3155 /* Reset descriptor ring */ 3156 bzero(adapter->rx_desc_base, 3157 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 3158 3159 /* Allocate new ones. */ 3160 for (i = 0; i < adapter->num_rx_desc; i++) { 3161 error = em_newbuf(adapter, i, 1); 3162 if (error) 3163 return (error); 3164 } 3165 3166 /* Setup our descriptor pointers */ 3167 adapter->next_rx_desc_to_check = 0; 3168 3169 return (0); 3170 } 3171 3172 static void 3173 em_init_rx_unit(struct adapter *adapter) 3174 { 3175 struct ifnet *ifp = &adapter->arpcom.ac_if; 3176 uint64_t bus_addr; 3177 uint32_t rctl; 3178 3179 /* 3180 * Make sure receives are disabled while setting 3181 * up the descriptor ring 3182 */ 3183 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3184 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3185 3186 if (adapter->hw.mac.type >= e1000_82540) { 3187 uint32_t itr; 3188 3189 /* 3190 * Set the interrupt throttling rate. Value is calculated 3191 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 3192 */ 3193 if (adapter->int_throttle_ceil) 3194 itr = 1000000000 / 256 / adapter->int_throttle_ceil; 3195 else 3196 itr = 0; 3197 em_set_itr(adapter, itr); 3198 } 3199 3200 /* Disable accelerated ackknowledge */ 3201 if (adapter->hw.mac.type == e1000_82574) { 3202 E1000_WRITE_REG(&adapter->hw, 3203 E1000_RFCTL, E1000_RFCTL_ACK_DIS); 3204 } 3205 3206 /* Receive Checksum Offload for TCP and UDP */ 3207 if (ifp->if_capenable & IFCAP_RXCSUM) { 3208 uint32_t rxcsum; 3209 3210 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 3211 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3212 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum); 3213 } 3214 3215 /* 3216 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3217 * long latencies are observed, like Lenovo X60. This 3218 * change eliminates the problem, but since having positive 3219 * values in RDTR is a known source of problems on other 3220 * platforms another solution is being sought. 3221 */ 3222 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) { 3223 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573); 3224 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573); 3225 } 3226 3227 /* 3228 * Setup the Base and Length of the Rx Descriptor Ring 3229 */ 3230 bus_addr = adapter->rxdma.dma_paddr; 3231 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 3232 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 3233 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 3234 (uint32_t)(bus_addr >> 32)); 3235 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 3236 (uint32_t)bus_addr); 3237 3238 /* 3239 * Setup the HW Rx Head and Tail Descriptor Pointers 3240 */ 3241 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 3242 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 3243 3244 /* Set early receive threshold on appropriate hw */ 3245 if (((adapter->hw.mac.type == e1000_ich9lan) || 3246 (adapter->hw.mac.type == e1000_pch2lan) || 3247 (adapter->hw.mac.type == e1000_ich10lan)) && 3248 (ifp->if_mtu > ETHERMTU)) { 3249 uint32_t rxdctl; 3250 3251 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0)); 3252 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3); 3253 E1000_WRITE_REG(&adapter->hw, E1000_ERT, 0x100 | (1 << 13)); 3254 } 3255 3256 if (adapter->hw.mac.type == e1000_pch2lan) { 3257 if (ifp->if_mtu > ETHERMTU) 3258 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE); 3259 else 3260 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE); 3261 } 3262 3263 /* Setup the Receive Control Register */ 3264 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3265 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3266 E1000_RCTL_RDMTS_HALF | 3267 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3268 3269 /* Make sure VLAN Filters are off */ 3270 rctl &= ~E1000_RCTL_VFE; 3271 3272 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 3273 rctl |= E1000_RCTL_SBP; 3274 else 3275 rctl &= ~E1000_RCTL_SBP; 3276 3277 switch (adapter->rx_buffer_len) { 3278 default: 3279 case 2048: 3280 rctl |= E1000_RCTL_SZ_2048; 3281 break; 3282 3283 case 4096: 3284 rctl |= E1000_RCTL_SZ_4096 | 3285 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3286 break; 3287 3288 case 8192: 3289 rctl |= E1000_RCTL_SZ_8192 | 3290 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3291 break; 3292 3293 case 16384: 3294 rctl |= E1000_RCTL_SZ_16384 | 3295 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3296 break; 3297 } 3298 3299 if (ifp->if_mtu > ETHERMTU) 3300 rctl |= E1000_RCTL_LPE; 3301 else 3302 rctl &= ~E1000_RCTL_LPE; 3303 3304 /* Enable Receives */ 3305 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3306 } 3307 3308 static void 3309 em_destroy_rx_ring(struct adapter *adapter, int ndesc) 3310 { 3311 struct em_buffer *rx_buffer; 3312 int i; 3313 3314 if (adapter->rx_buffer_area == NULL) 3315 return; 3316 3317 for (i = 0; i < ndesc; i++) { 3318 rx_buffer = &adapter->rx_buffer_area[i]; 3319 3320 KKASSERT(rx_buffer->m_head == NULL); 3321 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map); 3322 } 3323 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 3324 bus_dma_tag_destroy(adapter->rxtag); 3325 3326 kfree(adapter->rx_buffer_area, M_DEVBUF); 3327 adapter->rx_buffer_area = NULL; 3328 } 3329 3330 static void 3331 em_rxeof(struct adapter *adapter, int count) 3332 { 3333 struct ifnet *ifp = &adapter->arpcom.ac_if; 3334 uint8_t status, accept_frame = 0, eop = 0; 3335 uint16_t len, desc_len, prev_len_adj; 3336 struct e1000_rx_desc *current_desc; 3337 struct mbuf *mp; 3338 int i; 3339 3340 i = adapter->next_rx_desc_to_check; 3341 current_desc = &adapter->rx_desc_base[i]; 3342 3343 if (!(current_desc->status & E1000_RXD_STAT_DD)) 3344 return; 3345 3346 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) { 3347 struct mbuf *m = NULL; 3348 3349 logif(pkt_receive); 3350 3351 mp = adapter->rx_buffer_area[i].m_head; 3352 3353 /* 3354 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3355 * needs to access the last received byte in the mbuf. 3356 */ 3357 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3358 BUS_DMASYNC_POSTREAD); 3359 3360 accept_frame = 1; 3361 prev_len_adj = 0; 3362 desc_len = le16toh(current_desc->length); 3363 status = current_desc->status; 3364 if (status & E1000_RXD_STAT_EOP) { 3365 count--; 3366 eop = 1; 3367 if (desc_len < ETHER_CRC_LEN) { 3368 len = 0; 3369 prev_len_adj = ETHER_CRC_LEN - desc_len; 3370 } else { 3371 len = desc_len - ETHER_CRC_LEN; 3372 } 3373 } else { 3374 eop = 0; 3375 len = desc_len; 3376 } 3377 3378 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3379 uint8_t last_byte; 3380 uint32_t pkt_len = desc_len; 3381 3382 if (adapter->fmp != NULL) 3383 pkt_len += adapter->fmp->m_pkthdr.len; 3384 3385 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3386 if (TBI_ACCEPT(&adapter->hw, status, 3387 current_desc->errors, pkt_len, last_byte, 3388 adapter->min_frame_size, adapter->max_frame_size)) { 3389 e1000_tbi_adjust_stats_82543(&adapter->hw, 3390 &adapter->stats, pkt_len, 3391 adapter->hw.mac.addr, 3392 adapter->max_frame_size); 3393 if (len > 0) 3394 len--; 3395 } else { 3396 accept_frame = 0; 3397 } 3398 } 3399 3400 if (accept_frame) { 3401 if (em_newbuf(adapter, i, 0) != 0) { 3402 ifp->if_iqdrops++; 3403 goto discard; 3404 } 3405 3406 /* Assign correct length to the current fragment */ 3407 mp->m_len = len; 3408 3409 if (adapter->fmp == NULL) { 3410 mp->m_pkthdr.len = len; 3411 adapter->fmp = mp; /* Store the first mbuf */ 3412 adapter->lmp = mp; 3413 } else { 3414 /* 3415 * Chain mbuf's together 3416 */ 3417 3418 /* 3419 * Adjust length of previous mbuf in chain if 3420 * we received less than 4 bytes in the last 3421 * descriptor. 3422 */ 3423 if (prev_len_adj > 0) { 3424 adapter->lmp->m_len -= prev_len_adj; 3425 adapter->fmp->m_pkthdr.len -= 3426 prev_len_adj; 3427 } 3428 adapter->lmp->m_next = mp; 3429 adapter->lmp = adapter->lmp->m_next; 3430 adapter->fmp->m_pkthdr.len += len; 3431 } 3432 3433 if (eop) { 3434 adapter->fmp->m_pkthdr.rcvif = ifp; 3435 ifp->if_ipackets++; 3436 3437 if (ifp->if_capenable & IFCAP_RXCSUM) { 3438 em_rxcsum(adapter, current_desc, 3439 adapter->fmp); 3440 } 3441 3442 if (status & E1000_RXD_STAT_VP) { 3443 adapter->fmp->m_pkthdr.ether_vlantag = 3444 (le16toh(current_desc->special) & 3445 E1000_RXD_SPC_VLAN_MASK); 3446 adapter->fmp->m_flags |= M_VLANTAG; 3447 } 3448 m = adapter->fmp; 3449 adapter->fmp = NULL; 3450 adapter->lmp = NULL; 3451 } 3452 } else { 3453 ifp->if_ierrors++; 3454 discard: 3455 #ifdef foo 3456 /* Reuse loaded DMA map and just update mbuf chain */ 3457 mp = adapter->rx_buffer_area[i].m_head; 3458 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 3459 mp->m_data = mp->m_ext.ext_buf; 3460 mp->m_next = NULL; 3461 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 3462 m_adj(mp, ETHER_ALIGN); 3463 #endif 3464 if (adapter->fmp != NULL) { 3465 m_freem(adapter->fmp); 3466 adapter->fmp = NULL; 3467 adapter->lmp = NULL; 3468 } 3469 m = NULL; 3470 } 3471 3472 /* Zero out the receive descriptors status. */ 3473 current_desc->status = 0; 3474 3475 if (m != NULL) 3476 ifp->if_input(ifp, m); 3477 3478 /* Advance our pointers to the next descriptor. */ 3479 if (++i == adapter->num_rx_desc) 3480 i = 0; 3481 current_desc = &adapter->rx_desc_base[i]; 3482 } 3483 adapter->next_rx_desc_to_check = i; 3484 3485 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3486 if (--i < 0) 3487 i = adapter->num_rx_desc - 1; 3488 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 3489 } 3490 3491 static void 3492 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc, 3493 struct mbuf *mp) 3494 { 3495 /* 82543 or newer only */ 3496 if (adapter->hw.mac.type < e1000_82543 || 3497 /* Ignore Checksum bit is set */ 3498 (rx_desc->status & E1000_RXD_STAT_IXSM)) 3499 return; 3500 3501 if ((rx_desc->status & E1000_RXD_STAT_IPCS) && 3502 !(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3503 /* IP Checksum Good */ 3504 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 3505 } 3506 3507 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) && 3508 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3509 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3510 CSUM_PSEUDO_HDR | 3511 CSUM_FRAG_NOT_CHECKED; 3512 mp->m_pkthdr.csum_data = htons(0xffff); 3513 } 3514 } 3515 3516 static void 3517 em_enable_intr(struct adapter *adapter) 3518 { 3519 uint32_t ims_mask = IMS_ENABLE_MASK; 3520 3521 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer); 3522 3523 #if 0 3524 /* XXX MSIX */ 3525 if (adapter->hw.mac.type == e1000_82574) { 3526 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK); 3527 ims_mask |= EM_MSIX_MASK; 3528 } 3529 #endif 3530 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask); 3531 } 3532 3533 static void 3534 em_disable_intr(struct adapter *adapter) 3535 { 3536 uint32_t clear = 0xffffffff; 3537 3538 /* 3539 * The first version of 82542 had an errata where when link was forced 3540 * it would stay up even up even if the cable was disconnected. 3541 * Sequence errors were used to detect the disconnect and then the 3542 * driver would unforce the link. This code in the in the ISR. For 3543 * this to work correctly the Sequence error interrupt had to be 3544 * enabled all the time. 3545 */ 3546 if (adapter->hw.mac.type == e1000_82542 && 3547 adapter->hw.revision_id == E1000_REVISION_2) 3548 clear &= ~E1000_ICR_RXSEQ; 3549 else if (adapter->hw.mac.type == e1000_82574) 3550 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0); 3551 3552 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear); 3553 3554 adapter->npoll.ifpc_stcount = 0; 3555 3556 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer); 3557 } 3558 3559 /* 3560 * Bit of a misnomer, what this really means is 3561 * to enable OS management of the system... aka 3562 * to disable special hardware management features 3563 */ 3564 static void 3565 em_get_mgmt(struct adapter *adapter) 3566 { 3567 /* A shared code workaround */ 3568 #define E1000_82542_MANC2H E1000_MANC2H 3569 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3570 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3571 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3572 3573 /* disable hardware interception of ARP */ 3574 manc &= ~(E1000_MANC_ARP_EN); 3575 3576 /* enable receiving management packets to the host */ 3577 if (adapter->hw.mac.type >= e1000_82571) { 3578 manc |= E1000_MANC_EN_MNG2HOST; 3579 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3580 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3581 manc2h |= E1000_MNG2HOST_PORT_623; 3582 manc2h |= E1000_MNG2HOST_PORT_664; 3583 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3584 } 3585 3586 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3587 } 3588 } 3589 3590 /* 3591 * Give control back to hardware management 3592 * controller if there is one. 3593 */ 3594 static void 3595 em_rel_mgmt(struct adapter *adapter) 3596 { 3597 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3598 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3599 3600 /* re-enable hardware interception of ARP */ 3601 manc |= E1000_MANC_ARP_EN; 3602 3603 if (adapter->hw.mac.type >= e1000_82571) 3604 manc &= ~E1000_MANC_EN_MNG2HOST; 3605 3606 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3607 } 3608 } 3609 3610 /* 3611 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3612 * For ASF and Pass Through versions of f/w this means that 3613 * the driver is loaded. For AMT version (only with 82573) 3614 * of the f/w this means that the network i/f is open. 3615 */ 3616 static void 3617 em_get_hw_control(struct adapter *adapter) 3618 { 3619 /* Let firmware know the driver has taken over */ 3620 if (adapter->hw.mac.type == e1000_82573) { 3621 uint32_t swsm; 3622 3623 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3624 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3625 swsm | E1000_SWSM_DRV_LOAD); 3626 } else { 3627 uint32_t ctrl_ext; 3628 3629 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3630 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3631 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3632 } 3633 adapter->flags |= EM_FLAG_HW_CTRL; 3634 } 3635 3636 /* 3637 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3638 * For ASF and Pass Through versions of f/w this means that the 3639 * driver is no longer loaded. For AMT version (only with 82573) 3640 * of the f/w this means that the network i/f is closed. 3641 */ 3642 static void 3643 em_rel_hw_control(struct adapter *adapter) 3644 { 3645 if ((adapter->flags & EM_FLAG_HW_CTRL) == 0) 3646 return; 3647 adapter->flags &= ~EM_FLAG_HW_CTRL; 3648 3649 /* Let firmware taken over control of h/w */ 3650 if (adapter->hw.mac.type == e1000_82573) { 3651 uint32_t swsm; 3652 3653 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3654 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3655 swsm & ~E1000_SWSM_DRV_LOAD); 3656 } else { 3657 uint32_t ctrl_ext; 3658 3659 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3660 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3661 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3662 } 3663 } 3664 3665 static int 3666 em_is_valid_eaddr(const uint8_t *addr) 3667 { 3668 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3669 3670 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3671 return (FALSE); 3672 3673 return (TRUE); 3674 } 3675 3676 /* 3677 * Enable PCI Wake On Lan capability 3678 */ 3679 void 3680 em_enable_wol(device_t dev) 3681 { 3682 uint16_t cap, status; 3683 uint8_t id; 3684 3685 /* First find the capabilities pointer*/ 3686 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3687 3688 /* Read the PM Capabilities */ 3689 id = pci_read_config(dev, cap, 1); 3690 if (id != PCIY_PMG) /* Something wrong */ 3691 return; 3692 3693 /* 3694 * OK, we have the power capabilities, 3695 * so now get the status register 3696 */ 3697 cap += PCIR_POWER_STATUS; 3698 status = pci_read_config(dev, cap, 2); 3699 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3700 pci_write_config(dev, cap, status, 2); 3701 } 3702 3703 3704 /* 3705 * 82544 Coexistence issue workaround. 3706 * There are 2 issues. 3707 * 1. Transmit Hang issue. 3708 * To detect this issue, following equation can be used... 3709 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3710 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3711 * 3712 * 2. DAC issue. 3713 * To detect this issue, following equation can be used... 3714 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3715 * If SUM[3:0] is in between 9 to c, we will have this issue. 3716 * 3717 * WORKAROUND: 3718 * Make sure we do not have ending address 3719 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3720 */ 3721 static uint32_t 3722 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array) 3723 { 3724 uint32_t safe_terminator; 3725 3726 /* 3727 * Since issue is sensitive to length and address. 3728 * Let us first check the address... 3729 */ 3730 if (length <= 4) { 3731 desc_array->descriptor[0].address = address; 3732 desc_array->descriptor[0].length = length; 3733 desc_array->elements = 1; 3734 return (desc_array->elements); 3735 } 3736 3737 safe_terminator = 3738 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3739 3740 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3741 if (safe_terminator == 0 || 3742 (safe_terminator > 4 && safe_terminator < 9) || 3743 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 3744 desc_array->descriptor[0].address = address; 3745 desc_array->descriptor[0].length = length; 3746 desc_array->elements = 1; 3747 return (desc_array->elements); 3748 } 3749 3750 desc_array->descriptor[0].address = address; 3751 desc_array->descriptor[0].length = length - 4; 3752 desc_array->descriptor[1].address = address + (length - 4); 3753 desc_array->descriptor[1].length = 4; 3754 desc_array->elements = 2; 3755 return (desc_array->elements); 3756 } 3757 3758 static void 3759 em_update_stats(struct adapter *adapter) 3760 { 3761 struct ifnet *ifp = &adapter->arpcom.ac_if; 3762 3763 if (adapter->hw.phy.media_type == e1000_media_type_copper || 3764 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3765 adapter->stats.symerrs += 3766 E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3767 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3768 } 3769 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3770 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3771 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3772 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3773 3774 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3775 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3776 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3777 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3778 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3779 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3780 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3781 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3782 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3783 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3784 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3785 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3786 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3787 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3788 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3789 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3790 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3791 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3792 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3793 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3794 3795 /* For the 64-bit byte counters the low dword must be read first. */ 3796 /* Both registers clear on the read of the high dword */ 3797 3798 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 3799 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 3800 3801 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3802 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3803 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3804 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3805 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3806 3807 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3808 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3809 3810 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3811 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3812 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3813 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3814 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3815 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3816 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3817 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3818 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3819 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3820 3821 if (adapter->hw.mac.type >= e1000_82543) { 3822 adapter->stats.algnerrc += 3823 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3824 adapter->stats.rxerrc += 3825 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3826 adapter->stats.tncrs += 3827 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3828 adapter->stats.cexterr += 3829 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3830 adapter->stats.tsctc += 3831 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3832 adapter->stats.tsctfc += 3833 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3834 } 3835 3836 ifp->if_collisions = adapter->stats.colc; 3837 3838 /* Rx Errors */ 3839 ifp->if_ierrors = 3840 adapter->dropped_pkts + adapter->stats.rxerrc + 3841 adapter->stats.crcerrs + adapter->stats.algnerrc + 3842 adapter->stats.ruc + adapter->stats.roc + 3843 adapter->stats.mpc + adapter->stats.cexterr; 3844 3845 /* Tx Errors */ 3846 ifp->if_oerrors = 3847 adapter->stats.ecol + adapter->stats.latecol + 3848 adapter->watchdog_events; 3849 } 3850 3851 static void 3852 em_print_debug_info(struct adapter *adapter) 3853 { 3854 device_t dev = adapter->dev; 3855 uint8_t *hw_addr = adapter->hw.hw_addr; 3856 3857 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3858 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3859 E1000_READ_REG(&adapter->hw, E1000_CTRL), 3860 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 3861 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3862 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3863 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 3864 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3865 adapter->hw.fc.high_water, 3866 adapter->hw.fc.low_water); 3867 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3868 E1000_READ_REG(&adapter->hw, E1000_TIDV), 3869 E1000_READ_REG(&adapter->hw, E1000_TADV)); 3870 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3871 E1000_READ_REG(&adapter->hw, E1000_RDTR), 3872 E1000_READ_REG(&adapter->hw, E1000_RADV)); 3873 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3874 (long long)adapter->tx_fifo_wrk_cnt, 3875 (long long)adapter->tx_fifo_reset_cnt); 3876 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3877 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 3878 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 3879 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3880 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 3881 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 3882 device_printf(dev, "Num Tx descriptors avail = %d\n", 3883 adapter->num_tx_desc_avail); 3884 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3885 adapter->no_tx_desc_avail1); 3886 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3887 adapter->no_tx_desc_avail2); 3888 device_printf(dev, "Std mbuf failed = %ld\n", 3889 adapter->mbuf_alloc_failed); 3890 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3891 adapter->mbuf_cluster_failed); 3892 device_printf(dev, "Driver dropped packets = %ld\n", 3893 adapter->dropped_pkts); 3894 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3895 adapter->no_tx_dma_setup); 3896 } 3897 3898 static void 3899 em_print_hw_stats(struct adapter *adapter) 3900 { 3901 device_t dev = adapter->dev; 3902 3903 device_printf(dev, "Excessive collisions = %lld\n", 3904 (long long)adapter->stats.ecol); 3905 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3906 device_printf(dev, "Symbol errors = %lld\n", 3907 (long long)adapter->stats.symerrs); 3908 #endif 3909 device_printf(dev, "Sequence errors = %lld\n", 3910 (long long)adapter->stats.sec); 3911 device_printf(dev, "Defer count = %lld\n", 3912 (long long)adapter->stats.dc); 3913 device_printf(dev, "Missed Packets = %lld\n", 3914 (long long)adapter->stats.mpc); 3915 device_printf(dev, "Receive No Buffers = %lld\n", 3916 (long long)adapter->stats.rnbc); 3917 /* RLEC is inaccurate on some hardware, calculate our own. */ 3918 device_printf(dev, "Receive Length Errors = %lld\n", 3919 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 3920 device_printf(dev, "Receive errors = %lld\n", 3921 (long long)adapter->stats.rxerrc); 3922 device_printf(dev, "Crc errors = %lld\n", 3923 (long long)adapter->stats.crcerrs); 3924 device_printf(dev, "Alignment errors = %lld\n", 3925 (long long)adapter->stats.algnerrc); 3926 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3927 (long long)adapter->stats.cexterr); 3928 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 3929 device_printf(dev, "watchdog timeouts = %ld\n", 3930 adapter->watchdog_events); 3931 device_printf(dev, "XON Rcvd = %lld\n", 3932 (long long)adapter->stats.xonrxc); 3933 device_printf(dev, "XON Xmtd = %lld\n", 3934 (long long)adapter->stats.xontxc); 3935 device_printf(dev, "XOFF Rcvd = %lld\n", 3936 (long long)adapter->stats.xoffrxc); 3937 device_printf(dev, "XOFF Xmtd = %lld\n", 3938 (long long)adapter->stats.xofftxc); 3939 device_printf(dev, "Good Packets Rcvd = %lld\n", 3940 (long long)adapter->stats.gprc); 3941 device_printf(dev, "Good Packets Xmtd = %lld\n", 3942 (long long)adapter->stats.gptc); 3943 } 3944 3945 static void 3946 em_print_nvm_info(struct adapter *adapter) 3947 { 3948 uint16_t eeprom_data; 3949 int i, j, row = 0; 3950 3951 /* Its a bit crude, but it gets the job done */ 3952 kprintf("\nInterface EEPROM Dump:\n"); 3953 kprintf("Offset\n0x0000 "); 3954 for (i = 0, j = 0; i < 32; i++, j++) { 3955 if (j == 8) { /* Make the offset block */ 3956 j = 0; ++row; 3957 kprintf("\n0x00%x0 ",row); 3958 } 3959 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 3960 kprintf("%04x ", eeprom_data); 3961 } 3962 kprintf("\n"); 3963 } 3964 3965 static int 3966 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3967 { 3968 struct adapter *adapter; 3969 struct ifnet *ifp; 3970 int error, result; 3971 3972 result = -1; 3973 error = sysctl_handle_int(oidp, &result, 0, req); 3974 if (error || !req->newptr) 3975 return (error); 3976 3977 adapter = (struct adapter *)arg1; 3978 ifp = &adapter->arpcom.ac_if; 3979 3980 lwkt_serialize_enter(ifp->if_serializer); 3981 3982 if (result == 1) 3983 em_print_debug_info(adapter); 3984 3985 /* 3986 * This value will cause a hex dump of the 3987 * first 32 16-bit words of the EEPROM to 3988 * the screen. 3989 */ 3990 if (result == 2) 3991 em_print_nvm_info(adapter); 3992 3993 lwkt_serialize_exit(ifp->if_serializer); 3994 3995 return (error); 3996 } 3997 3998 static int 3999 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 4000 { 4001 int error, result; 4002 4003 result = -1; 4004 error = sysctl_handle_int(oidp, &result, 0, req); 4005 if (error || !req->newptr) 4006 return (error); 4007 4008 if (result == 1) { 4009 struct adapter *adapter = (struct adapter *)arg1; 4010 struct ifnet *ifp = &adapter->arpcom.ac_if; 4011 4012 lwkt_serialize_enter(ifp->if_serializer); 4013 em_print_hw_stats(adapter); 4014 lwkt_serialize_exit(ifp->if_serializer); 4015 } 4016 return (error); 4017 } 4018 4019 static void 4020 em_add_sysctl(struct adapter *adapter) 4021 { 4022 sysctl_ctx_init(&adapter->sysctl_ctx); 4023 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx, 4024 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 4025 device_get_nameunit(adapter->dev), 4026 CTLFLAG_RD, 0, ""); 4027 if (adapter->sysctl_tree == NULL) { 4028 device_printf(adapter->dev, "can't add sysctl node\n"); 4029 } else { 4030 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4031 SYSCTL_CHILDREN(adapter->sysctl_tree), 4032 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4033 em_sysctl_debug_info, "I", "Debug Information"); 4034 4035 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4036 SYSCTL_CHILDREN(adapter->sysctl_tree), 4037 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4038 em_sysctl_stats, "I", "Statistics"); 4039 4040 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4041 SYSCTL_CHILDREN(adapter->sysctl_tree), 4042 OID_AUTO, "rxd", CTLFLAG_RD, 4043 &adapter->num_rx_desc, 0, NULL); 4044 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4045 SYSCTL_CHILDREN(adapter->sysctl_tree), 4046 OID_AUTO, "txd", CTLFLAG_RD, 4047 &adapter->num_tx_desc, 0, NULL); 4048 4049 if (adapter->hw.mac.type >= e1000_82540) { 4050 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4051 SYSCTL_CHILDREN(adapter->sysctl_tree), 4052 OID_AUTO, "int_throttle_ceil", 4053 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4054 em_sysctl_int_throttle, "I", 4055 "interrupt throttling rate"); 4056 } 4057 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4058 SYSCTL_CHILDREN(adapter->sysctl_tree), 4059 OID_AUTO, "int_tx_nsegs", 4060 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4061 em_sysctl_int_tx_nsegs, "I", 4062 "# segments per TX interrupt"); 4063 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4064 SYSCTL_CHILDREN(adapter->sysctl_tree), 4065 OID_AUTO, "wreg_tx_nsegs", CTLFLAG_RW, 4066 &adapter->tx_wreg_nsegs, 0, 4067 "# segments before write to hardware register"); 4068 } 4069 } 4070 4071 static int 4072 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 4073 { 4074 struct adapter *adapter = (void *)arg1; 4075 struct ifnet *ifp = &adapter->arpcom.ac_if; 4076 int error, throttle; 4077 4078 throttle = adapter->int_throttle_ceil; 4079 error = sysctl_handle_int(oidp, &throttle, 0, req); 4080 if (error || req->newptr == NULL) 4081 return error; 4082 if (throttle < 0 || throttle > 1000000000 / 256) 4083 return EINVAL; 4084 4085 if (throttle) { 4086 /* 4087 * Set the interrupt throttling rate in 256ns increments, 4088 * recalculate sysctl value assignment to get exact frequency. 4089 */ 4090 throttle = 1000000000 / 256 / throttle; 4091 4092 /* Upper 16bits of ITR is reserved and should be zero */ 4093 if (throttle & 0xffff0000) 4094 return EINVAL; 4095 } 4096 4097 lwkt_serialize_enter(ifp->if_serializer); 4098 4099 if (throttle) 4100 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 4101 else 4102 adapter->int_throttle_ceil = 0; 4103 4104 if (ifp->if_flags & IFF_RUNNING) 4105 em_set_itr(adapter, throttle); 4106 4107 lwkt_serialize_exit(ifp->if_serializer); 4108 4109 if (bootverbose) { 4110 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 4111 adapter->int_throttle_ceil); 4112 } 4113 return 0; 4114 } 4115 4116 static int 4117 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 4118 { 4119 struct adapter *adapter = (void *)arg1; 4120 struct ifnet *ifp = &adapter->arpcom.ac_if; 4121 int error, segs; 4122 4123 segs = adapter->tx_int_nsegs; 4124 error = sysctl_handle_int(oidp, &segs, 0, req); 4125 if (error || req->newptr == NULL) 4126 return error; 4127 if (segs <= 0) 4128 return EINVAL; 4129 4130 lwkt_serialize_enter(ifp->if_serializer); 4131 4132 /* 4133 * Don't allow int_tx_nsegs to become: 4134 * o Less the oact_tx_desc 4135 * o Too large that no TX desc will cause TX interrupt to 4136 * be generated (OACTIVE will never recover) 4137 * o Too small that will cause tx_dd[] overflow 4138 */ 4139 if (segs < adapter->oact_tx_desc || 4140 segs >= adapter->num_tx_desc - adapter->oact_tx_desc || 4141 segs < adapter->num_tx_desc / EM_TXDD_SAFE) { 4142 error = EINVAL; 4143 } else { 4144 error = 0; 4145 adapter->tx_int_nsegs = segs; 4146 } 4147 4148 lwkt_serialize_exit(ifp->if_serializer); 4149 4150 return error; 4151 } 4152 4153 static void 4154 em_set_itr(struct adapter *adapter, uint32_t itr) 4155 { 4156 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr); 4157 if (adapter->hw.mac.type == e1000_82574) { 4158 int i; 4159 4160 /* 4161 * When using MSIX interrupts we need to 4162 * throttle using the EITR register 4163 */ 4164 for (i = 0; i < 4; ++i) { 4165 E1000_WRITE_REG(&adapter->hw, 4166 E1000_EITR_82574(i), itr); 4167 } 4168 } 4169 } 4170 4171 static void 4172 em_disable_aspm(struct adapter *adapter) 4173 { 4174 uint16_t link_cap, link_ctrl, disable; 4175 uint8_t pcie_ptr, reg; 4176 device_t dev = adapter->dev; 4177 4178 switch (adapter->hw.mac.type) { 4179 case e1000_82571: 4180 case e1000_82572: 4181 case e1000_82573: 4182 /* 4183 * 82573 specification update 4184 * errata #8 disable L0s 4185 * errata #41 disable L1 4186 * 4187 * 82571/82572 specification update 4188 # errata #13 disable L1 4189 * errata #68 disable L0s 4190 */ 4191 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 4192 break; 4193 4194 case e1000_82574: 4195 case e1000_82583: 4196 /* 4197 * 82574 specification update errata #20 4198 * 82583 specification update errata #9 4199 * 4200 * There is no need to disable L1 4201 */ 4202 disable = PCIEM_LNKCTL_ASPM_L0S; 4203 break; 4204 4205 default: 4206 return; 4207 } 4208 4209 pcie_ptr = pci_get_pciecap_ptr(dev); 4210 if (pcie_ptr == 0) 4211 return; 4212 4213 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 4214 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 4215 return; 4216 4217 if (bootverbose) { 4218 if_printf(&adapter->arpcom.ac_if, 4219 "disable ASPM %#02x\n", disable); 4220 } 4221 4222 reg = pcie_ptr + PCIER_LINKCTRL; 4223 link_ctrl = pci_read_config(dev, reg, 2); 4224 link_ctrl &= ~disable; 4225 pci_write_config(dev, reg, link_ctrl, 2); 4226 } 4227 4228 static int 4229 em_tso_pullup(struct adapter *adapter, struct mbuf **mp) 4230 { 4231 int iphlen, hoff, thoff, ex = 0; 4232 struct mbuf *m; 4233 struct ip *ip; 4234 4235 m = *mp; 4236 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 4237 4238 iphlen = m->m_pkthdr.csum_iphlen; 4239 thoff = m->m_pkthdr.csum_thlen; 4240 hoff = m->m_pkthdr.csum_lhlen; 4241 4242 KASSERT(iphlen > 0, ("invalid ip hlen")); 4243 KASSERT(thoff > 0, ("invalid tcp hlen")); 4244 KASSERT(hoff > 0, ("invalid ether hlen")); 4245 4246 if (adapter->flags & EM_FLAG_TSO_PULLEX) 4247 ex = 4; 4248 4249 if (m->m_len < hoff + iphlen + thoff + ex) { 4250 m = m_pullup(m, hoff + iphlen + thoff + ex); 4251 if (m == NULL) { 4252 *mp = NULL; 4253 return ENOBUFS; 4254 } 4255 *mp = m; 4256 } 4257 ip = mtodoff(m, struct ip *, hoff); 4258 ip->ip_len = 0; 4259 4260 return 0; 4261 } 4262 4263 static int 4264 em_tso_setup(struct adapter *adapter, struct mbuf *mp, 4265 uint32_t *txd_upper, uint32_t *txd_lower) 4266 { 4267 struct e1000_context_desc *TXD; 4268 int hoff, iphlen, thoff, hlen; 4269 int mss, pktlen, curr_txd; 4270 4271 iphlen = mp->m_pkthdr.csum_iphlen; 4272 thoff = mp->m_pkthdr.csum_thlen; 4273 hoff = mp->m_pkthdr.csum_lhlen; 4274 mss = mp->m_pkthdr.tso_segsz; 4275 pktlen = mp->m_pkthdr.len; 4276 4277 if (adapter->csum_flags == CSUM_TSO && 4278 adapter->csum_iphlen == iphlen && 4279 adapter->csum_lhlen == hoff && 4280 adapter->csum_thlen == thoff && 4281 adapter->csum_mss == mss && 4282 adapter->csum_pktlen == pktlen) { 4283 *txd_upper = adapter->csum_txd_upper; 4284 *txd_lower = adapter->csum_txd_lower; 4285 return 0; 4286 } 4287 hlen = hoff + iphlen + thoff; 4288 4289 /* 4290 * Setup a new TSO context. 4291 */ 4292 4293 curr_txd = adapter->next_avail_tx_desc; 4294 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 4295 4296 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 4297 E1000_TXD_DTYP_D | /* Data descr type */ 4298 E1000_TXD_CMD_TSE; /* Do TSE on this packet */ 4299 4300 /* IP and/or TCP header checksum calculation and insertion. */ 4301 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 4302 4303 /* 4304 * Start offset for header checksum calculation. 4305 * End offset for header checksum calculation. 4306 * Offset of place put the checksum. 4307 */ 4308 TXD->lower_setup.ip_fields.ipcss = hoff; 4309 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1); 4310 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum); 4311 4312 /* 4313 * Start offset for payload checksum calculation. 4314 * End offset for payload checksum calculation. 4315 * Offset of place to put the checksum. 4316 */ 4317 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen; 4318 TXD->upper_setup.tcp_fields.tucse = 0; 4319 TXD->upper_setup.tcp_fields.tucso = 4320 hoff + iphlen + offsetof(struct tcphdr, th_sum); 4321 4322 /* 4323 * Payload size per packet w/o any headers. 4324 * Length of all headers up to payload. 4325 */ 4326 TXD->tcp_seg_setup.fields.mss = htole16(mss); 4327 TXD->tcp_seg_setup.fields.hdr_len = hlen; 4328 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS | 4329 E1000_TXD_CMD_DEXT | /* Extended descr */ 4330 E1000_TXD_CMD_TSE | /* TSE context */ 4331 E1000_TXD_CMD_IP | /* Do IP csum */ 4332 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 4333 (pktlen - hlen)); /* Total len */ 4334 4335 /* Save the information for this TSO context */ 4336 adapter->csum_flags = CSUM_TSO; 4337 adapter->csum_lhlen = hoff; 4338 adapter->csum_iphlen = iphlen; 4339 adapter->csum_thlen = thoff; 4340 adapter->csum_mss = mss; 4341 adapter->csum_pktlen = pktlen; 4342 adapter->csum_txd_upper = *txd_upper; 4343 adapter->csum_txd_lower = *txd_lower; 4344 4345 if (++curr_txd == adapter->num_tx_desc) 4346 curr_txd = 0; 4347 4348 KKASSERT(adapter->num_tx_desc_avail > 0); 4349 adapter->num_tx_desc_avail--; 4350 4351 adapter->next_avail_tx_desc = curr_txd; 4352 return 1; 4353 } 4354