1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 */ 67 /* 68 * SERIALIZATION API RULES: 69 * 70 * - We must call lwkt_serialize_handler_enable() prior to enabling the 71 * hardware interrupt and lwkt_serialize_handler_disable() after disabling 72 * the hardware interrupt in order to avoid handler execution races from 73 * scheduled interrupt threads. 74 */ 75 76 #include "opt_ifpoll.h" 77 78 #include <sys/param.h> 79 #include <sys/bus.h> 80 #include <sys/endian.h> 81 #include <sys/interrupt.h> 82 #include <sys/kernel.h> 83 #include <sys/ktr.h> 84 #include <sys/malloc.h> 85 #include <sys/mbuf.h> 86 #include <sys/proc.h> 87 #include <sys/rman.h> 88 #include <sys/serialize.h> 89 #include <sys/socket.h> 90 #include <sys/sockio.h> 91 #include <sys/sysctl.h> 92 #include <sys/systm.h> 93 94 #include <net/bpf.h> 95 #include <net/ethernet.h> 96 #include <net/if.h> 97 #include <net/if_arp.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_poll.h> 101 #include <net/ifq_var.h> 102 #include <net/vlan/if_vlan_var.h> 103 #include <net/vlan/if_vlan_ether.h> 104 105 #include <netinet/ip.h> 106 #include <netinet/tcp.h> 107 #include <netinet/udp.h> 108 109 #include <bus/pci/pcivar.h> 110 #include <bus/pci/pcireg.h> 111 112 #include <dev/netif/ig_hal/e1000_api.h> 113 #include <dev/netif/ig_hal/e1000_82571.h> 114 #include <dev/netif/em/if_em.h> 115 116 #define DEBUG_HW 0 117 118 #define EM_NAME "Intel(R) PRO/1000 Network Connection " 119 #define EM_VER " 7.3.8" 120 121 #define _EM_DEVICE(id, ret) \ 122 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER } 123 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100) 124 #define EM_DEVICE(id) _EM_DEVICE(id, 0) 125 #define EM_DEVICE_NULL { 0, 0, 0, NULL } 126 127 static const struct em_vendor_info em_vendor_info_array[] = { 128 EM_DEVICE(82540EM), 129 EM_DEVICE(82540EM_LOM), 130 EM_DEVICE(82540EP), 131 EM_DEVICE(82540EP_LOM), 132 EM_DEVICE(82540EP_LP), 133 134 EM_DEVICE(82541EI), 135 EM_DEVICE(82541ER), 136 EM_DEVICE(82541ER_LOM), 137 EM_DEVICE(82541EI_MOBILE), 138 EM_DEVICE(82541GI), 139 EM_DEVICE(82541GI_LF), 140 EM_DEVICE(82541GI_MOBILE), 141 142 EM_DEVICE(82542), 143 144 EM_DEVICE(82543GC_FIBER), 145 EM_DEVICE(82543GC_COPPER), 146 147 EM_DEVICE(82544EI_COPPER), 148 EM_DEVICE(82544EI_FIBER), 149 EM_DEVICE(82544GC_COPPER), 150 EM_DEVICE(82544GC_LOM), 151 152 EM_DEVICE(82545EM_COPPER), 153 EM_DEVICE(82545EM_FIBER), 154 EM_DEVICE(82545GM_COPPER), 155 EM_DEVICE(82545GM_FIBER), 156 EM_DEVICE(82545GM_SERDES), 157 158 EM_DEVICE(82546EB_COPPER), 159 EM_DEVICE(82546EB_FIBER), 160 EM_DEVICE(82546EB_QUAD_COPPER), 161 EM_DEVICE(82546GB_COPPER), 162 EM_DEVICE(82546GB_FIBER), 163 EM_DEVICE(82546GB_SERDES), 164 EM_DEVICE(82546GB_PCIE), 165 EM_DEVICE(82546GB_QUAD_COPPER), 166 EM_DEVICE(82546GB_QUAD_COPPER_KSP3), 167 168 EM_DEVICE(82547EI), 169 EM_DEVICE(82547EI_MOBILE), 170 EM_DEVICE(82547GI), 171 172 EM_EMX_DEVICE(82571EB_COPPER), 173 EM_EMX_DEVICE(82571EB_FIBER), 174 EM_EMX_DEVICE(82571EB_SERDES), 175 EM_EMX_DEVICE(82571EB_SERDES_DUAL), 176 EM_EMX_DEVICE(82571EB_SERDES_QUAD), 177 EM_EMX_DEVICE(82571EB_QUAD_COPPER), 178 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP), 179 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP), 180 EM_EMX_DEVICE(82571EB_QUAD_FIBER), 181 EM_EMX_DEVICE(82571PT_QUAD_COPPER), 182 183 EM_EMX_DEVICE(82572EI_COPPER), 184 EM_EMX_DEVICE(82572EI_FIBER), 185 EM_EMX_DEVICE(82572EI_SERDES), 186 EM_EMX_DEVICE(82572EI), 187 188 EM_EMX_DEVICE(82573E), 189 EM_EMX_DEVICE(82573E_IAMT), 190 EM_EMX_DEVICE(82573L), 191 192 EM_DEVICE(82583V), 193 194 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT), 195 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT), 196 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT), 197 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT), 198 199 EM_DEVICE(ICH8_IGP_M_AMT), 200 EM_DEVICE(ICH8_IGP_AMT), 201 EM_DEVICE(ICH8_IGP_C), 202 EM_DEVICE(ICH8_IFE), 203 EM_DEVICE(ICH8_IFE_GT), 204 EM_DEVICE(ICH8_IFE_G), 205 EM_DEVICE(ICH8_IGP_M), 206 EM_DEVICE(ICH8_82567V_3), 207 208 EM_DEVICE(ICH9_IGP_M_AMT), 209 EM_DEVICE(ICH9_IGP_AMT), 210 EM_DEVICE(ICH9_IGP_C), 211 EM_DEVICE(ICH9_IGP_M), 212 EM_DEVICE(ICH9_IGP_M_V), 213 EM_DEVICE(ICH9_IFE), 214 EM_DEVICE(ICH9_IFE_GT), 215 EM_DEVICE(ICH9_IFE_G), 216 EM_DEVICE(ICH9_BM), 217 218 EM_EMX_DEVICE(82574L), 219 EM_EMX_DEVICE(82574LA), 220 221 EM_DEVICE(ICH10_R_BM_LM), 222 EM_DEVICE(ICH10_R_BM_LF), 223 EM_DEVICE(ICH10_R_BM_V), 224 EM_DEVICE(ICH10_D_BM_LM), 225 EM_DEVICE(ICH10_D_BM_LF), 226 EM_DEVICE(ICH10_D_BM_V), 227 228 EM_DEVICE(PCH_M_HV_LM), 229 EM_DEVICE(PCH_M_HV_LC), 230 EM_DEVICE(PCH_D_HV_DM), 231 EM_DEVICE(PCH_D_HV_DC), 232 233 EM_DEVICE(PCH2_LV_LM), 234 EM_DEVICE(PCH2_LV_V), 235 236 EM_DEVICE(PCH_LPT_I217_LM), 237 EM_DEVICE(PCH_LPT_I217_V), 238 EM_DEVICE(PCH_LPTLP_I218_LM), 239 EM_DEVICE(PCH_LPTLP_I218_V), 240 241 /* required last entry */ 242 EM_DEVICE_NULL 243 }; 244 245 static int em_probe(device_t); 246 static int em_attach(device_t); 247 static int em_detach(device_t); 248 static int em_shutdown(device_t); 249 static int em_suspend(device_t); 250 static int em_resume(device_t); 251 252 static void em_init(void *); 253 static void em_stop(struct adapter *); 254 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 255 static void em_start(struct ifnet *, struct ifaltq_subque *); 256 #ifdef IFPOLL_ENABLE 257 static void em_npoll(struct ifnet *, struct ifpoll_info *); 258 static void em_npoll_compat(struct ifnet *, void *, int); 259 #endif 260 static void em_watchdog(struct ifnet *); 261 static void em_media_status(struct ifnet *, struct ifmediareq *); 262 static int em_media_change(struct ifnet *); 263 static void em_timer(void *); 264 265 static void em_intr(void *); 266 static void em_intr_mask(void *); 267 static void em_intr_body(struct adapter *, boolean_t); 268 static void em_rxeof(struct adapter *, int); 269 static void em_txeof(struct adapter *); 270 static void em_tx_collect(struct adapter *); 271 static void em_tx_purge(struct adapter *); 272 static void em_enable_intr(struct adapter *); 273 static void em_disable_intr(struct adapter *); 274 275 static int em_dma_malloc(struct adapter *, bus_size_t, 276 struct em_dma_alloc *); 277 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 278 static void em_init_tx_ring(struct adapter *); 279 static int em_init_rx_ring(struct adapter *); 280 static int em_create_tx_ring(struct adapter *); 281 static int em_create_rx_ring(struct adapter *); 282 static void em_destroy_tx_ring(struct adapter *, int); 283 static void em_destroy_rx_ring(struct adapter *, int); 284 static int em_newbuf(struct adapter *, int, int); 285 static int em_encap(struct adapter *, struct mbuf **, int *, int *); 286 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *, 287 struct mbuf *); 288 static int em_txcsum(struct adapter *, struct mbuf *, 289 uint32_t *, uint32_t *); 290 static int em_tso_pullup(struct adapter *, struct mbuf **); 291 static int em_tso_setup(struct adapter *, struct mbuf *, 292 uint32_t *, uint32_t *); 293 294 static int em_get_hw_info(struct adapter *); 295 static int em_is_valid_eaddr(const uint8_t *); 296 static int em_alloc_pci_res(struct adapter *); 297 static void em_free_pci_res(struct adapter *); 298 static int em_reset(struct adapter *); 299 static void em_setup_ifp(struct adapter *); 300 static void em_init_tx_unit(struct adapter *); 301 static void em_init_rx_unit(struct adapter *); 302 static void em_update_stats(struct adapter *); 303 static void em_set_promisc(struct adapter *); 304 static void em_disable_promisc(struct adapter *); 305 static void em_set_multi(struct adapter *); 306 static void em_update_link_status(struct adapter *); 307 static void em_smartspeed(struct adapter *); 308 static void em_set_itr(struct adapter *, uint32_t); 309 static void em_disable_aspm(struct adapter *); 310 311 /* Hardware workarounds */ 312 static int em_82547_fifo_workaround(struct adapter *, int); 313 static void em_82547_update_fifo_head(struct adapter *, int); 314 static int em_82547_tx_fifo_reset(struct adapter *); 315 static void em_82547_move_tail(void *); 316 static void em_82547_move_tail_serialized(struct adapter *); 317 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY); 318 319 static void em_print_debug_info(struct adapter *); 320 static void em_print_nvm_info(struct adapter *); 321 static void em_print_hw_stats(struct adapter *); 322 323 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 324 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 325 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 326 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 327 static void em_add_sysctl(struct adapter *adapter); 328 329 /* Management and WOL Support */ 330 static void em_get_mgmt(struct adapter *); 331 static void em_rel_mgmt(struct adapter *); 332 static void em_get_hw_control(struct adapter *); 333 static void em_rel_hw_control(struct adapter *); 334 static void em_enable_wol(device_t); 335 336 static device_method_t em_methods[] = { 337 /* Device interface */ 338 DEVMETHOD(device_probe, em_probe), 339 DEVMETHOD(device_attach, em_attach), 340 DEVMETHOD(device_detach, em_detach), 341 DEVMETHOD(device_shutdown, em_shutdown), 342 DEVMETHOD(device_suspend, em_suspend), 343 DEVMETHOD(device_resume, em_resume), 344 DEVMETHOD_END 345 }; 346 347 static driver_t em_driver = { 348 "em", 349 em_methods, 350 sizeof(struct adapter), 351 }; 352 353 static devclass_t em_devclass; 354 355 DECLARE_DUMMY_MODULE(if_em); 356 MODULE_DEPEND(em, ig_hal, 1, 1, 1); 357 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL); 358 359 /* 360 * Tunables 361 */ 362 static int em_int_throttle_ceil = EM_DEFAULT_ITR; 363 static int em_rxd = EM_DEFAULT_RXD; 364 static int em_txd = EM_DEFAULT_TXD; 365 static int em_smart_pwr_down = 0; 366 367 /* Controls whether promiscuous also shows bad packets */ 368 static int em_debug_sbp = FALSE; 369 370 static int em_82573_workaround = 1; 371 static int em_msi_enable = 1; 372 373 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil); 374 TUNABLE_INT("hw.em.rxd", &em_rxd); 375 TUNABLE_INT("hw.em.txd", &em_txd); 376 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 377 TUNABLE_INT("hw.em.sbp", &em_debug_sbp); 378 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround); 379 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable); 380 381 /* Global used in WOL setup with multiport cards */ 382 static int em_global_quad_port_a = 0; 383 384 /* Set this to one to display debug statistics */ 385 static int em_display_debug_stats = 0; 386 387 #if !defined(KTR_IF_EM) 388 #define KTR_IF_EM KTR_ALL 389 #endif 390 KTR_INFO_MASTER(if_em); 391 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin"); 392 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end"); 393 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet"); 394 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet"); 395 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean"); 396 #define logif(name) KTR_LOG(if_em_ ## name) 397 398 static int 399 em_probe(device_t dev) 400 { 401 const struct em_vendor_info *ent; 402 uint16_t vid, did; 403 404 vid = pci_get_vendor(dev); 405 did = pci_get_device(dev); 406 407 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) { 408 if (vid == ent->vendor_id && did == ent->device_id) { 409 device_set_desc(dev, ent->desc); 410 device_set_async_attach(dev, TRUE); 411 return (ent->ret); 412 } 413 } 414 return (ENXIO); 415 } 416 417 static int 418 em_attach(device_t dev) 419 { 420 struct adapter *adapter = device_get_softc(dev); 421 struct ifnet *ifp = &adapter->arpcom.ac_if; 422 int tsize, rsize; 423 int error = 0; 424 uint16_t eeprom_data, device_id, apme_mask; 425 driver_intr_t *intr_func; 426 427 adapter->dev = adapter->osdep.dev = dev; 428 429 callout_init_mp(&adapter->timer); 430 callout_init_mp(&adapter->tx_fifo_timer); 431 432 /* Determine hardware and mac info */ 433 error = em_get_hw_info(adapter); 434 if (error) { 435 device_printf(dev, "Identify hardware failed\n"); 436 goto fail; 437 } 438 439 /* Setup PCI resources */ 440 error = em_alloc_pci_res(adapter); 441 if (error) { 442 device_printf(dev, "Allocation of PCI resources failed\n"); 443 goto fail; 444 } 445 446 /* 447 * For ICH8 and family we need to map the flash memory, 448 * and this must happen after the MAC is identified. 449 */ 450 if (adapter->hw.mac.type == e1000_ich8lan || 451 adapter->hw.mac.type == e1000_ich9lan || 452 adapter->hw.mac.type == e1000_ich10lan || 453 adapter->hw.mac.type == e1000_pchlan || 454 adapter->hw.mac.type == e1000_pch2lan || 455 adapter->hw.mac.type == e1000_pch_lpt) { 456 adapter->flash_rid = EM_BAR_FLASH; 457 458 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 459 &adapter->flash_rid, RF_ACTIVE); 460 if (adapter->flash == NULL) { 461 device_printf(dev, "Mapping of Flash failed\n"); 462 error = ENXIO; 463 goto fail; 464 } 465 adapter->osdep.flash_bus_space_tag = 466 rman_get_bustag(adapter->flash); 467 adapter->osdep.flash_bus_space_handle = 468 rman_get_bushandle(adapter->flash); 469 470 /* 471 * This is used in the shared code 472 * XXX this goof is actually not used. 473 */ 474 adapter->hw.flash_address = (uint8_t *)adapter->flash; 475 } 476 477 switch (adapter->hw.mac.type) { 478 case e1000_82571: 479 case e1000_82572: 480 /* 481 * Pullup extra 4bytes into the first data segment, see: 482 * 82571/82572 specification update errata #7 483 * 484 * NOTE: 485 * 4bytes instead of 2bytes, which are mentioned in the 486 * errata, are pulled; mainly to keep rest of the data 487 * properly aligned. 488 */ 489 adapter->flags |= EM_FLAG_TSO_PULLEX; 490 /* FALL THROUGH */ 491 492 default: 493 if (pci_is_pcie(dev)) 494 adapter->flags |= EM_FLAG_TSO; 495 break; 496 } 497 498 /* Do Shared Code initialization */ 499 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 500 device_printf(dev, "Setup of Shared code failed\n"); 501 error = ENXIO; 502 goto fail; 503 } 504 505 e1000_get_bus_info(&adapter->hw); 506 507 /* 508 * Validate number of transmit and receive descriptors. It 509 * must not exceed hardware maximum, and must be multiple 510 * of E1000_DBA_ALIGN. 511 */ 512 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 || 513 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 514 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 515 em_txd < EM_MIN_TXD) { 516 if (adapter->hw.mac.type < e1000_82544) 517 adapter->num_tx_desc = EM_MAX_TXD_82543; 518 else 519 adapter->num_tx_desc = EM_DEFAULT_TXD; 520 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 521 adapter->num_tx_desc, em_txd); 522 } else { 523 adapter->num_tx_desc = em_txd; 524 } 525 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 || 526 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 527 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 528 em_rxd < EM_MIN_RXD) { 529 if (adapter->hw.mac.type < e1000_82544) 530 adapter->num_rx_desc = EM_MAX_RXD_82543; 531 else 532 adapter->num_rx_desc = EM_DEFAULT_RXD; 533 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 534 adapter->num_rx_desc, em_rxd); 535 } else { 536 adapter->num_rx_desc = em_rxd; 537 } 538 539 adapter->hw.mac.autoneg = DO_AUTO_NEG; 540 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 541 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 542 adapter->rx_buffer_len = MCLBYTES; 543 544 /* 545 * Interrupt throttle rate 546 */ 547 if (em_int_throttle_ceil == 0) { 548 adapter->int_throttle_ceil = 0; 549 } else { 550 int throttle = em_int_throttle_ceil; 551 552 if (throttle < 0) 553 throttle = EM_DEFAULT_ITR; 554 555 /* Recalculate the tunable value to get the exact frequency. */ 556 throttle = 1000000000 / 256 / throttle; 557 558 /* Upper 16bits of ITR is reserved and should be zero */ 559 if (throttle & 0xffff0000) 560 throttle = 1000000000 / 256 / EM_DEFAULT_ITR; 561 562 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 563 } 564 565 e1000_init_script_state_82541(&adapter->hw, TRUE); 566 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 567 568 /* Copper options */ 569 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 570 adapter->hw.phy.mdix = AUTO_ALL_MODES; 571 adapter->hw.phy.disable_polarity_correction = FALSE; 572 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 573 } 574 575 /* Set the frame limits assuming standard ethernet sized frames. */ 576 adapter->hw.mac.max_frame_size = 577 ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 578 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN; 579 580 /* This controls when hardware reports transmit completion status. */ 581 adapter->hw.mac.report_tx_early = 1; 582 583 /* 584 * Create top level busdma tag 585 */ 586 error = bus_dma_tag_create(NULL, 1, 0, 587 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 588 NULL, NULL, 589 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 590 0, &adapter->parent_dtag); 591 if (error) { 592 device_printf(dev, "could not create top level DMA tag\n"); 593 goto fail; 594 } 595 596 /* 597 * Allocate Transmit Descriptor ring 598 */ 599 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 600 EM_DBA_ALIGN); 601 error = em_dma_malloc(adapter, tsize, &adapter->txdma); 602 if (error) { 603 device_printf(dev, "Unable to allocate tx_desc memory\n"); 604 goto fail; 605 } 606 adapter->tx_desc_base = adapter->txdma.dma_vaddr; 607 608 /* 609 * Allocate Receive Descriptor ring 610 */ 611 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 612 EM_DBA_ALIGN); 613 error = em_dma_malloc(adapter, rsize, &adapter->rxdma); 614 if (error) { 615 device_printf(dev, "Unable to allocate rx_desc memory\n"); 616 goto fail; 617 } 618 adapter->rx_desc_base = adapter->rxdma.dma_vaddr; 619 620 /* Allocate multicast array memory. */ 621 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES, 622 M_DEVBUF, M_WAITOK); 623 624 /* Indicate SOL/IDER usage */ 625 if (e1000_check_reset_block(&adapter->hw)) { 626 device_printf(dev, 627 "PHY reset is blocked due to SOL/IDER session.\n"); 628 } 629 630 /* Disable EEE */ 631 adapter->hw.dev_spec.ich8lan.eee_disable = 1; 632 633 /* 634 * Start from a known state, this is important in reading the 635 * nvm and mac from that. 636 */ 637 e1000_reset_hw(&adapter->hw); 638 639 /* Make sure we have a good EEPROM before we read from it */ 640 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 641 /* 642 * Some PCI-E parts fail the first check due to 643 * the link being in sleep state, call it again, 644 * if it fails a second time its a real issue. 645 */ 646 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 647 device_printf(dev, 648 "The EEPROM Checksum Is Not Valid\n"); 649 error = EIO; 650 goto fail; 651 } 652 } 653 654 /* Copy the permanent MAC address out of the EEPROM */ 655 if (e1000_read_mac_addr(&adapter->hw) < 0) { 656 device_printf(dev, "EEPROM read error while reading MAC" 657 " address\n"); 658 error = EIO; 659 goto fail; 660 } 661 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) { 662 device_printf(dev, "Invalid MAC address\n"); 663 error = EIO; 664 goto fail; 665 } 666 667 /* Allocate transmit descriptors and buffers */ 668 error = em_create_tx_ring(adapter); 669 if (error) { 670 device_printf(dev, "Could not setup transmit structures\n"); 671 goto fail; 672 } 673 674 /* Allocate receive descriptors and buffers */ 675 error = em_create_rx_ring(adapter); 676 if (error) { 677 device_printf(dev, "Could not setup receive structures\n"); 678 goto fail; 679 } 680 681 /* Manually turn off all interrupts */ 682 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 683 684 /* Determine if we have to control management hardware */ 685 if (e1000_enable_mng_pass_thru(&adapter->hw)) 686 adapter->flags |= EM_FLAG_HAS_MGMT; 687 688 /* 689 * Setup Wake-on-Lan 690 */ 691 apme_mask = EM_EEPROM_APME; 692 eeprom_data = 0; 693 switch (adapter->hw.mac.type) { 694 case e1000_82542: 695 case e1000_82543: 696 break; 697 698 case e1000_82573: 699 case e1000_82583: 700 adapter->flags |= EM_FLAG_HAS_AMT; 701 /* FALL THROUGH */ 702 703 case e1000_82546: 704 case e1000_82546_rev_3: 705 case e1000_82571: 706 case e1000_82572: 707 case e1000_80003es2lan: 708 if (adapter->hw.bus.func == 1) { 709 e1000_read_nvm(&adapter->hw, 710 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 711 } else { 712 e1000_read_nvm(&adapter->hw, 713 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 714 } 715 break; 716 717 case e1000_ich8lan: 718 case e1000_ich9lan: 719 case e1000_ich10lan: 720 case e1000_pchlan: 721 case e1000_pch2lan: 722 apme_mask = E1000_WUC_APME; 723 adapter->flags |= EM_FLAG_HAS_AMT; 724 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 725 break; 726 727 default: 728 e1000_read_nvm(&adapter->hw, 729 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 730 break; 731 } 732 if (eeprom_data & apme_mask) 733 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 734 735 /* 736 * We have the eeprom settings, now apply the special cases 737 * where the eeprom may be wrong or the board won't support 738 * wake on lan on a particular port 739 */ 740 device_id = pci_get_device(dev); 741 switch (device_id) { 742 case E1000_DEV_ID_82546GB_PCIE: 743 adapter->wol = 0; 744 break; 745 746 case E1000_DEV_ID_82546EB_FIBER: 747 case E1000_DEV_ID_82546GB_FIBER: 748 case E1000_DEV_ID_82571EB_FIBER: 749 /* 750 * Wake events only supported on port A for dual fiber 751 * regardless of eeprom setting 752 */ 753 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 754 E1000_STATUS_FUNC_1) 755 adapter->wol = 0; 756 break; 757 758 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 759 case E1000_DEV_ID_82571EB_QUAD_COPPER: 760 case E1000_DEV_ID_82571EB_QUAD_FIBER: 761 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 762 /* if quad port adapter, disable WoL on all but port A */ 763 if (em_global_quad_port_a != 0) 764 adapter->wol = 0; 765 /* Reset for multiple quad port adapters */ 766 if (++em_global_quad_port_a == 4) 767 em_global_quad_port_a = 0; 768 break; 769 } 770 771 /* XXX disable wol */ 772 adapter->wol = 0; 773 774 /* Setup OS specific network interface */ 775 em_setup_ifp(adapter); 776 777 /* Add sysctl tree, must after em_setup_ifp() */ 778 em_add_sysctl(adapter); 779 780 #ifdef IFPOLL_ENABLE 781 /* Polling setup */ 782 ifpoll_compat_setup(&adapter->npoll, 783 &adapter->sysctl_ctx, adapter->sysctl_tree, device_get_unit(dev), 784 ifp->if_serializer); 785 #endif 786 787 /* Reset the hardware */ 788 error = em_reset(adapter); 789 if (error) { 790 device_printf(dev, "Unable to reset the hardware\n"); 791 goto fail; 792 } 793 794 /* Initialize statistics */ 795 em_update_stats(adapter); 796 797 adapter->hw.mac.get_link_status = 1; 798 em_update_link_status(adapter); 799 800 /* Do we need workaround for 82544 PCI-X adapter? */ 801 if (adapter->hw.bus.type == e1000_bus_type_pcix && 802 adapter->hw.mac.type == e1000_82544) 803 adapter->pcix_82544 = TRUE; 804 else 805 adapter->pcix_82544 = FALSE; 806 807 if (adapter->pcix_82544) { 808 /* 809 * 82544 on PCI-X may split one TX segment 810 * into two TX descs, so we double its number 811 * of spare TX desc here. 812 */ 813 adapter->spare_tx_desc = 2 * EM_TX_SPARE; 814 } else { 815 adapter->spare_tx_desc = EM_TX_SPARE; 816 } 817 if (adapter->flags & EM_FLAG_TSO) 818 adapter->spare_tx_desc = EM_TX_SPARE_TSO; 819 adapter->tx_wreg_nsegs = EM_DEFAULT_TXWREG; 820 821 /* 822 * Keep following relationship between spare_tx_desc, oact_tx_desc 823 * and tx_int_nsegs: 824 * (spare_tx_desc + EM_TX_RESERVED) <= 825 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs 826 */ 827 adapter->oact_tx_desc = adapter->num_tx_desc / 8; 828 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX) 829 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX; 830 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED) 831 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED; 832 833 adapter->tx_int_nsegs = adapter->num_tx_desc / 16; 834 if (adapter->tx_int_nsegs < adapter->oact_tx_desc) 835 adapter->tx_int_nsegs = adapter->oact_tx_desc; 836 837 /* Non-AMT based hardware can now take control from firmware */ 838 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 839 EM_FLAG_HAS_MGMT && adapter->hw.mac.type >= e1000_82571) 840 em_get_hw_control(adapter); 841 842 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 843 844 /* 845 * Missing Interrupt Following ICR read: 846 * 847 * 82571/82572 specification update errata #76 848 * 82573 specification update errata #31 849 * 82574 specification update errata #12 850 * 82583 specification update errata #4 851 */ 852 intr_func = em_intr; 853 if ((adapter->flags & EM_FLAG_SHARED_INTR) && 854 (adapter->hw.mac.type == e1000_82571 || 855 adapter->hw.mac.type == e1000_82572 || 856 adapter->hw.mac.type == e1000_82573 || 857 adapter->hw.mac.type == e1000_82574 || 858 adapter->hw.mac.type == e1000_82583)) 859 intr_func = em_intr_mask; 860 861 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE, 862 intr_func, adapter, &adapter->intr_tag, 863 ifp->if_serializer); 864 if (error) { 865 device_printf(dev, "Failed to register interrupt handler"); 866 ether_ifdetach(&adapter->arpcom.ac_if); 867 goto fail; 868 } 869 return (0); 870 fail: 871 em_detach(dev); 872 return (error); 873 } 874 875 static int 876 em_detach(device_t dev) 877 { 878 struct adapter *adapter = device_get_softc(dev); 879 880 if (device_is_attached(dev)) { 881 struct ifnet *ifp = &adapter->arpcom.ac_if; 882 883 lwkt_serialize_enter(ifp->if_serializer); 884 885 em_stop(adapter); 886 887 e1000_phy_hw_reset(&adapter->hw); 888 889 em_rel_mgmt(adapter); 890 em_rel_hw_control(adapter); 891 892 if (adapter->wol) { 893 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 894 E1000_WUC_PME_EN); 895 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 896 em_enable_wol(dev); 897 } 898 899 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag); 900 901 lwkt_serialize_exit(ifp->if_serializer); 902 903 ether_ifdetach(ifp); 904 } else if (adapter->memory != NULL) { 905 em_rel_hw_control(adapter); 906 } 907 bus_generic_detach(dev); 908 909 em_free_pci_res(adapter); 910 911 em_destroy_tx_ring(adapter, adapter->num_tx_desc); 912 em_destroy_rx_ring(adapter, adapter->num_rx_desc); 913 914 /* Free Transmit Descriptor ring */ 915 if (adapter->tx_desc_base) 916 em_dma_free(adapter, &adapter->txdma); 917 918 /* Free Receive Descriptor ring */ 919 if (adapter->rx_desc_base) 920 em_dma_free(adapter, &adapter->rxdma); 921 922 /* Free top level busdma tag */ 923 if (adapter->parent_dtag != NULL) 924 bus_dma_tag_destroy(adapter->parent_dtag); 925 926 /* Free sysctl tree */ 927 if (adapter->sysctl_tree != NULL) 928 sysctl_ctx_free(&adapter->sysctl_ctx); 929 930 if (adapter->mta != NULL) 931 kfree(adapter->mta, M_DEVBUF); 932 933 return (0); 934 } 935 936 static int 937 em_shutdown(device_t dev) 938 { 939 return em_suspend(dev); 940 } 941 942 static int 943 em_suspend(device_t dev) 944 { 945 struct adapter *adapter = device_get_softc(dev); 946 struct ifnet *ifp = &adapter->arpcom.ac_if; 947 948 lwkt_serialize_enter(ifp->if_serializer); 949 950 em_stop(adapter); 951 952 em_rel_mgmt(adapter); 953 em_rel_hw_control(adapter); 954 955 if (adapter->wol) { 956 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 957 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 958 em_enable_wol(dev); 959 } 960 961 lwkt_serialize_exit(ifp->if_serializer); 962 963 return bus_generic_suspend(dev); 964 } 965 966 static int 967 em_resume(device_t dev) 968 { 969 struct adapter *adapter = device_get_softc(dev); 970 struct ifnet *ifp = &adapter->arpcom.ac_if; 971 972 lwkt_serialize_enter(ifp->if_serializer); 973 974 if (adapter->hw.mac.type == e1000_pch2lan) 975 e1000_resume_workarounds_pchlan(&adapter->hw); 976 977 em_init(adapter); 978 em_get_mgmt(adapter); 979 if_devstart(ifp); 980 981 lwkt_serialize_exit(ifp->if_serializer); 982 983 return bus_generic_resume(dev); 984 } 985 986 static void 987 em_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 988 { 989 struct adapter *adapter = ifp->if_softc; 990 struct mbuf *m_head; 991 int idx = -1, nsegs = 0; 992 993 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 994 ASSERT_SERIALIZED(ifp->if_serializer); 995 996 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 997 return; 998 999 if (!adapter->link_active) { 1000 ifq_purge(&ifp->if_snd); 1001 return; 1002 } 1003 1004 while (!ifq_is_empty(&ifp->if_snd)) { 1005 /* Now do we at least have a minimal? */ 1006 if (EM_IS_OACTIVE(adapter)) { 1007 em_tx_collect(adapter); 1008 if (EM_IS_OACTIVE(adapter)) { 1009 ifq_set_oactive(&ifp->if_snd); 1010 adapter->no_tx_desc_avail1++; 1011 break; 1012 } 1013 } 1014 1015 logif(pkt_txqueue); 1016 m_head = ifq_dequeue(&ifp->if_snd); 1017 if (m_head == NULL) 1018 break; 1019 1020 if (em_encap(adapter, &m_head, &nsegs, &idx)) { 1021 IFNET_STAT_INC(ifp, oerrors, 1); 1022 em_tx_collect(adapter); 1023 continue; 1024 } 1025 1026 if (nsegs >= adapter->tx_wreg_nsegs && idx >= 0) { 1027 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1028 nsegs = 0; 1029 idx = -1; 1030 } 1031 1032 /* Send a copy of the frame to the BPF listener */ 1033 ETHER_BPF_MTAP(ifp, m_head); 1034 1035 /* Set timeout in case hardware has problems transmitting. */ 1036 ifp->if_timer = EM_TX_TIMEOUT; 1037 } 1038 if (idx >= 0) 1039 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1040 } 1041 1042 static int 1043 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1044 { 1045 struct adapter *adapter = ifp->if_softc; 1046 struct ifreq *ifr = (struct ifreq *)data; 1047 uint16_t eeprom_data = 0; 1048 int max_frame_size, mask, reinit; 1049 int error = 0; 1050 1051 ASSERT_SERIALIZED(ifp->if_serializer); 1052 1053 switch (command) { 1054 case SIOCSIFMTU: 1055 switch (adapter->hw.mac.type) { 1056 case e1000_82573: 1057 /* 1058 * 82573 only supports jumbo frames 1059 * if ASPM is disabled. 1060 */ 1061 e1000_read_nvm(&adapter->hw, 1062 NVM_INIT_3GIO_3, 1, &eeprom_data); 1063 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1064 max_frame_size = ETHER_MAX_LEN; 1065 break; 1066 } 1067 /* FALL THROUGH */ 1068 1069 /* Limit Jumbo Frame size */ 1070 case e1000_82571: 1071 case e1000_82572: 1072 case e1000_ich9lan: 1073 case e1000_ich10lan: 1074 case e1000_pch2lan: 1075 case e1000_pch_lpt: 1076 case e1000_82574: 1077 case e1000_82583: 1078 case e1000_80003es2lan: 1079 max_frame_size = 9234; 1080 break; 1081 1082 case e1000_pchlan: 1083 max_frame_size = 4096; 1084 break; 1085 1086 /* Adapters that do not support jumbo frames */ 1087 case e1000_82542: 1088 case e1000_ich8lan: 1089 max_frame_size = ETHER_MAX_LEN; 1090 break; 1091 1092 default: 1093 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1094 break; 1095 } 1096 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1097 ETHER_CRC_LEN) { 1098 error = EINVAL; 1099 break; 1100 } 1101 1102 ifp->if_mtu = ifr->ifr_mtu; 1103 adapter->hw.mac.max_frame_size = 1104 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1105 1106 if (ifp->if_flags & IFF_RUNNING) 1107 em_init(adapter); 1108 break; 1109 1110 case SIOCSIFFLAGS: 1111 if (ifp->if_flags & IFF_UP) { 1112 if ((ifp->if_flags & IFF_RUNNING)) { 1113 if ((ifp->if_flags ^ adapter->if_flags) & 1114 (IFF_PROMISC | IFF_ALLMULTI)) { 1115 em_disable_promisc(adapter); 1116 em_set_promisc(adapter); 1117 } 1118 } else { 1119 em_init(adapter); 1120 } 1121 } else if (ifp->if_flags & IFF_RUNNING) { 1122 em_stop(adapter); 1123 } 1124 adapter->if_flags = ifp->if_flags; 1125 break; 1126 1127 case SIOCADDMULTI: 1128 case SIOCDELMULTI: 1129 if (ifp->if_flags & IFF_RUNNING) { 1130 em_disable_intr(adapter); 1131 em_set_multi(adapter); 1132 if (adapter->hw.mac.type == e1000_82542 && 1133 adapter->hw.revision_id == E1000_REVISION_2) 1134 em_init_rx_unit(adapter); 1135 #ifdef IFPOLL_ENABLE 1136 if (!(ifp->if_flags & IFF_NPOLLING)) 1137 #endif 1138 em_enable_intr(adapter); 1139 } 1140 break; 1141 1142 case SIOCSIFMEDIA: 1143 /* Check SOL/IDER usage */ 1144 if (e1000_check_reset_block(&adapter->hw)) { 1145 device_printf(adapter->dev, "Media change is" 1146 " blocked due to SOL/IDER session.\n"); 1147 break; 1148 } 1149 /* FALL THROUGH */ 1150 1151 case SIOCGIFMEDIA: 1152 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1153 break; 1154 1155 case SIOCSIFCAP: 1156 reinit = 0; 1157 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1158 if (mask & IFCAP_RXCSUM) { 1159 ifp->if_capenable ^= IFCAP_RXCSUM; 1160 reinit = 1; 1161 } 1162 if (mask & IFCAP_TXCSUM) { 1163 ifp->if_capenable ^= IFCAP_TXCSUM; 1164 if (ifp->if_capenable & IFCAP_TXCSUM) 1165 ifp->if_hwassist |= EM_CSUM_FEATURES; 1166 else 1167 ifp->if_hwassist &= ~EM_CSUM_FEATURES; 1168 } 1169 if (mask & IFCAP_TSO) { 1170 ifp->if_capenable ^= IFCAP_TSO; 1171 if (ifp->if_capenable & IFCAP_TSO) 1172 ifp->if_hwassist |= CSUM_TSO; 1173 else 1174 ifp->if_hwassist &= ~CSUM_TSO; 1175 } 1176 if (mask & IFCAP_VLAN_HWTAGGING) { 1177 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1178 reinit = 1; 1179 } 1180 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1181 em_init(adapter); 1182 break; 1183 1184 default: 1185 error = ether_ioctl(ifp, command, data); 1186 break; 1187 } 1188 return (error); 1189 } 1190 1191 static void 1192 em_watchdog(struct ifnet *ifp) 1193 { 1194 struct adapter *adapter = ifp->if_softc; 1195 1196 ASSERT_SERIALIZED(ifp->if_serializer); 1197 1198 /* 1199 * The timer is set to 5 every time start queues a packet. 1200 * Then txeof keeps resetting it as long as it cleans at 1201 * least one descriptor. 1202 * Finally, anytime all descriptors are clean the timer is 1203 * set to 0. 1204 */ 1205 1206 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1207 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) { 1208 /* 1209 * If we reach here, all TX jobs are completed and 1210 * the TX engine should have been idled for some time. 1211 * We don't need to call if_devstart() here. 1212 */ 1213 ifq_clr_oactive(&ifp->if_snd); 1214 ifp->if_timer = 0; 1215 return; 1216 } 1217 1218 /* 1219 * If we are in this routine because of pause frames, then 1220 * don't reset the hardware. 1221 */ 1222 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1223 E1000_STATUS_TXOFF) { 1224 ifp->if_timer = EM_TX_TIMEOUT; 1225 return; 1226 } 1227 1228 if (e1000_check_for_link(&adapter->hw) == 0) 1229 if_printf(ifp, "watchdog timeout -- resetting\n"); 1230 1231 IFNET_STAT_INC(ifp, oerrors, 1); 1232 adapter->watchdog_events++; 1233 1234 em_init(adapter); 1235 1236 if (!ifq_is_empty(&ifp->if_snd)) 1237 if_devstart(ifp); 1238 } 1239 1240 static void 1241 em_init(void *xsc) 1242 { 1243 struct adapter *adapter = xsc; 1244 struct ifnet *ifp = &adapter->arpcom.ac_if; 1245 device_t dev = adapter->dev; 1246 1247 ASSERT_SERIALIZED(ifp->if_serializer); 1248 1249 em_stop(adapter); 1250 1251 /* Get the latest mac address, User can use a LAA */ 1252 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN); 1253 1254 /* Put the address into the Receive Address Array */ 1255 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1256 1257 /* 1258 * With the 82571 adapter, RAR[0] may be overwritten 1259 * when the other port is reset, we make a duplicate 1260 * in RAR[14] for that eventuality, this assures 1261 * the interface continues to function. 1262 */ 1263 if (adapter->hw.mac.type == e1000_82571) { 1264 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1265 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1266 E1000_RAR_ENTRIES - 1); 1267 } 1268 1269 /* Reset the hardware */ 1270 if (em_reset(adapter)) { 1271 device_printf(dev, "Unable to reset the hardware\n"); 1272 /* XXX em_stop()? */ 1273 return; 1274 } 1275 em_update_link_status(adapter); 1276 1277 /* Setup VLAN support, basic and offload if available */ 1278 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1279 1280 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1281 uint32_t ctrl; 1282 1283 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1284 ctrl |= E1000_CTRL_VME; 1285 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1286 } 1287 1288 /* Configure for OS presence */ 1289 em_get_mgmt(adapter); 1290 1291 /* Prepare transmit descriptors and buffers */ 1292 em_init_tx_ring(adapter); 1293 em_init_tx_unit(adapter); 1294 1295 /* Setup Multicast table */ 1296 em_set_multi(adapter); 1297 1298 /* Prepare receive descriptors and buffers */ 1299 if (em_init_rx_ring(adapter)) { 1300 device_printf(dev, "Could not setup receive structures\n"); 1301 em_stop(adapter); 1302 return; 1303 } 1304 em_init_rx_unit(adapter); 1305 1306 /* Don't lose promiscuous settings */ 1307 em_set_promisc(adapter); 1308 1309 ifp->if_flags |= IFF_RUNNING; 1310 ifq_clr_oactive(&ifp->if_snd); 1311 1312 callout_reset(&adapter->timer, hz, em_timer, adapter); 1313 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1314 1315 /* MSI/X configuration for 82574 */ 1316 if (adapter->hw.mac.type == e1000_82574) { 1317 int tmp; 1318 1319 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1320 tmp |= E1000_CTRL_EXT_PBA_CLR; 1321 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1322 /* 1323 * XXX MSIX 1324 * Set the IVAR - interrupt vector routing. 1325 * Each nibble represents a vector, high bit 1326 * is enable, other 3 bits are the MSIX table 1327 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1328 * Link (other) to 2, hence the magic number. 1329 */ 1330 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); 1331 } 1332 1333 #ifdef IFPOLL_ENABLE 1334 /* 1335 * Only enable interrupts if we are not polling, make sure 1336 * they are off otherwise. 1337 */ 1338 if (ifp->if_flags & IFF_NPOLLING) 1339 em_disable_intr(adapter); 1340 else 1341 #endif /* IFPOLL_ENABLE */ 1342 em_enable_intr(adapter); 1343 1344 /* AMT based hardware can now take control from firmware */ 1345 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 1346 (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT) && 1347 adapter->hw.mac.type >= e1000_82571) 1348 em_get_hw_control(adapter); 1349 } 1350 1351 #ifdef IFPOLL_ENABLE 1352 1353 static void 1354 em_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 1355 { 1356 struct adapter *adapter = ifp->if_softc; 1357 1358 ASSERT_SERIALIZED(ifp->if_serializer); 1359 1360 if (adapter->npoll.ifpc_stcount-- == 0) { 1361 uint32_t reg_icr; 1362 1363 adapter->npoll.ifpc_stcount = adapter->npoll.ifpc_stfrac; 1364 1365 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1366 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1367 callout_stop(&adapter->timer); 1368 adapter->hw.mac.get_link_status = 1; 1369 em_update_link_status(adapter); 1370 callout_reset(&adapter->timer, hz, em_timer, adapter); 1371 } 1372 } 1373 1374 em_rxeof(adapter, count); 1375 em_txeof(adapter); 1376 1377 if (!ifq_is_empty(&ifp->if_snd)) 1378 if_devstart(ifp); 1379 } 1380 1381 static void 1382 em_npoll(struct ifnet *ifp, struct ifpoll_info *info) 1383 { 1384 struct adapter *adapter = ifp->if_softc; 1385 1386 ASSERT_SERIALIZED(ifp->if_serializer); 1387 1388 if (info != NULL) { 1389 int cpuid = adapter->npoll.ifpc_cpuid; 1390 1391 info->ifpi_rx[cpuid].poll_func = em_npoll_compat; 1392 info->ifpi_rx[cpuid].arg = NULL; 1393 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 1394 1395 if (ifp->if_flags & IFF_RUNNING) 1396 em_disable_intr(adapter); 1397 ifq_set_cpuid(&ifp->if_snd, cpuid); 1398 } else { 1399 if (ifp->if_flags & IFF_RUNNING) 1400 em_enable_intr(adapter); 1401 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 1402 } 1403 } 1404 1405 #endif /* IFPOLL_ENABLE */ 1406 1407 static void 1408 em_intr(void *xsc) 1409 { 1410 em_intr_body(xsc, TRUE); 1411 } 1412 1413 static void 1414 em_intr_body(struct adapter *adapter, boolean_t chk_asserted) 1415 { 1416 struct ifnet *ifp = &adapter->arpcom.ac_if; 1417 uint32_t reg_icr; 1418 1419 logif(intr_beg); 1420 ASSERT_SERIALIZED(ifp->if_serializer); 1421 1422 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1423 1424 if (chk_asserted && 1425 ((adapter->hw.mac.type >= e1000_82571 && 1426 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1427 reg_icr == 0)) { 1428 logif(intr_end); 1429 return; 1430 } 1431 1432 /* 1433 * XXX: some laptops trigger several spurious interrupts 1434 * on em(4) when in the resume cycle. The ICR register 1435 * reports all-ones value in this case. Processing such 1436 * interrupts would lead to a freeze. I don't know why. 1437 */ 1438 if (reg_icr == 0xffffffff) { 1439 logif(intr_end); 1440 return; 1441 } 1442 1443 if (ifp->if_flags & IFF_RUNNING) { 1444 if (reg_icr & 1445 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) 1446 em_rxeof(adapter, -1); 1447 if (reg_icr & E1000_ICR_TXDW) { 1448 em_txeof(adapter); 1449 if (!ifq_is_empty(&ifp->if_snd)) 1450 if_devstart(ifp); 1451 } 1452 } 1453 1454 /* Link status change */ 1455 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1456 callout_stop(&adapter->timer); 1457 adapter->hw.mac.get_link_status = 1; 1458 em_update_link_status(adapter); 1459 1460 /* Deal with TX cruft when link lost */ 1461 em_tx_purge(adapter); 1462 1463 callout_reset(&adapter->timer, hz, em_timer, adapter); 1464 } 1465 1466 if (reg_icr & E1000_ICR_RXO) 1467 adapter->rx_overruns++; 1468 1469 logif(intr_end); 1470 } 1471 1472 static void 1473 em_intr_mask(void *xsc) 1474 { 1475 struct adapter *adapter = xsc; 1476 1477 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 1478 /* 1479 * NOTE: 1480 * ICR.INT_ASSERTED bit will never be set if IMS is 0, 1481 * so don't check it. 1482 */ 1483 em_intr_body(adapter, FALSE); 1484 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK); 1485 } 1486 1487 static void 1488 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1489 { 1490 struct adapter *adapter = ifp->if_softc; 1491 u_char fiber_type = IFM_1000_SX; 1492 1493 ASSERT_SERIALIZED(ifp->if_serializer); 1494 1495 em_update_link_status(adapter); 1496 1497 ifmr->ifm_status = IFM_AVALID; 1498 ifmr->ifm_active = IFM_ETHER; 1499 1500 if (!adapter->link_active) 1501 return; 1502 1503 ifmr->ifm_status |= IFM_ACTIVE; 1504 1505 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 1506 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 1507 if (adapter->hw.mac.type == e1000_82545) 1508 fiber_type = IFM_1000_LX; 1509 ifmr->ifm_active |= fiber_type | IFM_FDX; 1510 } else { 1511 switch (adapter->link_speed) { 1512 case 10: 1513 ifmr->ifm_active |= IFM_10_T; 1514 break; 1515 case 100: 1516 ifmr->ifm_active |= IFM_100_TX; 1517 break; 1518 1519 case 1000: 1520 ifmr->ifm_active |= IFM_1000_T; 1521 break; 1522 } 1523 if (adapter->link_duplex == FULL_DUPLEX) 1524 ifmr->ifm_active |= IFM_FDX; 1525 else 1526 ifmr->ifm_active |= IFM_HDX; 1527 } 1528 } 1529 1530 static int 1531 em_media_change(struct ifnet *ifp) 1532 { 1533 struct adapter *adapter = ifp->if_softc; 1534 struct ifmedia *ifm = &adapter->media; 1535 1536 ASSERT_SERIALIZED(ifp->if_serializer); 1537 1538 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1539 return (EINVAL); 1540 1541 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1542 case IFM_AUTO: 1543 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1544 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1545 break; 1546 1547 case IFM_1000_LX: 1548 case IFM_1000_SX: 1549 case IFM_1000_T: 1550 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1551 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1552 break; 1553 1554 case IFM_100_TX: 1555 adapter->hw.mac.autoneg = FALSE; 1556 adapter->hw.phy.autoneg_advertised = 0; 1557 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1558 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1559 else 1560 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1561 break; 1562 1563 case IFM_10_T: 1564 adapter->hw.mac.autoneg = FALSE; 1565 adapter->hw.phy.autoneg_advertised = 0; 1566 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1567 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1568 else 1569 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1570 break; 1571 1572 default: 1573 if_printf(ifp, "Unsupported media type\n"); 1574 break; 1575 } 1576 1577 em_init(adapter); 1578 1579 return (0); 1580 } 1581 1582 static int 1583 em_encap(struct adapter *adapter, struct mbuf **m_headp, 1584 int *segs_used, int *idx) 1585 { 1586 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1587 bus_dmamap_t map; 1588 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1589 struct e1000_tx_desc *ctxd = NULL; 1590 struct mbuf *m_head = *m_headp; 1591 uint32_t txd_upper, txd_lower, txd_used, cmd = 0; 1592 int maxsegs, nsegs, i, j, first, last = 0, error; 1593 1594 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1595 error = em_tso_pullup(adapter, m_headp); 1596 if (error) 1597 return error; 1598 m_head = *m_headp; 1599 } 1600 1601 txd_upper = txd_lower = 0; 1602 txd_used = 0; 1603 1604 /* 1605 * Capture the first descriptor index, this descriptor 1606 * will have the index of the EOP which is the only one 1607 * that now gets a DONE bit writeback. 1608 */ 1609 first = adapter->next_avail_tx_desc; 1610 tx_buffer = &adapter->tx_buffer_area[first]; 1611 tx_buffer_mapped = tx_buffer; 1612 map = tx_buffer->map; 1613 1614 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED; 1615 KASSERT(maxsegs >= adapter->spare_tx_desc, 1616 ("not enough spare TX desc")); 1617 if (adapter->pcix_82544) { 1618 /* Half it; see the comment in em_attach() */ 1619 maxsegs >>= 1; 1620 } 1621 if (maxsegs > EM_MAX_SCATTER) 1622 maxsegs = EM_MAX_SCATTER; 1623 1624 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp, 1625 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1626 if (error) { 1627 if (error == ENOBUFS) 1628 adapter->mbuf_alloc_failed++; 1629 else 1630 adapter->no_tx_dma_setup++; 1631 1632 m_freem(*m_headp); 1633 *m_headp = NULL; 1634 return error; 1635 } 1636 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1637 1638 m_head = *m_headp; 1639 adapter->tx_nsegs += nsegs; 1640 *segs_used += nsegs; 1641 1642 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1643 /* TSO will consume one TX desc */ 1644 i = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower); 1645 adapter->tx_nsegs += i; 1646 *segs_used += i; 1647 } else if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) { 1648 /* TX csum offloading will consume one TX desc */ 1649 i = em_txcsum(adapter, m_head, &txd_upper, &txd_lower); 1650 adapter->tx_nsegs += i; 1651 *segs_used += i; 1652 } 1653 1654 /* Handle VLAN tag */ 1655 if (m_head->m_flags & M_VLANTAG) { 1656 /* Set the vlan id. */ 1657 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16); 1658 /* Tell hardware to add tag */ 1659 txd_lower |= htole32(E1000_TXD_CMD_VLE); 1660 } 1661 1662 i = adapter->next_avail_tx_desc; 1663 1664 /* Set up our transmit descriptors */ 1665 for (j = 0; j < nsegs; j++) { 1666 /* If adapter is 82544 and on PCIX bus */ 1667 if(adapter->pcix_82544) { 1668 DESC_ARRAY desc_array; 1669 uint32_t array_elements, counter; 1670 1671 /* 1672 * Check the Address and Length combination and 1673 * split the data accordingly 1674 */ 1675 array_elements = em_82544_fill_desc(segs[j].ds_addr, 1676 segs[j].ds_len, &desc_array); 1677 for (counter = 0; counter < array_elements; counter++) { 1678 KKASSERT(txd_used < adapter->num_tx_desc_avail); 1679 1680 tx_buffer = &adapter->tx_buffer_area[i]; 1681 ctxd = &adapter->tx_desc_base[i]; 1682 1683 ctxd->buffer_addr = htole64( 1684 desc_array.descriptor[counter].address); 1685 ctxd->lower.data = htole32( 1686 E1000_TXD_CMD_IFCS | txd_lower | 1687 desc_array.descriptor[counter].length); 1688 ctxd->upper.data = htole32(txd_upper); 1689 1690 last = i; 1691 if (++i == adapter->num_tx_desc) 1692 i = 0; 1693 1694 txd_used++; 1695 } 1696 } else { 1697 tx_buffer = &adapter->tx_buffer_area[i]; 1698 ctxd = &adapter->tx_desc_base[i]; 1699 1700 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1701 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1702 txd_lower | segs[j].ds_len); 1703 ctxd->upper.data = htole32(txd_upper); 1704 1705 last = i; 1706 if (++i == adapter->num_tx_desc) 1707 i = 0; 1708 } 1709 } 1710 1711 adapter->next_avail_tx_desc = i; 1712 if (adapter->pcix_82544) { 1713 KKASSERT(adapter->num_tx_desc_avail > txd_used); 1714 adapter->num_tx_desc_avail -= txd_used; 1715 } else { 1716 KKASSERT(adapter->num_tx_desc_avail > nsegs); 1717 adapter->num_tx_desc_avail -= nsegs; 1718 } 1719 1720 tx_buffer->m_head = m_head; 1721 tx_buffer_mapped->map = tx_buffer->map; 1722 tx_buffer->map = map; 1723 1724 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) { 1725 adapter->tx_nsegs = 0; 1726 1727 /* 1728 * Report Status (RS) is turned on 1729 * every tx_int_nsegs descriptors. 1730 */ 1731 cmd = E1000_TXD_CMD_RS; 1732 1733 /* 1734 * Keep track of the descriptor, which will 1735 * be written back by hardware. 1736 */ 1737 adapter->tx_dd[adapter->tx_dd_tail] = last; 1738 EM_INC_TXDD_IDX(adapter->tx_dd_tail); 1739 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head); 1740 } 1741 1742 /* 1743 * Last Descriptor of Packet needs End Of Packet (EOP) 1744 */ 1745 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1746 1747 if (adapter->hw.mac.type == e1000_82547) { 1748 /* 1749 * Advance the Transmit Descriptor Tail (TDT), this tells the 1750 * E1000 that this frame is available to transmit. 1751 */ 1752 if (adapter->link_duplex == HALF_DUPLEX) { 1753 em_82547_move_tail_serialized(adapter); 1754 } else { 1755 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 1756 em_82547_update_fifo_head(adapter, 1757 m_head->m_pkthdr.len); 1758 } 1759 } else { 1760 /* 1761 * Defer TDT updating, until enough descriptors are setup 1762 */ 1763 *idx = i; 1764 } 1765 return (0); 1766 } 1767 1768 /* 1769 * 82547 workaround to avoid controller hang in half-duplex environment. 1770 * The workaround is to avoid queuing a large packet that would span 1771 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1772 * in this case. We do that only when FIFO is quiescent. 1773 */ 1774 static void 1775 em_82547_move_tail_serialized(struct adapter *adapter) 1776 { 1777 struct e1000_tx_desc *tx_desc; 1778 uint16_t hw_tdt, sw_tdt, length = 0; 1779 bool eop = 0; 1780 1781 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer); 1782 1783 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 1784 sw_tdt = adapter->next_avail_tx_desc; 1785 1786 while (hw_tdt != sw_tdt) { 1787 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1788 length += tx_desc->lower.flags.length; 1789 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1790 if (++hw_tdt == adapter->num_tx_desc) 1791 hw_tdt = 0; 1792 1793 if (eop) { 1794 if (em_82547_fifo_workaround(adapter, length)) { 1795 adapter->tx_fifo_wrk_cnt++; 1796 callout_reset(&adapter->tx_fifo_timer, 1, 1797 em_82547_move_tail, adapter); 1798 break; 1799 } 1800 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 1801 em_82547_update_fifo_head(adapter, length); 1802 length = 0; 1803 } 1804 } 1805 } 1806 1807 static void 1808 em_82547_move_tail(void *xsc) 1809 { 1810 struct adapter *adapter = xsc; 1811 struct ifnet *ifp = &adapter->arpcom.ac_if; 1812 1813 lwkt_serialize_enter(ifp->if_serializer); 1814 em_82547_move_tail_serialized(adapter); 1815 lwkt_serialize_exit(ifp->if_serializer); 1816 } 1817 1818 static int 1819 em_82547_fifo_workaround(struct adapter *adapter, int len) 1820 { 1821 int fifo_space, fifo_pkt_len; 1822 1823 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1824 1825 if (adapter->link_duplex == HALF_DUPLEX) { 1826 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 1827 1828 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1829 if (em_82547_tx_fifo_reset(adapter)) 1830 return (0); 1831 else 1832 return (1); 1833 } 1834 } 1835 return (0); 1836 } 1837 1838 static void 1839 em_82547_update_fifo_head(struct adapter *adapter, int len) 1840 { 1841 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1842 1843 /* tx_fifo_head is always 16 byte aligned */ 1844 adapter->tx_fifo_head += fifo_pkt_len; 1845 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) 1846 adapter->tx_fifo_head -= adapter->tx_fifo_size; 1847 } 1848 1849 static int 1850 em_82547_tx_fifo_reset(struct adapter *adapter) 1851 { 1852 uint32_t tctl; 1853 1854 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1855 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 1856 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 1857 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 1858 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 1859 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 1860 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 1861 /* Disable TX unit */ 1862 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 1863 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 1864 tctl & ~E1000_TCTL_EN); 1865 1866 /* Reset FIFO pointers */ 1867 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 1868 adapter->tx_head_addr); 1869 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 1870 adapter->tx_head_addr); 1871 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 1872 adapter->tx_head_addr); 1873 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 1874 adapter->tx_head_addr); 1875 1876 /* Re-enable TX unit */ 1877 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 1878 E1000_WRITE_FLUSH(&adapter->hw); 1879 1880 adapter->tx_fifo_head = 0; 1881 adapter->tx_fifo_reset_cnt++; 1882 1883 return (TRUE); 1884 } else { 1885 return (FALSE); 1886 } 1887 } 1888 1889 static void 1890 em_set_promisc(struct adapter *adapter) 1891 { 1892 struct ifnet *ifp = &adapter->arpcom.ac_if; 1893 uint32_t reg_rctl; 1894 1895 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1896 1897 if (ifp->if_flags & IFF_PROMISC) { 1898 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1899 /* Turn this on if you want to see bad packets */ 1900 if (em_debug_sbp) 1901 reg_rctl |= E1000_RCTL_SBP; 1902 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1903 } else if (ifp->if_flags & IFF_ALLMULTI) { 1904 reg_rctl |= E1000_RCTL_MPE; 1905 reg_rctl &= ~E1000_RCTL_UPE; 1906 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1907 } 1908 } 1909 1910 static void 1911 em_disable_promisc(struct adapter *adapter) 1912 { 1913 uint32_t reg_rctl; 1914 1915 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1916 1917 reg_rctl &= ~E1000_RCTL_UPE; 1918 reg_rctl &= ~E1000_RCTL_MPE; 1919 reg_rctl &= ~E1000_RCTL_SBP; 1920 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1921 } 1922 1923 static void 1924 em_set_multi(struct adapter *adapter) 1925 { 1926 struct ifnet *ifp = &adapter->arpcom.ac_if; 1927 struct ifmultiaddr *ifma; 1928 uint32_t reg_rctl = 0; 1929 uint8_t *mta; 1930 int mcnt = 0; 1931 1932 mta = adapter->mta; 1933 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1934 1935 if (adapter->hw.mac.type == e1000_82542 && 1936 adapter->hw.revision_id == E1000_REVISION_2) { 1937 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1938 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1939 e1000_pci_clear_mwi(&adapter->hw); 1940 reg_rctl |= E1000_RCTL_RST; 1941 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1942 msec_delay(5); 1943 } 1944 1945 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1946 if (ifma->ifma_addr->sa_family != AF_LINK) 1947 continue; 1948 1949 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1950 break; 1951 1952 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1953 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1954 mcnt++; 1955 } 1956 1957 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1958 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1959 reg_rctl |= E1000_RCTL_MPE; 1960 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1961 } else { 1962 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1963 } 1964 1965 if (adapter->hw.mac.type == e1000_82542 && 1966 adapter->hw.revision_id == E1000_REVISION_2) { 1967 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1968 reg_rctl &= ~E1000_RCTL_RST; 1969 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1970 msec_delay(5); 1971 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1972 e1000_pci_set_mwi(&adapter->hw); 1973 } 1974 } 1975 1976 /* 1977 * This routine checks for link status and updates statistics. 1978 */ 1979 static void 1980 em_timer(void *xsc) 1981 { 1982 struct adapter *adapter = xsc; 1983 struct ifnet *ifp = &adapter->arpcom.ac_if; 1984 1985 lwkt_serialize_enter(ifp->if_serializer); 1986 1987 em_update_link_status(adapter); 1988 em_update_stats(adapter); 1989 1990 /* Reset LAA into RAR[0] on 82571 */ 1991 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 1992 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1993 1994 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1995 em_print_hw_stats(adapter); 1996 1997 em_smartspeed(adapter); 1998 1999 callout_reset(&adapter->timer, hz, em_timer, adapter); 2000 2001 lwkt_serialize_exit(ifp->if_serializer); 2002 } 2003 2004 static void 2005 em_update_link_status(struct adapter *adapter) 2006 { 2007 struct e1000_hw *hw = &adapter->hw; 2008 struct ifnet *ifp = &adapter->arpcom.ac_if; 2009 device_t dev = adapter->dev; 2010 uint32_t link_check = 0; 2011 2012 /* Get the cached link value or read phy for real */ 2013 switch (hw->phy.media_type) { 2014 case e1000_media_type_copper: 2015 if (hw->mac.get_link_status) { 2016 /* Do the work to read phy */ 2017 e1000_check_for_link(hw); 2018 link_check = !hw->mac.get_link_status; 2019 if (link_check) /* ESB2 fix */ 2020 e1000_cfg_on_link_up(hw); 2021 } else { 2022 link_check = TRUE; 2023 } 2024 break; 2025 2026 case e1000_media_type_fiber: 2027 e1000_check_for_link(hw); 2028 link_check = 2029 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 2030 break; 2031 2032 case e1000_media_type_internal_serdes: 2033 e1000_check_for_link(hw); 2034 link_check = adapter->hw.mac.serdes_has_link; 2035 break; 2036 2037 case e1000_media_type_unknown: 2038 default: 2039 break; 2040 } 2041 2042 /* Now check for a transition */ 2043 if (link_check && adapter->link_active == 0) { 2044 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 2045 &adapter->link_duplex); 2046 2047 /* 2048 * Check if we should enable/disable SPEED_MODE bit on 2049 * 82571/82572 2050 */ 2051 if (adapter->link_speed != SPEED_1000 && 2052 (hw->mac.type == e1000_82571 || 2053 hw->mac.type == e1000_82572)) { 2054 int tarc0; 2055 2056 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2057 tarc0 &= ~SPEED_MODE_BIT; 2058 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2059 } 2060 if (bootverbose) { 2061 device_printf(dev, "Link is up %d Mbps %s\n", 2062 adapter->link_speed, 2063 ((adapter->link_duplex == FULL_DUPLEX) ? 2064 "Full Duplex" : "Half Duplex")); 2065 } 2066 adapter->link_active = 1; 2067 adapter->smartspeed = 0; 2068 ifp->if_baudrate = adapter->link_speed * 1000000; 2069 ifp->if_link_state = LINK_STATE_UP; 2070 if_link_state_change(ifp); 2071 } else if (!link_check && adapter->link_active == 1) { 2072 ifp->if_baudrate = adapter->link_speed = 0; 2073 adapter->link_duplex = 0; 2074 if (bootverbose) 2075 device_printf(dev, "Link is Down\n"); 2076 adapter->link_active = 0; 2077 #if 0 2078 /* Link down, disable watchdog */ 2079 if->if_timer = 0; 2080 #endif 2081 ifp->if_link_state = LINK_STATE_DOWN; 2082 if_link_state_change(ifp); 2083 } 2084 } 2085 2086 static void 2087 em_stop(struct adapter *adapter) 2088 { 2089 struct ifnet *ifp = &adapter->arpcom.ac_if; 2090 int i; 2091 2092 ASSERT_SERIALIZED(ifp->if_serializer); 2093 2094 em_disable_intr(adapter); 2095 2096 callout_stop(&adapter->timer); 2097 callout_stop(&adapter->tx_fifo_timer); 2098 2099 ifp->if_flags &= ~IFF_RUNNING; 2100 ifq_clr_oactive(&ifp->if_snd); 2101 ifp->if_timer = 0; 2102 2103 e1000_reset_hw(&adapter->hw); 2104 if (adapter->hw.mac.type >= e1000_82544) 2105 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2106 2107 for (i = 0; i < adapter->num_tx_desc; i++) { 2108 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i]; 2109 2110 if (tx_buffer->m_head != NULL) { 2111 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 2112 m_freem(tx_buffer->m_head); 2113 tx_buffer->m_head = NULL; 2114 } 2115 } 2116 2117 for (i = 0; i < adapter->num_rx_desc; i++) { 2118 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i]; 2119 2120 if (rx_buffer->m_head != NULL) { 2121 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 2122 m_freem(rx_buffer->m_head); 2123 rx_buffer->m_head = NULL; 2124 } 2125 } 2126 2127 if (adapter->fmp != NULL) 2128 m_freem(adapter->fmp); 2129 adapter->fmp = NULL; 2130 adapter->lmp = NULL; 2131 2132 adapter->csum_flags = 0; 2133 adapter->csum_lhlen = 0; 2134 adapter->csum_iphlen = 0; 2135 adapter->csum_thlen = 0; 2136 adapter->csum_mss = 0; 2137 adapter->csum_pktlen = 0; 2138 2139 adapter->tx_dd_head = 0; 2140 adapter->tx_dd_tail = 0; 2141 adapter->tx_nsegs = 0; 2142 } 2143 2144 static int 2145 em_get_hw_info(struct adapter *adapter) 2146 { 2147 device_t dev = adapter->dev; 2148 2149 /* Save off the information about this board */ 2150 adapter->hw.vendor_id = pci_get_vendor(dev); 2151 adapter->hw.device_id = pci_get_device(dev); 2152 adapter->hw.revision_id = pci_get_revid(dev); 2153 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev); 2154 adapter->hw.subsystem_device_id = pci_get_subdevice(dev); 2155 2156 /* Do Shared Code Init and Setup */ 2157 if (e1000_set_mac_type(&adapter->hw)) 2158 return ENXIO; 2159 return 0; 2160 } 2161 2162 static int 2163 em_alloc_pci_res(struct adapter *adapter) 2164 { 2165 device_t dev = adapter->dev; 2166 u_int intr_flags; 2167 int val, rid, msi_enable; 2168 2169 /* Enable bus mastering */ 2170 pci_enable_busmaster(dev); 2171 2172 adapter->memory_rid = EM_BAR_MEM; 2173 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2174 &adapter->memory_rid, RF_ACTIVE); 2175 if (adapter->memory == NULL) { 2176 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2177 return (ENXIO); 2178 } 2179 adapter->osdep.mem_bus_space_tag = 2180 rman_get_bustag(adapter->memory); 2181 adapter->osdep.mem_bus_space_handle = 2182 rman_get_bushandle(adapter->memory); 2183 2184 /* XXX This is quite goofy, it is not actually used */ 2185 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2186 2187 /* Only older adapters use IO mapping */ 2188 if (adapter->hw.mac.type > e1000_82543 && 2189 adapter->hw.mac.type < e1000_82571) { 2190 /* Figure our where our IO BAR is ? */ 2191 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) { 2192 val = pci_read_config(dev, rid, 4); 2193 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2194 adapter->io_rid = rid; 2195 break; 2196 } 2197 rid += 4; 2198 /* check for 64bit BAR */ 2199 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2200 rid += 4; 2201 } 2202 if (rid >= PCIR_CARDBUSCIS) { 2203 device_printf(dev, "Unable to locate IO BAR\n"); 2204 return (ENXIO); 2205 } 2206 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2207 &adapter->io_rid, RF_ACTIVE); 2208 if (adapter->ioport == NULL) { 2209 device_printf(dev, "Unable to allocate bus resource: " 2210 "ioport\n"); 2211 return (ENXIO); 2212 } 2213 adapter->hw.io_base = 0; 2214 adapter->osdep.io_bus_space_tag = 2215 rman_get_bustag(adapter->ioport); 2216 adapter->osdep.io_bus_space_handle = 2217 rman_get_bushandle(adapter->ioport); 2218 } 2219 2220 /* 2221 * Don't enable MSI-X on 82574, see: 2222 * 82574 specification update errata #15 2223 * 2224 * Don't enable MSI on PCI/PCI-X chips, see: 2225 * 82540 specification update errata #6 2226 * 82545 specification update errata #4 2227 * 2228 * Don't enable MSI on 82571/82572, see: 2229 * 82571/82572 specification update errata #63 2230 */ 2231 msi_enable = em_msi_enable; 2232 if (msi_enable && 2233 (!pci_is_pcie(dev) || 2234 adapter->hw.mac.type == e1000_82571 || 2235 adapter->hw.mac.type == e1000_82572)) 2236 msi_enable = 0; 2237 2238 adapter->intr_type = pci_alloc_1intr(dev, msi_enable, 2239 &adapter->intr_rid, &intr_flags); 2240 2241 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) { 2242 int unshared; 2243 2244 unshared = device_getenv_int(dev, "irq.unshared", 0); 2245 if (!unshared) { 2246 adapter->flags |= EM_FLAG_SHARED_INTR; 2247 if (bootverbose) 2248 device_printf(dev, "IRQ shared\n"); 2249 } else { 2250 intr_flags &= ~RF_SHAREABLE; 2251 if (bootverbose) 2252 device_printf(dev, "IRQ unshared\n"); 2253 } 2254 } 2255 2256 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 2257 &adapter->intr_rid, intr_flags); 2258 if (adapter->intr_res == NULL) { 2259 device_printf(dev, "Unable to allocate bus resource: " 2260 "interrupt\n"); 2261 return (ENXIO); 2262 } 2263 2264 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2265 adapter->hw.back = &adapter->osdep; 2266 return (0); 2267 } 2268 2269 static void 2270 em_free_pci_res(struct adapter *adapter) 2271 { 2272 device_t dev = adapter->dev; 2273 2274 if (adapter->intr_res != NULL) { 2275 bus_release_resource(dev, SYS_RES_IRQ, 2276 adapter->intr_rid, adapter->intr_res); 2277 } 2278 2279 if (adapter->intr_type == PCI_INTR_TYPE_MSI) 2280 pci_release_msi(dev); 2281 2282 if (adapter->memory != NULL) { 2283 bus_release_resource(dev, SYS_RES_MEMORY, 2284 adapter->memory_rid, adapter->memory); 2285 } 2286 2287 if (adapter->flash != NULL) { 2288 bus_release_resource(dev, SYS_RES_MEMORY, 2289 adapter->flash_rid, adapter->flash); 2290 } 2291 2292 if (adapter->ioport != NULL) { 2293 bus_release_resource(dev, SYS_RES_IOPORT, 2294 adapter->io_rid, adapter->ioport); 2295 } 2296 } 2297 2298 static int 2299 em_reset(struct adapter *adapter) 2300 { 2301 device_t dev = adapter->dev; 2302 uint16_t rx_buffer_size; 2303 uint32_t pba; 2304 2305 /* When hardware is reset, fifo_head is also reset */ 2306 adapter->tx_fifo_head = 0; 2307 2308 /* Set up smart power down as default off on newer adapters. */ 2309 if (!em_smart_pwr_down && 2310 (adapter->hw.mac.type == e1000_82571 || 2311 adapter->hw.mac.type == e1000_82572)) { 2312 uint16_t phy_tmp = 0; 2313 2314 /* Speed up time to link by disabling smart power down. */ 2315 e1000_read_phy_reg(&adapter->hw, 2316 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2317 phy_tmp &= ~IGP02E1000_PM_SPD; 2318 e1000_write_phy_reg(&adapter->hw, 2319 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2320 } 2321 2322 /* 2323 * Packet Buffer Allocation (PBA) 2324 * Writing PBA sets the receive portion of the buffer 2325 * the remainder is used for the transmit buffer. 2326 * 2327 * Devices before the 82547 had a Packet Buffer of 64K. 2328 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 2329 * After the 82547 the buffer was reduced to 40K. 2330 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 2331 * Note: default does not leave enough room for Jumbo Frame >10k. 2332 */ 2333 switch (adapter->hw.mac.type) { 2334 case e1000_82547: 2335 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 2336 if (adapter->hw.mac.max_frame_size > 8192) 2337 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2338 else 2339 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2340 adapter->tx_fifo_head = 0; 2341 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 2342 adapter->tx_fifo_size = 2343 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 2344 break; 2345 2346 /* Total Packet Buffer on these is 48K */ 2347 case e1000_82571: 2348 case e1000_82572: 2349 case e1000_80003es2lan: 2350 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2351 break; 2352 2353 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2354 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2355 break; 2356 2357 case e1000_82574: 2358 case e1000_82583: 2359 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2360 break; 2361 2362 case e1000_ich8lan: 2363 pba = E1000_PBA_8K; 2364 break; 2365 2366 case e1000_ich9lan: 2367 case e1000_ich10lan: 2368 #define E1000_PBA_10K 0x000A 2369 pba = E1000_PBA_10K; 2370 break; 2371 2372 case e1000_pchlan: 2373 case e1000_pch2lan: 2374 case e1000_pch_lpt: 2375 pba = E1000_PBA_26K; 2376 break; 2377 2378 default: 2379 /* Devices before 82547 had a Packet Buffer of 64K. */ 2380 if (adapter->hw.mac.max_frame_size > 8192) 2381 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2382 else 2383 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2384 } 2385 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2386 2387 /* 2388 * These parameters control the automatic generation (Tx) and 2389 * response (Rx) to Ethernet PAUSE frames. 2390 * - High water mark should allow for at least two frames to be 2391 * received after sending an XOFF. 2392 * - Low water mark works best when it is very near the high water mark. 2393 * This allows the receiver to restart by sending XON when it has 2394 * drained a bit. Here we use an arbitary value of 1500 which will 2395 * restart after one full frame is pulled from the buffer. There 2396 * could be several smaller frames in the buffer and if so they will 2397 * not trigger the XON until their total number reduces the buffer 2398 * by 1500. 2399 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2400 */ 2401 rx_buffer_size = 2402 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10; 2403 2404 adapter->hw.fc.high_water = rx_buffer_size - 2405 roundup2(adapter->hw.mac.max_frame_size, 1024); 2406 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 2407 2408 if (adapter->hw.mac.type == e1000_80003es2lan) 2409 adapter->hw.fc.pause_time = 0xFFFF; 2410 else 2411 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 2412 2413 adapter->hw.fc.send_xon = TRUE; 2414 2415 adapter->hw.fc.requested_mode = e1000_fc_full; 2416 2417 /* 2418 * Device specific overrides/settings 2419 */ 2420 switch (adapter->hw.mac.type) { 2421 case e1000_pchlan: 2422 /* Workaround: no TX flow ctrl for PCH */ 2423 adapter->hw.fc.requested_mode = e1000_fc_rx_pause; 2424 adapter->hw.fc.pause_time = 0xFFFF; /* override */ 2425 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) { 2426 adapter->hw.fc.high_water = 0x3500; 2427 adapter->hw.fc.low_water = 0x1500; 2428 } else { 2429 adapter->hw.fc.high_water = 0x5000; 2430 adapter->hw.fc.low_water = 0x3000; 2431 } 2432 adapter->hw.fc.refresh_time = 0x1000; 2433 break; 2434 2435 case e1000_pch2lan: 2436 case e1000_pch_lpt: 2437 adapter->hw.fc.high_water = 0x5C20; 2438 adapter->hw.fc.low_water = 0x5048; 2439 adapter->hw.fc.pause_time = 0x0650; 2440 adapter->hw.fc.refresh_time = 0x0400; 2441 /* Jumbos need adjusted PBA */ 2442 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) 2443 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12); 2444 else 2445 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26); 2446 break; 2447 2448 case e1000_ich9lan: 2449 case e1000_ich10lan: 2450 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) { 2451 adapter->hw.fc.high_water = 0x2800; 2452 adapter->hw.fc.low_water = 2453 adapter->hw.fc.high_water - 8; 2454 break; 2455 } 2456 /* FALL THROUGH */ 2457 default: 2458 if (adapter->hw.mac.type == e1000_80003es2lan) 2459 adapter->hw.fc.pause_time = 0xFFFF; 2460 break; 2461 } 2462 2463 /* Issue a global reset */ 2464 e1000_reset_hw(&adapter->hw); 2465 if (adapter->hw.mac.type >= e1000_82544) 2466 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2467 em_disable_aspm(adapter); 2468 2469 if (e1000_init_hw(&adapter->hw) < 0) { 2470 device_printf(dev, "Hardware Initialization Failed\n"); 2471 return (EIO); 2472 } 2473 2474 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 2475 e1000_get_phy_info(&adapter->hw); 2476 e1000_check_for_link(&adapter->hw); 2477 2478 return (0); 2479 } 2480 2481 static void 2482 em_setup_ifp(struct adapter *adapter) 2483 { 2484 struct ifnet *ifp = &adapter->arpcom.ac_if; 2485 2486 if_initname(ifp, device_get_name(adapter->dev), 2487 device_get_unit(adapter->dev)); 2488 ifp->if_softc = adapter; 2489 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2490 ifp->if_init = em_init; 2491 ifp->if_ioctl = em_ioctl; 2492 ifp->if_start = em_start; 2493 #ifdef IFPOLL_ENABLE 2494 ifp->if_npoll = em_npoll; 2495 #endif 2496 ifp->if_watchdog = em_watchdog; 2497 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1); 2498 ifq_set_ready(&ifp->if_snd); 2499 2500 ether_ifattach(ifp, adapter->hw.mac.addr, NULL); 2501 2502 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2503 if (adapter->hw.mac.type >= e1000_82543) 2504 ifp->if_capabilities |= IFCAP_HWCSUM; 2505 if (adapter->flags & EM_FLAG_TSO) 2506 ifp->if_capabilities |= IFCAP_TSO; 2507 ifp->if_capenable = ifp->if_capabilities; 2508 2509 if (ifp->if_capenable & IFCAP_TXCSUM) 2510 ifp->if_hwassist |= EM_CSUM_FEATURES; 2511 if (ifp->if_capenable & IFCAP_TSO) 2512 ifp->if_hwassist |= CSUM_TSO; 2513 2514 /* 2515 * Tell the upper layer(s) we support long frames. 2516 */ 2517 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2518 2519 /* 2520 * Specify the media types supported by this adapter and register 2521 * callbacks to update media and link information 2522 */ 2523 ifmedia_init(&adapter->media, IFM_IMASK, 2524 em_media_change, em_media_status); 2525 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2526 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2527 u_char fiber_type = IFM_1000_SX; /* default type */ 2528 2529 if (adapter->hw.mac.type == e1000_82545) 2530 fiber_type = IFM_1000_LX; 2531 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2532 0, NULL); 2533 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2534 } else { 2535 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2536 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2537 0, NULL); 2538 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2539 0, NULL); 2540 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2541 0, NULL); 2542 if (adapter->hw.phy.type != e1000_phy_ife) { 2543 ifmedia_add(&adapter->media, 2544 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2545 ifmedia_add(&adapter->media, 2546 IFM_ETHER | IFM_1000_T, 0, NULL); 2547 } 2548 } 2549 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2550 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2551 } 2552 2553 2554 /* 2555 * Workaround for SmartSpeed on 82541 and 82547 controllers 2556 */ 2557 static void 2558 em_smartspeed(struct adapter *adapter) 2559 { 2560 uint16_t phy_tmp; 2561 2562 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp || 2563 adapter->hw.mac.autoneg == 0 || 2564 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2565 return; 2566 2567 if (adapter->smartspeed == 0) { 2568 /* 2569 * If Master/Slave config fault is asserted twice, 2570 * we assume back-to-back 2571 */ 2572 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2573 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2574 return; 2575 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2576 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2577 e1000_read_phy_reg(&adapter->hw, 2578 PHY_1000T_CTRL, &phy_tmp); 2579 if (phy_tmp & CR_1000T_MS_ENABLE) { 2580 phy_tmp &= ~CR_1000T_MS_ENABLE; 2581 e1000_write_phy_reg(&adapter->hw, 2582 PHY_1000T_CTRL, phy_tmp); 2583 adapter->smartspeed++; 2584 if (adapter->hw.mac.autoneg && 2585 !e1000_phy_setup_autoneg(&adapter->hw) && 2586 !e1000_read_phy_reg(&adapter->hw, 2587 PHY_CONTROL, &phy_tmp)) { 2588 phy_tmp |= MII_CR_AUTO_NEG_EN | 2589 MII_CR_RESTART_AUTO_NEG; 2590 e1000_write_phy_reg(&adapter->hw, 2591 PHY_CONTROL, phy_tmp); 2592 } 2593 } 2594 } 2595 return; 2596 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2597 /* If still no link, perhaps using 2/3 pair cable */ 2598 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2599 phy_tmp |= CR_1000T_MS_ENABLE; 2600 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2601 if (adapter->hw.mac.autoneg && 2602 !e1000_phy_setup_autoneg(&adapter->hw) && 2603 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2604 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2605 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2606 } 2607 } 2608 2609 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2610 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2611 adapter->smartspeed = 0; 2612 } 2613 2614 static int 2615 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2616 struct em_dma_alloc *dma) 2617 { 2618 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag, 2619 EM_DBA_ALIGN, size, BUS_DMA_WAITOK, 2620 &dma->dma_tag, &dma->dma_map, 2621 &dma->dma_paddr); 2622 if (dma->dma_vaddr == NULL) 2623 return ENOMEM; 2624 else 2625 return 0; 2626 } 2627 2628 static void 2629 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2630 { 2631 if (dma->dma_tag == NULL) 2632 return; 2633 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2634 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2635 bus_dma_tag_destroy(dma->dma_tag); 2636 } 2637 2638 static int 2639 em_create_tx_ring(struct adapter *adapter) 2640 { 2641 device_t dev = adapter->dev; 2642 struct em_buffer *tx_buffer; 2643 int error, i; 2644 2645 adapter->tx_buffer_area = 2646 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc, 2647 M_DEVBUF, M_WAITOK | M_ZERO); 2648 2649 /* 2650 * Create DMA tags for tx buffers 2651 */ 2652 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 2653 1, 0, /* alignment, bounds */ 2654 BUS_SPACE_MAXADDR, /* lowaddr */ 2655 BUS_SPACE_MAXADDR, /* highaddr */ 2656 NULL, NULL, /* filter, filterarg */ 2657 EM_TSO_SIZE, /* maxsize */ 2658 EM_MAX_SCATTER, /* nsegments */ 2659 PAGE_SIZE, /* maxsegsize */ 2660 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2661 BUS_DMA_ONEBPAGE, /* flags */ 2662 &adapter->txtag); 2663 if (error) { 2664 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2665 kfree(adapter->tx_buffer_area, M_DEVBUF); 2666 adapter->tx_buffer_area = NULL; 2667 return error; 2668 } 2669 2670 /* 2671 * Create DMA maps for tx buffers 2672 */ 2673 for (i = 0; i < adapter->num_tx_desc; i++) { 2674 tx_buffer = &adapter->tx_buffer_area[i]; 2675 2676 error = bus_dmamap_create(adapter->txtag, 2677 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2678 &tx_buffer->map); 2679 if (error) { 2680 device_printf(dev, "Unable to create TX DMA map\n"); 2681 em_destroy_tx_ring(adapter, i); 2682 return error; 2683 } 2684 } 2685 return (0); 2686 } 2687 2688 static void 2689 em_init_tx_ring(struct adapter *adapter) 2690 { 2691 /* Clear the old ring contents */ 2692 bzero(adapter->tx_desc_base, 2693 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 2694 2695 /* Reset state */ 2696 adapter->next_avail_tx_desc = 0; 2697 adapter->next_tx_to_clean = 0; 2698 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2699 } 2700 2701 static void 2702 em_init_tx_unit(struct adapter *adapter) 2703 { 2704 uint32_t tctl, tarc, tipg = 0; 2705 uint64_t bus_addr; 2706 2707 /* Setup the Base and Length of the Tx Descriptor Ring */ 2708 bus_addr = adapter->txdma.dma_paddr; 2709 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 2710 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 2711 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 2712 (uint32_t)(bus_addr >> 32)); 2713 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 2714 (uint32_t)bus_addr); 2715 /* Setup the HW Tx Head and Tail descriptor pointers */ 2716 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 2717 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 2718 2719 /* Set the default values for the Tx Inter Packet Gap timer */ 2720 switch (adapter->hw.mac.type) { 2721 case e1000_82542: 2722 tipg = DEFAULT_82542_TIPG_IPGT; 2723 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2724 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2725 break; 2726 2727 case e1000_80003es2lan: 2728 tipg = DEFAULT_82543_TIPG_IPGR1; 2729 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2730 E1000_TIPG_IPGR2_SHIFT; 2731 break; 2732 2733 default: 2734 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2735 adapter->hw.phy.media_type == 2736 e1000_media_type_internal_serdes) 2737 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2738 else 2739 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2740 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2741 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2742 break; 2743 } 2744 2745 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2746 2747 /* NOTE: 0 is not allowed for TIDV */ 2748 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1); 2749 if(adapter->hw.mac.type >= e1000_82540) 2750 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0); 2751 2752 if (adapter->hw.mac.type == e1000_82571 || 2753 adapter->hw.mac.type == e1000_82572) { 2754 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2755 tarc |= SPEED_MODE_BIT; 2756 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2757 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2758 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2759 tarc |= 1; 2760 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2761 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2762 tarc |= 1; 2763 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2764 } 2765 2766 /* Program the Transmit Control Register */ 2767 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2768 tctl &= ~E1000_TCTL_CT; 2769 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2770 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2771 2772 if (adapter->hw.mac.type >= e1000_82571) 2773 tctl |= E1000_TCTL_MULR; 2774 2775 /* This write will effectively turn on the transmit unit. */ 2776 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2777 2778 if (adapter->hw.mac.type == e1000_82571 || 2779 adapter->hw.mac.type == e1000_82572 || 2780 adapter->hw.mac.type == e1000_80003es2lan) { 2781 /* Bit 28 of TARC1 must be cleared when MULR is enabled */ 2782 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2783 tarc &= ~(1 << 28); 2784 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2785 } 2786 } 2787 2788 static void 2789 em_destroy_tx_ring(struct adapter *adapter, int ndesc) 2790 { 2791 struct em_buffer *tx_buffer; 2792 int i; 2793 2794 if (adapter->tx_buffer_area == NULL) 2795 return; 2796 2797 for (i = 0; i < ndesc; i++) { 2798 tx_buffer = &adapter->tx_buffer_area[i]; 2799 2800 KKASSERT(tx_buffer->m_head == NULL); 2801 bus_dmamap_destroy(adapter->txtag, tx_buffer->map); 2802 } 2803 bus_dma_tag_destroy(adapter->txtag); 2804 2805 kfree(adapter->tx_buffer_area, M_DEVBUF); 2806 adapter->tx_buffer_area = NULL; 2807 } 2808 2809 /* 2810 * The offload context needs to be set when we transfer the first 2811 * packet of a particular protocol (TCP/UDP). This routine has been 2812 * enhanced to deal with inserted VLAN headers. 2813 * 2814 * If the new packet's ether header length, ip header length and 2815 * csum offloading type are same as the previous packet, we should 2816 * avoid allocating a new csum context descriptor; mainly to take 2817 * advantage of the pipeline effect of the TX data read request. 2818 * 2819 * This function returns number of TX descrptors allocated for 2820 * csum context. 2821 */ 2822 static int 2823 em_txcsum(struct adapter *adapter, struct mbuf *mp, 2824 uint32_t *txd_upper, uint32_t *txd_lower) 2825 { 2826 struct e1000_context_desc *TXD; 2827 int curr_txd, ehdrlen, csum_flags; 2828 uint32_t cmd, hdr_len, ip_hlen; 2829 2830 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES; 2831 ip_hlen = mp->m_pkthdr.csum_iphlen; 2832 ehdrlen = mp->m_pkthdr.csum_lhlen; 2833 2834 if (adapter->csum_lhlen == ehdrlen && 2835 adapter->csum_iphlen == ip_hlen && 2836 adapter->csum_flags == csum_flags) { 2837 /* 2838 * Same csum offload context as the previous packets; 2839 * just return. 2840 */ 2841 *txd_upper = adapter->csum_txd_upper; 2842 *txd_lower = adapter->csum_txd_lower; 2843 return 0; 2844 } 2845 2846 /* 2847 * Setup a new csum offload context. 2848 */ 2849 2850 curr_txd = adapter->next_avail_tx_desc; 2851 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 2852 2853 cmd = 0; 2854 2855 /* Setup of IP header checksum. */ 2856 if (csum_flags & CSUM_IP) { 2857 /* 2858 * Start offset for header checksum calculation. 2859 * End offset for header checksum calculation. 2860 * Offset of place to put the checksum. 2861 */ 2862 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2863 TXD->lower_setup.ip_fields.ipcse = 2864 htole16(ehdrlen + ip_hlen - 1); 2865 TXD->lower_setup.ip_fields.ipcso = 2866 ehdrlen + offsetof(struct ip, ip_sum); 2867 cmd |= E1000_TXD_CMD_IP; 2868 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2869 } 2870 hdr_len = ehdrlen + ip_hlen; 2871 2872 if (csum_flags & CSUM_TCP) { 2873 /* 2874 * Start offset for payload checksum calculation. 2875 * End offset for payload checksum calculation. 2876 * Offset of place to put the checksum. 2877 */ 2878 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2879 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2880 TXD->upper_setup.tcp_fields.tucso = 2881 hdr_len + offsetof(struct tcphdr, th_sum); 2882 cmd |= E1000_TXD_CMD_TCP; 2883 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2884 } else if (csum_flags & CSUM_UDP) { 2885 /* 2886 * Start offset for header checksum calculation. 2887 * End offset for header checksum calculation. 2888 * Offset of place to put the checksum. 2889 */ 2890 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2891 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2892 TXD->upper_setup.tcp_fields.tucso = 2893 hdr_len + offsetof(struct udphdr, uh_sum); 2894 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2895 } 2896 2897 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2898 E1000_TXD_DTYP_D; /* Data descr */ 2899 2900 /* Save the information for this csum offloading context */ 2901 adapter->csum_lhlen = ehdrlen; 2902 adapter->csum_iphlen = ip_hlen; 2903 adapter->csum_flags = csum_flags; 2904 adapter->csum_txd_upper = *txd_upper; 2905 adapter->csum_txd_lower = *txd_lower; 2906 2907 TXD->tcp_seg_setup.data = htole32(0); 2908 TXD->cmd_and_length = 2909 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2910 2911 if (++curr_txd == adapter->num_tx_desc) 2912 curr_txd = 0; 2913 2914 KKASSERT(adapter->num_tx_desc_avail > 0); 2915 adapter->num_tx_desc_avail--; 2916 2917 adapter->next_avail_tx_desc = curr_txd; 2918 return 1; 2919 } 2920 2921 static void 2922 em_txeof(struct adapter *adapter) 2923 { 2924 struct ifnet *ifp = &adapter->arpcom.ac_if; 2925 struct em_buffer *tx_buffer; 2926 int first, num_avail; 2927 2928 if (adapter->tx_dd_head == adapter->tx_dd_tail) 2929 return; 2930 2931 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2932 return; 2933 2934 num_avail = adapter->num_tx_desc_avail; 2935 first = adapter->next_tx_to_clean; 2936 2937 while (adapter->tx_dd_head != adapter->tx_dd_tail) { 2938 struct e1000_tx_desc *tx_desc; 2939 int dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2940 2941 tx_desc = &adapter->tx_desc_base[dd_idx]; 2942 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2943 EM_INC_TXDD_IDX(adapter->tx_dd_head); 2944 2945 if (++dd_idx == adapter->num_tx_desc) 2946 dd_idx = 0; 2947 2948 while (first != dd_idx) { 2949 logif(pkt_txclean); 2950 2951 num_avail++; 2952 2953 tx_buffer = &adapter->tx_buffer_area[first]; 2954 if (tx_buffer->m_head) { 2955 IFNET_STAT_INC(ifp, opackets, 1); 2956 bus_dmamap_unload(adapter->txtag, 2957 tx_buffer->map); 2958 m_freem(tx_buffer->m_head); 2959 tx_buffer->m_head = NULL; 2960 } 2961 2962 if (++first == adapter->num_tx_desc) 2963 first = 0; 2964 } 2965 } else { 2966 break; 2967 } 2968 } 2969 adapter->next_tx_to_clean = first; 2970 adapter->num_tx_desc_avail = num_avail; 2971 2972 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 2973 adapter->tx_dd_head = 0; 2974 adapter->tx_dd_tail = 0; 2975 } 2976 2977 if (!EM_IS_OACTIVE(adapter)) { 2978 ifq_clr_oactive(&ifp->if_snd); 2979 2980 /* All clean, turn off the timer */ 2981 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2982 ifp->if_timer = 0; 2983 } 2984 } 2985 2986 static void 2987 em_tx_collect(struct adapter *adapter) 2988 { 2989 struct ifnet *ifp = &adapter->arpcom.ac_if; 2990 struct em_buffer *tx_buffer; 2991 int tdh, first, num_avail, dd_idx = -1; 2992 2993 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2994 return; 2995 2996 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0)); 2997 if (tdh == adapter->next_tx_to_clean) 2998 return; 2999 3000 if (adapter->tx_dd_head != adapter->tx_dd_tail) 3001 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3002 3003 num_avail = adapter->num_tx_desc_avail; 3004 first = adapter->next_tx_to_clean; 3005 3006 while (first != tdh) { 3007 logif(pkt_txclean); 3008 3009 num_avail++; 3010 3011 tx_buffer = &adapter->tx_buffer_area[first]; 3012 if (tx_buffer->m_head) { 3013 IFNET_STAT_INC(ifp, opackets, 1); 3014 bus_dmamap_unload(adapter->txtag, 3015 tx_buffer->map); 3016 m_freem(tx_buffer->m_head); 3017 tx_buffer->m_head = NULL; 3018 } 3019 3020 if (first == dd_idx) { 3021 EM_INC_TXDD_IDX(adapter->tx_dd_head); 3022 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 3023 adapter->tx_dd_head = 0; 3024 adapter->tx_dd_tail = 0; 3025 dd_idx = -1; 3026 } else { 3027 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3028 } 3029 } 3030 3031 if (++first == adapter->num_tx_desc) 3032 first = 0; 3033 } 3034 adapter->next_tx_to_clean = first; 3035 adapter->num_tx_desc_avail = num_avail; 3036 3037 if (!EM_IS_OACTIVE(adapter)) { 3038 ifq_clr_oactive(&ifp->if_snd); 3039 3040 /* All clean, turn off the timer */ 3041 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3042 ifp->if_timer = 0; 3043 } 3044 } 3045 3046 /* 3047 * When Link is lost sometimes there is work still in the TX ring 3048 * which will result in a watchdog, rather than allow that do an 3049 * attempted cleanup and then reinit here. Note that this has been 3050 * seens mostly with fiber adapters. 3051 */ 3052 static void 3053 em_tx_purge(struct adapter *adapter) 3054 { 3055 struct ifnet *ifp = &adapter->arpcom.ac_if; 3056 3057 if (!adapter->link_active && ifp->if_timer) { 3058 em_tx_collect(adapter); 3059 if (ifp->if_timer) { 3060 if_printf(ifp, "Link lost, TX pending, reinit\n"); 3061 ifp->if_timer = 0; 3062 em_init(adapter); 3063 } 3064 } 3065 } 3066 3067 static int 3068 em_newbuf(struct adapter *adapter, int i, int init) 3069 { 3070 struct mbuf *m; 3071 bus_dma_segment_t seg; 3072 bus_dmamap_t map; 3073 struct em_buffer *rx_buffer; 3074 int error, nseg; 3075 3076 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 3077 if (m == NULL) { 3078 adapter->mbuf_cluster_failed++; 3079 if (init) { 3080 if_printf(&adapter->arpcom.ac_if, 3081 "Unable to allocate RX mbuf\n"); 3082 } 3083 return (ENOBUFS); 3084 } 3085 m->m_len = m->m_pkthdr.len = MCLBYTES; 3086 3087 if (adapter->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN) 3088 m_adj(m, ETHER_ALIGN); 3089 3090 error = bus_dmamap_load_mbuf_segment(adapter->rxtag, 3091 adapter->rx_sparemap, m, 3092 &seg, 1, &nseg, BUS_DMA_NOWAIT); 3093 if (error) { 3094 m_freem(m); 3095 if (init) { 3096 if_printf(&adapter->arpcom.ac_if, 3097 "Unable to load RX mbuf\n"); 3098 } 3099 return (error); 3100 } 3101 3102 rx_buffer = &adapter->rx_buffer_area[i]; 3103 if (rx_buffer->m_head != NULL) 3104 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 3105 3106 map = rx_buffer->map; 3107 rx_buffer->map = adapter->rx_sparemap; 3108 adapter->rx_sparemap = map; 3109 3110 rx_buffer->m_head = m; 3111 3112 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr); 3113 return (0); 3114 } 3115 3116 static int 3117 em_create_rx_ring(struct adapter *adapter) 3118 { 3119 device_t dev = adapter->dev; 3120 struct em_buffer *rx_buffer; 3121 int i, error; 3122 3123 adapter->rx_buffer_area = 3124 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc, 3125 M_DEVBUF, M_WAITOK | M_ZERO); 3126 3127 /* 3128 * Create DMA tag for rx buffers 3129 */ 3130 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 3131 1, 0, /* alignment, bounds */ 3132 BUS_SPACE_MAXADDR, /* lowaddr */ 3133 BUS_SPACE_MAXADDR, /* highaddr */ 3134 NULL, NULL, /* filter, filterarg */ 3135 MCLBYTES, /* maxsize */ 3136 1, /* nsegments */ 3137 MCLBYTES, /* maxsegsize */ 3138 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 3139 &adapter->rxtag); 3140 if (error) { 3141 device_printf(dev, "Unable to allocate RX DMA tag\n"); 3142 kfree(adapter->rx_buffer_area, M_DEVBUF); 3143 adapter->rx_buffer_area = NULL; 3144 return error; 3145 } 3146 3147 /* 3148 * Create spare DMA map for rx buffers 3149 */ 3150 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3151 &adapter->rx_sparemap); 3152 if (error) { 3153 device_printf(dev, "Unable to create spare RX DMA map\n"); 3154 bus_dma_tag_destroy(adapter->rxtag); 3155 kfree(adapter->rx_buffer_area, M_DEVBUF); 3156 adapter->rx_buffer_area = NULL; 3157 return error; 3158 } 3159 3160 /* 3161 * Create DMA maps for rx buffers 3162 */ 3163 for (i = 0; i < adapter->num_rx_desc; i++) { 3164 rx_buffer = &adapter->rx_buffer_area[i]; 3165 3166 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3167 &rx_buffer->map); 3168 if (error) { 3169 device_printf(dev, "Unable to create RX DMA map\n"); 3170 em_destroy_rx_ring(adapter, i); 3171 return error; 3172 } 3173 } 3174 return (0); 3175 } 3176 3177 static int 3178 em_init_rx_ring(struct adapter *adapter) 3179 { 3180 int i, error; 3181 3182 /* Reset descriptor ring */ 3183 bzero(adapter->rx_desc_base, 3184 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 3185 3186 /* Allocate new ones. */ 3187 for (i = 0; i < adapter->num_rx_desc; i++) { 3188 error = em_newbuf(adapter, i, 1); 3189 if (error) 3190 return (error); 3191 } 3192 3193 /* Setup our descriptor pointers */ 3194 adapter->next_rx_desc_to_check = 0; 3195 3196 return (0); 3197 } 3198 3199 static void 3200 em_init_rx_unit(struct adapter *adapter) 3201 { 3202 struct ifnet *ifp = &adapter->arpcom.ac_if; 3203 uint64_t bus_addr; 3204 uint32_t rctl; 3205 3206 /* 3207 * Make sure receives are disabled while setting 3208 * up the descriptor ring 3209 */ 3210 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3211 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3212 3213 if (adapter->hw.mac.type >= e1000_82540) { 3214 uint32_t itr; 3215 3216 /* 3217 * Set the interrupt throttling rate. Value is calculated 3218 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 3219 */ 3220 if (adapter->int_throttle_ceil) 3221 itr = 1000000000 / 256 / adapter->int_throttle_ceil; 3222 else 3223 itr = 0; 3224 em_set_itr(adapter, itr); 3225 } 3226 3227 /* Disable accelerated ackknowledge */ 3228 if (adapter->hw.mac.type == e1000_82574) { 3229 E1000_WRITE_REG(&adapter->hw, 3230 E1000_RFCTL, E1000_RFCTL_ACK_DIS); 3231 } 3232 3233 /* Receive Checksum Offload for TCP and UDP */ 3234 if (ifp->if_capenable & IFCAP_RXCSUM) { 3235 uint32_t rxcsum; 3236 3237 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 3238 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3239 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum); 3240 } 3241 3242 /* 3243 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3244 * long latencies are observed, like Lenovo X60. This 3245 * change eliminates the problem, but since having positive 3246 * values in RDTR is a known source of problems on other 3247 * platforms another solution is being sought. 3248 */ 3249 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) { 3250 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573); 3251 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573); 3252 } 3253 3254 /* 3255 * Setup the Base and Length of the Rx Descriptor Ring 3256 */ 3257 bus_addr = adapter->rxdma.dma_paddr; 3258 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 3259 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 3260 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 3261 (uint32_t)(bus_addr >> 32)); 3262 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 3263 (uint32_t)bus_addr); 3264 3265 /* 3266 * Setup the HW Rx Head and Tail Descriptor Pointers 3267 */ 3268 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 3269 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 3270 3271 /* Set PTHRESH for improved jumbo performance */ 3272 if (((adapter->hw.mac.type == e1000_ich9lan) || 3273 (adapter->hw.mac.type == e1000_pch2lan) || 3274 (adapter->hw.mac.type == e1000_ich10lan)) && 3275 (ifp->if_mtu > ETHERMTU)) { 3276 uint32_t rxdctl; 3277 3278 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0)); 3279 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3); 3280 } 3281 3282 if (adapter->hw.mac.type >= e1000_pch2lan) { 3283 if (ifp->if_mtu > ETHERMTU) 3284 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE); 3285 else 3286 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE); 3287 } 3288 3289 /* Setup the Receive Control Register */ 3290 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3291 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3292 E1000_RCTL_RDMTS_HALF | 3293 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3294 3295 /* Make sure VLAN Filters are off */ 3296 rctl &= ~E1000_RCTL_VFE; 3297 3298 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 3299 rctl |= E1000_RCTL_SBP; 3300 else 3301 rctl &= ~E1000_RCTL_SBP; 3302 3303 switch (adapter->rx_buffer_len) { 3304 default: 3305 case 2048: 3306 rctl |= E1000_RCTL_SZ_2048; 3307 break; 3308 3309 case 4096: 3310 rctl |= E1000_RCTL_SZ_4096 | 3311 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3312 break; 3313 3314 case 8192: 3315 rctl |= E1000_RCTL_SZ_8192 | 3316 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3317 break; 3318 3319 case 16384: 3320 rctl |= E1000_RCTL_SZ_16384 | 3321 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3322 break; 3323 } 3324 3325 if (ifp->if_mtu > ETHERMTU) 3326 rctl |= E1000_RCTL_LPE; 3327 else 3328 rctl &= ~E1000_RCTL_LPE; 3329 3330 /* Enable Receives */ 3331 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3332 } 3333 3334 static void 3335 em_destroy_rx_ring(struct adapter *adapter, int ndesc) 3336 { 3337 struct em_buffer *rx_buffer; 3338 int i; 3339 3340 if (adapter->rx_buffer_area == NULL) 3341 return; 3342 3343 for (i = 0; i < ndesc; i++) { 3344 rx_buffer = &adapter->rx_buffer_area[i]; 3345 3346 KKASSERT(rx_buffer->m_head == NULL); 3347 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map); 3348 } 3349 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 3350 bus_dma_tag_destroy(adapter->rxtag); 3351 3352 kfree(adapter->rx_buffer_area, M_DEVBUF); 3353 adapter->rx_buffer_area = NULL; 3354 } 3355 3356 static void 3357 em_rxeof(struct adapter *adapter, int count) 3358 { 3359 struct ifnet *ifp = &adapter->arpcom.ac_if; 3360 uint8_t status, accept_frame = 0, eop = 0; 3361 uint16_t len, desc_len, prev_len_adj; 3362 struct e1000_rx_desc *current_desc; 3363 struct mbuf *mp; 3364 int i; 3365 3366 i = adapter->next_rx_desc_to_check; 3367 current_desc = &adapter->rx_desc_base[i]; 3368 3369 if (!(current_desc->status & E1000_RXD_STAT_DD)) 3370 return; 3371 3372 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) { 3373 struct mbuf *m = NULL; 3374 3375 logif(pkt_receive); 3376 3377 mp = adapter->rx_buffer_area[i].m_head; 3378 3379 /* 3380 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3381 * needs to access the last received byte in the mbuf. 3382 */ 3383 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3384 BUS_DMASYNC_POSTREAD); 3385 3386 accept_frame = 1; 3387 prev_len_adj = 0; 3388 desc_len = le16toh(current_desc->length); 3389 status = current_desc->status; 3390 if (status & E1000_RXD_STAT_EOP) { 3391 count--; 3392 eop = 1; 3393 if (desc_len < ETHER_CRC_LEN) { 3394 len = 0; 3395 prev_len_adj = ETHER_CRC_LEN - desc_len; 3396 } else { 3397 len = desc_len - ETHER_CRC_LEN; 3398 } 3399 } else { 3400 eop = 0; 3401 len = desc_len; 3402 } 3403 3404 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3405 uint8_t last_byte; 3406 uint32_t pkt_len = desc_len; 3407 3408 if (adapter->fmp != NULL) 3409 pkt_len += adapter->fmp->m_pkthdr.len; 3410 3411 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3412 if (TBI_ACCEPT(&adapter->hw, status, 3413 current_desc->errors, pkt_len, last_byte, 3414 adapter->min_frame_size, 3415 adapter->hw.mac.max_frame_size)) { 3416 e1000_tbi_adjust_stats_82543(&adapter->hw, 3417 &adapter->stats, pkt_len, 3418 adapter->hw.mac.addr, 3419 adapter->hw.mac.max_frame_size); 3420 if (len > 0) 3421 len--; 3422 } else { 3423 accept_frame = 0; 3424 } 3425 } 3426 3427 if (accept_frame) { 3428 if (em_newbuf(adapter, i, 0) != 0) { 3429 IFNET_STAT_INC(ifp, iqdrops, 1); 3430 goto discard; 3431 } 3432 3433 /* Assign correct length to the current fragment */ 3434 mp->m_len = len; 3435 3436 if (adapter->fmp == NULL) { 3437 mp->m_pkthdr.len = len; 3438 adapter->fmp = mp; /* Store the first mbuf */ 3439 adapter->lmp = mp; 3440 } else { 3441 /* 3442 * Chain mbuf's together 3443 */ 3444 3445 /* 3446 * Adjust length of previous mbuf in chain if 3447 * we received less than 4 bytes in the last 3448 * descriptor. 3449 */ 3450 if (prev_len_adj > 0) { 3451 adapter->lmp->m_len -= prev_len_adj; 3452 adapter->fmp->m_pkthdr.len -= 3453 prev_len_adj; 3454 } 3455 adapter->lmp->m_next = mp; 3456 adapter->lmp = adapter->lmp->m_next; 3457 adapter->fmp->m_pkthdr.len += len; 3458 } 3459 3460 if (eop) { 3461 adapter->fmp->m_pkthdr.rcvif = ifp; 3462 IFNET_STAT_INC(ifp, ipackets, 1); 3463 3464 if (ifp->if_capenable & IFCAP_RXCSUM) { 3465 em_rxcsum(adapter, current_desc, 3466 adapter->fmp); 3467 } 3468 3469 if (status & E1000_RXD_STAT_VP) { 3470 adapter->fmp->m_pkthdr.ether_vlantag = 3471 (le16toh(current_desc->special) & 3472 E1000_RXD_SPC_VLAN_MASK); 3473 adapter->fmp->m_flags |= M_VLANTAG; 3474 } 3475 m = adapter->fmp; 3476 adapter->fmp = NULL; 3477 adapter->lmp = NULL; 3478 } 3479 } else { 3480 IFNET_STAT_INC(ifp, ierrors, 1); 3481 discard: 3482 #ifdef foo 3483 /* Reuse loaded DMA map and just update mbuf chain */ 3484 mp = adapter->rx_buffer_area[i].m_head; 3485 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 3486 mp->m_data = mp->m_ext.ext_buf; 3487 mp->m_next = NULL; 3488 if (adapter->hw.mac.max_frame_size <= 3489 (MCLBYTES - ETHER_ALIGN)) 3490 m_adj(mp, ETHER_ALIGN); 3491 #endif 3492 if (adapter->fmp != NULL) { 3493 m_freem(adapter->fmp); 3494 adapter->fmp = NULL; 3495 adapter->lmp = NULL; 3496 } 3497 m = NULL; 3498 } 3499 3500 /* Zero out the receive descriptors status. */ 3501 current_desc->status = 0; 3502 3503 if (m != NULL) 3504 ifp->if_input(ifp, m); 3505 3506 /* Advance our pointers to the next descriptor. */ 3507 if (++i == adapter->num_rx_desc) 3508 i = 0; 3509 current_desc = &adapter->rx_desc_base[i]; 3510 } 3511 adapter->next_rx_desc_to_check = i; 3512 3513 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3514 if (--i < 0) 3515 i = adapter->num_rx_desc - 1; 3516 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 3517 } 3518 3519 static void 3520 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc, 3521 struct mbuf *mp) 3522 { 3523 /* 82543 or newer only */ 3524 if (adapter->hw.mac.type < e1000_82543 || 3525 /* Ignore Checksum bit is set */ 3526 (rx_desc->status & E1000_RXD_STAT_IXSM)) 3527 return; 3528 3529 if ((rx_desc->status & E1000_RXD_STAT_IPCS) && 3530 !(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3531 /* IP Checksum Good */ 3532 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 3533 } 3534 3535 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) && 3536 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3537 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3538 CSUM_PSEUDO_HDR | 3539 CSUM_FRAG_NOT_CHECKED; 3540 mp->m_pkthdr.csum_data = htons(0xffff); 3541 } 3542 } 3543 3544 static void 3545 em_enable_intr(struct adapter *adapter) 3546 { 3547 uint32_t ims_mask = IMS_ENABLE_MASK; 3548 3549 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer); 3550 3551 #if 0 3552 /* XXX MSIX */ 3553 if (adapter->hw.mac.type == e1000_82574) { 3554 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK); 3555 ims_mask |= EM_MSIX_MASK; 3556 } 3557 #endif 3558 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask); 3559 } 3560 3561 static void 3562 em_disable_intr(struct adapter *adapter) 3563 { 3564 uint32_t clear = 0xffffffff; 3565 3566 /* 3567 * The first version of 82542 had an errata where when link was forced 3568 * it would stay up even up even if the cable was disconnected. 3569 * Sequence errors were used to detect the disconnect and then the 3570 * driver would unforce the link. This code in the in the ISR. For 3571 * this to work correctly the Sequence error interrupt had to be 3572 * enabled all the time. 3573 */ 3574 if (adapter->hw.mac.type == e1000_82542 && 3575 adapter->hw.revision_id == E1000_REVISION_2) 3576 clear &= ~E1000_ICR_RXSEQ; 3577 else if (adapter->hw.mac.type == e1000_82574) 3578 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0); 3579 3580 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear); 3581 3582 adapter->npoll.ifpc_stcount = 0; 3583 3584 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer); 3585 } 3586 3587 /* 3588 * Bit of a misnomer, what this really means is 3589 * to enable OS management of the system... aka 3590 * to disable special hardware management features 3591 */ 3592 static void 3593 em_get_mgmt(struct adapter *adapter) 3594 { 3595 /* A shared code workaround */ 3596 #define E1000_82542_MANC2H E1000_MANC2H 3597 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3598 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3599 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3600 3601 /* disable hardware interception of ARP */ 3602 manc &= ~(E1000_MANC_ARP_EN); 3603 3604 /* enable receiving management packets to the host */ 3605 if (adapter->hw.mac.type >= e1000_82571) { 3606 manc |= E1000_MANC_EN_MNG2HOST; 3607 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3608 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3609 manc2h |= E1000_MNG2HOST_PORT_623; 3610 manc2h |= E1000_MNG2HOST_PORT_664; 3611 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3612 } 3613 3614 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3615 } 3616 } 3617 3618 /* 3619 * Give control back to hardware management 3620 * controller if there is one. 3621 */ 3622 static void 3623 em_rel_mgmt(struct adapter *adapter) 3624 { 3625 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3626 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3627 3628 /* re-enable hardware interception of ARP */ 3629 manc |= E1000_MANC_ARP_EN; 3630 3631 if (adapter->hw.mac.type >= e1000_82571) 3632 manc &= ~E1000_MANC_EN_MNG2HOST; 3633 3634 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3635 } 3636 } 3637 3638 /* 3639 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3640 * For ASF and Pass Through versions of f/w this means that 3641 * the driver is loaded. For AMT version (only with 82573) 3642 * of the f/w this means that the network i/f is open. 3643 */ 3644 static void 3645 em_get_hw_control(struct adapter *adapter) 3646 { 3647 /* Let firmware know the driver has taken over */ 3648 if (adapter->hw.mac.type == e1000_82573) { 3649 uint32_t swsm; 3650 3651 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3652 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3653 swsm | E1000_SWSM_DRV_LOAD); 3654 } else { 3655 uint32_t ctrl_ext; 3656 3657 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3658 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3659 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3660 } 3661 adapter->flags |= EM_FLAG_HW_CTRL; 3662 } 3663 3664 /* 3665 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3666 * For ASF and Pass Through versions of f/w this means that the 3667 * driver is no longer loaded. For AMT version (only with 82573) 3668 * of the f/w this means that the network i/f is closed. 3669 */ 3670 static void 3671 em_rel_hw_control(struct adapter *adapter) 3672 { 3673 if ((adapter->flags & EM_FLAG_HW_CTRL) == 0) 3674 return; 3675 adapter->flags &= ~EM_FLAG_HW_CTRL; 3676 3677 /* Let firmware taken over control of h/w */ 3678 if (adapter->hw.mac.type == e1000_82573) { 3679 uint32_t swsm; 3680 3681 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3682 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3683 swsm & ~E1000_SWSM_DRV_LOAD); 3684 } else { 3685 uint32_t ctrl_ext; 3686 3687 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3688 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3689 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3690 } 3691 } 3692 3693 static int 3694 em_is_valid_eaddr(const uint8_t *addr) 3695 { 3696 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3697 3698 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3699 return (FALSE); 3700 3701 return (TRUE); 3702 } 3703 3704 /* 3705 * Enable PCI Wake On Lan capability 3706 */ 3707 void 3708 em_enable_wol(device_t dev) 3709 { 3710 uint16_t cap, status; 3711 uint8_t id; 3712 3713 /* First find the capabilities pointer*/ 3714 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3715 3716 /* Read the PM Capabilities */ 3717 id = pci_read_config(dev, cap, 1); 3718 if (id != PCIY_PMG) /* Something wrong */ 3719 return; 3720 3721 /* 3722 * OK, we have the power capabilities, 3723 * so now get the status register 3724 */ 3725 cap += PCIR_POWER_STATUS; 3726 status = pci_read_config(dev, cap, 2); 3727 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3728 pci_write_config(dev, cap, status, 2); 3729 } 3730 3731 3732 /* 3733 * 82544 Coexistence issue workaround. 3734 * There are 2 issues. 3735 * 1. Transmit Hang issue. 3736 * To detect this issue, following equation can be used... 3737 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3738 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3739 * 3740 * 2. DAC issue. 3741 * To detect this issue, following equation can be used... 3742 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3743 * If SUM[3:0] is in between 9 to c, we will have this issue. 3744 * 3745 * WORKAROUND: 3746 * Make sure we do not have ending address 3747 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3748 */ 3749 static uint32_t 3750 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array) 3751 { 3752 uint32_t safe_terminator; 3753 3754 /* 3755 * Since issue is sensitive to length and address. 3756 * Let us first check the address... 3757 */ 3758 if (length <= 4) { 3759 desc_array->descriptor[0].address = address; 3760 desc_array->descriptor[0].length = length; 3761 desc_array->elements = 1; 3762 return (desc_array->elements); 3763 } 3764 3765 safe_terminator = 3766 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3767 3768 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3769 if (safe_terminator == 0 || 3770 (safe_terminator > 4 && safe_terminator < 9) || 3771 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 3772 desc_array->descriptor[0].address = address; 3773 desc_array->descriptor[0].length = length; 3774 desc_array->elements = 1; 3775 return (desc_array->elements); 3776 } 3777 3778 desc_array->descriptor[0].address = address; 3779 desc_array->descriptor[0].length = length - 4; 3780 desc_array->descriptor[1].address = address + (length - 4); 3781 desc_array->descriptor[1].length = 4; 3782 desc_array->elements = 2; 3783 return (desc_array->elements); 3784 } 3785 3786 static void 3787 em_update_stats(struct adapter *adapter) 3788 { 3789 struct ifnet *ifp = &adapter->arpcom.ac_if; 3790 3791 if (adapter->hw.phy.media_type == e1000_media_type_copper || 3792 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3793 adapter->stats.symerrs += 3794 E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3795 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3796 } 3797 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3798 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3799 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3800 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3801 3802 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3803 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3804 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3805 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3806 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3807 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3808 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3809 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3810 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3811 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3812 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3813 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3814 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3815 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3816 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3817 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3818 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3819 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3820 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3821 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3822 3823 /* For the 64-bit byte counters the low dword must be read first. */ 3824 /* Both registers clear on the read of the high dword */ 3825 3826 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 3827 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 3828 3829 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3830 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3831 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3832 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3833 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3834 3835 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3836 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3837 3838 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3839 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3840 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3841 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3842 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3843 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3844 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3845 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3846 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3847 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3848 3849 if (adapter->hw.mac.type >= e1000_82543) { 3850 adapter->stats.algnerrc += 3851 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3852 adapter->stats.rxerrc += 3853 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3854 adapter->stats.tncrs += 3855 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3856 adapter->stats.cexterr += 3857 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3858 adapter->stats.tsctc += 3859 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3860 adapter->stats.tsctfc += 3861 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3862 } 3863 3864 IFNET_STAT_SET(ifp, collisions, adapter->stats.colc); 3865 3866 /* Rx Errors */ 3867 IFNET_STAT_SET(ifp, ierrors, 3868 adapter->dropped_pkts + adapter->stats.rxerrc + 3869 adapter->stats.crcerrs + adapter->stats.algnerrc + 3870 adapter->stats.ruc + adapter->stats.roc + 3871 adapter->stats.mpc + adapter->stats.cexterr); 3872 3873 /* Tx Errors */ 3874 IFNET_STAT_SET(ifp, oerrors, 3875 adapter->stats.ecol + adapter->stats.latecol + 3876 adapter->watchdog_events); 3877 } 3878 3879 static void 3880 em_print_debug_info(struct adapter *adapter) 3881 { 3882 device_t dev = adapter->dev; 3883 uint8_t *hw_addr = adapter->hw.hw_addr; 3884 3885 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3886 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3887 E1000_READ_REG(&adapter->hw, E1000_CTRL), 3888 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 3889 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3890 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3891 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 3892 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3893 adapter->hw.fc.high_water, 3894 adapter->hw.fc.low_water); 3895 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3896 E1000_READ_REG(&adapter->hw, E1000_TIDV), 3897 E1000_READ_REG(&adapter->hw, E1000_TADV)); 3898 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3899 E1000_READ_REG(&adapter->hw, E1000_RDTR), 3900 E1000_READ_REG(&adapter->hw, E1000_RADV)); 3901 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3902 (long long)adapter->tx_fifo_wrk_cnt, 3903 (long long)adapter->tx_fifo_reset_cnt); 3904 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3905 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 3906 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 3907 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3908 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 3909 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 3910 device_printf(dev, "Num Tx descriptors avail = %d\n", 3911 adapter->num_tx_desc_avail); 3912 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3913 adapter->no_tx_desc_avail1); 3914 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3915 adapter->no_tx_desc_avail2); 3916 device_printf(dev, "Std mbuf failed = %ld\n", 3917 adapter->mbuf_alloc_failed); 3918 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3919 adapter->mbuf_cluster_failed); 3920 device_printf(dev, "Driver dropped packets = %ld\n", 3921 adapter->dropped_pkts); 3922 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3923 adapter->no_tx_dma_setup); 3924 } 3925 3926 static void 3927 em_print_hw_stats(struct adapter *adapter) 3928 { 3929 device_t dev = adapter->dev; 3930 3931 device_printf(dev, "Excessive collisions = %lld\n", 3932 (long long)adapter->stats.ecol); 3933 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3934 device_printf(dev, "Symbol errors = %lld\n", 3935 (long long)adapter->stats.symerrs); 3936 #endif 3937 device_printf(dev, "Sequence errors = %lld\n", 3938 (long long)adapter->stats.sec); 3939 device_printf(dev, "Defer count = %lld\n", 3940 (long long)adapter->stats.dc); 3941 device_printf(dev, "Missed Packets = %lld\n", 3942 (long long)adapter->stats.mpc); 3943 device_printf(dev, "Receive No Buffers = %lld\n", 3944 (long long)adapter->stats.rnbc); 3945 /* RLEC is inaccurate on some hardware, calculate our own. */ 3946 device_printf(dev, "Receive Length Errors = %lld\n", 3947 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 3948 device_printf(dev, "Receive errors = %lld\n", 3949 (long long)adapter->stats.rxerrc); 3950 device_printf(dev, "Crc errors = %lld\n", 3951 (long long)adapter->stats.crcerrs); 3952 device_printf(dev, "Alignment errors = %lld\n", 3953 (long long)adapter->stats.algnerrc); 3954 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3955 (long long)adapter->stats.cexterr); 3956 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 3957 device_printf(dev, "watchdog timeouts = %ld\n", 3958 adapter->watchdog_events); 3959 device_printf(dev, "XON Rcvd = %lld\n", 3960 (long long)adapter->stats.xonrxc); 3961 device_printf(dev, "XON Xmtd = %lld\n", 3962 (long long)adapter->stats.xontxc); 3963 device_printf(dev, "XOFF Rcvd = %lld\n", 3964 (long long)adapter->stats.xoffrxc); 3965 device_printf(dev, "XOFF Xmtd = %lld\n", 3966 (long long)adapter->stats.xofftxc); 3967 device_printf(dev, "Good Packets Rcvd = %lld\n", 3968 (long long)adapter->stats.gprc); 3969 device_printf(dev, "Good Packets Xmtd = %lld\n", 3970 (long long)adapter->stats.gptc); 3971 } 3972 3973 static void 3974 em_print_nvm_info(struct adapter *adapter) 3975 { 3976 uint16_t eeprom_data; 3977 int i, j, row = 0; 3978 3979 /* Its a bit crude, but it gets the job done */ 3980 kprintf("\nInterface EEPROM Dump:\n"); 3981 kprintf("Offset\n0x0000 "); 3982 for (i = 0, j = 0; i < 32; i++, j++) { 3983 if (j == 8) { /* Make the offset block */ 3984 j = 0; ++row; 3985 kprintf("\n0x00%x0 ",row); 3986 } 3987 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 3988 kprintf("%04x ", eeprom_data); 3989 } 3990 kprintf("\n"); 3991 } 3992 3993 static int 3994 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3995 { 3996 struct adapter *adapter; 3997 struct ifnet *ifp; 3998 int error, result; 3999 4000 result = -1; 4001 error = sysctl_handle_int(oidp, &result, 0, req); 4002 if (error || !req->newptr) 4003 return (error); 4004 4005 adapter = (struct adapter *)arg1; 4006 ifp = &adapter->arpcom.ac_if; 4007 4008 lwkt_serialize_enter(ifp->if_serializer); 4009 4010 if (result == 1) 4011 em_print_debug_info(adapter); 4012 4013 /* 4014 * This value will cause a hex dump of the 4015 * first 32 16-bit words of the EEPROM to 4016 * the screen. 4017 */ 4018 if (result == 2) 4019 em_print_nvm_info(adapter); 4020 4021 lwkt_serialize_exit(ifp->if_serializer); 4022 4023 return (error); 4024 } 4025 4026 static int 4027 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 4028 { 4029 int error, result; 4030 4031 result = -1; 4032 error = sysctl_handle_int(oidp, &result, 0, req); 4033 if (error || !req->newptr) 4034 return (error); 4035 4036 if (result == 1) { 4037 struct adapter *adapter = (struct adapter *)arg1; 4038 struct ifnet *ifp = &adapter->arpcom.ac_if; 4039 4040 lwkt_serialize_enter(ifp->if_serializer); 4041 em_print_hw_stats(adapter); 4042 lwkt_serialize_exit(ifp->if_serializer); 4043 } 4044 return (error); 4045 } 4046 4047 static void 4048 em_add_sysctl(struct adapter *adapter) 4049 { 4050 sysctl_ctx_init(&adapter->sysctl_ctx); 4051 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx, 4052 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 4053 device_get_nameunit(adapter->dev), 4054 CTLFLAG_RD, 0, ""); 4055 if (adapter->sysctl_tree == NULL) { 4056 device_printf(adapter->dev, "can't add sysctl node\n"); 4057 } else { 4058 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4059 SYSCTL_CHILDREN(adapter->sysctl_tree), 4060 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4061 em_sysctl_debug_info, "I", "Debug Information"); 4062 4063 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4064 SYSCTL_CHILDREN(adapter->sysctl_tree), 4065 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4066 em_sysctl_stats, "I", "Statistics"); 4067 4068 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4069 SYSCTL_CHILDREN(adapter->sysctl_tree), 4070 OID_AUTO, "rxd", CTLFLAG_RD, 4071 &adapter->num_rx_desc, 0, NULL); 4072 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4073 SYSCTL_CHILDREN(adapter->sysctl_tree), 4074 OID_AUTO, "txd", CTLFLAG_RD, 4075 &adapter->num_tx_desc, 0, NULL); 4076 4077 if (adapter->hw.mac.type >= e1000_82540) { 4078 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4079 SYSCTL_CHILDREN(adapter->sysctl_tree), 4080 OID_AUTO, "int_throttle_ceil", 4081 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4082 em_sysctl_int_throttle, "I", 4083 "interrupt throttling rate"); 4084 } 4085 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4086 SYSCTL_CHILDREN(adapter->sysctl_tree), 4087 OID_AUTO, "int_tx_nsegs", 4088 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4089 em_sysctl_int_tx_nsegs, "I", 4090 "# segments per TX interrupt"); 4091 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4092 SYSCTL_CHILDREN(adapter->sysctl_tree), 4093 OID_AUTO, "wreg_tx_nsegs", CTLFLAG_RW, 4094 &adapter->tx_wreg_nsegs, 0, 4095 "# segments before write to hardware register"); 4096 } 4097 } 4098 4099 static int 4100 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 4101 { 4102 struct adapter *adapter = (void *)arg1; 4103 struct ifnet *ifp = &adapter->arpcom.ac_if; 4104 int error, throttle; 4105 4106 throttle = adapter->int_throttle_ceil; 4107 error = sysctl_handle_int(oidp, &throttle, 0, req); 4108 if (error || req->newptr == NULL) 4109 return error; 4110 if (throttle < 0 || throttle > 1000000000 / 256) 4111 return EINVAL; 4112 4113 if (throttle) { 4114 /* 4115 * Set the interrupt throttling rate in 256ns increments, 4116 * recalculate sysctl value assignment to get exact frequency. 4117 */ 4118 throttle = 1000000000 / 256 / throttle; 4119 4120 /* Upper 16bits of ITR is reserved and should be zero */ 4121 if (throttle & 0xffff0000) 4122 return EINVAL; 4123 } 4124 4125 lwkt_serialize_enter(ifp->if_serializer); 4126 4127 if (throttle) 4128 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 4129 else 4130 adapter->int_throttle_ceil = 0; 4131 4132 if (ifp->if_flags & IFF_RUNNING) 4133 em_set_itr(adapter, throttle); 4134 4135 lwkt_serialize_exit(ifp->if_serializer); 4136 4137 if (bootverbose) { 4138 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 4139 adapter->int_throttle_ceil); 4140 } 4141 return 0; 4142 } 4143 4144 static int 4145 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 4146 { 4147 struct adapter *adapter = (void *)arg1; 4148 struct ifnet *ifp = &adapter->arpcom.ac_if; 4149 int error, segs; 4150 4151 segs = adapter->tx_int_nsegs; 4152 error = sysctl_handle_int(oidp, &segs, 0, req); 4153 if (error || req->newptr == NULL) 4154 return error; 4155 if (segs <= 0) 4156 return EINVAL; 4157 4158 lwkt_serialize_enter(ifp->if_serializer); 4159 4160 /* 4161 * Don't allow int_tx_nsegs to become: 4162 * o Less the oact_tx_desc 4163 * o Too large that no TX desc will cause TX interrupt to 4164 * be generated (OACTIVE will never recover) 4165 * o Too small that will cause tx_dd[] overflow 4166 */ 4167 if (segs < adapter->oact_tx_desc || 4168 segs >= adapter->num_tx_desc - adapter->oact_tx_desc || 4169 segs < adapter->num_tx_desc / EM_TXDD_SAFE) { 4170 error = EINVAL; 4171 } else { 4172 error = 0; 4173 adapter->tx_int_nsegs = segs; 4174 } 4175 4176 lwkt_serialize_exit(ifp->if_serializer); 4177 4178 return error; 4179 } 4180 4181 static void 4182 em_set_itr(struct adapter *adapter, uint32_t itr) 4183 { 4184 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr); 4185 if (adapter->hw.mac.type == e1000_82574) { 4186 int i; 4187 4188 /* 4189 * When using MSIX interrupts we need to 4190 * throttle using the EITR register 4191 */ 4192 for (i = 0; i < 4; ++i) { 4193 E1000_WRITE_REG(&adapter->hw, 4194 E1000_EITR_82574(i), itr); 4195 } 4196 } 4197 } 4198 4199 static void 4200 em_disable_aspm(struct adapter *adapter) 4201 { 4202 uint16_t link_cap, link_ctrl, disable; 4203 uint8_t pcie_ptr, reg; 4204 device_t dev = adapter->dev; 4205 4206 switch (adapter->hw.mac.type) { 4207 case e1000_82571: 4208 case e1000_82572: 4209 case e1000_82573: 4210 /* 4211 * 82573 specification update 4212 * errata #8 disable L0s 4213 * errata #41 disable L1 4214 * 4215 * 82571/82572 specification update 4216 # errata #13 disable L1 4217 * errata #68 disable L0s 4218 */ 4219 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 4220 break; 4221 4222 case e1000_82574: 4223 case e1000_82583: 4224 /* 4225 * 82574 specification update errata #20 4226 * 82583 specification update errata #9 4227 * 4228 * There is no need to disable L1 4229 */ 4230 disable = PCIEM_LNKCTL_ASPM_L0S; 4231 break; 4232 4233 default: 4234 return; 4235 } 4236 4237 pcie_ptr = pci_get_pciecap_ptr(dev); 4238 if (pcie_ptr == 0) 4239 return; 4240 4241 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 4242 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 4243 return; 4244 4245 if (bootverbose) { 4246 if_printf(&adapter->arpcom.ac_if, 4247 "disable ASPM %#02x\n", disable); 4248 } 4249 4250 reg = pcie_ptr + PCIER_LINKCTRL; 4251 link_ctrl = pci_read_config(dev, reg, 2); 4252 link_ctrl &= ~disable; 4253 pci_write_config(dev, reg, link_ctrl, 2); 4254 } 4255 4256 static int 4257 em_tso_pullup(struct adapter *adapter, struct mbuf **mp) 4258 { 4259 int iphlen, hoff, thoff, ex = 0; 4260 struct mbuf *m; 4261 struct ip *ip; 4262 4263 m = *mp; 4264 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 4265 4266 iphlen = m->m_pkthdr.csum_iphlen; 4267 thoff = m->m_pkthdr.csum_thlen; 4268 hoff = m->m_pkthdr.csum_lhlen; 4269 4270 KASSERT(iphlen > 0, ("invalid ip hlen")); 4271 KASSERT(thoff > 0, ("invalid tcp hlen")); 4272 KASSERT(hoff > 0, ("invalid ether hlen")); 4273 4274 if (adapter->flags & EM_FLAG_TSO_PULLEX) 4275 ex = 4; 4276 4277 if (m->m_len < hoff + iphlen + thoff + ex) { 4278 m = m_pullup(m, hoff + iphlen + thoff + ex); 4279 if (m == NULL) { 4280 *mp = NULL; 4281 return ENOBUFS; 4282 } 4283 *mp = m; 4284 } 4285 ip = mtodoff(m, struct ip *, hoff); 4286 ip->ip_len = 0; 4287 4288 return 0; 4289 } 4290 4291 static int 4292 em_tso_setup(struct adapter *adapter, struct mbuf *mp, 4293 uint32_t *txd_upper, uint32_t *txd_lower) 4294 { 4295 struct e1000_context_desc *TXD; 4296 int hoff, iphlen, thoff, hlen; 4297 int mss, pktlen, curr_txd; 4298 4299 iphlen = mp->m_pkthdr.csum_iphlen; 4300 thoff = mp->m_pkthdr.csum_thlen; 4301 hoff = mp->m_pkthdr.csum_lhlen; 4302 mss = mp->m_pkthdr.tso_segsz; 4303 pktlen = mp->m_pkthdr.len; 4304 4305 if (adapter->csum_flags == CSUM_TSO && 4306 adapter->csum_iphlen == iphlen && 4307 adapter->csum_lhlen == hoff && 4308 adapter->csum_thlen == thoff && 4309 adapter->csum_mss == mss && 4310 adapter->csum_pktlen == pktlen) { 4311 *txd_upper = adapter->csum_txd_upper; 4312 *txd_lower = adapter->csum_txd_lower; 4313 return 0; 4314 } 4315 hlen = hoff + iphlen + thoff; 4316 4317 /* 4318 * Setup a new TSO context. 4319 */ 4320 4321 curr_txd = adapter->next_avail_tx_desc; 4322 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 4323 4324 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 4325 E1000_TXD_DTYP_D | /* Data descr type */ 4326 E1000_TXD_CMD_TSE; /* Do TSE on this packet */ 4327 4328 /* IP and/or TCP header checksum calculation and insertion. */ 4329 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 4330 4331 /* 4332 * Start offset for header checksum calculation. 4333 * End offset for header checksum calculation. 4334 * Offset of place put the checksum. 4335 */ 4336 TXD->lower_setup.ip_fields.ipcss = hoff; 4337 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1); 4338 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum); 4339 4340 /* 4341 * Start offset for payload checksum calculation. 4342 * End offset for payload checksum calculation. 4343 * Offset of place to put the checksum. 4344 */ 4345 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen; 4346 TXD->upper_setup.tcp_fields.tucse = 0; 4347 TXD->upper_setup.tcp_fields.tucso = 4348 hoff + iphlen + offsetof(struct tcphdr, th_sum); 4349 4350 /* 4351 * Payload size per packet w/o any headers. 4352 * Length of all headers up to payload. 4353 */ 4354 TXD->tcp_seg_setup.fields.mss = htole16(mss); 4355 TXD->tcp_seg_setup.fields.hdr_len = hlen; 4356 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS | 4357 E1000_TXD_CMD_DEXT | /* Extended descr */ 4358 E1000_TXD_CMD_TSE | /* TSE context */ 4359 E1000_TXD_CMD_IP | /* Do IP csum */ 4360 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 4361 (pktlen - hlen)); /* Total len */ 4362 4363 /* Save the information for this TSO context */ 4364 adapter->csum_flags = CSUM_TSO; 4365 adapter->csum_lhlen = hoff; 4366 adapter->csum_iphlen = iphlen; 4367 adapter->csum_thlen = thoff; 4368 adapter->csum_mss = mss; 4369 adapter->csum_pktlen = pktlen; 4370 adapter->csum_txd_upper = *txd_upper; 4371 adapter->csum_txd_lower = *txd_lower; 4372 4373 if (++curr_txd == adapter->num_tx_desc) 4374 curr_txd = 0; 4375 4376 KKASSERT(adapter->num_tx_desc_avail > 0); 4377 adapter->num_tx_desc_avail--; 4378 4379 adapter->next_avail_tx_desc = curr_txd; 4380 return 1; 4381 } 4382