1 /* 2 * 3 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 2001-2006, Intel Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * 3. Neither the name of the Intel Corporation nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * 35 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 36 * 37 * This code is derived from software contributed to The DragonFly Project 38 * by Matthew Dillon <dillon@backplane.com> 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * 3. Neither the name of The DragonFly Project nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific, prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 57 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 58 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 60 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 61 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 62 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 64 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * $DragonFly: src/sys/dev/netif/em/if_em.c,v 1.68 2008/04/03 12:55:15 sephe Exp $ 68 * $FreeBSD$ 69 */ 70 /* 71 * SERIALIZATION API RULES: 72 * 73 * - If the driver uses the same serializer for the interrupt as for the 74 * ifnet, most of the serialization will be done automatically for the 75 * driver. 76 * 77 * - ifmedia entry points will be serialized by the ifmedia code using the 78 * ifnet serializer. 79 * 80 * - if_* entry points except for if_input will be serialized by the IF 81 * and protocol layers. 82 * 83 * - The device driver must be sure to serialize access from timeout code 84 * installed by the device driver. 85 * 86 * - The device driver typically holds the serializer at the time it wishes 87 * to call if_input. If so, it should pass the serializer to if_input and 88 * note that the serializer might be dropped temporarily by if_input 89 * (e.g. in case it has to bridge the packet to another interface). 90 * 91 * NOTE! Since callers into the device driver hold the ifnet serializer, 92 * the device driver may be holding a serializer at the time it calls 93 * if_input even if it is not serializer-aware. 94 */ 95 96 #include "opt_polling.h" 97 #include "opt_inet.h" 98 #include "opt_serializer.h" 99 100 #include <sys/param.h> 101 #include <sys/bus.h> 102 #include <sys/endian.h> 103 #include <sys/kernel.h> 104 #include <sys/ktr.h> 105 #include <sys/malloc.h> 106 #include <sys/mbuf.h> 107 #include <sys/module.h> 108 #include <sys/rman.h> 109 #include <sys/serialize.h> 110 #include <sys/socket.h> 111 #include <sys/sockio.h> 112 #include <sys/sysctl.h> 113 114 #include <net/bpf.h> 115 #include <net/ethernet.h> 116 #include <net/if.h> 117 #include <net/if_arp.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/if_types.h> 121 #include <net/ifq_var.h> 122 #include <net/vlan/if_vlan_var.h> 123 #include <net/vlan/if_vlan_ether.h> 124 125 #ifdef INET 126 #include <netinet/in.h> 127 #include <netinet/in_systm.h> 128 #include <netinet/in_var.h> 129 #include <netinet/ip.h> 130 #include <netinet/tcp.h> 131 #include <netinet/udp.h> 132 #endif 133 134 #include <dev/netif/em/if_em_hw.h> 135 #include <dev/netif/em/if_em.h> 136 137 #define EM_X60_WORKAROUND 138 139 /********************************************************************* 140 * Set this to one to display debug statistics 141 *********************************************************************/ 142 int em_display_debug_stats = 0; 143 144 /********************************************************************* 145 * Driver version 146 *********************************************************************/ 147 148 char em_driver_version[] = "6.2.9"; 149 150 151 /********************************************************************* 152 * PCI Device ID Table 153 * 154 * Used by probe to select devices to load on 155 * Last field stores an index into em_strings 156 * Last entry must be all 0s 157 * 158 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 159 *********************************************************************/ 160 161 static em_vendor_info_t em_vendor_info_array[] = 162 { 163 /* Intel(R) PRO/1000 Network Connection */ 164 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 165 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 166 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 167 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 168 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 169 170 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 171 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 172 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 173 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 174 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 175 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 176 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 177 178 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 179 180 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 181 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 182 183 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 184 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 185 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 186 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 187 188 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 189 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 190 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 191 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 192 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 193 194 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 195 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 196 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 197 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 198 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 199 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 200 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 201 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 202 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 203 PCI_ANY_ID, PCI_ANY_ID, 0}, 204 205 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 206 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 207 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 208 209 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 210 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 211 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 212 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 213 PCI_ANY_ID, PCI_ANY_ID, 0}, 214 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE, 215 PCI_ANY_ID, PCI_ANY_ID, 0}, 216 217 { 0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 218 PCI_ANY_ID, PCI_ANY_ID, 0}, 219 { 0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, 220 PCI_ANY_ID, PCI_ANY_ID, 0}, 221 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 222 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 223 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 224 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 225 226 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 227 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 228 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 229 230 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 231 PCI_ANY_ID, PCI_ANY_ID, 0}, 232 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 233 PCI_ANY_ID, PCI_ANY_ID, 0}, 234 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 235 PCI_ANY_ID, PCI_ANY_ID, 0}, 236 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 237 PCI_ANY_ID, PCI_ANY_ID, 0}, 238 239 { 0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 240 { 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 241 { 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 242 { 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 243 { 0x8086, E1000_DEV_ID_ICH8_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 244 { 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 245 { 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0}, 246 247 { 0x8086, E1000_DEV_ID_ICH9_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 248 { 0x8086, E1000_DEV_ID_ICH9_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 249 { 0x8086, E1000_DEV_ID_ICH9_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 250 { 0x8086, E1000_DEV_ID_ICH9_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 251 { 0x8086, E1000_DEV_ID_ICH9_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 252 253 { 0x8086, E1000_DEV_ID_82575EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 254 { 0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, 255 PCI_ANY_ID, PCI_ANY_ID, 0}, 256 { 0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, 257 PCI_ANY_ID, PCI_ANY_ID, 0}, 258 { 0x8086, 0x101A, PCI_ANY_ID, PCI_ANY_ID, 0}, 259 { 0x8086, 0x1014, PCI_ANY_ID, PCI_ANY_ID, 0}, 260 /* required last entry */ 261 { 0, 0, 0, 0, 0} 262 }; 263 264 /********************************************************************* 265 * Table of branding strings for all supported NICs. 266 *********************************************************************/ 267 268 static const char *em_strings[] = { 269 "Intel(R) PRO/1000 Network Connection" 270 }; 271 272 /********************************************************************* 273 * Function prototypes 274 *********************************************************************/ 275 static int em_probe(device_t); 276 static int em_attach(device_t); 277 static int em_detach(device_t); 278 static int em_shutdown(device_t); 279 static void em_intr(void *); 280 static int em_suspend(device_t); 281 static int em_resume(device_t); 282 static void em_start(struct ifnet *); 283 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 284 static void em_watchdog(struct ifnet *); 285 static void em_init(void *); 286 static void em_stop(void *); 287 static void em_media_status(struct ifnet *, struct ifmediareq *); 288 static int em_media_change(struct ifnet *); 289 static void em_identify_hardware(struct adapter *); 290 static int em_allocate_pci_resources(device_t); 291 static void em_free_pci_resources(device_t); 292 static void em_local_timer(void *); 293 static int em_hardware_init(struct adapter *); 294 static void em_setup_interface(device_t, struct adapter *); 295 static int em_setup_transmit_structures(struct adapter *); 296 static void em_initialize_transmit_unit(struct adapter *); 297 static int em_setup_receive_structures(struct adapter *); 298 static void em_initialize_receive_unit(struct adapter *); 299 static void em_enable_intr(struct adapter *); 300 static void em_disable_intr(struct adapter *); 301 static void em_free_transmit_structures(struct adapter *); 302 static void em_free_receive_structures(struct adapter *); 303 static void em_update_stats_counters(struct adapter *); 304 static void em_txeof(struct adapter *); 305 static int em_allocate_receive_structures(struct adapter *); 306 static void em_rxeof(struct adapter *, int); 307 static void em_receive_checksum(struct adapter *, struct em_rx_desc *, 308 struct mbuf *); 309 static void em_transmit_checksum_setup(struct adapter *, struct mbuf *, 310 uint32_t *, uint32_t *); 311 static void em_set_promisc(struct adapter *); 312 static void em_disable_promisc(struct adapter *); 313 static void em_set_multi(struct adapter *); 314 static void em_print_hw_stats(struct adapter *); 315 static void em_update_link_status(struct adapter *); 316 static int em_get_buf(int i, struct adapter *, struct mbuf *, int how); 317 static void em_enable_vlans(struct adapter *); 318 static void em_disable_vlans(struct adapter *); 319 static int em_encap(struct adapter *, struct mbuf *); 320 static void em_smartspeed(struct adapter *); 321 static int em_82547_fifo_workaround(struct adapter *, int); 322 static void em_82547_update_fifo_head(struct adapter *, int); 323 static int em_82547_tx_fifo_reset(struct adapter *); 324 static void em_82547_move_tail(void *); 325 static void em_82547_move_tail_serialized(struct adapter *); 326 static int em_dma_malloc(struct adapter *, bus_size_t, 327 struct em_dma_alloc *); 328 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 329 static void em_print_debug_info(struct adapter *); 330 static int em_is_valid_ether_addr(uint8_t *); 331 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 332 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 333 static uint32_t em_fill_descriptors(bus_addr_t address, uint32_t length, 334 PDESC_ARRAY desc_array); 335 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 336 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 337 static void em_add_int_delay_sysctl(struct adapter *, const char *, 338 const char *, 339 struct em_int_delay_info *, int, int); 340 341 /********************************************************************* 342 * FreeBSD Device Interface Entry Points 343 *********************************************************************/ 344 345 static device_method_t em_methods[] = { 346 /* Device interface */ 347 DEVMETHOD(device_probe, em_probe), 348 DEVMETHOD(device_attach, em_attach), 349 DEVMETHOD(device_detach, em_detach), 350 DEVMETHOD(device_shutdown, em_shutdown), 351 DEVMETHOD(device_suspend, em_suspend), 352 DEVMETHOD(device_resume, em_resume), 353 {0, 0} 354 }; 355 356 static driver_t em_driver = { 357 "em", em_methods, sizeof(struct adapter), 358 }; 359 360 static devclass_t em_devclass; 361 362 DECLARE_DUMMY_MODULE(if_em); 363 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, 0, 0); 364 365 /********************************************************************* 366 * Tunable default values. 367 *********************************************************************/ 368 369 #define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 370 #define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 371 372 static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV); 373 static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR); 374 static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV); 375 static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV); 376 static int em_int_throttle_ceil = 10000; 377 static int em_rxd = EM_DEFAULT_RXD; 378 static int em_txd = EM_DEFAULT_TXD; 379 static int em_smart_pwr_down = FALSE; 380 381 TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 382 TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 383 TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 384 TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 385 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil); 386 TUNABLE_INT("hw.em.rxd", &em_rxd); 387 TUNABLE_INT("hw.em.txd", &em_txd); 388 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 389 390 /* 391 * Kernel trace for characterization of operations 392 */ 393 #if !defined(KTR_IF_EM) 394 #define KTR_IF_EM KTR_ALL 395 #endif 396 KTR_INFO_MASTER(if_em); 397 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin", 0); 398 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end", 0); 399 #ifdef DEVICE_POLLING 400 KTR_INFO(KTR_IF_EM, if_em, poll_beg, 2, "poll begin", 0); 401 KTR_INFO(KTR_IF_EM, if_em, poll_end, 3, "poll end", 0); 402 #endif 403 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet", 0); 404 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet", 0); 405 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean", 0); 406 #define logif(name) KTR_LOG(if_em_ ## name) 407 408 /********************************************************************* 409 * Device identification routine 410 * 411 * em_probe determines if the driver should be loaded on 412 * adapter based on PCI vendor/device id of the adapter. 413 * 414 * return 0 on success, positive on failure 415 *********************************************************************/ 416 417 static int 418 em_probe(device_t dev) 419 { 420 em_vendor_info_t *ent; 421 422 uint16_t pci_vendor_id = 0; 423 uint16_t pci_device_id = 0; 424 uint16_t pci_subvendor_id = 0; 425 uint16_t pci_subdevice_id = 0; 426 char adapter_name[60]; 427 428 INIT_DEBUGOUT("em_probe: begin"); 429 430 pci_vendor_id = pci_get_vendor(dev); 431 if (pci_vendor_id != EM_VENDOR_ID) 432 return (ENXIO); 433 434 pci_device_id = pci_get_device(dev); 435 pci_subvendor_id = pci_get_subvendor(dev); 436 pci_subdevice_id = pci_get_subdevice(dev); 437 438 ent = em_vendor_info_array; 439 while (ent->vendor_id != 0) { 440 if ((pci_vendor_id == ent->vendor_id) && 441 (pci_device_id == ent->device_id) && 442 443 ((pci_subvendor_id == ent->subvendor_id) || 444 (ent->subvendor_id == PCI_ANY_ID)) && 445 446 ((pci_subdevice_id == ent->subdevice_id) || 447 (ent->subdevice_id == PCI_ANY_ID))) { 448 ksnprintf(adapter_name, sizeof(adapter_name), 449 "%s, Version - %s", em_strings[ent->index], 450 em_driver_version); 451 device_set_desc_copy(dev, adapter_name); 452 device_set_async_attach(dev, TRUE); 453 return (0); 454 } 455 ent++; 456 } 457 458 return (ENXIO); 459 } 460 461 /********************************************************************* 462 * Device initialization routine 463 * 464 * The attach entry point is called when the driver is being loaded. 465 * This routine identifies the type of hardware, allocates all resources 466 * and initializes the hardware. 467 * 468 * return 0 on success, positive on failure 469 *********************************************************************/ 470 471 static int 472 em_attach(device_t dev) 473 { 474 struct adapter *adapter; 475 int tsize, rsize; 476 int error = 0; 477 478 INIT_DEBUGOUT("em_attach: begin"); 479 480 adapter = device_get_softc(dev); 481 482 callout_init(&adapter->timer); 483 callout_init(&adapter->tx_fifo_timer); 484 485 adapter->dev = dev; 486 adapter->osdep.dev = dev; 487 488 /* SYSCTL stuff */ 489 sysctl_ctx_init(&adapter->sysctl_ctx); 490 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx, 491 SYSCTL_STATIC_CHILDREN(_hw), 492 OID_AUTO, 493 device_get_nameunit(dev), 494 CTLFLAG_RD, 495 0, ""); 496 497 if (adapter->sysctl_tree == NULL) { 498 device_printf(dev, "Unable to create sysctl tree\n"); 499 return EIO; 500 } 501 502 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 503 SYSCTL_CHILDREN(adapter->sysctl_tree), 504 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, 505 (void *)adapter, 0, 506 em_sysctl_debug_info, "I", "Debug Information"); 507 508 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 509 SYSCTL_CHILDREN(adapter->sysctl_tree), 510 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, 511 (void *)adapter, 0, 512 em_sysctl_stats, "I", "Statistics"); 513 514 /* Determine hardware revision */ 515 em_identify_hardware(adapter); 516 517 /* Set up some sysctls for the tunable interrupt delays */ 518 em_add_int_delay_sysctl(adapter, "rx_int_delay", 519 "receive interrupt delay in usecs", 520 &adapter->rx_int_delay, 521 E1000_REG_OFFSET(&adapter->hw, RDTR), 522 em_rx_int_delay_dflt); 523 em_add_int_delay_sysctl(adapter, "tx_int_delay", 524 "transmit interrupt delay in usecs", 525 &adapter->tx_int_delay, 526 E1000_REG_OFFSET(&adapter->hw, TIDV), 527 em_tx_int_delay_dflt); 528 if (adapter->hw.mac_type >= em_82540) { 529 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 530 "receive interrupt delay limit in usecs", 531 &adapter->rx_abs_int_delay, 532 E1000_REG_OFFSET(&adapter->hw, RADV), 533 em_rx_abs_int_delay_dflt); 534 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 535 "transmit interrupt delay limit in usecs", 536 &adapter->tx_abs_int_delay, 537 E1000_REG_OFFSET(&adapter->hw, TADV), 538 em_tx_abs_int_delay_dflt); 539 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 540 SYSCTL_CHILDREN(adapter->sysctl_tree), 541 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, 542 adapter, 0, em_sysctl_int_throttle, "I", NULL); 543 } 544 545 /* 546 * Validate number of transmit and receive descriptors. It 547 * must not exceed hardware maximum, and must be multiple 548 * of EM_DBA_ALIGN. 549 */ 550 if (((em_txd * sizeof(struct em_tx_desc)) % EM_DBA_ALIGN) != 0 || 551 (adapter->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) || 552 (adapter->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) || 553 (em_txd < EM_MIN_TXD)) { 554 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 555 EM_DEFAULT_TXD, em_txd); 556 adapter->num_tx_desc = EM_DEFAULT_TXD; 557 } else { 558 adapter->num_tx_desc = em_txd; 559 } 560 561 if (((em_rxd * sizeof(struct em_rx_desc)) % EM_DBA_ALIGN) != 0 || 562 (adapter->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) || 563 (adapter->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) || 564 (em_rxd < EM_MIN_RXD)) { 565 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 566 EM_DEFAULT_RXD, em_rxd); 567 adapter->num_rx_desc = EM_DEFAULT_RXD; 568 } else { 569 adapter->num_rx_desc = em_rxd; 570 } 571 572 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 573 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, "rxd", 574 CTLFLAG_RD, &adapter->num_rx_desc, 0, NULL); 575 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 576 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, "txd", 577 CTLFLAG_RD, &adapter->num_tx_desc, 0, NULL); 578 579 adapter->hw.autoneg = DO_AUTO_NEG; 580 adapter->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 581 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 582 adapter->hw.tbi_compatibility_en = TRUE; 583 adapter->rx_buffer_len = EM_RXBUFFER_2048; 584 585 adapter->hw.phy_init_script = 1; 586 adapter->hw.phy_reset_disable = FALSE; 587 588 #ifndef EM_MASTER_SLAVE 589 adapter->hw.master_slave = em_ms_hw_default; 590 #else 591 adapter->hw.master_slave = EM_MASTER_SLAVE; 592 #endif 593 594 /* 595 * Set the max frame size assuming standard ethernet 596 * sized frames. 597 */ 598 adapter->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 599 600 adapter->hw.min_frame_size = 601 MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN; 602 603 /* 604 * This controls when hardware reports transmit completion 605 * status. 606 */ 607 adapter->hw.report_tx_early = 1; 608 609 error = em_allocate_pci_resources(dev); 610 if (error) 611 goto fail; 612 613 /* Initialize eeprom parameters */ 614 em_init_eeprom_params(&adapter->hw); 615 616 tsize = roundup2(adapter->num_tx_desc * sizeof(struct em_tx_desc), 617 EM_DBA_ALIGN); 618 619 /* Allocate Transmit Descriptor ring */ 620 error = em_dma_malloc(adapter, tsize, &adapter->txdma); 621 if (error) { 622 device_printf(dev, "Unable to allocate TxDescriptor memory\n"); 623 goto fail; 624 } 625 adapter->tx_desc_base = (struct em_tx_desc *)adapter->txdma.dma_vaddr; 626 627 rsize = roundup2(adapter->num_rx_desc * sizeof(struct em_rx_desc), 628 EM_DBA_ALIGN); 629 630 /* Allocate Receive Descriptor ring */ 631 error = em_dma_malloc(adapter, rsize, &adapter->rxdma); 632 if (error) { 633 device_printf(dev, "Unable to allocate rx_desc memory\n"); 634 goto fail; 635 } 636 adapter->rx_desc_base = (struct em_rx_desc *)adapter->rxdma.dma_vaddr; 637 638 /* Initialize the hardware */ 639 if (em_hardware_init(adapter)) { 640 device_printf(dev, "Unable to initialize the hardware\n"); 641 error = EIO; 642 goto fail; 643 } 644 645 /* Copy the permanent MAC address out of the EEPROM */ 646 if (em_read_mac_addr(&adapter->hw) < 0) { 647 device_printf(dev, 648 "EEPROM read error while reading MAC address\n"); 649 error = EIO; 650 goto fail; 651 } 652 653 if (!em_is_valid_ether_addr(adapter->hw.mac_addr)) { 654 device_printf(dev, "Invalid MAC address\n"); 655 error = EIO; 656 goto fail; 657 } 658 659 /* Setup OS specific network interface */ 660 em_setup_interface(dev, adapter); 661 662 /* Initialize statistics */ 663 em_clear_hw_cntrs(&adapter->hw); 664 em_update_stats_counters(adapter); 665 adapter->hw.get_link_status = 1; 666 em_update_link_status(adapter); 667 668 /* Indicate SOL/IDER usage */ 669 if (em_check_phy_reset_block(&adapter->hw)) { 670 device_printf(dev, "PHY reset is blocked due to " 671 "SOL/IDER session.\n"); 672 } 673 674 /* Identify 82544 on PCIX */ 675 em_get_bus_info(&adapter->hw); 676 if (adapter->hw.bus_type == em_bus_type_pcix && 677 adapter->hw.mac_type == em_82544) 678 adapter->pcix_82544 = TRUE; 679 else 680 adapter->pcix_82544 = FALSE; 681 682 error = bus_setup_intr(dev, adapter->res_interrupt, INTR_NETSAFE, 683 em_intr, adapter, 684 &adapter->int_handler_tag, 685 adapter->interface_data.ac_if.if_serializer); 686 if (error) { 687 device_printf(dev, "Error registering interrupt handler!\n"); 688 ether_ifdetach(&adapter->interface_data.ac_if); 689 goto fail; 690 } 691 692 INIT_DEBUGOUT("em_attach: end"); 693 return(0); 694 695 fail: 696 em_detach(dev); 697 return(error); 698 } 699 700 /********************************************************************* 701 * Device removal routine 702 * 703 * The detach entry point is called when the driver is being removed. 704 * This routine stops the adapter and deallocates all the resources 705 * that were allocated for driver operation. 706 * 707 * return 0 on success, positive on failure 708 *********************************************************************/ 709 710 static int 711 em_detach(device_t dev) 712 { 713 struct adapter *adapter = device_get_softc(dev); 714 715 INIT_DEBUGOUT("em_detach: begin"); 716 717 if (device_is_attached(dev)) { 718 struct ifnet *ifp = &adapter->interface_data.ac_if; 719 720 lwkt_serialize_enter(ifp->if_serializer); 721 adapter->in_detach = 1; 722 em_stop(adapter); 723 em_phy_hw_reset(&adapter->hw); 724 bus_teardown_intr(dev, adapter->res_interrupt, 725 adapter->int_handler_tag); 726 lwkt_serialize_exit(ifp->if_serializer); 727 728 ether_ifdetach(ifp); 729 } 730 bus_generic_detach(dev); 731 732 em_free_pci_resources(dev); 733 734 /* Free Transmit Descriptor ring */ 735 if (adapter->tx_desc_base != NULL) { 736 em_dma_free(adapter, &adapter->txdma); 737 adapter->tx_desc_base = NULL; 738 } 739 740 /* Free Receive Descriptor ring */ 741 if (adapter->rx_desc_base != NULL) { 742 em_dma_free(adapter, &adapter->rxdma); 743 adapter->rx_desc_base = NULL; 744 } 745 746 /* Free sysctl tree */ 747 if (adapter->sysctl_tree != NULL) { 748 adapter->sysctl_tree = NULL; 749 sysctl_ctx_free(&adapter->sysctl_ctx); 750 } 751 752 return (0); 753 } 754 755 /********************************************************************* 756 * 757 * Shutdown entry point 758 * 759 **********************************************************************/ 760 761 static int 762 em_shutdown(device_t dev) 763 { 764 struct adapter *adapter = device_get_softc(dev); 765 struct ifnet *ifp = &adapter->interface_data.ac_if; 766 767 lwkt_serialize_enter(ifp->if_serializer); 768 em_stop(adapter); 769 lwkt_serialize_exit(ifp->if_serializer); 770 771 return (0); 772 } 773 774 /* 775 * Suspend/resume device methods. 776 */ 777 static int 778 em_suspend(device_t dev) 779 { 780 struct adapter *adapter = device_get_softc(dev); 781 struct ifnet *ifp = &adapter->interface_data.ac_if; 782 783 lwkt_serialize_enter(ifp->if_serializer); 784 em_stop(adapter); 785 lwkt_serialize_exit(ifp->if_serializer); 786 return (0); 787 } 788 789 static int 790 em_resume(device_t dev) 791 { 792 struct adapter *adapter = device_get_softc(dev); 793 struct ifnet *ifp = &adapter->interface_data.ac_if; 794 795 lwkt_serialize_enter(ifp->if_serializer); 796 ifp->if_flags &= ~IFF_RUNNING; 797 em_init(adapter); 798 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 799 em_start(ifp); 800 lwkt_serialize_exit(ifp->if_serializer); 801 802 return bus_generic_resume(dev); 803 } 804 805 /********************************************************************* 806 * Transmit entry point 807 * 808 * em_start is called by the stack to initiate a transmit. 809 * The driver will remain in this routine as long as there are 810 * packets to transmit and transmit resources are available. 811 * In case resources are not available stack is notified and 812 * the packet is requeued. 813 **********************************************************************/ 814 815 static void 816 em_start(struct ifnet *ifp) 817 { 818 struct mbuf *m_head; 819 struct adapter *adapter = ifp->if_softc; 820 821 ASSERT_SERIALIZED(ifp->if_serializer); 822 823 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 824 return; 825 if (!adapter->link_active) 826 return; 827 while (!ifq_is_empty(&ifp->if_snd)) { 828 m_head = ifq_poll(&ifp->if_snd); 829 830 if (m_head == NULL) 831 break; 832 833 logif(pkt_txqueue); 834 if (em_encap(adapter, m_head)) { 835 ifp->if_flags |= IFF_OACTIVE; 836 break; 837 } 838 ifq_dequeue(&ifp->if_snd, m_head); 839 840 /* Send a copy of the frame to the BPF listener */ 841 ETHER_BPF_MTAP(ifp, m_head); 842 843 /* Set timeout in case hardware has problems transmitting. */ 844 ifp->if_timer = EM_TX_TIMEOUT; 845 } 846 } 847 848 /********************************************************************* 849 * Ioctl entry point 850 * 851 * em_ioctl is called when the user wants to configure the 852 * interface. 853 * 854 * return 0 on success, positive on failure 855 **********************************************************************/ 856 857 static int 858 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 859 { 860 int max_frame_size, mask, error = 0, reinit = 0; 861 struct ifreq *ifr = (struct ifreq *) data; 862 struct adapter *adapter = ifp->if_softc; 863 uint16_t eeprom_data = 0; 864 865 ASSERT_SERIALIZED(ifp->if_serializer); 866 867 if (adapter->in_detach) 868 return 0; 869 870 switch (command) { 871 case SIOCSIFMTU: 872 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 873 switch (adapter->hw.mac_type) { 874 case em_82573: 875 /* 876 * 82573 only supports jumbo frames 877 * if ASPM is disabled. 878 */ 879 em_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 880 1, &eeprom_data); 881 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 882 max_frame_size = ETHER_MAX_LEN; 883 break; 884 } 885 /* Allow Jumbo frames */ 886 /* FALLTHROUGH */ 887 case em_82571: 888 case em_82572: 889 case em_ich9lan: 890 case em_80003es2lan: /* Limit Jumbo Frame size */ 891 max_frame_size = 9234; 892 break; 893 case em_ich8lan: 894 /* ICH8 does not support jumbo frames */ 895 max_frame_size = ETHER_MAX_LEN; 896 break; 897 default: 898 max_frame_size = MAX_JUMBO_FRAME_SIZE; 899 break; 900 } 901 if (ifr->ifr_mtu > 902 max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 903 error = EINVAL; 904 } else { 905 ifp->if_mtu = ifr->ifr_mtu; 906 adapter->hw.max_frame_size = 907 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 908 ifp->if_flags &= ~IFF_RUNNING; 909 em_init(adapter); 910 } 911 break; 912 case SIOCSIFFLAGS: 913 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS " 914 "(Set Interface Flags)"); 915 if (ifp->if_flags & IFF_UP) { 916 if (!(ifp->if_flags & IFF_RUNNING)) { 917 em_init(adapter); 918 } else if ((ifp->if_flags ^ adapter->if_flags) & 919 IFF_PROMISC) { 920 em_disable_promisc(adapter); 921 em_set_promisc(adapter); 922 } 923 } else { 924 if (ifp->if_flags & IFF_RUNNING) 925 em_stop(adapter); 926 } 927 adapter->if_flags = ifp->if_flags; 928 break; 929 case SIOCADDMULTI: 930 case SIOCDELMULTI: 931 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 932 if (ifp->if_flags & IFF_RUNNING) { 933 em_disable_intr(adapter); 934 em_set_multi(adapter); 935 if (adapter->hw.mac_type == em_82542_rev2_0) 936 em_initialize_receive_unit(adapter); 937 #ifdef DEVICE_POLLING 938 /* Do not enable interrupt if polling(4) is enabled */ 939 if ((ifp->if_flags & IFF_POLLING) == 0) 940 #endif 941 em_enable_intr(adapter); 942 } 943 break; 944 case SIOCSIFMEDIA: 945 /* Check SOL/IDER usage */ 946 if (em_check_phy_reset_block(&adapter->hw)) { 947 if_printf(ifp, "Media change is blocked due to " 948 "SOL/IDER session.\n"); 949 break; 950 } 951 /* FALLTHROUGH */ 952 case SIOCGIFMEDIA: 953 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA " 954 "(Get/Set Interface Media)"); 955 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 956 break; 957 case SIOCSIFCAP: 958 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 959 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 960 if (mask & IFCAP_HWCSUM) { 961 ifp->if_capenable ^= IFCAP_HWCSUM; 962 reinit = 1; 963 } 964 if (mask & IFCAP_VLAN_HWTAGGING) { 965 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 966 reinit = 1; 967 } 968 if (reinit && (ifp->if_flags & IFF_RUNNING)) { 969 ifp->if_flags &= ~IFF_RUNNING; 970 em_init(adapter); 971 } 972 break; 973 default: 974 error = ether_ioctl(ifp, command, data); 975 break; 976 } 977 978 return (error); 979 } 980 981 /********************************************************************* 982 * Watchdog entry point 983 * 984 * This routine is called whenever hardware quits transmitting. 985 * 986 **********************************************************************/ 987 988 static void 989 em_watchdog(struct ifnet *ifp) 990 { 991 struct adapter *adapter = ifp->if_softc; 992 993 /* 994 * If we are in this routine because of pause frames, then 995 * don't reset the hardware. 996 */ 997 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF) { 998 ifp->if_timer = EM_TX_TIMEOUT; 999 return; 1000 } 1001 1002 if (em_check_for_link(&adapter->hw) == 0) 1003 if_printf(ifp, "watchdog timeout -- resetting\n"); 1004 1005 ifp->if_flags &= ~IFF_RUNNING; 1006 em_init(adapter); 1007 1008 adapter->watchdog_timeouts++; 1009 } 1010 1011 /********************************************************************* 1012 * Init entry point 1013 * 1014 * This routine is used in two ways. It is used by the stack as 1015 * init entry point in network interface structure. It is also used 1016 * by the driver as a hw/sw initialization routine to get to a 1017 * consistent state. 1018 * 1019 * return 0 on success, positive on failure 1020 **********************************************************************/ 1021 1022 static void 1023 em_init(void *arg) 1024 { 1025 struct adapter *adapter = arg; 1026 uint32_t pba; 1027 struct ifnet *ifp = &adapter->interface_data.ac_if; 1028 1029 ASSERT_SERIALIZED(ifp->if_serializer); 1030 1031 INIT_DEBUGOUT("em_init: begin"); 1032 1033 if (ifp->if_flags & IFF_RUNNING) 1034 return; 1035 1036 em_stop(adapter); 1037 1038 /* 1039 * Packet Buffer Allocation (PBA) 1040 * Writing PBA sets the receive portion of the buffer 1041 * the remainder is used for the transmit buffer. 1042 * 1043 * Devices before the 82547 had a Packet Buffer of 64K. 1044 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 1045 * After the 82547 the buffer was reduced to 40K. 1046 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 1047 * Note: default does not leave enough room for Jumbo Frame >10k. 1048 */ 1049 switch (adapter->hw.mac_type) { 1050 case em_82547: 1051 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 1052 if (adapter->hw.max_frame_size > EM_RXBUFFER_8192) 1053 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1054 else 1055 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1056 1057 adapter->tx_fifo_head = 0; 1058 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 1059 adapter->tx_fifo_size = 1060 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 1061 break; 1062 /* Total Packet Buffer on these is 48K */ 1063 case em_82571: 1064 case em_82572: 1065 case em_80003es2lan: 1066 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1067 break; 1068 case em_82573: /* 82573: Total Packet Buffer is 32K */ 1069 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1070 break; 1071 case em_ich8lan: 1072 pba = E1000_PBA_8K; 1073 break; 1074 case em_ich9lan: 1075 #define E1000_PBA_10K 0x000A 1076 pba = E1000_PBA_10K; 1077 break; 1078 default: 1079 /* Devices before 82547 had a Packet Buffer of 64K. */ 1080 if(adapter->hw.max_frame_size > EM_RXBUFFER_8192) 1081 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1082 else 1083 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1084 } 1085 1086 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 1087 E1000_WRITE_REG(&adapter->hw, PBA, pba); 1088 1089 /* Get the latest mac address, User can use a LAA */ 1090 bcopy(adapter->interface_data.ac_enaddr, adapter->hw.mac_addr, 1091 ETHER_ADDR_LEN); 1092 1093 /* Initialize the hardware */ 1094 if (em_hardware_init(adapter)) { 1095 if_printf(ifp, "Unable to initialize the hardware\n"); 1096 return; 1097 } 1098 em_update_link_status(adapter); 1099 1100 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1101 em_enable_vlans(adapter); 1102 1103 /* Set hardware offload abilities */ 1104 if (adapter->hw.mac_type >= em_82543) { 1105 if (ifp->if_capenable & IFCAP_TXCSUM) 1106 ifp->if_hwassist = EM_CHECKSUM_FEATURES; 1107 else 1108 ifp->if_hwassist = 0; 1109 } 1110 1111 /* Prepare transmit descriptors and buffers */ 1112 if (em_setup_transmit_structures(adapter)) { 1113 if_printf(ifp, "Could not setup transmit structures\n"); 1114 em_stop(adapter); 1115 return; 1116 } 1117 em_initialize_transmit_unit(adapter); 1118 1119 /* Setup Multicast table */ 1120 em_set_multi(adapter); 1121 1122 /* Prepare receive descriptors and buffers */ 1123 if (em_setup_receive_structures(adapter)) { 1124 if_printf(ifp, "Could not setup receive structures\n"); 1125 em_stop(adapter); 1126 return; 1127 } 1128 em_initialize_receive_unit(adapter); 1129 1130 /* Don't lose promiscuous settings */ 1131 em_set_promisc(adapter); 1132 1133 ifp->if_flags |= IFF_RUNNING; 1134 ifp->if_flags &= ~IFF_OACTIVE; 1135 1136 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1137 em_clear_hw_cntrs(&adapter->hw); 1138 1139 #ifdef DEVICE_POLLING 1140 /* Do not enable interrupt if polling(4) is enabled */ 1141 if (ifp->if_flags & IFF_POLLING) 1142 em_disable_intr(adapter); 1143 else 1144 #endif 1145 em_enable_intr(adapter); 1146 1147 /* Don't reset the phy next time init gets called */ 1148 adapter->hw.phy_reset_disable = TRUE; 1149 } 1150 1151 #ifdef DEVICE_POLLING 1152 1153 static void 1154 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1155 { 1156 struct adapter *adapter = ifp->if_softc; 1157 uint32_t reg_icr; 1158 1159 logif(poll_beg); 1160 1161 ASSERT_SERIALIZED(ifp->if_serializer); 1162 1163 switch(cmd) { 1164 case POLL_REGISTER: 1165 em_disable_intr(adapter); 1166 break; 1167 case POLL_DEREGISTER: 1168 em_enable_intr(adapter); 1169 break; 1170 case POLL_AND_CHECK_STATUS: 1171 reg_icr = E1000_READ_REG(&adapter->hw, ICR); 1172 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1173 callout_stop(&adapter->timer); 1174 adapter->hw.get_link_status = 1; 1175 em_check_for_link(&adapter->hw); 1176 em_update_link_status(adapter); 1177 callout_reset(&adapter->timer, hz, em_local_timer, 1178 adapter); 1179 } 1180 /* fall through */ 1181 case POLL_ONLY: 1182 if (ifp->if_flags & IFF_RUNNING) { 1183 em_rxeof(adapter, count); 1184 em_txeof(adapter); 1185 1186 if (!ifq_is_empty(&ifp->if_snd)) 1187 em_start(ifp); 1188 } 1189 break; 1190 } 1191 logif(poll_end); 1192 } 1193 1194 #endif /* DEVICE_POLLING */ 1195 1196 /********************************************************************* 1197 * 1198 * Interrupt Service routine 1199 * 1200 *********************************************************************/ 1201 static void 1202 em_intr(void *arg) 1203 { 1204 uint32_t reg_icr; 1205 struct ifnet *ifp; 1206 struct adapter *adapter = arg; 1207 1208 ifp = &adapter->interface_data.ac_if; 1209 1210 logif(intr_beg); 1211 ASSERT_SERIALIZED(ifp->if_serializer); 1212 1213 reg_icr = E1000_READ_REG(&adapter->hw, ICR); 1214 if ((adapter->hw.mac_type >= em_82571 && 1215 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1216 reg_icr == 0) { 1217 logif(intr_end); 1218 return; 1219 } 1220 1221 /* 1222 * XXX: some laptops trigger several spurious interrupts on em(4) 1223 * when in the resume cycle. The ICR register reports all-ones 1224 * value in this case. Processing such interrupts would lead to 1225 * a freeze. I don't know why. 1226 */ 1227 if (reg_icr == 0xffffffff) { 1228 logif(intr_end); 1229 return; 1230 } 1231 1232 /* 1233 * note: do not attempt to improve efficiency by looping. This 1234 * only results in unnecessary piecemeal collection of received 1235 * packets and unnecessary piecemeal cleanups of the transmit ring. 1236 */ 1237 if (ifp->if_flags & IFF_RUNNING) { 1238 em_rxeof(adapter, -1); 1239 em_txeof(adapter); 1240 } 1241 1242 /* Link status change */ 1243 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1244 callout_stop(&adapter->timer); 1245 adapter->hw.get_link_status = 1; 1246 em_check_for_link(&adapter->hw); 1247 em_update_link_status(adapter); 1248 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1249 } 1250 1251 if (reg_icr & E1000_ICR_RXO) 1252 adapter->rx_overruns++; 1253 1254 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1255 em_start(ifp); 1256 logif(intr_end); 1257 } 1258 1259 /********************************************************************* 1260 * 1261 * Media Ioctl callback 1262 * 1263 * This routine is called whenever the user queries the status of 1264 * the interface using ifconfig. 1265 * 1266 **********************************************************************/ 1267 static void 1268 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1269 { 1270 struct adapter *adapter = ifp->if_softc; 1271 u_char fiber_type = IFM_1000_SX; 1272 1273 INIT_DEBUGOUT("em_media_status: begin"); 1274 1275 ASSERT_SERIALIZED(ifp->if_serializer); 1276 1277 em_check_for_link(&adapter->hw); 1278 em_update_link_status(adapter); 1279 1280 ifmr->ifm_status = IFM_AVALID; 1281 ifmr->ifm_active = IFM_ETHER; 1282 1283 if (!adapter->link_active) 1284 return; 1285 1286 ifmr->ifm_status |= IFM_ACTIVE; 1287 1288 if (adapter->hw.media_type == em_media_type_fiber || 1289 adapter->hw.media_type == em_media_type_internal_serdes) { 1290 if (adapter->hw.mac_type == em_82545) 1291 fiber_type = IFM_1000_LX; 1292 ifmr->ifm_active |= fiber_type | IFM_FDX; 1293 } else { 1294 switch (adapter->link_speed) { 1295 case 10: 1296 ifmr->ifm_active |= IFM_10_T; 1297 break; 1298 case 100: 1299 ifmr->ifm_active |= IFM_100_TX; 1300 break; 1301 case 1000: 1302 ifmr->ifm_active |= IFM_1000_T; 1303 break; 1304 } 1305 if (adapter->link_duplex == FULL_DUPLEX) 1306 ifmr->ifm_active |= IFM_FDX; 1307 else 1308 ifmr->ifm_active |= IFM_HDX; 1309 } 1310 } 1311 1312 /********************************************************************* 1313 * 1314 * Media Ioctl callback 1315 * 1316 * This routine is called when the user changes speed/duplex using 1317 * media/mediopt option with ifconfig. 1318 * 1319 **********************************************************************/ 1320 static int 1321 em_media_change(struct ifnet *ifp) 1322 { 1323 struct adapter *adapter = ifp->if_softc; 1324 struct ifmedia *ifm = &adapter->media; 1325 1326 INIT_DEBUGOUT("em_media_change: begin"); 1327 1328 ASSERT_SERIALIZED(ifp->if_serializer); 1329 1330 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1331 return (EINVAL); 1332 1333 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1334 case IFM_AUTO: 1335 adapter->hw.autoneg = DO_AUTO_NEG; 1336 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1337 break; 1338 case IFM_1000_LX: 1339 case IFM_1000_SX: 1340 case IFM_1000_T: 1341 adapter->hw.autoneg = DO_AUTO_NEG; 1342 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1343 break; 1344 case IFM_100_TX: 1345 adapter->hw.autoneg = FALSE; 1346 adapter->hw.autoneg_advertised = 0; 1347 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1348 adapter->hw.forced_speed_duplex = em_100_full; 1349 else 1350 adapter->hw.forced_speed_duplex = em_100_half; 1351 break; 1352 case IFM_10_T: 1353 adapter->hw.autoneg = FALSE; 1354 adapter->hw.autoneg_advertised = 0; 1355 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1356 adapter->hw.forced_speed_duplex = em_10_full; 1357 else 1358 adapter->hw.forced_speed_duplex = em_10_half; 1359 break; 1360 default: 1361 if_printf(ifp, "Unsupported media type\n"); 1362 } 1363 /* 1364 * As the speed/duplex settings may have changed we need to 1365 * reset the PHY. 1366 */ 1367 adapter->hw.phy_reset_disable = FALSE; 1368 1369 ifp->if_flags &= ~IFF_RUNNING; 1370 em_init(adapter); 1371 1372 return(0); 1373 } 1374 1375 static void 1376 em_tx_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, 1377 int error) 1378 { 1379 struct em_q *q = arg; 1380 1381 if (error) 1382 return; 1383 KASSERT(nsegs <= EM_MAX_SCATTER, 1384 ("Too many DMA segments returned when mapping tx packet")); 1385 q->nsegs = nsegs; 1386 bcopy(seg, q->segs, nsegs * sizeof(seg[0])); 1387 } 1388 1389 /********************************************************************* 1390 * 1391 * This routine maps the mbufs to tx descriptors. 1392 * 1393 * return 0 on success, positive on failure 1394 **********************************************************************/ 1395 static int 1396 em_encap(struct adapter *adapter, struct mbuf *m_head) 1397 { 1398 uint32_t txd_upper = 0, txd_lower = 0, txd_used = 0, txd_saved = 0; 1399 int i, j, error, last = 0; 1400 1401 struct em_q q; 1402 struct em_buffer *tx_buffer = NULL, *tx_buffer_first; 1403 bus_dmamap_t map; 1404 struct em_tx_desc *current_tx_desc = NULL; 1405 struct ifnet *ifp = &adapter->interface_data.ac_if; 1406 1407 /* 1408 * Force a cleanup if number of TX descriptors 1409 * available hits the threshold 1410 */ 1411 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1412 em_txeof(adapter); 1413 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1414 adapter->no_tx_desc_avail1++; 1415 return (ENOBUFS); 1416 } 1417 } 1418 1419 /* 1420 * Capture the first descriptor index, this descriptor will have 1421 * the index of the EOP which is the only one that now gets a 1422 * DONE bit writeback. 1423 */ 1424 tx_buffer_first = &adapter->tx_buffer_area[adapter->next_avail_tx_desc]; 1425 1426 /* 1427 * Map the packet for DMA. 1428 */ 1429 map = tx_buffer_first->map; 1430 error = bus_dmamap_load_mbuf(adapter->txtag, map, m_head, em_tx_cb, 1431 &q, BUS_DMA_NOWAIT); 1432 if (error != 0) { 1433 adapter->no_tx_dma_setup++; 1434 return (error); 1435 } 1436 KASSERT(q.nsegs != 0, ("em_encap: empty packet")); 1437 1438 if (q.nsegs > (adapter->num_tx_desc_avail - 2)) { 1439 adapter->no_tx_desc_avail2++; 1440 error = ENOBUFS; 1441 goto fail; 1442 } 1443 1444 if (ifp->if_hwassist > 0) { 1445 em_transmit_checksum_setup(adapter, m_head, 1446 &txd_upper, &txd_lower); 1447 } 1448 1449 i = adapter->next_avail_tx_desc; 1450 if (adapter->pcix_82544) 1451 txd_saved = i; 1452 1453 /* Set up our transmit descriptors */ 1454 for (j = 0; j < q.nsegs; j++) { 1455 /* If adapter is 82544 and on PCIX bus */ 1456 if(adapter->pcix_82544) { 1457 DESC_ARRAY desc_array; 1458 uint32_t array_elements, counter; 1459 1460 /* 1461 * Check the Address and Length combination and 1462 * split the data accordingly 1463 */ 1464 array_elements = em_fill_descriptors(q.segs[j].ds_addr, 1465 q.segs[j].ds_len, &desc_array); 1466 for (counter = 0; counter < array_elements; counter++) { 1467 if (txd_used == adapter->num_tx_desc_avail) { 1468 adapter->next_avail_tx_desc = txd_saved; 1469 adapter->no_tx_desc_avail2++; 1470 error = ENOBUFS; 1471 goto fail; 1472 } 1473 tx_buffer = &adapter->tx_buffer_area[i]; 1474 current_tx_desc = &adapter->tx_desc_base[i]; 1475 current_tx_desc->buffer_addr = htole64( 1476 desc_array.descriptor[counter].address); 1477 current_tx_desc->lower.data = htole32( 1478 adapter->txd_cmd | txd_lower | 1479 (uint16_t)desc_array.descriptor[counter].length); 1480 current_tx_desc->upper.data = htole32(txd_upper); 1481 1482 last = i; 1483 if (++i == adapter->num_tx_desc) 1484 i = 0; 1485 1486 tx_buffer->m_head = NULL; 1487 tx_buffer->next_eop = -1; 1488 txd_used++; 1489 } 1490 } else { 1491 tx_buffer = &adapter->tx_buffer_area[i]; 1492 current_tx_desc = &adapter->tx_desc_base[i]; 1493 1494 current_tx_desc->buffer_addr = htole64(q.segs[j].ds_addr); 1495 current_tx_desc->lower.data = htole32( 1496 adapter->txd_cmd | txd_lower | q.segs[j].ds_len); 1497 current_tx_desc->upper.data = htole32(txd_upper); 1498 1499 last = i; 1500 if (++i == adapter->num_tx_desc) 1501 i = 0; 1502 1503 tx_buffer->m_head = NULL; 1504 tx_buffer->next_eop = -1; 1505 } 1506 } 1507 1508 adapter->next_avail_tx_desc = i; 1509 if (adapter->pcix_82544) 1510 adapter->num_tx_desc_avail -= txd_used; 1511 else 1512 adapter->num_tx_desc_avail -= q.nsegs; 1513 1514 /* Find out if we are in vlan mode */ 1515 if (m_head->m_flags & M_VLANTAG) { 1516 /* Set the vlan id */ 1517 current_tx_desc->upper.fields.special = 1518 htole16(m_head->m_pkthdr.ether_vlantag); 1519 1520 /* Tell hardware to add tag */ 1521 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1522 } 1523 1524 tx_buffer->m_head = m_head; 1525 tx_buffer_first->map = tx_buffer->map; 1526 tx_buffer->map = map; 1527 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1528 1529 /* 1530 * Last Descriptor of Packet needs End Of Packet (EOP) 1531 * and Report Status (RS) 1532 */ 1533 current_tx_desc->lower.data |= 1534 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1535 1536 /* 1537 * Keep track in the first buffer which descriptor will be 1538 * written back. 1539 */ 1540 tx_buffer_first->next_eop = last; 1541 1542 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 1543 BUS_DMASYNC_PREWRITE); 1544 1545 /* 1546 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000 1547 * that this frame is available to transmit. 1548 */ 1549 if (adapter->hw.mac_type == em_82547 && 1550 adapter->link_duplex == HALF_DUPLEX) { 1551 em_82547_move_tail_serialized(adapter); 1552 } else { 1553 E1000_WRITE_REG(&adapter->hw, TDT, i); 1554 if (adapter->hw.mac_type == em_82547) { 1555 em_82547_update_fifo_head(adapter, 1556 m_head->m_pkthdr.len); 1557 } 1558 } 1559 1560 return (0); 1561 fail: 1562 bus_dmamap_unload(adapter->txtag, map); 1563 return error; 1564 } 1565 1566 /********************************************************************* 1567 * 1568 * 82547 workaround to avoid controller hang in half-duplex environment. 1569 * The workaround is to avoid queuing a large packet that would span 1570 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1571 * in this case. We do that only when FIFO is quiescent. 1572 * 1573 **********************************************************************/ 1574 static void 1575 em_82547_move_tail(void *arg) 1576 { 1577 struct adapter *adapter = arg; 1578 struct ifnet *ifp = &adapter->interface_data.ac_if; 1579 1580 lwkt_serialize_enter(ifp->if_serializer); 1581 em_82547_move_tail_serialized(adapter); 1582 lwkt_serialize_exit(ifp->if_serializer); 1583 } 1584 1585 static void 1586 em_82547_move_tail_serialized(struct adapter *adapter) 1587 { 1588 uint16_t hw_tdt; 1589 uint16_t sw_tdt; 1590 struct em_tx_desc *tx_desc; 1591 uint16_t length = 0; 1592 boolean_t eop = 0; 1593 1594 hw_tdt = E1000_READ_REG(&adapter->hw, TDT); 1595 sw_tdt = adapter->next_avail_tx_desc; 1596 1597 while (hw_tdt != sw_tdt) { 1598 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1599 length += tx_desc->lower.flags.length; 1600 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1601 if (++hw_tdt == adapter->num_tx_desc) 1602 hw_tdt = 0; 1603 1604 if (eop) { 1605 if (em_82547_fifo_workaround(adapter, length)) { 1606 adapter->tx_fifo_wrk_cnt++; 1607 callout_reset(&adapter->tx_fifo_timer, 1, 1608 em_82547_move_tail, adapter); 1609 break; 1610 } 1611 E1000_WRITE_REG(&adapter->hw, TDT, hw_tdt); 1612 em_82547_update_fifo_head(adapter, length); 1613 length = 0; 1614 } 1615 } 1616 } 1617 1618 static int 1619 em_82547_fifo_workaround(struct adapter *adapter, int len) 1620 { 1621 int fifo_space, fifo_pkt_len; 1622 1623 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1624 1625 if (adapter->link_duplex == HALF_DUPLEX) { 1626 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 1627 1628 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1629 if (em_82547_tx_fifo_reset(adapter)) 1630 return (0); 1631 else 1632 return (1); 1633 } 1634 } 1635 1636 return (0); 1637 } 1638 1639 static void 1640 em_82547_update_fifo_head(struct adapter *adapter, int len) 1641 { 1642 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1643 1644 /* tx_fifo_head is always 16 byte aligned */ 1645 adapter->tx_fifo_head += fifo_pkt_len; 1646 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) 1647 adapter->tx_fifo_head -= adapter->tx_fifo_size; 1648 } 1649 1650 static int 1651 em_82547_tx_fifo_reset(struct adapter *adapter) 1652 { 1653 uint32_t tctl; 1654 1655 if (E1000_READ_REG(&adapter->hw, TDT) == E1000_READ_REG(&adapter->hw, TDH) && 1656 E1000_READ_REG(&adapter->hw, TDFT) == E1000_READ_REG(&adapter->hw, TDFH) && 1657 E1000_READ_REG(&adapter->hw, TDFTS) == E1000_READ_REG(&adapter->hw, TDFHS) && 1658 E1000_READ_REG(&adapter->hw, TDFPC) == 0) { 1659 /* Disable TX unit */ 1660 tctl = E1000_READ_REG(&adapter->hw, TCTL); 1661 E1000_WRITE_REG(&adapter->hw, TCTL, tctl & ~E1000_TCTL_EN); 1662 1663 /* Reset FIFO pointers */ 1664 E1000_WRITE_REG(&adapter->hw, TDFT, adapter->tx_head_addr); 1665 E1000_WRITE_REG(&adapter->hw, TDFH, adapter->tx_head_addr); 1666 E1000_WRITE_REG(&adapter->hw, TDFTS, adapter->tx_head_addr); 1667 E1000_WRITE_REG(&adapter->hw, TDFHS, adapter->tx_head_addr); 1668 1669 /* Re-enable TX unit */ 1670 E1000_WRITE_REG(&adapter->hw, TCTL, tctl); 1671 E1000_WRITE_FLUSH(&adapter->hw); 1672 1673 adapter->tx_fifo_head = 0; 1674 adapter->tx_fifo_reset_cnt++; 1675 1676 return (TRUE); 1677 } else { 1678 return (FALSE); 1679 } 1680 } 1681 1682 static void 1683 em_set_promisc(struct adapter *adapter) 1684 { 1685 uint32_t reg_rctl; 1686 struct ifnet *ifp = &adapter->interface_data.ac_if; 1687 1688 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1689 1690 adapter->em_insert_vlan_header = 0; 1691 if (ifp->if_flags & IFF_PROMISC) { 1692 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1693 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1694 1695 /* 1696 * Disable VLAN stripping in promiscous mode. 1697 * This enables bridging of vlan tagged frames to occur 1698 * and also allows vlan tags to be seen in tcpdump. 1699 */ 1700 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1701 em_disable_vlans(adapter); 1702 adapter->em_insert_vlan_header = 1; 1703 } else if (ifp->if_flags & IFF_ALLMULTI) { 1704 reg_rctl |= E1000_RCTL_MPE; 1705 reg_rctl &= ~E1000_RCTL_UPE; 1706 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1707 } 1708 } 1709 1710 static void 1711 em_disable_promisc(struct adapter *adapter) 1712 { 1713 struct ifnet *ifp = &adapter->interface_data.ac_if; 1714 1715 uint32_t reg_rctl; 1716 1717 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1718 1719 reg_rctl &= (~E1000_RCTL_UPE); 1720 reg_rctl &= (~E1000_RCTL_MPE); 1721 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1722 1723 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1724 em_enable_vlans(adapter); 1725 adapter->em_insert_vlan_header = 0; 1726 } 1727 1728 /********************************************************************* 1729 * Multicast Update 1730 * 1731 * This routine is called whenever multicast address list is updated. 1732 * 1733 **********************************************************************/ 1734 1735 static void 1736 em_set_multi(struct adapter *adapter) 1737 { 1738 uint32_t reg_rctl = 0; 1739 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1740 struct ifmultiaddr *ifma; 1741 int mcnt = 0; 1742 struct ifnet *ifp = &adapter->interface_data.ac_if; 1743 1744 IOCTL_DEBUGOUT("em_set_multi: begin"); 1745 1746 if (adapter->hw.mac_type == em_82542_rev2_0) { 1747 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1748 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1749 em_pci_clear_mwi(&adapter->hw); 1750 reg_rctl |= E1000_RCTL_RST; 1751 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1752 msec_delay(5); 1753 } 1754 1755 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1756 if (ifma->ifma_addr->sa_family != AF_LINK) 1757 continue; 1758 1759 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1760 break; 1761 1762 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1763 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS); 1764 mcnt++; 1765 } 1766 1767 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1768 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1769 reg_rctl |= E1000_RCTL_MPE; 1770 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1771 } else { 1772 em_mc_addr_list_update(&adapter->hw, mta, mcnt, 0, 1); 1773 } 1774 1775 if (adapter->hw.mac_type == em_82542_rev2_0) { 1776 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1777 reg_rctl &= ~E1000_RCTL_RST; 1778 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1779 msec_delay(5); 1780 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1781 em_pci_set_mwi(&adapter->hw); 1782 } 1783 } 1784 1785 /********************************************************************* 1786 * Timer routine 1787 * 1788 * This routine checks for link status and updates statistics. 1789 * 1790 **********************************************************************/ 1791 1792 static void 1793 em_local_timer(void *arg) 1794 { 1795 struct ifnet *ifp; 1796 struct adapter *adapter = arg; 1797 ifp = &adapter->interface_data.ac_if; 1798 1799 lwkt_serialize_enter(ifp->if_serializer); 1800 1801 em_check_for_link(&adapter->hw); 1802 em_update_link_status(adapter); 1803 em_update_stats_counters(adapter); 1804 if (em_display_debug_stats && ifp->if_flags & IFF_RUNNING) 1805 em_print_hw_stats(adapter); 1806 em_smartspeed(adapter); 1807 1808 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1809 1810 lwkt_serialize_exit(ifp->if_serializer); 1811 } 1812 1813 static void 1814 em_update_link_status(struct adapter *adapter) 1815 { 1816 struct ifnet *ifp; 1817 ifp = &adapter->interface_data.ac_if; 1818 1819 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) { 1820 if (adapter->link_active == 0) { 1821 em_get_speed_and_duplex(&adapter->hw, 1822 &adapter->link_speed, 1823 &adapter->link_duplex); 1824 /* Check if we may set SPEED_MODE bit on PCI-E */ 1825 if (adapter->link_speed == SPEED_1000 && 1826 (adapter->hw.mac_type == em_82571 || 1827 adapter->hw.mac_type == em_82572)) { 1828 int tarc0; 1829 1830 tarc0 = E1000_READ_REG(&adapter->hw, TARC0); 1831 tarc0 |= SPEED_MODE_BIT; 1832 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0); 1833 } 1834 if (bootverbose) { 1835 if_printf(&adapter->interface_data.ac_if, 1836 "Link is up %d Mbps %s\n", 1837 adapter->link_speed, 1838 adapter->link_duplex == FULL_DUPLEX ? 1839 "Full Duplex" : "Half Duplex"); 1840 } 1841 adapter->link_active = 1; 1842 adapter->smartspeed = 0; 1843 ifp->if_baudrate = adapter->link_speed * 1000000; 1844 ifp->if_link_state = LINK_STATE_UP; 1845 if_link_state_change(ifp); 1846 } 1847 } else { 1848 if (adapter->link_active == 1) { 1849 ifp->if_baudrate = 0; 1850 adapter->link_speed = 0; 1851 adapter->link_duplex = 0; 1852 if (bootverbose) { 1853 if_printf(&adapter->interface_data.ac_if, 1854 "Link is Down\n"); 1855 } 1856 adapter->link_active = 0; 1857 ifp->if_link_state = LINK_STATE_DOWN; 1858 if_link_state_change(ifp); 1859 } 1860 } 1861 } 1862 1863 /********************************************************************* 1864 * 1865 * This routine disables all traffic on the adapter by issuing a 1866 * global reset on the MAC and deallocates TX/RX buffers. 1867 * 1868 **********************************************************************/ 1869 1870 static void 1871 em_stop(void *arg) 1872 { 1873 struct ifnet *ifp; 1874 struct adapter * adapter = arg; 1875 ifp = &adapter->interface_data.ac_if; 1876 1877 ASSERT_SERIALIZED(ifp->if_serializer); 1878 1879 INIT_DEBUGOUT("em_stop: begin"); 1880 em_disable_intr(adapter); 1881 em_reset_hw(&adapter->hw); 1882 callout_stop(&adapter->timer); 1883 callout_stop(&adapter->tx_fifo_timer); 1884 em_free_transmit_structures(adapter); 1885 em_free_receive_structures(adapter); 1886 1887 /* Tell the stack that the interface is no longer active */ 1888 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1889 ifp->if_timer = 0; 1890 } 1891 1892 /********************************************************************* 1893 * 1894 * Determine hardware revision. 1895 * 1896 **********************************************************************/ 1897 static void 1898 em_identify_hardware(struct adapter *adapter) 1899 { 1900 device_t dev = adapter->dev; 1901 1902 /* Make sure our PCI config space has the necessary stuff set */ 1903 adapter->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1904 if (!((adapter->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) && 1905 (adapter->hw.pci_cmd_word & PCIM_CMD_MEMEN))) { 1906 device_printf(dev, "Memory Access and/or Bus Master bits " 1907 "were not set!\n"); 1908 adapter->hw.pci_cmd_word |= PCIM_CMD_BUSMASTEREN | 1909 PCIM_CMD_MEMEN; 1910 pci_write_config(dev, PCIR_COMMAND, 1911 adapter->hw.pci_cmd_word, 2); 1912 } 1913 1914 /* Save off the information about this board */ 1915 adapter->hw.vendor_id = pci_get_vendor(dev); 1916 adapter->hw.device_id = pci_get_device(dev); 1917 adapter->hw.revision_id = pci_get_revid(dev); 1918 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev); 1919 adapter->hw.subsystem_id = pci_get_subdevice(dev); 1920 1921 /* Identify the MAC */ 1922 if (em_set_mac_type(&adapter->hw)) 1923 device_printf(dev, "Unknown MAC Type\n"); 1924 1925 if (adapter->hw.mac_type == em_82541 || 1926 adapter->hw.mac_type == em_82541_rev_2 || 1927 adapter->hw.mac_type == em_82547 || 1928 adapter->hw.mac_type == em_82547_rev_2) 1929 adapter->hw.phy_init_script = TRUE; 1930 } 1931 1932 static int 1933 em_allocate_pci_resources(device_t dev) 1934 { 1935 struct adapter *adapter = device_get_softc(dev); 1936 int rid; 1937 1938 rid = PCIR_BAR(0); 1939 adapter->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1940 &rid, RF_ACTIVE); 1941 if (adapter->res_memory == NULL) { 1942 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1943 return ENXIO; 1944 } 1945 adapter->osdep.mem_bus_space_tag = 1946 rman_get_bustag(adapter->res_memory); 1947 adapter->osdep.mem_bus_space_handle = 1948 rman_get_bushandle(adapter->res_memory); 1949 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 1950 1951 if (adapter->hw.mac_type > em_82543) { 1952 /* Figure our where our IO BAR is ? */ 1953 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1954 uint32_t val; 1955 1956 val = pci_read_config(dev, rid, 4); 1957 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1958 adapter->io_rid = rid; 1959 break; 1960 } 1961 rid += 4; 1962 /* check for 64bit BAR */ 1963 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1964 rid += 4; 1965 } 1966 if (rid >= PCIR_CIS) { 1967 device_printf(dev, "Unable to locate IO BAR\n"); 1968 return (ENXIO); 1969 } 1970 1971 adapter->res_ioport = bus_alloc_resource_any(dev, 1972 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1973 if (!(adapter->res_ioport)) { 1974 device_printf(dev, "Unable to allocate bus resource: " 1975 "ioport\n"); 1976 return ENXIO; 1977 } 1978 adapter->hw.io_base = 0; 1979 adapter->osdep.io_bus_space_tag = 1980 rman_get_bustag(adapter->res_ioport); 1981 adapter->osdep.io_bus_space_handle = 1982 rman_get_bushandle(adapter->res_ioport); 1983 } 1984 1985 /* For ICH8 we need to find the flash memory. */ 1986 if ((adapter->hw.mac_type == em_ich8lan) || 1987 (adapter->hw.mac_type == em_ich9lan)) { 1988 rid = EM_FLASH; 1989 adapter->flash_mem = bus_alloc_resource_any(dev, 1990 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1991 if (adapter->flash_mem == NULL) { 1992 device_printf(dev, "Unable to allocate bus resource: " 1993 "flash memory\n"); 1994 return ENXIO; 1995 } 1996 adapter->osdep.flash_bus_space_tag = 1997 rman_get_bustag(adapter->flash_mem); 1998 adapter->osdep.flash_bus_space_handle = 1999 rman_get_bushandle(adapter->flash_mem); 2000 } 2001 2002 rid = 0x0; 2003 adapter->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ, 2004 &rid, RF_SHAREABLE | RF_ACTIVE); 2005 if (adapter->res_interrupt == NULL) { 2006 device_printf(dev, "Unable to allocate bus resource: " 2007 "interrupt\n"); 2008 return ENXIO; 2009 } 2010 2011 adapter->hw.back = &adapter->osdep; 2012 2013 return 0; 2014 } 2015 2016 static void 2017 em_free_pci_resources(device_t dev) 2018 { 2019 struct adapter *adapter = device_get_softc(dev); 2020 2021 if (adapter->res_interrupt != NULL) { 2022 bus_release_resource(dev, SYS_RES_IRQ, 0, 2023 adapter->res_interrupt); 2024 } 2025 if (adapter->res_memory != NULL) { 2026 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2027 adapter->res_memory); 2028 } 2029 2030 if (adapter->res_ioport != NULL) { 2031 bus_release_resource(dev, SYS_RES_IOPORT, adapter->io_rid, 2032 adapter->res_ioport); 2033 } 2034 2035 if (adapter->flash_mem != NULL) { 2036 bus_release_resource(dev, SYS_RES_MEMORY, EM_FLASH, 2037 adapter->flash_mem); 2038 } 2039 } 2040 2041 /********************************************************************* 2042 * 2043 * Initialize the hardware to a configuration as specified by the 2044 * adapter structure. The controller is reset, the EEPROM is 2045 * verified, the MAC address is set, then the shared initialization 2046 * routines are called. 2047 * 2048 **********************************************************************/ 2049 static int 2050 em_hardware_init(struct adapter *adapter) 2051 { 2052 uint16_t rx_buffer_size; 2053 2054 INIT_DEBUGOUT("em_hardware_init: begin"); 2055 /* Issue a global reset */ 2056 em_reset_hw(&adapter->hw); 2057 2058 /* When hardware is reset, fifo_head is also reset */ 2059 adapter->tx_fifo_head = 0; 2060 2061 /* Make sure we have a good EEPROM before we read from it */ 2062 if (em_validate_eeprom_checksum(&adapter->hw) < 0) { 2063 if (em_validate_eeprom_checksum(&adapter->hw) < 0) { 2064 device_printf(adapter->dev, 2065 "The EEPROM Checksum Is Not Valid\n"); 2066 return (EIO); 2067 } 2068 } 2069 2070 if (em_read_part_num(&adapter->hw, &(adapter->part_num)) < 0) { 2071 device_printf(adapter->dev, 2072 "EEPROM read error while reading part number\n"); 2073 return (EIO); 2074 } 2075 2076 /* Set up smart power down as default off on newer adapters. */ 2077 if (!em_smart_pwr_down && 2078 (adapter->hw.mac_type == em_82571 || 2079 adapter->hw.mac_type == em_82572)) { 2080 uint16_t phy_tmp = 0; 2081 2082 /* Speed up time to link by disabling smart power down. */ 2083 em_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT, 2084 &phy_tmp); 2085 phy_tmp &= ~IGP02E1000_PM_SPD; 2086 em_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT, 2087 phy_tmp); 2088 } 2089 2090 /* 2091 * These parameters control the automatic generation (Tx) and 2092 * response (Rx) to Ethernet PAUSE frames. 2093 * - High water mark should allow for at least two frames to be 2094 * received after sending an XOFF. 2095 * - Low water mark works best when it is very near the high water mark. 2096 * This allows the receiver to restart by sending XON when it has 2097 * drained a bit. Here we use an arbitary value of 1500 which will 2098 * restart after one full frame is pulled from the buffer. There 2099 * could be several smaller frames in the buffer and if so they will 2100 * not trigger the XON until their total number reduces the buffer 2101 * by 1500. 2102 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2103 */ 2104 rx_buffer_size = ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff) << 10); 2105 2106 adapter->hw.fc_high_water = 2107 rx_buffer_size - roundup2(adapter->hw.max_frame_size, 1024); 2108 adapter->hw.fc_low_water = adapter->hw.fc_high_water - 1500; 2109 if (adapter->hw.mac_type == em_80003es2lan) 2110 adapter->hw.fc_pause_time = 0xFFFF; 2111 else 2112 adapter->hw.fc_pause_time = 1000; 2113 adapter->hw.fc_send_xon = TRUE; 2114 adapter->hw.fc = E1000_FC_FULL; 2115 2116 if (em_init_hw(&adapter->hw) < 0) { 2117 device_printf(adapter->dev, "Hardware Initialization Failed"); 2118 return (EIO); 2119 } 2120 2121 em_check_for_link(&adapter->hw); 2122 2123 return (0); 2124 } 2125 2126 /********************************************************************* 2127 * 2128 * Setup networking device structure and register an interface. 2129 * 2130 **********************************************************************/ 2131 static void 2132 em_setup_interface(device_t dev, struct adapter *adapter) 2133 { 2134 struct ifnet *ifp; 2135 u_char fiber_type = IFM_1000_SX; /* default type */ 2136 INIT_DEBUGOUT("em_setup_interface: begin"); 2137 2138 ifp = &adapter->interface_data.ac_if; 2139 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2140 ifp->if_mtu = ETHERMTU; 2141 ifp->if_baudrate = 1000000000; 2142 ifp->if_init = em_init; 2143 ifp->if_softc = adapter; 2144 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2145 ifp->if_ioctl = em_ioctl; 2146 ifp->if_start = em_start; 2147 #ifdef DEVICE_POLLING 2148 ifp->if_poll = em_poll; 2149 #endif 2150 ifp->if_watchdog = em_watchdog; 2151 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1); 2152 ifq_set_ready(&ifp->if_snd); 2153 2154 if (adapter->hw.mac_type >= em_82543) 2155 ifp->if_capabilities |= IFCAP_HWCSUM; 2156 2157 ifp->if_capenable = ifp->if_capabilities; 2158 2159 ether_ifattach(ifp, adapter->hw.mac_addr, NULL); 2160 2161 #ifdef PROFILE_SERIALIZER 2162 SYSCTL_ADD_UINT(&adapter->sysctl_ctx, 2163 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, 2164 "serializer_sleep", CTLFLAG_RW, 2165 &ifp->if_serializer->sleep_cnt, 0, NULL); 2166 SYSCTL_ADD_UINT(&adapter->sysctl_ctx, 2167 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, 2168 "serializer_tryfail", CTLFLAG_RW, 2169 &ifp->if_serializer->tryfail_cnt, 0, NULL); 2170 SYSCTL_ADD_UINT(&adapter->sysctl_ctx, 2171 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, 2172 "serializer_enter", CTLFLAG_RW, 2173 &ifp->if_serializer->enter_cnt, 0, NULL); 2174 SYSCTL_ADD_UINT(&adapter->sysctl_ctx, 2175 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, 2176 "serializer_try", CTLFLAG_RW, 2177 &ifp->if_serializer->try_cnt, 0, NULL); 2178 #endif 2179 2180 /* 2181 * Tell the upper layer(s) we support long frames. 2182 */ 2183 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2184 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2185 #if 0 2186 ifp->if_capenable |= IFCAP_VLAN_MTU; 2187 #endif 2188 2189 /* 2190 * Specify the media types supported by this adapter and register 2191 * callbacks to update media and link information 2192 */ 2193 ifmedia_init(&adapter->media, IFM_IMASK, em_media_change, 2194 em_media_status); 2195 if (adapter->hw.media_type == em_media_type_fiber || 2196 adapter->hw.media_type == em_media_type_internal_serdes) { 2197 if (adapter->hw.mac_type == em_82545) 2198 fiber_type = IFM_1000_LX; 2199 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2200 0, NULL); 2201 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2202 } else { 2203 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2204 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2205 0, NULL); 2206 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2207 0, NULL); 2208 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2209 0, NULL); 2210 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 2211 0, NULL); 2212 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2213 } 2214 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2215 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2216 } 2217 2218 /********************************************************************* 2219 * 2220 * Workaround for SmartSpeed on 82541 and 82547 controllers 2221 * 2222 **********************************************************************/ 2223 static void 2224 em_smartspeed(struct adapter *adapter) 2225 { 2226 uint16_t phy_tmp; 2227 2228 if (adapter->link_active || (adapter->hw.phy_type != em_phy_igp) || 2229 !adapter->hw.autoneg || 2230 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL)) 2231 return; 2232 2233 if (adapter->smartspeed == 0) { 2234 /* 2235 * If Master/Slave config fault is asserted twice, 2236 * we assume back-to-back. 2237 */ 2238 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2239 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2240 return; 2241 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2242 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2243 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2244 if (phy_tmp & CR_1000T_MS_ENABLE) { 2245 phy_tmp &= ~CR_1000T_MS_ENABLE; 2246 em_write_phy_reg(&adapter->hw, 2247 PHY_1000T_CTRL, phy_tmp); 2248 adapter->smartspeed++; 2249 if (adapter->hw.autoneg && 2250 !em_phy_setup_autoneg(&adapter->hw) && 2251 !em_read_phy_reg(&adapter->hw, PHY_CTRL, 2252 &phy_tmp)) { 2253 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2254 MII_CR_RESTART_AUTO_NEG); 2255 em_write_phy_reg(&adapter->hw, 2256 PHY_CTRL, phy_tmp); 2257 } 2258 } 2259 } 2260 return; 2261 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2262 /* If still no link, perhaps using 2/3 pair cable */ 2263 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2264 phy_tmp |= CR_1000T_MS_ENABLE; 2265 em_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2266 if (adapter->hw.autoneg && 2267 !em_phy_setup_autoneg(&adapter->hw) && 2268 !em_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_tmp)) { 2269 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2270 MII_CR_RESTART_AUTO_NEG); 2271 em_write_phy_reg(&adapter->hw, PHY_CTRL, phy_tmp); 2272 } 2273 } 2274 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2275 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2276 adapter->smartspeed = 0; 2277 } 2278 2279 /* 2280 * Manage DMA'able memory. 2281 */ 2282 static void 2283 em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2284 { 2285 if (error) 2286 return; 2287 *(bus_addr_t *)arg = segs->ds_addr; 2288 } 2289 2290 static int 2291 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2292 struct em_dma_alloc *dma) 2293 { 2294 device_t dev = adapter->dev; 2295 int error; 2296 2297 error = bus_dma_tag_create(NULL, /* parent */ 2298 EM_DBA_ALIGN, 0, /* alignment, bounds */ 2299 BUS_SPACE_MAXADDR, /* lowaddr */ 2300 BUS_SPACE_MAXADDR, /* highaddr */ 2301 NULL, NULL, /* filter, filterarg */ 2302 size, /* maxsize */ 2303 1, /* nsegments */ 2304 size, /* maxsegsize */ 2305 0, /* flags */ 2306 &dma->dma_tag); 2307 if (error) { 2308 device_printf(dev, "%s: bus_dma_tag_create failed; error %d\n", 2309 __func__, error); 2310 return error; 2311 } 2312 2313 error = bus_dmamem_alloc(dma->dma_tag, (void**)&dma->dma_vaddr, 2314 BUS_DMA_WAITOK, &dma->dma_map); 2315 if (error) { 2316 device_printf(dev, "%s: bus_dmammem_alloc failed; " 2317 "size %llu, error %d\n", 2318 __func__, (uintmax_t)size, error); 2319 goto fail; 2320 } 2321 2322 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, 2323 dma->dma_vaddr, size, 2324 em_dmamap_cb, &dma->dma_paddr, 2325 BUS_DMA_WAITOK); 2326 if (error) { 2327 device_printf(dev, "%s: bus_dmamap_load failed; error %u\n", 2328 __func__, error); 2329 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2330 goto fail; 2331 } 2332 2333 return 0; 2334 fail: 2335 bus_dma_tag_destroy(dma->dma_tag); 2336 dma->dma_tag = NULL; 2337 return error; 2338 } 2339 2340 static void 2341 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2342 { 2343 if (dma->dma_tag != NULL) { 2344 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2345 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2346 bus_dma_tag_destroy(dma->dma_tag); 2347 dma->dma_tag = NULL; 2348 } 2349 } 2350 2351 /********************************************************************* 2352 * 2353 * Allocate and initialize transmit structures. 2354 * 2355 **********************************************************************/ 2356 static int 2357 em_setup_transmit_structures(struct adapter *adapter) 2358 { 2359 struct em_buffer *tx_buffer; 2360 bus_size_t size; 2361 int error, i; 2362 2363 /* 2364 * Setup DMA descriptor areas. 2365 */ 2366 size = roundup2(adapter->hw.max_frame_size, MCLBYTES); 2367 if (bus_dma_tag_create(NULL, /* parent */ 2368 1, 0, /* alignment, bounds */ 2369 BUS_SPACE_MAXADDR, /* lowaddr */ 2370 BUS_SPACE_MAXADDR, /* highaddr */ 2371 NULL, NULL, /* filter, filterarg */ 2372 size, /* maxsize */ 2373 EM_MAX_SCATTER, /* nsegments */ 2374 size, /* maxsegsize */ 2375 0, /* flags */ 2376 &adapter->txtag)) { 2377 device_printf(adapter->dev, "Unable to allocate TX DMA tag\n"); 2378 return(ENOMEM); 2379 } 2380 2381 adapter->tx_buffer_area = 2382 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc, 2383 M_DEVBUF, M_WAITOK | M_ZERO); 2384 2385 bzero(adapter->tx_desc_base, 2386 sizeof(struct em_tx_desc) * adapter->num_tx_desc); 2387 tx_buffer = adapter->tx_buffer_area; 2388 for (i = 0; i < adapter->num_tx_desc; i++) { 2389 error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map); 2390 if (error) { 2391 device_printf(adapter->dev, 2392 "Unable to create TX DMA map\n"); 2393 goto fail; 2394 } 2395 tx_buffer++; 2396 } 2397 2398 adapter->next_avail_tx_desc = 0; 2399 adapter->next_tx_to_clean = 0; 2400 2401 /* Set number of descriptors available */ 2402 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2403 2404 /* Set checksum context */ 2405 adapter->active_checksum_context = OFFLOAD_NONE; 2406 2407 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2408 BUS_DMASYNC_PREWRITE); 2409 2410 return (0); 2411 fail: 2412 em_free_transmit_structures(adapter); 2413 return (error); 2414 } 2415 2416 /********************************************************************* 2417 * 2418 * Enable transmit unit. 2419 * 2420 **********************************************************************/ 2421 static void 2422 em_initialize_transmit_unit(struct adapter *adapter) 2423 { 2424 uint32_t reg_tctl; 2425 uint32_t reg_tipg = 0; 2426 uint64_t bus_addr; 2427 2428 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2429 2430 /* Setup the Base and Length of the Tx Descriptor Ring */ 2431 bus_addr = adapter->txdma.dma_paddr; 2432 E1000_WRITE_REG(&adapter->hw, TDLEN, 2433 adapter->num_tx_desc * sizeof(struct em_tx_desc)); 2434 E1000_WRITE_REG(&adapter->hw, TDBAH, (uint32_t)(bus_addr >> 32)); 2435 E1000_WRITE_REG(&adapter->hw, TDBAL, (uint32_t)bus_addr); 2436 2437 /* Setup the HW Tx Head and Tail descriptor pointers */ 2438 E1000_WRITE_REG(&adapter->hw, TDT, 0); 2439 E1000_WRITE_REG(&adapter->hw, TDH, 0); 2440 2441 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2442 E1000_READ_REG(&adapter->hw, TDBAL), 2443 E1000_READ_REG(&adapter->hw, TDLEN)); 2444 2445 /* Set the default values for the Tx Inter Packet Gap timer */ 2446 switch (adapter->hw.mac_type) { 2447 case em_82542_rev2_0: 2448 case em_82542_rev2_1: 2449 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2450 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2451 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2452 break; 2453 case em_80003es2lan: 2454 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2455 reg_tipg |= 2456 DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2457 break; 2458 default: 2459 if (adapter->hw.media_type == em_media_type_fiber || 2460 adapter->hw.media_type == em_media_type_internal_serdes) 2461 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2462 else 2463 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2464 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2465 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2466 } 2467 2468 E1000_WRITE_REG(&adapter->hw, TIPG, reg_tipg); 2469 E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay.value); 2470 if (adapter->hw.mac_type >= em_82540) { 2471 E1000_WRITE_REG(&adapter->hw, TADV, 2472 adapter->tx_abs_int_delay.value); 2473 } 2474 2475 /* Program the Transmit Control Register */ 2476 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2477 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2478 if (adapter->hw.mac_type >= em_82571) 2479 reg_tctl |= E1000_TCTL_MULR; 2480 if (adapter->link_duplex == 1) 2481 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2482 else 2483 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2484 2485 /* This write will effectively turn on the transmit unit. */ 2486 E1000_WRITE_REG(&adapter->hw, TCTL, reg_tctl); 2487 2488 /* Setup Transmit Descriptor Base Settings */ 2489 adapter->txd_cmd = E1000_TXD_CMD_IFCS; 2490 2491 if (adapter->tx_int_delay.value > 0) 2492 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2493 } 2494 2495 /********************************************************************* 2496 * 2497 * Free all transmit related data structures. 2498 * 2499 **********************************************************************/ 2500 static void 2501 em_free_transmit_structures(struct adapter *adapter) 2502 { 2503 struct em_buffer *tx_buffer; 2504 int i; 2505 2506 INIT_DEBUGOUT("free_transmit_structures: begin"); 2507 2508 if (adapter->tx_buffer_area != NULL) { 2509 tx_buffer = adapter->tx_buffer_area; 2510 for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) { 2511 if (tx_buffer->m_head != NULL) { 2512 bus_dmamap_unload(adapter->txtag, 2513 tx_buffer->map); 2514 m_freem(tx_buffer->m_head); 2515 } 2516 2517 if (tx_buffer->map != NULL) { 2518 bus_dmamap_destroy(adapter->txtag, tx_buffer->map); 2519 tx_buffer->map = NULL; 2520 } 2521 tx_buffer->m_head = NULL; 2522 } 2523 } 2524 if (adapter->tx_buffer_area != NULL) { 2525 kfree(adapter->tx_buffer_area, M_DEVBUF); 2526 adapter->tx_buffer_area = NULL; 2527 } 2528 if (adapter->txtag != NULL) { 2529 bus_dma_tag_destroy(adapter->txtag); 2530 adapter->txtag = NULL; 2531 } 2532 } 2533 2534 /********************************************************************* 2535 * 2536 * The offload context needs to be set when we transfer the first 2537 * packet of a particular protocol (TCP/UDP). We change the 2538 * context only if the protocol type changes. 2539 * 2540 **********************************************************************/ 2541 static void 2542 em_transmit_checksum_setup(struct adapter *adapter, 2543 struct mbuf *mp, 2544 uint32_t *txd_upper, 2545 uint32_t *txd_lower) 2546 { 2547 struct em_context_desc *TXD; 2548 struct em_buffer *tx_buffer; 2549 int curr_txd; 2550 2551 if (mp->m_pkthdr.csum_flags) { 2552 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 2553 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2554 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2555 if (adapter->active_checksum_context == OFFLOAD_TCP_IP) 2556 return; 2557 else 2558 adapter->active_checksum_context = OFFLOAD_TCP_IP; 2559 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 2560 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2561 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2562 if (adapter->active_checksum_context == OFFLOAD_UDP_IP) 2563 return; 2564 else 2565 adapter->active_checksum_context = OFFLOAD_UDP_IP; 2566 } else { 2567 *txd_upper = 0; 2568 *txd_lower = 0; 2569 return; 2570 } 2571 } else { 2572 *txd_upper = 0; 2573 *txd_lower = 0; 2574 return; 2575 } 2576 2577 /* 2578 * If we reach this point, the checksum offload context 2579 * needs to be reset. 2580 */ 2581 curr_txd = adapter->next_avail_tx_desc; 2582 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 2583 TXD = (struct em_context_desc *) &adapter->tx_desc_base[curr_txd]; 2584 2585 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2586 TXD->lower_setup.ip_fields.ipcso = 2587 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2588 TXD->lower_setup.ip_fields.ipcse = 2589 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2590 2591 TXD->upper_setup.tcp_fields.tucss = 2592 ETHER_HDR_LEN + sizeof(struct ip); 2593 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2594 2595 if (adapter->active_checksum_context == OFFLOAD_TCP_IP) { 2596 TXD->upper_setup.tcp_fields.tucso = 2597 ETHER_HDR_LEN + sizeof(struct ip) + 2598 offsetof(struct tcphdr, th_sum); 2599 } else if (adapter->active_checksum_context == OFFLOAD_UDP_IP) { 2600 TXD->upper_setup.tcp_fields.tucso = 2601 ETHER_HDR_LEN + sizeof(struct ip) + 2602 offsetof(struct udphdr, uh_sum); 2603 } 2604 2605 TXD->tcp_seg_setup.data = htole32(0); 2606 TXD->cmd_and_length = htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT); 2607 2608 tx_buffer->m_head = NULL; 2609 tx_buffer->next_eop = -1; 2610 2611 if (++curr_txd == adapter->num_tx_desc) 2612 curr_txd = 0; 2613 2614 adapter->num_tx_desc_avail--; 2615 adapter->next_avail_tx_desc = curr_txd; 2616 } 2617 2618 /********************************************************************** 2619 * 2620 * Examine each tx_buffer in the used queue. If the hardware is done 2621 * processing the packet then free associated resources. The 2622 * tx_buffer is put back on the free queue. 2623 * 2624 **********************************************************************/ 2625 2626 static void 2627 em_txeof(struct adapter *adapter) 2628 { 2629 int first, last, done, num_avail; 2630 struct em_buffer *tx_buffer; 2631 struct em_tx_desc *tx_desc, *eop_desc; 2632 struct ifnet *ifp = &adapter->interface_data.ac_if; 2633 2634 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2635 return; 2636 2637 num_avail = adapter->num_tx_desc_avail; 2638 first = adapter->next_tx_to_clean; 2639 tx_desc = &adapter->tx_desc_base[first]; 2640 tx_buffer = &adapter->tx_buffer_area[first]; 2641 last = tx_buffer->next_eop; 2642 KKASSERT(last >= 0 && last < adapter->num_tx_desc); 2643 eop_desc = &adapter->tx_desc_base[last]; 2644 2645 /* 2646 * Now caculate the terminating index for the cleanup loop below 2647 */ 2648 if (++last == adapter->num_tx_desc) 2649 last = 0; 2650 done = last; 2651 2652 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2653 BUS_DMASYNC_POSTREAD); 2654 2655 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2656 while (first != done) { 2657 tx_desc->upper.data = 0; 2658 tx_desc->lower.data = 0; 2659 num_avail++; 2660 2661 logif(pkt_txclean); 2662 2663 if (tx_buffer->m_head) { 2664 ifp->if_opackets++; 2665 bus_dmamap_sync(adapter->txtag, tx_buffer->map, 2666 BUS_DMASYNC_POSTWRITE); 2667 bus_dmamap_unload(adapter->txtag, 2668 tx_buffer->map); 2669 2670 m_freem(tx_buffer->m_head); 2671 tx_buffer->m_head = NULL; 2672 } 2673 tx_buffer->next_eop = -1; 2674 2675 if (++first == adapter->num_tx_desc) 2676 first = 0; 2677 2678 tx_buffer = &adapter->tx_buffer_area[first]; 2679 tx_desc = &adapter->tx_desc_base[first]; 2680 } 2681 /* See if we can continue to the next packet */ 2682 last = tx_buffer->next_eop; 2683 if (last != -1) { 2684 KKASSERT(last >= 0 && last < adapter->num_tx_desc); 2685 eop_desc = &adapter->tx_desc_base[last]; 2686 if (++last == adapter->num_tx_desc) 2687 last = 0; 2688 done = last; 2689 } else { 2690 break; 2691 } 2692 } 2693 2694 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2695 BUS_DMASYNC_PREWRITE); 2696 2697 adapter->next_tx_to_clean = first; 2698 2699 /* 2700 * If we have enough room, clear IFF_OACTIVE to tell the stack 2701 * that it is OK to send packets. 2702 * If there are no pending descriptors, clear the timeout. Otherwise, 2703 * if some descriptors have been freed, restart the timeout. 2704 */ 2705 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 2706 ifp->if_flags &= ~IFF_OACTIVE; 2707 if (num_avail == adapter->num_tx_desc) 2708 ifp->if_timer = 0; 2709 else if (num_avail == adapter->num_tx_desc_avail) 2710 ifp->if_timer = EM_TX_TIMEOUT; 2711 } 2712 adapter->num_tx_desc_avail = num_avail; 2713 } 2714 2715 /********************************************************************* 2716 * 2717 * Get a buffer from system mbuf buffer pool. 2718 * 2719 **********************************************************************/ 2720 static int 2721 em_get_buf(int i, struct adapter *adapter, struct mbuf *nmp, int how) 2722 { 2723 struct mbuf *mp = nmp; 2724 struct em_buffer *rx_buffer; 2725 struct ifnet *ifp; 2726 bus_addr_t paddr; 2727 int error; 2728 2729 ifp = &adapter->interface_data.ac_if; 2730 2731 if (mp == NULL) { 2732 mp = m_getcl(how, MT_DATA, M_PKTHDR); 2733 if (mp == NULL) { 2734 adapter->mbuf_cluster_failed++; 2735 return (ENOBUFS); 2736 } 2737 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2738 } else { 2739 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 2740 mp->m_data = mp->m_ext.ext_buf; 2741 mp->m_next = NULL; 2742 } 2743 2744 if (ifp->if_mtu <= ETHERMTU) 2745 m_adj(mp, ETHER_ALIGN); 2746 2747 rx_buffer = &adapter->rx_buffer_area[i]; 2748 2749 /* 2750 * Using memory from the mbuf cluster pool, invoke the 2751 * bus_dma machinery to arrange the memory mapping. 2752 */ 2753 error = bus_dmamap_load(adapter->rxtag, rx_buffer->map, 2754 mtod(mp, void *), mp->m_len, 2755 em_dmamap_cb, &paddr, 0); 2756 if (error) { 2757 m_freem(mp); 2758 return (error); 2759 } 2760 rx_buffer->m_head = mp; 2761 adapter->rx_desc_base[i].buffer_addr = htole64(paddr); 2762 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 2763 2764 return (0); 2765 } 2766 2767 /********************************************************************* 2768 * 2769 * Allocate memory for rx_buffer structures. Since we use one 2770 * rx_buffer per received packet, the maximum number of rx_buffer's 2771 * that we'll need is equal to the number of receive descriptors 2772 * that we've allocated. 2773 * 2774 **********************************************************************/ 2775 static int 2776 em_allocate_receive_structures(struct adapter *adapter) 2777 { 2778 int i, error, size; 2779 struct em_buffer *rx_buffer; 2780 2781 size = adapter->num_rx_desc * sizeof(struct em_buffer); 2782 adapter->rx_buffer_area = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 2783 2784 error = bus_dma_tag_create(NULL, /* parent */ 2785 1, 0, /* alignment, bounds */ 2786 BUS_SPACE_MAXADDR, /* lowaddr */ 2787 BUS_SPACE_MAXADDR, /* highaddr */ 2788 NULL, NULL, /* filter, filterarg */ 2789 MCLBYTES, /* maxsize */ 2790 1, /* nsegments */ 2791 MCLBYTES, /* maxsegsize */ 2792 0, /* flags */ 2793 &adapter->rxtag); 2794 if (error) { 2795 device_printf(adapter->dev, "%s: bus_dma_tag_create failed; " 2796 "error %u\n", __func__, error); 2797 goto fail; 2798 } 2799 2800 rx_buffer = adapter->rx_buffer_area; 2801 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 2802 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 2803 &rx_buffer->map); 2804 if (error) { 2805 device_printf(adapter->dev, 2806 "%s: bus_dmamap_create failed; " 2807 "error %u\n", __func__, error); 2808 goto fail; 2809 } 2810 } 2811 2812 for (i = 0; i < adapter->num_rx_desc; i++) { 2813 error = em_get_buf(i, adapter, NULL, MB_DONTWAIT); 2814 if (error) 2815 goto fail; 2816 } 2817 2818 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 2819 BUS_DMASYNC_PREWRITE); 2820 2821 return (0); 2822 fail: 2823 em_free_receive_structures(adapter); 2824 return (error); 2825 } 2826 2827 /********************************************************************* 2828 * 2829 * Allocate and initialize receive structures. 2830 * 2831 **********************************************************************/ 2832 static int 2833 em_setup_receive_structures(struct adapter *adapter) 2834 { 2835 int error; 2836 2837 bzero(adapter->rx_desc_base, 2838 sizeof(struct em_rx_desc) * adapter->num_rx_desc); 2839 2840 error = em_allocate_receive_structures(adapter); 2841 if (error) 2842 return (error); 2843 2844 /* Setup our descriptor pointers */ 2845 adapter->next_rx_desc_to_check = 0; 2846 2847 return (0); 2848 } 2849 2850 /********************************************************************* 2851 * 2852 * Enable receive unit. 2853 * 2854 **********************************************************************/ 2855 static void 2856 em_initialize_receive_unit(struct adapter *adapter) 2857 { 2858 uint32_t reg_rctl; 2859 uint32_t reg_rxcsum; 2860 struct ifnet *ifp; 2861 uint64_t bus_addr; 2862 2863 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2864 2865 ifp = &adapter->interface_data.ac_if; 2866 2867 /* 2868 * Make sure receives are disabled while setting 2869 * up the descriptor ring 2870 */ 2871 E1000_WRITE_REG(&adapter->hw, RCTL, 0); 2872 2873 /* Set the Receive Delay Timer Register */ 2874 E1000_WRITE_REG(&adapter->hw, RDTR, 2875 adapter->rx_int_delay.value | E1000_RDT_FPDB); 2876 2877 if(adapter->hw.mac_type >= em_82540) { 2878 E1000_WRITE_REG(&adapter->hw, RADV, 2879 adapter->rx_abs_int_delay.value); 2880 2881 /* Set the interrupt throttling rate in 256ns increments */ 2882 if (em_int_throttle_ceil) { 2883 E1000_WRITE_REG(&adapter->hw, ITR, 2884 1000000000 / 256 / em_int_throttle_ceil); 2885 } else { 2886 E1000_WRITE_REG(&adapter->hw, ITR, 0); 2887 } 2888 } 2889 2890 /* Setup the Base and Length of the Rx Descriptor Ring */ 2891 bus_addr = adapter->rxdma.dma_paddr; 2892 E1000_WRITE_REG(&adapter->hw, RDLEN, adapter->num_rx_desc * 2893 sizeof(struct em_rx_desc)); 2894 E1000_WRITE_REG(&adapter->hw, RDBAH, (uint32_t)(bus_addr >> 32)); 2895 E1000_WRITE_REG(&adapter->hw, RDBAL, (uint32_t)bus_addr); 2896 2897 /* Setup the Receive Control Register */ 2898 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2899 E1000_RCTL_RDMTS_HALF | 2900 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2901 2902 if (adapter->hw.tbi_compatibility_on == TRUE) 2903 reg_rctl |= E1000_RCTL_SBP; 2904 2905 switch (adapter->rx_buffer_len) { 2906 default: 2907 case EM_RXBUFFER_2048: 2908 reg_rctl |= E1000_RCTL_SZ_2048; 2909 break; 2910 case EM_RXBUFFER_4096: 2911 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | 2912 E1000_RCTL_LPE; 2913 break; 2914 case EM_RXBUFFER_8192: 2915 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | 2916 E1000_RCTL_LPE; 2917 break; 2918 case EM_RXBUFFER_16384: 2919 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | 2920 E1000_RCTL_LPE; 2921 break; 2922 } 2923 2924 if (ifp->if_mtu > ETHERMTU) 2925 reg_rctl |= E1000_RCTL_LPE; 2926 2927 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2928 if ((adapter->hw.mac_type >= em_82543) && 2929 (ifp->if_capenable & IFCAP_RXCSUM)) { 2930 reg_rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM); 2931 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2932 E1000_WRITE_REG(&adapter->hw, RXCSUM, reg_rxcsum); 2933 } 2934 2935 #ifdef EM_X60_WORKAROUND 2936 if (adapter->hw.mac_type == em_82573) 2937 E1000_WRITE_REG(&adapter->hw, RDTR, 32); 2938 #endif 2939 2940 /* Enable Receives */ 2941 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 2942 2943 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2944 E1000_WRITE_REG(&adapter->hw, RDH, 0); 2945 E1000_WRITE_REG(&adapter->hw, RDT, adapter->num_rx_desc - 1); 2946 } 2947 2948 /********************************************************************* 2949 * 2950 * Free receive related data structures. 2951 * 2952 **********************************************************************/ 2953 static void 2954 em_free_receive_structures(struct adapter *adapter) 2955 { 2956 struct em_buffer *rx_buffer; 2957 int i; 2958 2959 INIT_DEBUGOUT("free_receive_structures: begin"); 2960 2961 if (adapter->rx_buffer_area != NULL) { 2962 rx_buffer = adapter->rx_buffer_area; 2963 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 2964 if (rx_buffer->m_head != NULL) { 2965 bus_dmamap_unload(adapter->rxtag, 2966 rx_buffer->map); 2967 m_freem(rx_buffer->m_head); 2968 rx_buffer->m_head = NULL; 2969 } 2970 if (rx_buffer->map != NULL) { 2971 bus_dmamap_destroy(adapter->rxtag, 2972 rx_buffer->map); 2973 rx_buffer->map = NULL; 2974 } 2975 } 2976 } 2977 if (adapter->rx_buffer_area != NULL) { 2978 kfree(adapter->rx_buffer_area, M_DEVBUF); 2979 adapter->rx_buffer_area = NULL; 2980 } 2981 if (adapter->rxtag != NULL) { 2982 bus_dma_tag_destroy(adapter->rxtag); 2983 adapter->rxtag = NULL; 2984 } 2985 } 2986 2987 /********************************************************************* 2988 * 2989 * This routine executes in interrupt context. It replenishes 2990 * the mbufs in the descriptor and sends data which has been 2991 * dma'ed into host memory to upper layer. 2992 * 2993 * We loop at most count times if count is > 0, or until done if 2994 * count < 0. 2995 * 2996 *********************************************************************/ 2997 static void 2998 em_rxeof(struct adapter *adapter, int count) 2999 { 3000 struct ifnet *ifp; 3001 struct mbuf *mp; 3002 uint8_t accept_frame = 0; 3003 uint8_t eop = 0; 3004 uint16_t len, desc_len, prev_len_adj; 3005 int i; 3006 3007 /* Pointer to the receive descriptor being examined. */ 3008 struct em_rx_desc *current_desc; 3009 3010 ifp = &adapter->interface_data.ac_if; 3011 i = adapter->next_rx_desc_to_check; 3012 current_desc = &adapter->rx_desc_base[i]; 3013 3014 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 3015 BUS_DMASYNC_POSTREAD); 3016 3017 if (!(current_desc->status & E1000_RXD_STAT_DD)) 3018 return; 3019 3020 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) { 3021 logif(pkt_receive); 3022 mp = adapter->rx_buffer_area[i].m_head; 3023 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3024 BUS_DMASYNC_POSTREAD); 3025 bus_dmamap_unload(adapter->rxtag, 3026 adapter->rx_buffer_area[i].map); 3027 3028 accept_frame = 1; 3029 prev_len_adj = 0; 3030 desc_len = le16toh(current_desc->length); 3031 if (current_desc->status & E1000_RXD_STAT_EOP) { 3032 count--; 3033 eop = 1; 3034 if (desc_len < ETHER_CRC_LEN) { 3035 len = 0; 3036 prev_len_adj = ETHER_CRC_LEN - desc_len; 3037 } else { 3038 len = desc_len - ETHER_CRC_LEN; 3039 } 3040 } else { 3041 eop = 0; 3042 len = desc_len; 3043 } 3044 3045 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3046 uint8_t last_byte; 3047 uint32_t pkt_len = desc_len; 3048 3049 if (adapter->fmp != NULL) 3050 pkt_len += adapter->fmp->m_pkthdr.len; 3051 3052 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3053 3054 if (TBI_ACCEPT(&adapter->hw, current_desc->status, 3055 current_desc->errors, 3056 pkt_len, last_byte)) { 3057 em_tbi_adjust_stats(&adapter->hw, 3058 &adapter->stats, 3059 pkt_len, 3060 adapter->hw.mac_addr); 3061 if (len > 0) 3062 len--; 3063 } else { 3064 accept_frame = 0; 3065 } 3066 } 3067 3068 if (accept_frame) { 3069 if (em_get_buf(i, adapter, NULL, MB_DONTWAIT) == ENOBUFS) { 3070 adapter->dropped_pkts++; 3071 em_get_buf(i, adapter, mp, MB_DONTWAIT); 3072 if (adapter->fmp != NULL) 3073 m_freem(adapter->fmp); 3074 adapter->fmp = NULL; 3075 adapter->lmp = NULL; 3076 goto skip; 3077 } 3078 3079 /* Assign correct length to the current fragment */ 3080 mp->m_len = len; 3081 3082 if (adapter->fmp == NULL) { 3083 mp->m_pkthdr.len = len; 3084 adapter->fmp = mp; /* Store the first mbuf */ 3085 adapter->lmp = mp; 3086 } else { 3087 /* Chain mbuf's together */ 3088 /* 3089 * Adjust length of previous mbuf in chain if 3090 * we received less than 4 bytes in the last 3091 * descriptor. 3092 */ 3093 if (prev_len_adj > 0) { 3094 adapter->lmp->m_len -= prev_len_adj; 3095 adapter->fmp->m_pkthdr.len -= prev_len_adj; 3096 } 3097 adapter->lmp->m_next = mp; 3098 adapter->lmp = adapter->lmp->m_next; 3099 adapter->fmp->m_pkthdr.len += len; 3100 } 3101 3102 if (eop) { 3103 adapter->fmp->m_pkthdr.rcvif = ifp; 3104 ifp->if_ipackets++; 3105 3106 em_receive_checksum(adapter, current_desc, 3107 adapter->fmp); 3108 if (current_desc->status & E1000_RXD_STAT_VP) { 3109 VLAN_INPUT_TAG(adapter->fmp, 3110 (current_desc->special & 3111 E1000_RXD_SPC_VLAN_MASK)); 3112 } else { 3113 ifp->if_input(ifp, adapter->fmp); 3114 } 3115 adapter->fmp = NULL; 3116 adapter->lmp = NULL; 3117 } 3118 } else { 3119 adapter->dropped_pkts++; 3120 em_get_buf(i, adapter, mp, MB_DONTWAIT); 3121 if (adapter->fmp != NULL) 3122 m_freem(adapter->fmp); 3123 adapter->fmp = NULL; 3124 adapter->lmp = NULL; 3125 } 3126 3127 skip: 3128 /* Zero out the receive descriptors status. */ 3129 current_desc->status = 0; 3130 3131 /* Advance our pointers to the next descriptor. */ 3132 if (++i == adapter->num_rx_desc) { 3133 i = 0; 3134 current_desc = adapter->rx_desc_base; 3135 } else { 3136 current_desc++; 3137 } 3138 } 3139 3140 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 3141 BUS_DMASYNC_PREWRITE); 3142 3143 adapter->next_rx_desc_to_check = i; 3144 3145 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3146 if (--i < 0) 3147 i = adapter->num_rx_desc - 1; 3148 3149 E1000_WRITE_REG(&adapter->hw, RDT, i); 3150 } 3151 3152 /********************************************************************* 3153 * 3154 * Verify that the hardware indicated that the checksum is valid. 3155 * Inform the stack about the status of checksum so that stack 3156 * doesn't spend time verifying the checksum. 3157 * 3158 *********************************************************************/ 3159 static void 3160 em_receive_checksum(struct adapter *adapter, 3161 struct em_rx_desc *rx_desc, 3162 struct mbuf *mp) 3163 { 3164 /* 82543 or newer only */ 3165 if ((adapter->hw.mac_type < em_82543) || 3166 /* Ignore Checksum bit is set */ 3167 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 3168 mp->m_pkthdr.csum_flags = 0; 3169 return; 3170 } 3171 3172 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 3173 /* Did it pass? */ 3174 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3175 /* IP Checksum Good */ 3176 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3177 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3178 } else { 3179 mp->m_pkthdr.csum_flags = 0; 3180 } 3181 } 3182 3183 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 3184 /* Did it pass? */ 3185 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3186 mp->m_pkthdr.csum_flags |= 3187 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR | 3188 CSUM_FRAG_NOT_CHECKED); 3189 mp->m_pkthdr.csum_data = htons(0xffff); 3190 } 3191 } 3192 } 3193 3194 3195 static void 3196 em_enable_vlans(struct adapter *adapter) 3197 { 3198 uint32_t ctrl; 3199 3200 E1000_WRITE_REG(&adapter->hw, VET, ETHERTYPE_VLAN); 3201 3202 ctrl = E1000_READ_REG(&adapter->hw, CTRL); 3203 ctrl |= E1000_CTRL_VME; 3204 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 3205 } 3206 3207 static void 3208 em_disable_vlans(struct adapter *adapter) 3209 { 3210 uint32_t ctrl; 3211 3212 ctrl = E1000_READ_REG(&adapter->hw, CTRL); 3213 ctrl &= ~E1000_CTRL_VME; 3214 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 3215 } 3216 3217 /* 3218 * note: we must call bus_enable_intr() prior to enabling the hardware 3219 * interrupt and bus_disable_intr() after disabling the hardware interrupt 3220 * in order to avoid handler execution races from scheduled interrupt 3221 * threads. 3222 */ 3223 static void 3224 em_enable_intr(struct adapter *adapter) 3225 { 3226 struct ifnet *ifp = &adapter->interface_data.ac_if; 3227 3228 if ((ifp->if_flags & IFF_POLLING) == 0) { 3229 lwkt_serialize_handler_enable(ifp->if_serializer); 3230 E1000_WRITE_REG(&adapter->hw, IMS, (IMS_ENABLE_MASK)); 3231 } 3232 } 3233 3234 static void 3235 em_disable_intr(struct adapter *adapter) 3236 { 3237 /* 3238 * The first version of 82542 had an errata where when link was forced 3239 * it would stay up even up even if the cable was disconnected. 3240 * Sequence errors were used to detect the disconnect and then the 3241 * driver would unforce the link. This code in the in the ISR. For 3242 * this to work correctly the Sequence error interrupt had to be 3243 * enabled all the time. 3244 */ 3245 if (adapter->hw.mac_type == em_82542_rev2_0) { 3246 E1000_WRITE_REG(&adapter->hw, IMC, 3247 (0xffffffff & ~E1000_IMC_RXSEQ)); 3248 } else { 3249 E1000_WRITE_REG(&adapter->hw, IMC, 0xffffffff); 3250 } 3251 3252 lwkt_serialize_handler_disable(adapter->interface_data.ac_if.if_serializer); 3253 } 3254 3255 static int 3256 em_is_valid_ether_addr(uint8_t *addr) 3257 { 3258 static const char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3259 3260 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3261 return (FALSE); 3262 else 3263 return (TRUE); 3264 } 3265 3266 void 3267 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3268 { 3269 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2); 3270 } 3271 3272 void 3273 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3274 { 3275 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2); 3276 } 3277 3278 void 3279 em_pci_set_mwi(struct em_hw *hw) 3280 { 3281 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3282 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 3283 } 3284 3285 void 3286 em_pci_clear_mwi(struct em_hw *hw) 3287 { 3288 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3289 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 3290 } 3291 3292 uint32_t 3293 em_io_read(struct em_hw *hw, unsigned long port) 3294 { 3295 struct em_osdep *io = hw->back; 3296 3297 return bus_space_read_4(io->io_bus_space_tag, 3298 io->io_bus_space_handle, port); 3299 } 3300 3301 void 3302 em_io_write(struct em_hw *hw, unsigned long port, uint32_t value) 3303 { 3304 struct em_osdep *io = hw->back; 3305 3306 bus_space_write_4(io->io_bus_space_tag, 3307 io->io_bus_space_handle, port, value); 3308 } 3309 3310 /* 3311 * We may eventually really do this, but its unnecessary 3312 * for now so we just return unsupported. 3313 */ 3314 int32_t 3315 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3316 { 3317 return (0); 3318 } 3319 3320 3321 /********************************************************************* 3322 * 82544 Coexistence issue workaround. 3323 * There are 2 issues. 3324 * 1. Transmit Hang issue. 3325 * To detect this issue, following equation can be used... 3326 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3327 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3328 * 3329 * 2. DAC issue. 3330 * To detect this issue, following equation can be used... 3331 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3332 * If SUM[3:0] is in between 9 to c, we will have this issue. 3333 * 3334 * 3335 * WORKAROUND: 3336 * Make sure we do not have ending address as 1,2,3,4(Hang) or 3337 * 9,a,b,c (DAC) 3338 * 3339 *************************************************************************/ 3340 static uint32_t 3341 em_fill_descriptors(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array) 3342 { 3343 /* Since issue is sensitive to length and address.*/ 3344 /* Let us first check the address...*/ 3345 uint32_t safe_terminator; 3346 if (length <= 4) { 3347 desc_array->descriptor[0].address = address; 3348 desc_array->descriptor[0].length = length; 3349 desc_array->elements = 1; 3350 return (desc_array->elements); 3351 } 3352 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3353 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3354 if (safe_terminator == 0 || 3355 (safe_terminator > 4 && safe_terminator < 9) || 3356 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 3357 desc_array->descriptor[0].address = address; 3358 desc_array->descriptor[0].length = length; 3359 desc_array->elements = 1; 3360 return (desc_array->elements); 3361 } 3362 3363 desc_array->descriptor[0].address = address; 3364 desc_array->descriptor[0].length = length - 4; 3365 desc_array->descriptor[1].address = address + (length - 4); 3366 desc_array->descriptor[1].length = 4; 3367 desc_array->elements = 2; 3368 return (desc_array->elements); 3369 } 3370 3371 /********************************************************************** 3372 * 3373 * Update the board statistics counters. 3374 * 3375 **********************************************************************/ 3376 static void 3377 em_update_stats_counters(struct adapter *adapter) 3378 { 3379 struct ifnet *ifp; 3380 3381 if (adapter->hw.media_type == em_media_type_copper || 3382 (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) { 3383 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, SYMERRS); 3384 adapter->stats.sec += E1000_READ_REG(&adapter->hw, SEC); 3385 } 3386 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, CRCERRS); 3387 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, MPC); 3388 adapter->stats.scc += E1000_READ_REG(&adapter->hw, SCC); 3389 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, ECOL); 3390 3391 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, MCC); 3392 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, LATECOL); 3393 adapter->stats.colc += E1000_READ_REG(&adapter->hw, COLC); 3394 adapter->stats.dc += E1000_READ_REG(&adapter->hw, DC); 3395 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, RLEC); 3396 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, XONRXC); 3397 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, XONTXC); 3398 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, XOFFRXC); 3399 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, XOFFTXC); 3400 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, FCRUC); 3401 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, PRC64); 3402 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, PRC127); 3403 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, PRC255); 3404 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, PRC511); 3405 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, PRC1023); 3406 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, PRC1522); 3407 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, GPRC); 3408 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, BPRC); 3409 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, MPRC); 3410 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, GPTC); 3411 3412 /* For the 64-bit byte counters the low dword must be read first. */ 3413 /* Both registers clear on the read of the high dword */ 3414 3415 adapter->stats.gorcl += E1000_READ_REG(&adapter->hw, GORCL); 3416 adapter->stats.gorch += E1000_READ_REG(&adapter->hw, GORCH); 3417 adapter->stats.gotcl += E1000_READ_REG(&adapter->hw, GOTCL); 3418 adapter->stats.gotch += E1000_READ_REG(&adapter->hw, GOTCH); 3419 3420 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, RNBC); 3421 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, RUC); 3422 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, RFC); 3423 adapter->stats.roc += E1000_READ_REG(&adapter->hw, ROC); 3424 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, RJC); 3425 3426 adapter->stats.torl += E1000_READ_REG(&adapter->hw, TORL); 3427 adapter->stats.torh += E1000_READ_REG(&adapter->hw, TORH); 3428 adapter->stats.totl += E1000_READ_REG(&adapter->hw, TOTL); 3429 adapter->stats.toth += E1000_READ_REG(&adapter->hw, TOTH); 3430 3431 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, TPR); 3432 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, TPT); 3433 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, PTC64); 3434 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, PTC127); 3435 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, PTC255); 3436 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, PTC511); 3437 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, PTC1023); 3438 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, PTC1522); 3439 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, MPTC); 3440 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, BPTC); 3441 3442 if (adapter->hw.mac_type >= em_82543) { 3443 adapter->stats.algnerrc += 3444 E1000_READ_REG(&adapter->hw, ALGNERRC); 3445 adapter->stats.rxerrc += 3446 E1000_READ_REG(&adapter->hw, RXERRC); 3447 adapter->stats.tncrs += 3448 E1000_READ_REG(&adapter->hw, TNCRS); 3449 adapter->stats.cexterr += 3450 E1000_READ_REG(&adapter->hw, CEXTERR); 3451 adapter->stats.tsctc += 3452 E1000_READ_REG(&adapter->hw, TSCTC); 3453 adapter->stats.tsctfc += 3454 E1000_READ_REG(&adapter->hw, TSCTFC); 3455 } 3456 ifp = &adapter->interface_data.ac_if; 3457 3458 /* Fill out the OS statistics structure */ 3459 ifp->if_collisions = adapter->stats.colc; 3460 3461 /* Rx Errors */ 3462 ifp->if_ierrors = 3463 adapter->dropped_pkts + 3464 adapter->stats.rxerrc + 3465 adapter->stats.crcerrs + 3466 adapter->stats.algnerrc + 3467 adapter->stats.ruc + adapter->stats.roc + 3468 adapter->stats.mpc + adapter->stats.cexterr + 3469 adapter->rx_overruns; 3470 3471 /* Tx Errors */ 3472 ifp->if_oerrors = adapter->stats.ecol + adapter->stats.latecol + 3473 adapter->watchdog_timeouts; 3474 } 3475 3476 3477 /********************************************************************** 3478 * 3479 * This routine is called only when em_display_debug_stats is enabled. 3480 * This routine provides a way to take a look at important statistics 3481 * maintained by the driver and hardware. 3482 * 3483 **********************************************************************/ 3484 static void 3485 em_print_debug_info(struct adapter *adapter) 3486 { 3487 device_t dev= adapter->dev; 3488 uint8_t *hw_addr = adapter->hw.hw_addr; 3489 3490 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3491 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x\n", 3492 E1000_READ_REG(&adapter->hw, CTRL), 3493 E1000_READ_REG(&adapter->hw, RCTL)); 3494 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk\n", 3495 ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff0000) >> 16), 3496 (E1000_READ_REG(&adapter->hw, PBA) & 0xffff)); 3497 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3498 adapter->hw.fc_high_water, adapter->hw.fc_low_water); 3499 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3500 E1000_READ_REG(&adapter->hw, TIDV), 3501 E1000_READ_REG(&adapter->hw, TADV)); 3502 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3503 E1000_READ_REG(&adapter->hw, RDTR), 3504 E1000_READ_REG(&adapter->hw, RADV)); 3505 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3506 (long long)adapter->tx_fifo_wrk_cnt, 3507 (long long)adapter->tx_fifo_reset_cnt); 3508 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3509 E1000_READ_REG(&adapter->hw, TDH), 3510 E1000_READ_REG(&adapter->hw, TDT)); 3511 device_printf(dev, "Num Tx descriptors avail = %d\n", 3512 adapter->num_tx_desc_avail); 3513 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3514 adapter->no_tx_desc_avail1); 3515 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3516 adapter->no_tx_desc_avail2); 3517 device_printf(dev, "Std mbuf failed = %ld\n", 3518 adapter->mbuf_alloc_failed); 3519 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3520 adapter->mbuf_cluster_failed); 3521 device_printf(dev, "Driver dropped packets = %ld\n", 3522 adapter->dropped_pkts); 3523 } 3524 3525 static void 3526 em_print_hw_stats(struct adapter *adapter) 3527 { 3528 device_t dev= adapter->dev; 3529 3530 device_printf(dev, "Excessive collisions = %lld\n", 3531 (long long)adapter->stats.ecol); 3532 device_printf(dev, "Symbol errors = %lld\n", 3533 (long long)adapter->stats.symerrs); 3534 device_printf(dev, "Sequence errors = %lld\n", 3535 (long long)adapter->stats.sec); 3536 device_printf(dev, "Defer count = %lld\n", 3537 (long long)adapter->stats.dc); 3538 3539 device_printf(dev, "Missed Packets = %lld\n", 3540 (long long)adapter->stats.mpc); 3541 device_printf(dev, "Receive No Buffers = %lld\n", 3542 (long long)adapter->stats.rnbc); 3543 /* RLEC is inaccurate on some hardware, calculate our own. */ 3544 device_printf(dev, "Receive Length errors = %lld\n", 3545 (long long)adapter->stats.roc + 3546 (long long)adapter->stats.ruc); 3547 device_printf(dev, "Receive errors = %lld\n", 3548 (long long)adapter->stats.rxerrc); 3549 device_printf(dev, "Crc errors = %lld\n", 3550 (long long)adapter->stats.crcerrs); 3551 device_printf(dev, "Alignment errors = %lld\n", 3552 (long long)adapter->stats.algnerrc); 3553 device_printf(dev, "Carrier extension errors = %lld\n", 3554 (long long)adapter->stats.cexterr); 3555 device_printf(dev, "RX overruns = %lu\n", adapter->rx_overruns); 3556 device_printf(dev, "Watchdog timeouts = %lu\n", 3557 adapter->watchdog_timeouts); 3558 3559 device_printf(dev, "XON Rcvd = %lld\n", 3560 (long long)adapter->stats.xonrxc); 3561 device_printf(dev, "XON Xmtd = %lld\n", 3562 (long long)adapter->stats.xontxc); 3563 device_printf(dev, "XOFF Rcvd = %lld\n", 3564 (long long)adapter->stats.xoffrxc); 3565 device_printf(dev, "XOFF Xmtd = %lld\n", 3566 (long long)adapter->stats.xofftxc); 3567 3568 device_printf(dev, "Good Packets Rcvd = %lld\n", 3569 (long long)adapter->stats.gprc); 3570 device_printf(dev, "Good Packets Xmtd = %lld\n", 3571 (long long)adapter->stats.gptc); 3572 } 3573 3574 static int 3575 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3576 { 3577 int error; 3578 int result; 3579 struct adapter *adapter; 3580 3581 result = -1; 3582 error = sysctl_handle_int(oidp, &result, 0, req); 3583 3584 if (error || !req->newptr) 3585 return (error); 3586 3587 if (result == 1) { 3588 adapter = (struct adapter *)arg1; 3589 em_print_debug_info(adapter); 3590 } 3591 3592 return (error); 3593 } 3594 3595 static int 3596 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3597 { 3598 int error; 3599 int result; 3600 struct adapter *adapter; 3601 3602 result = -1; 3603 error = sysctl_handle_int(oidp, &result, 0, req); 3604 3605 if (error || !req->newptr) 3606 return (error); 3607 3608 if (result == 1) { 3609 adapter = (struct adapter *)arg1; 3610 em_print_hw_stats(adapter); 3611 } 3612 3613 return (error); 3614 } 3615 3616 static int 3617 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3618 { 3619 struct em_int_delay_info *info; 3620 struct adapter *adapter; 3621 uint32_t regval; 3622 int error; 3623 int usecs; 3624 int ticks; 3625 3626 info = (struct em_int_delay_info *)arg1; 3627 adapter = info->adapter; 3628 usecs = info->value; 3629 error = sysctl_handle_int(oidp, &usecs, 0, req); 3630 if (error != 0 || req->newptr == NULL) 3631 return (error); 3632 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535)) 3633 return (EINVAL); 3634 info->value = usecs; 3635 ticks = E1000_USECS_TO_TICKS(usecs); 3636 3637 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer); 3638 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 3639 regval = (regval & ~0xffff) | (ticks & 0xffff); 3640 /* Handle a few special cases. */ 3641 switch (info->offset) { 3642 case E1000_RDTR: 3643 case E1000_82542_RDTR: 3644 regval |= E1000_RDT_FPDB; 3645 break; 3646 case E1000_TIDV: 3647 case E1000_82542_TIDV: 3648 if (ticks == 0) { 3649 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 3650 /* Don't write 0 into the TIDV register. */ 3651 regval++; 3652 } else 3653 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3654 break; 3655 } 3656 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 3657 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer); 3658 return (0); 3659 } 3660 3661 static void 3662 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 3663 const char *description, struct em_int_delay_info *info, 3664 int offset, int value) 3665 { 3666 info->adapter = adapter; 3667 info->offset = offset; 3668 info->value = value; 3669 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 3670 SYSCTL_CHILDREN(adapter->sysctl_tree), 3671 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 3672 info, 0, em_sysctl_int_delay, "I", description); 3673 } 3674 3675 static int 3676 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 3677 { 3678 struct adapter *adapter = (void *)arg1; 3679 int error; 3680 int throttle; 3681 3682 throttle = em_int_throttle_ceil; 3683 error = sysctl_handle_int(oidp, &throttle, 0, req); 3684 if (error || req->newptr == NULL) 3685 return error; 3686 if (throttle < 0 || throttle > 1000000000 / 256) 3687 return EINVAL; 3688 if (throttle) { 3689 /* 3690 * Set the interrupt throttling rate in 256ns increments, 3691 * recalculate sysctl value assignment to get exact frequency. 3692 */ 3693 throttle = 1000000000 / 256 / throttle; 3694 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer); 3695 em_int_throttle_ceil = 1000000000 / 256 / throttle; 3696 E1000_WRITE_REG(&adapter->hw, ITR, throttle); 3697 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer); 3698 } else { 3699 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer); 3700 em_int_throttle_ceil = 0; 3701 E1000_WRITE_REG(&adapter->hw, ITR, 0); 3702 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer); 3703 } 3704 device_printf(adapter->dev, "Interrupt moderation set to %d/sec\n", 3705 em_int_throttle_ceil); 3706 return 0; 3707 } 3708