1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 */ 67 /* 68 * SERIALIZATION API RULES: 69 * 70 * - If the driver uses the same serializer for the interrupt as for the 71 * ifnet, most of the serialization will be done automatically for the 72 * driver. 73 * 74 * - ifmedia entry points will be serialized by the ifmedia code using the 75 * ifnet serializer. 76 * 77 * - if_* entry points except for if_input will be serialized by the IF 78 * and protocol layers. 79 * 80 * - The device driver must be sure to serialize access from timeout code 81 * installed by the device driver. 82 * 83 * - The device driver typically holds the serializer at the time it wishes 84 * to call if_input. 85 * 86 * - We must call lwkt_serialize_handler_enable() prior to enabling the 87 * hardware interrupt and lwkt_serialize_handler_disable() after disabling 88 * the hardware interrupt in order to avoid handler execution races from 89 * scheduled interrupt threads. 90 * 91 * NOTE! Since callers into the device driver hold the ifnet serializer, 92 * the device driver may be holding a serializer at the time it calls 93 * if_input even if it is not serializer-aware. 94 */ 95 96 /* 97 * NOTE: 98 * 99 * MSI-X MUST NOT be enabled on 82574: 100 * <<82574 specification update>> errata #15 101 */ 102 103 #include "opt_polling.h" 104 105 #include <sys/param.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/interrupt.h> 109 #include <sys/kernel.h> 110 #include <sys/ktr.h> 111 #include <sys/malloc.h> 112 #include <sys/mbuf.h> 113 #include <sys/proc.h> 114 #include <sys/rman.h> 115 #include <sys/serialize.h> 116 #include <sys/socket.h> 117 #include <sys/sockio.h> 118 #include <sys/sysctl.h> 119 #include <sys/systm.h> 120 121 #include <net/bpf.h> 122 #include <net/ethernet.h> 123 #include <net/if.h> 124 #include <net/if_arp.h> 125 #include <net/if_dl.h> 126 #include <net/if_media.h> 127 #include <net/ifq_var.h> 128 #include <net/vlan/if_vlan_var.h> 129 #include <net/vlan/if_vlan_ether.h> 130 131 #include <netinet/in_systm.h> 132 #include <netinet/in.h> 133 #include <netinet/ip.h> 134 #include <netinet/tcp.h> 135 #include <netinet/udp.h> 136 137 #include <bus/pci/pcivar.h> 138 #include <bus/pci/pcireg.h> 139 140 #include <dev/netif/ig_hal/e1000_api.h> 141 #include <dev/netif/ig_hal/e1000_82571.h> 142 #include <dev/netif/em/if_em.h> 143 144 #define EM_NAME "Intel(R) PRO/1000 Network Connection " 145 #define EM_VER " 7.2.4" 146 147 #define _EM_DEVICE(id, ret) \ 148 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER } 149 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100) 150 #define EM_DEVICE(id) _EM_DEVICE(id, 0) 151 #define EM_DEVICE_NULL { 0, 0, 0, NULL } 152 153 static const struct em_vendor_info em_vendor_info_array[] = { 154 EM_DEVICE(82540EM), 155 EM_DEVICE(82540EM_LOM), 156 EM_DEVICE(82540EP), 157 EM_DEVICE(82540EP_LOM), 158 EM_DEVICE(82540EP_LP), 159 160 EM_DEVICE(82541EI), 161 EM_DEVICE(82541ER), 162 EM_DEVICE(82541ER_LOM), 163 EM_DEVICE(82541EI_MOBILE), 164 EM_DEVICE(82541GI), 165 EM_DEVICE(82541GI_LF), 166 EM_DEVICE(82541GI_MOBILE), 167 168 EM_DEVICE(82542), 169 170 EM_DEVICE(82543GC_FIBER), 171 EM_DEVICE(82543GC_COPPER), 172 173 EM_DEVICE(82544EI_COPPER), 174 EM_DEVICE(82544EI_FIBER), 175 EM_DEVICE(82544GC_COPPER), 176 EM_DEVICE(82544GC_LOM), 177 178 EM_DEVICE(82545EM_COPPER), 179 EM_DEVICE(82545EM_FIBER), 180 EM_DEVICE(82545GM_COPPER), 181 EM_DEVICE(82545GM_FIBER), 182 EM_DEVICE(82545GM_SERDES), 183 184 EM_DEVICE(82546EB_COPPER), 185 EM_DEVICE(82546EB_FIBER), 186 EM_DEVICE(82546EB_QUAD_COPPER), 187 EM_DEVICE(82546GB_COPPER), 188 EM_DEVICE(82546GB_FIBER), 189 EM_DEVICE(82546GB_SERDES), 190 EM_DEVICE(82546GB_PCIE), 191 EM_DEVICE(82546GB_QUAD_COPPER), 192 EM_DEVICE(82546GB_QUAD_COPPER_KSP3), 193 194 EM_DEVICE(82547EI), 195 EM_DEVICE(82547EI_MOBILE), 196 EM_DEVICE(82547GI), 197 198 EM_EMX_DEVICE(82571EB_COPPER), 199 EM_EMX_DEVICE(82571EB_FIBER), 200 EM_EMX_DEVICE(82571EB_SERDES), 201 EM_EMX_DEVICE(82571EB_SERDES_DUAL), 202 EM_EMX_DEVICE(82571EB_SERDES_QUAD), 203 EM_EMX_DEVICE(82571EB_QUAD_COPPER), 204 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP), 205 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP), 206 EM_EMX_DEVICE(82571EB_QUAD_FIBER), 207 EM_EMX_DEVICE(82571PT_QUAD_COPPER), 208 209 EM_EMX_DEVICE(82572EI_COPPER), 210 EM_EMX_DEVICE(82572EI_FIBER), 211 EM_EMX_DEVICE(82572EI_SERDES), 212 EM_EMX_DEVICE(82572EI), 213 214 EM_EMX_DEVICE(82573E), 215 EM_EMX_DEVICE(82573E_IAMT), 216 EM_EMX_DEVICE(82573L), 217 218 EM_DEVICE(82583V), 219 220 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT), 221 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT), 222 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT), 223 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT), 224 225 EM_DEVICE(ICH8_IGP_M_AMT), 226 EM_DEVICE(ICH8_IGP_AMT), 227 EM_DEVICE(ICH8_IGP_C), 228 EM_DEVICE(ICH8_IFE), 229 EM_DEVICE(ICH8_IFE_GT), 230 EM_DEVICE(ICH8_IFE_G), 231 EM_DEVICE(ICH8_IGP_M), 232 EM_DEVICE(ICH8_82567V_3), 233 234 EM_DEVICE(ICH9_IGP_M_AMT), 235 EM_DEVICE(ICH9_IGP_AMT), 236 EM_DEVICE(ICH9_IGP_C), 237 EM_DEVICE(ICH9_IGP_M), 238 EM_DEVICE(ICH9_IGP_M_V), 239 EM_DEVICE(ICH9_IFE), 240 EM_DEVICE(ICH9_IFE_GT), 241 EM_DEVICE(ICH9_IFE_G), 242 EM_DEVICE(ICH9_BM), 243 244 EM_EMX_DEVICE(82574L), 245 EM_EMX_DEVICE(82574LA), 246 247 EM_DEVICE(ICH10_R_BM_LM), 248 EM_DEVICE(ICH10_R_BM_LF), 249 EM_DEVICE(ICH10_R_BM_V), 250 EM_DEVICE(ICH10_D_BM_LM), 251 EM_DEVICE(ICH10_D_BM_LF), 252 EM_DEVICE(ICH10_D_BM_V), 253 254 EM_DEVICE(PCH_M_HV_LM), 255 EM_DEVICE(PCH_M_HV_LC), 256 EM_DEVICE(PCH_D_HV_DM), 257 EM_DEVICE(PCH_D_HV_DC), 258 259 EM_DEVICE(PCH2_LV_LM), 260 EM_DEVICE(PCH2_LV_V), 261 262 /* required last entry */ 263 EM_DEVICE_NULL 264 }; 265 266 static int em_probe(device_t); 267 static int em_attach(device_t); 268 static int em_detach(device_t); 269 static int em_shutdown(device_t); 270 static int em_suspend(device_t); 271 static int em_resume(device_t); 272 273 static void em_init(void *); 274 static void em_stop(struct adapter *); 275 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 276 static void em_start(struct ifnet *); 277 #ifdef DEVICE_POLLING 278 static void em_poll(struct ifnet *, enum poll_cmd, int); 279 #endif 280 static void em_watchdog(struct ifnet *); 281 static void em_media_status(struct ifnet *, struct ifmediareq *); 282 static int em_media_change(struct ifnet *); 283 static void em_timer(void *); 284 285 static void em_intr(void *); 286 static void em_rxeof(struct adapter *, int); 287 static void em_txeof(struct adapter *); 288 static void em_tx_collect(struct adapter *); 289 static void em_tx_purge(struct adapter *); 290 static void em_enable_intr(struct adapter *); 291 static void em_disable_intr(struct adapter *); 292 293 static int em_dma_malloc(struct adapter *, bus_size_t, 294 struct em_dma_alloc *); 295 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 296 static void em_init_tx_ring(struct adapter *); 297 static int em_init_rx_ring(struct adapter *); 298 static int em_create_tx_ring(struct adapter *); 299 static int em_create_rx_ring(struct adapter *); 300 static void em_destroy_tx_ring(struct adapter *, int); 301 static void em_destroy_rx_ring(struct adapter *, int); 302 static int em_newbuf(struct adapter *, int, int); 303 static int em_encap(struct adapter *, struct mbuf **); 304 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *, 305 struct mbuf *); 306 static int em_txcsum_pullup(struct adapter *, struct mbuf **); 307 static int em_txcsum(struct adapter *, struct mbuf *, 308 uint32_t *, uint32_t *); 309 310 static int em_get_hw_info(struct adapter *); 311 static int em_is_valid_eaddr(const uint8_t *); 312 static int em_alloc_pci_res(struct adapter *); 313 static void em_free_pci_res(struct adapter *); 314 static int em_reset(struct adapter *); 315 static void em_setup_ifp(struct adapter *); 316 static void em_init_tx_unit(struct adapter *); 317 static void em_init_rx_unit(struct adapter *); 318 static void em_update_stats(struct adapter *); 319 static void em_set_promisc(struct adapter *); 320 static void em_disable_promisc(struct adapter *); 321 static void em_set_multi(struct adapter *); 322 static void em_update_link_status(struct adapter *); 323 static void em_smartspeed(struct adapter *); 324 static void em_set_itr(struct adapter *, uint32_t); 325 static void em_disable_aspm(struct adapter *); 326 327 /* Hardware workarounds */ 328 static int em_82547_fifo_workaround(struct adapter *, int); 329 static void em_82547_update_fifo_head(struct adapter *, int); 330 static int em_82547_tx_fifo_reset(struct adapter *); 331 static void em_82547_move_tail(void *); 332 static void em_82547_move_tail_serialized(struct adapter *); 333 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY); 334 335 static void em_print_debug_info(struct adapter *); 336 static void em_print_nvm_info(struct adapter *); 337 static void em_print_hw_stats(struct adapter *); 338 339 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 340 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 341 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 342 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 343 static void em_add_sysctl(struct adapter *adapter); 344 345 /* Management and WOL Support */ 346 static void em_get_mgmt(struct adapter *); 347 static void em_rel_mgmt(struct adapter *); 348 static void em_get_hw_control(struct adapter *); 349 static void em_rel_hw_control(struct adapter *); 350 static void em_enable_wol(device_t); 351 352 static device_method_t em_methods[] = { 353 /* Device interface */ 354 DEVMETHOD(device_probe, em_probe), 355 DEVMETHOD(device_attach, em_attach), 356 DEVMETHOD(device_detach, em_detach), 357 DEVMETHOD(device_shutdown, em_shutdown), 358 DEVMETHOD(device_suspend, em_suspend), 359 DEVMETHOD(device_resume, em_resume), 360 { 0, 0 } 361 }; 362 363 static driver_t em_driver = { 364 "em", 365 em_methods, 366 sizeof(struct adapter), 367 }; 368 369 static devclass_t em_devclass; 370 371 DECLARE_DUMMY_MODULE(if_em); 372 MODULE_DEPEND(em, ig_hal, 1, 1, 1); 373 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL); 374 375 /* 376 * Tunables 377 */ 378 static int em_int_throttle_ceil = EM_DEFAULT_ITR; 379 static int em_rxd = EM_DEFAULT_RXD; 380 static int em_txd = EM_DEFAULT_TXD; 381 static int em_smart_pwr_down = 0; 382 383 /* Controls whether promiscuous also shows bad packets */ 384 static int em_debug_sbp = FALSE; 385 386 static int em_82573_workaround = 1; 387 static int em_msi_enable = 1; 388 389 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil); 390 TUNABLE_INT("hw.em.rxd", &em_rxd); 391 TUNABLE_INT("hw.em.txd", &em_txd); 392 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 393 TUNABLE_INT("hw.em.sbp", &em_debug_sbp); 394 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround); 395 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable); 396 397 /* Global used in WOL setup with multiport cards */ 398 static int em_global_quad_port_a = 0; 399 400 /* Set this to one to display debug statistics */ 401 static int em_display_debug_stats = 0; 402 403 #if !defined(KTR_IF_EM) 404 #define KTR_IF_EM KTR_ALL 405 #endif 406 KTR_INFO_MASTER(if_em); 407 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin"); 408 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end"); 409 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet"); 410 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet"); 411 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean"); 412 #define logif(name) KTR_LOG(if_em_ ## name) 413 414 static int 415 em_probe(device_t dev) 416 { 417 const struct em_vendor_info *ent; 418 uint16_t vid, did; 419 420 vid = pci_get_vendor(dev); 421 did = pci_get_device(dev); 422 423 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) { 424 if (vid == ent->vendor_id && did == ent->device_id) { 425 device_set_desc(dev, ent->desc); 426 device_set_async_attach(dev, TRUE); 427 return (ent->ret); 428 } 429 } 430 return (ENXIO); 431 } 432 433 static int 434 em_attach(device_t dev) 435 { 436 struct adapter *adapter = device_get_softc(dev); 437 struct ifnet *ifp = &adapter->arpcom.ac_if; 438 int tsize, rsize; 439 int error = 0; 440 uint16_t eeprom_data, device_id, apme_mask; 441 442 adapter->dev = adapter->osdep.dev = dev; 443 444 callout_init_mp(&adapter->timer); 445 callout_init_mp(&adapter->tx_fifo_timer); 446 447 /* Determine hardware and mac info */ 448 error = em_get_hw_info(adapter); 449 if (error) { 450 device_printf(dev, "Identify hardware failed\n"); 451 goto fail; 452 } 453 454 /* Setup PCI resources */ 455 error = em_alloc_pci_res(adapter); 456 if (error) { 457 device_printf(dev, "Allocation of PCI resources failed\n"); 458 goto fail; 459 } 460 461 /* 462 * For ICH8 and family we need to map the flash memory, 463 * and this must happen after the MAC is identified. 464 */ 465 if (adapter->hw.mac.type == e1000_ich8lan || 466 adapter->hw.mac.type == e1000_ich9lan || 467 adapter->hw.mac.type == e1000_ich10lan || 468 adapter->hw.mac.type == e1000_pchlan || 469 adapter->hw.mac.type == e1000_pch2lan) { 470 adapter->flash_rid = EM_BAR_FLASH; 471 472 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 473 &adapter->flash_rid, RF_ACTIVE); 474 if (adapter->flash == NULL) { 475 device_printf(dev, "Mapping of Flash failed\n"); 476 error = ENXIO; 477 goto fail; 478 } 479 adapter->osdep.flash_bus_space_tag = 480 rman_get_bustag(adapter->flash); 481 adapter->osdep.flash_bus_space_handle = 482 rman_get_bushandle(adapter->flash); 483 484 /* 485 * This is used in the shared code 486 * XXX this goof is actually not used. 487 */ 488 adapter->hw.flash_address = (uint8_t *)adapter->flash; 489 } 490 491 /* Do Shared Code initialization */ 492 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 493 device_printf(dev, "Setup of Shared code failed\n"); 494 error = ENXIO; 495 goto fail; 496 } 497 498 e1000_get_bus_info(&adapter->hw); 499 500 /* 501 * Validate number of transmit and receive descriptors. It 502 * must not exceed hardware maximum, and must be multiple 503 * of E1000_DBA_ALIGN. 504 */ 505 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 || 506 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 507 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 508 em_txd < EM_MIN_TXD) { 509 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 510 EM_DEFAULT_TXD, em_txd); 511 adapter->num_tx_desc = EM_DEFAULT_TXD; 512 } else { 513 adapter->num_tx_desc = em_txd; 514 } 515 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 || 516 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 517 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 518 em_rxd < EM_MIN_RXD) { 519 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 520 EM_DEFAULT_RXD, em_rxd); 521 adapter->num_rx_desc = EM_DEFAULT_RXD; 522 } else { 523 adapter->num_rx_desc = em_rxd; 524 } 525 526 adapter->hw.mac.autoneg = DO_AUTO_NEG; 527 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 528 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 529 adapter->rx_buffer_len = MCLBYTES; 530 531 /* 532 * Interrupt throttle rate 533 */ 534 if (em_int_throttle_ceil == 0) { 535 adapter->int_throttle_ceil = 0; 536 } else { 537 int throttle = em_int_throttle_ceil; 538 539 if (throttle < 0) 540 throttle = EM_DEFAULT_ITR; 541 542 /* Recalculate the tunable value to get the exact frequency. */ 543 throttle = 1000000000 / 256 / throttle; 544 545 /* Upper 16bits of ITR is reserved and should be zero */ 546 if (throttle & 0xffff0000) 547 throttle = 1000000000 / 256 / EM_DEFAULT_ITR; 548 549 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 550 } 551 552 e1000_init_script_state_82541(&adapter->hw, TRUE); 553 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 554 555 /* Copper options */ 556 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 557 adapter->hw.phy.mdix = AUTO_ALL_MODES; 558 adapter->hw.phy.disable_polarity_correction = FALSE; 559 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 560 } 561 562 /* Set the frame limits assuming standard ethernet sized frames. */ 563 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 564 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN; 565 566 /* This controls when hardware reports transmit completion status. */ 567 adapter->hw.mac.report_tx_early = 1; 568 569 /* 570 * Create top level busdma tag 571 */ 572 error = bus_dma_tag_create(NULL, 1, 0, 573 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 574 NULL, NULL, 575 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 576 0, &adapter->parent_dtag); 577 if (error) { 578 device_printf(dev, "could not create top level DMA tag\n"); 579 goto fail; 580 } 581 582 /* 583 * Allocate Transmit Descriptor ring 584 */ 585 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 586 EM_DBA_ALIGN); 587 error = em_dma_malloc(adapter, tsize, &adapter->txdma); 588 if (error) { 589 device_printf(dev, "Unable to allocate tx_desc memory\n"); 590 goto fail; 591 } 592 adapter->tx_desc_base = adapter->txdma.dma_vaddr; 593 594 /* 595 * Allocate Receive Descriptor ring 596 */ 597 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 598 EM_DBA_ALIGN); 599 error = em_dma_malloc(adapter, rsize, &adapter->rxdma); 600 if (error) { 601 device_printf(dev, "Unable to allocate rx_desc memory\n"); 602 goto fail; 603 } 604 adapter->rx_desc_base = adapter->rxdma.dma_vaddr; 605 606 /* Allocate multicast array memory. */ 607 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES, 608 M_DEVBUF, M_WAITOK); 609 610 /* Indicate SOL/IDER usage */ 611 if (e1000_check_reset_block(&adapter->hw)) { 612 device_printf(dev, 613 "PHY reset is blocked due to SOL/IDER session.\n"); 614 } 615 616 /* 617 * Start from a known state, this is important in reading the 618 * nvm and mac from that. 619 */ 620 e1000_reset_hw(&adapter->hw); 621 622 /* Make sure we have a good EEPROM before we read from it */ 623 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 624 /* 625 * Some PCI-E parts fail the first check due to 626 * the link being in sleep state, call it again, 627 * if it fails a second time its a real issue. 628 */ 629 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 630 device_printf(dev, 631 "The EEPROM Checksum Is Not Valid\n"); 632 error = EIO; 633 goto fail; 634 } 635 } 636 637 /* Copy the permanent MAC address out of the EEPROM */ 638 if (e1000_read_mac_addr(&adapter->hw) < 0) { 639 device_printf(dev, "EEPROM read error while reading MAC" 640 " address\n"); 641 error = EIO; 642 goto fail; 643 } 644 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) { 645 device_printf(dev, "Invalid MAC address\n"); 646 error = EIO; 647 goto fail; 648 } 649 650 /* Allocate transmit descriptors and buffers */ 651 error = em_create_tx_ring(adapter); 652 if (error) { 653 device_printf(dev, "Could not setup transmit structures\n"); 654 goto fail; 655 } 656 657 /* Allocate receive descriptors and buffers */ 658 error = em_create_rx_ring(adapter); 659 if (error) { 660 device_printf(dev, "Could not setup receive structures\n"); 661 goto fail; 662 } 663 664 /* Manually turn off all interrupts */ 665 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 666 667 /* Determine if we have to control management hardware */ 668 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 669 670 /* 671 * Setup Wake-on-Lan 672 */ 673 apme_mask = EM_EEPROM_APME; 674 eeprom_data = 0; 675 switch (adapter->hw.mac.type) { 676 case e1000_82542: 677 case e1000_82543: 678 break; 679 680 case e1000_82573: 681 case e1000_82583: 682 adapter->has_amt = 1; 683 /* FALL THROUGH */ 684 685 case e1000_82546: 686 case e1000_82546_rev_3: 687 case e1000_82571: 688 case e1000_82572: 689 case e1000_80003es2lan: 690 if (adapter->hw.bus.func == 1) { 691 e1000_read_nvm(&adapter->hw, 692 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 693 } else { 694 e1000_read_nvm(&adapter->hw, 695 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 696 } 697 break; 698 699 case e1000_ich8lan: 700 case e1000_ich9lan: 701 case e1000_ich10lan: 702 case e1000_pchlan: 703 case e1000_pch2lan: 704 apme_mask = E1000_WUC_APME; 705 adapter->has_amt = TRUE; 706 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 707 break; 708 709 default: 710 e1000_read_nvm(&adapter->hw, 711 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 712 break; 713 } 714 if (eeprom_data & apme_mask) 715 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 716 717 /* 718 * We have the eeprom settings, now apply the special cases 719 * where the eeprom may be wrong or the board won't support 720 * wake on lan on a particular port 721 */ 722 device_id = pci_get_device(dev); 723 switch (device_id) { 724 case E1000_DEV_ID_82546GB_PCIE: 725 adapter->wol = 0; 726 break; 727 728 case E1000_DEV_ID_82546EB_FIBER: 729 case E1000_DEV_ID_82546GB_FIBER: 730 case E1000_DEV_ID_82571EB_FIBER: 731 /* 732 * Wake events only supported on port A for dual fiber 733 * regardless of eeprom setting 734 */ 735 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 736 E1000_STATUS_FUNC_1) 737 adapter->wol = 0; 738 break; 739 740 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 741 case E1000_DEV_ID_82571EB_QUAD_COPPER: 742 case E1000_DEV_ID_82571EB_QUAD_FIBER: 743 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 744 /* if quad port adapter, disable WoL on all but port A */ 745 if (em_global_quad_port_a != 0) 746 adapter->wol = 0; 747 /* Reset for multiple quad port adapters */ 748 if (++em_global_quad_port_a == 4) 749 em_global_quad_port_a = 0; 750 break; 751 } 752 753 /* XXX disable wol */ 754 adapter->wol = 0; 755 756 /* Setup OS specific network interface */ 757 em_setup_ifp(adapter); 758 759 /* Add sysctl tree, must after em_setup_ifp() */ 760 em_add_sysctl(adapter); 761 762 /* Reset the hardware */ 763 error = em_reset(adapter); 764 if (error) { 765 device_printf(dev, "Unable to reset the hardware\n"); 766 goto fail; 767 } 768 769 /* Initialize statistics */ 770 em_update_stats(adapter); 771 772 adapter->hw.mac.get_link_status = 1; 773 em_update_link_status(adapter); 774 775 /* Do we need workaround for 82544 PCI-X adapter? */ 776 if (adapter->hw.bus.type == e1000_bus_type_pcix && 777 adapter->hw.mac.type == e1000_82544) 778 adapter->pcix_82544 = TRUE; 779 else 780 adapter->pcix_82544 = FALSE; 781 782 if (adapter->pcix_82544) { 783 /* 784 * 82544 on PCI-X may split one TX segment 785 * into two TX descs, so we double its number 786 * of spare TX desc here. 787 */ 788 adapter->spare_tx_desc = 2 * EM_TX_SPARE; 789 } else { 790 adapter->spare_tx_desc = EM_TX_SPARE; 791 } 792 793 /* 794 * Keep following relationship between spare_tx_desc, oact_tx_desc 795 * and tx_int_nsegs: 796 * (spare_tx_desc + EM_TX_RESERVED) <= 797 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs 798 */ 799 adapter->oact_tx_desc = adapter->num_tx_desc / 8; 800 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX) 801 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX; 802 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED) 803 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED; 804 805 adapter->tx_int_nsegs = adapter->num_tx_desc / 16; 806 if (adapter->tx_int_nsegs < adapter->oact_tx_desc) 807 adapter->tx_int_nsegs = adapter->oact_tx_desc; 808 809 /* Non-AMT based hardware can now take control from firmware */ 810 if (adapter->has_manage && !adapter->has_amt && 811 adapter->hw.mac.type >= e1000_82571) 812 em_get_hw_control(adapter); 813 814 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE, 815 em_intr, adapter, &adapter->intr_tag, 816 ifp->if_serializer); 817 if (error) { 818 device_printf(dev, "Failed to register interrupt handler"); 819 ether_ifdetach(&adapter->arpcom.ac_if); 820 goto fail; 821 } 822 823 ifp->if_cpuid = rman_get_cpuid(adapter->intr_res); 824 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 825 return (0); 826 fail: 827 em_detach(dev); 828 return (error); 829 } 830 831 static int 832 em_detach(device_t dev) 833 { 834 struct adapter *adapter = device_get_softc(dev); 835 836 if (device_is_attached(dev)) { 837 struct ifnet *ifp = &adapter->arpcom.ac_if; 838 839 lwkt_serialize_enter(ifp->if_serializer); 840 841 em_stop(adapter); 842 843 e1000_phy_hw_reset(&adapter->hw); 844 845 em_rel_mgmt(adapter); 846 em_rel_hw_control(adapter); 847 848 if (adapter->wol) { 849 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 850 E1000_WUC_PME_EN); 851 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 852 em_enable_wol(dev); 853 } 854 855 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag); 856 857 lwkt_serialize_exit(ifp->if_serializer); 858 859 ether_ifdetach(ifp); 860 } else { 861 em_rel_hw_control(adapter); 862 } 863 bus_generic_detach(dev); 864 865 em_free_pci_res(adapter); 866 867 em_destroy_tx_ring(adapter, adapter->num_tx_desc); 868 em_destroy_rx_ring(adapter, adapter->num_rx_desc); 869 870 /* Free Transmit Descriptor ring */ 871 if (adapter->tx_desc_base) 872 em_dma_free(adapter, &adapter->txdma); 873 874 /* Free Receive Descriptor ring */ 875 if (adapter->rx_desc_base) 876 em_dma_free(adapter, &adapter->rxdma); 877 878 /* Free top level busdma tag */ 879 if (adapter->parent_dtag != NULL) 880 bus_dma_tag_destroy(adapter->parent_dtag); 881 882 /* Free sysctl tree */ 883 if (adapter->sysctl_tree != NULL) 884 sysctl_ctx_free(&adapter->sysctl_ctx); 885 886 return (0); 887 } 888 889 static int 890 em_shutdown(device_t dev) 891 { 892 return em_suspend(dev); 893 } 894 895 static int 896 em_suspend(device_t dev) 897 { 898 struct adapter *adapter = device_get_softc(dev); 899 struct ifnet *ifp = &adapter->arpcom.ac_if; 900 901 lwkt_serialize_enter(ifp->if_serializer); 902 903 em_stop(adapter); 904 905 em_rel_mgmt(adapter); 906 em_rel_hw_control(adapter); 907 908 if (adapter->wol) { 909 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 910 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 911 em_enable_wol(dev); 912 } 913 914 lwkt_serialize_exit(ifp->if_serializer); 915 916 return bus_generic_suspend(dev); 917 } 918 919 static int 920 em_resume(device_t dev) 921 { 922 struct adapter *adapter = device_get_softc(dev); 923 struct ifnet *ifp = &adapter->arpcom.ac_if; 924 925 lwkt_serialize_enter(ifp->if_serializer); 926 927 em_init(adapter); 928 em_get_mgmt(adapter); 929 if_devstart(ifp); 930 931 lwkt_serialize_exit(ifp->if_serializer); 932 933 return bus_generic_resume(dev); 934 } 935 936 static void 937 em_start(struct ifnet *ifp) 938 { 939 struct adapter *adapter = ifp->if_softc; 940 struct mbuf *m_head; 941 942 ASSERT_SERIALIZED(ifp->if_serializer); 943 944 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 945 return; 946 947 if (!adapter->link_active) { 948 ifq_purge(&ifp->if_snd); 949 return; 950 } 951 952 while (!ifq_is_empty(&ifp->if_snd)) { 953 /* Now do we at least have a minimal? */ 954 if (EM_IS_OACTIVE(adapter)) { 955 em_tx_collect(adapter); 956 if (EM_IS_OACTIVE(adapter)) { 957 ifp->if_flags |= IFF_OACTIVE; 958 adapter->no_tx_desc_avail1++; 959 break; 960 } 961 } 962 963 logif(pkt_txqueue); 964 m_head = ifq_dequeue(&ifp->if_snd, NULL); 965 if (m_head == NULL) 966 break; 967 968 if (em_encap(adapter, &m_head)) { 969 ifp->if_oerrors++; 970 em_tx_collect(adapter); 971 continue; 972 } 973 974 /* Send a copy of the frame to the BPF listener */ 975 ETHER_BPF_MTAP(ifp, m_head); 976 977 /* Set timeout in case hardware has problems transmitting. */ 978 ifp->if_timer = EM_TX_TIMEOUT; 979 } 980 } 981 982 static int 983 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 984 { 985 struct adapter *adapter = ifp->if_softc; 986 struct ifreq *ifr = (struct ifreq *)data; 987 uint16_t eeprom_data = 0; 988 int max_frame_size, mask, reinit; 989 int error = 0; 990 991 ASSERT_SERIALIZED(ifp->if_serializer); 992 993 switch (command) { 994 case SIOCSIFMTU: 995 switch (adapter->hw.mac.type) { 996 case e1000_82573: 997 /* 998 * 82573 only supports jumbo frames 999 * if ASPM is disabled. 1000 */ 1001 e1000_read_nvm(&adapter->hw, 1002 NVM_INIT_3GIO_3, 1, &eeprom_data); 1003 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1004 max_frame_size = ETHER_MAX_LEN; 1005 break; 1006 } 1007 /* FALL THROUGH */ 1008 1009 /* Limit Jumbo Frame size */ 1010 case e1000_82571: 1011 case e1000_82572: 1012 case e1000_ich9lan: 1013 case e1000_ich10lan: 1014 case e1000_pch2lan: 1015 case e1000_82574: 1016 case e1000_82583: 1017 case e1000_80003es2lan: 1018 max_frame_size = 9234; 1019 break; 1020 1021 case e1000_pchlan: 1022 max_frame_size = 4096; 1023 break; 1024 1025 /* Adapters that do not support jumbo frames */ 1026 case e1000_82542: 1027 case e1000_ich8lan: 1028 max_frame_size = ETHER_MAX_LEN; 1029 break; 1030 1031 default: 1032 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1033 break; 1034 } 1035 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1036 ETHER_CRC_LEN) { 1037 error = EINVAL; 1038 break; 1039 } 1040 1041 ifp->if_mtu = ifr->ifr_mtu; 1042 adapter->max_frame_size = 1043 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1044 1045 if (ifp->if_flags & IFF_RUNNING) 1046 em_init(adapter); 1047 break; 1048 1049 case SIOCSIFFLAGS: 1050 if (ifp->if_flags & IFF_UP) { 1051 if ((ifp->if_flags & IFF_RUNNING)) { 1052 if ((ifp->if_flags ^ adapter->if_flags) & 1053 (IFF_PROMISC | IFF_ALLMULTI)) { 1054 em_disable_promisc(adapter); 1055 em_set_promisc(adapter); 1056 } 1057 } else { 1058 em_init(adapter); 1059 } 1060 } else if (ifp->if_flags & IFF_RUNNING) { 1061 em_stop(adapter); 1062 } 1063 adapter->if_flags = ifp->if_flags; 1064 break; 1065 1066 case SIOCADDMULTI: 1067 case SIOCDELMULTI: 1068 if (ifp->if_flags & IFF_RUNNING) { 1069 em_disable_intr(adapter); 1070 em_set_multi(adapter); 1071 if (adapter->hw.mac.type == e1000_82542 && 1072 adapter->hw.revision_id == E1000_REVISION_2) 1073 em_init_rx_unit(adapter); 1074 #ifdef DEVICE_POLLING 1075 if (!(ifp->if_flags & IFF_POLLING)) 1076 #endif 1077 em_enable_intr(adapter); 1078 } 1079 break; 1080 1081 case SIOCSIFMEDIA: 1082 /* Check SOL/IDER usage */ 1083 if (e1000_check_reset_block(&adapter->hw)) { 1084 device_printf(adapter->dev, "Media change is" 1085 " blocked due to SOL/IDER session.\n"); 1086 break; 1087 } 1088 /* FALL THROUGH */ 1089 1090 case SIOCGIFMEDIA: 1091 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1092 break; 1093 1094 case SIOCSIFCAP: 1095 reinit = 0; 1096 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1097 if (mask & IFCAP_HWCSUM) { 1098 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 1099 reinit = 1; 1100 } 1101 if (mask & IFCAP_VLAN_HWTAGGING) { 1102 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1103 reinit = 1; 1104 } 1105 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1106 em_init(adapter); 1107 break; 1108 1109 default: 1110 error = ether_ioctl(ifp, command, data); 1111 break; 1112 } 1113 return (error); 1114 } 1115 1116 static void 1117 em_watchdog(struct ifnet *ifp) 1118 { 1119 struct adapter *adapter = ifp->if_softc; 1120 1121 ASSERT_SERIALIZED(ifp->if_serializer); 1122 1123 /* 1124 * The timer is set to 5 every time start queues a packet. 1125 * Then txeof keeps resetting it as long as it cleans at 1126 * least one descriptor. 1127 * Finally, anytime all descriptors are clean the timer is 1128 * set to 0. 1129 */ 1130 1131 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1132 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) { 1133 /* 1134 * If we reach here, all TX jobs are completed and 1135 * the TX engine should have been idled for some time. 1136 * We don't need to call if_devstart() here. 1137 */ 1138 ifp->if_flags &= ~IFF_OACTIVE; 1139 ifp->if_timer = 0; 1140 return; 1141 } 1142 1143 /* 1144 * If we are in this routine because of pause frames, then 1145 * don't reset the hardware. 1146 */ 1147 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1148 E1000_STATUS_TXOFF) { 1149 ifp->if_timer = EM_TX_TIMEOUT; 1150 return; 1151 } 1152 1153 if (e1000_check_for_link(&adapter->hw) == 0) 1154 if_printf(ifp, "watchdog timeout -- resetting\n"); 1155 1156 ifp->if_oerrors++; 1157 adapter->watchdog_events++; 1158 1159 em_init(adapter); 1160 1161 if (!ifq_is_empty(&ifp->if_snd)) 1162 if_devstart(ifp); 1163 } 1164 1165 static void 1166 em_init(void *xsc) 1167 { 1168 struct adapter *adapter = xsc; 1169 struct ifnet *ifp = &adapter->arpcom.ac_if; 1170 device_t dev = adapter->dev; 1171 uint32_t pba; 1172 1173 ASSERT_SERIALIZED(ifp->if_serializer); 1174 1175 em_stop(adapter); 1176 1177 /* 1178 * Packet Buffer Allocation (PBA) 1179 * Writing PBA sets the receive portion of the buffer 1180 * the remainder is used for the transmit buffer. 1181 * 1182 * Devices before the 82547 had a Packet Buffer of 64K. 1183 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 1184 * After the 82547 the buffer was reduced to 40K. 1185 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 1186 * Note: default does not leave enough room for Jumbo Frame >10k. 1187 */ 1188 switch (adapter->hw.mac.type) { 1189 case e1000_82547: 1190 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 1191 if (adapter->max_frame_size > 8192) 1192 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1193 else 1194 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1195 adapter->tx_fifo_head = 0; 1196 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 1197 adapter->tx_fifo_size = 1198 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 1199 break; 1200 1201 /* Total Packet Buffer on these is 48K */ 1202 case e1000_82571: 1203 case e1000_82572: 1204 case e1000_80003es2lan: 1205 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1206 break; 1207 1208 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1209 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1210 break; 1211 1212 case e1000_82574: 1213 case e1000_82583: 1214 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1215 break; 1216 1217 case e1000_ich8lan: 1218 pba = E1000_PBA_8K; 1219 break; 1220 1221 case e1000_ich9lan: 1222 case e1000_ich10lan: 1223 #define E1000_PBA_10K 0x000A 1224 pba = E1000_PBA_10K; 1225 break; 1226 1227 case e1000_pchlan: 1228 case e1000_pch2lan: 1229 pba = E1000_PBA_26K; 1230 break; 1231 1232 default: 1233 /* Devices before 82547 had a Packet Buffer of 64K. */ 1234 if (adapter->max_frame_size > 8192) 1235 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1236 else 1237 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1238 } 1239 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 1240 1241 /* Get the latest mac address, User can use a LAA */ 1242 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN); 1243 1244 /* Put the address into the Receive Address Array */ 1245 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1246 1247 /* 1248 * With the 82571 adapter, RAR[0] may be overwritten 1249 * when the other port is reset, we make a duplicate 1250 * in RAR[14] for that eventuality, this assures 1251 * the interface continues to function. 1252 */ 1253 if (adapter->hw.mac.type == e1000_82571) { 1254 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1255 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1256 E1000_RAR_ENTRIES - 1); 1257 } 1258 1259 /* Reset the hardware */ 1260 if (em_reset(adapter)) { 1261 device_printf(dev, "Unable to reset the hardware\n"); 1262 /* XXX em_stop()? */ 1263 return; 1264 } 1265 em_update_link_status(adapter); 1266 1267 /* Setup VLAN support, basic and offload if available */ 1268 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1269 1270 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1271 uint32_t ctrl; 1272 1273 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1274 ctrl |= E1000_CTRL_VME; 1275 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1276 } 1277 1278 /* Set hardware offload abilities */ 1279 if (ifp->if_capenable & IFCAP_TXCSUM) 1280 ifp->if_hwassist = EM_CSUM_FEATURES; 1281 else 1282 ifp->if_hwassist = 0; 1283 1284 /* Configure for OS presence */ 1285 em_get_mgmt(adapter); 1286 1287 /* Prepare transmit descriptors and buffers */ 1288 em_init_tx_ring(adapter); 1289 em_init_tx_unit(adapter); 1290 1291 /* Setup Multicast table */ 1292 em_set_multi(adapter); 1293 1294 /* Prepare receive descriptors and buffers */ 1295 if (em_init_rx_ring(adapter)) { 1296 device_printf(dev, "Could not setup receive structures\n"); 1297 em_stop(adapter); 1298 return; 1299 } 1300 em_init_rx_unit(adapter); 1301 1302 /* Don't lose promiscuous settings */ 1303 em_set_promisc(adapter); 1304 1305 ifp->if_flags |= IFF_RUNNING; 1306 ifp->if_flags &= ~IFF_OACTIVE; 1307 1308 callout_reset(&adapter->timer, hz, em_timer, adapter); 1309 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1310 1311 /* MSI/X configuration for 82574 */ 1312 if (adapter->hw.mac.type == e1000_82574) { 1313 int tmp; 1314 1315 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1316 tmp |= E1000_CTRL_EXT_PBA_CLR; 1317 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1318 /* 1319 * XXX MSIX 1320 * Set the IVAR - interrupt vector routing. 1321 * Each nibble represents a vector, high bit 1322 * is enable, other 3 bits are the MSIX table 1323 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1324 * Link (other) to 2, hence the magic number. 1325 */ 1326 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); 1327 } 1328 1329 #ifdef DEVICE_POLLING 1330 /* 1331 * Only enable interrupts if we are not polling, make sure 1332 * they are off otherwise. 1333 */ 1334 if (ifp->if_flags & IFF_POLLING) 1335 em_disable_intr(adapter); 1336 else 1337 #endif /* DEVICE_POLLING */ 1338 em_enable_intr(adapter); 1339 1340 /* AMT based hardware can now take control from firmware */ 1341 if (adapter->has_manage && adapter->has_amt && 1342 adapter->hw.mac.type >= e1000_82571) 1343 em_get_hw_control(adapter); 1344 1345 /* Don't reset the phy next time init gets called */ 1346 adapter->hw.phy.reset_disable = TRUE; 1347 } 1348 1349 #ifdef DEVICE_POLLING 1350 1351 static void 1352 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1353 { 1354 struct adapter *adapter = ifp->if_softc; 1355 uint32_t reg_icr; 1356 1357 ASSERT_SERIALIZED(ifp->if_serializer); 1358 1359 switch (cmd) { 1360 case POLL_REGISTER: 1361 em_disable_intr(adapter); 1362 break; 1363 1364 case POLL_DEREGISTER: 1365 em_enable_intr(adapter); 1366 break; 1367 1368 case POLL_AND_CHECK_STATUS: 1369 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1370 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1371 callout_stop(&adapter->timer); 1372 adapter->hw.mac.get_link_status = 1; 1373 em_update_link_status(adapter); 1374 callout_reset(&adapter->timer, hz, em_timer, adapter); 1375 } 1376 /* FALL THROUGH */ 1377 case POLL_ONLY: 1378 if (ifp->if_flags & IFF_RUNNING) { 1379 em_rxeof(adapter, count); 1380 em_txeof(adapter); 1381 1382 if (!ifq_is_empty(&ifp->if_snd)) 1383 if_devstart(ifp); 1384 } 1385 break; 1386 } 1387 } 1388 1389 #endif /* DEVICE_POLLING */ 1390 1391 static void 1392 em_intr(void *xsc) 1393 { 1394 struct adapter *adapter = xsc; 1395 struct ifnet *ifp = &adapter->arpcom.ac_if; 1396 uint32_t reg_icr; 1397 1398 logif(intr_beg); 1399 ASSERT_SERIALIZED(ifp->if_serializer); 1400 1401 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1402 1403 if ((adapter->hw.mac.type >= e1000_82571 && 1404 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1405 reg_icr == 0) { 1406 logif(intr_end); 1407 return; 1408 } 1409 1410 /* 1411 * XXX: some laptops trigger several spurious interrupts 1412 * on em(4) when in the resume cycle. The ICR register 1413 * reports all-ones value in this case. Processing such 1414 * interrupts would lead to a freeze. I don't know why. 1415 */ 1416 if (reg_icr == 0xffffffff) { 1417 logif(intr_end); 1418 return; 1419 } 1420 1421 if (ifp->if_flags & IFF_RUNNING) { 1422 if (reg_icr & 1423 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) 1424 em_rxeof(adapter, -1); 1425 if (reg_icr & E1000_ICR_TXDW) { 1426 em_txeof(adapter); 1427 if (!ifq_is_empty(&ifp->if_snd)) 1428 if_devstart(ifp); 1429 } 1430 } 1431 1432 /* Link status change */ 1433 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1434 callout_stop(&adapter->timer); 1435 adapter->hw.mac.get_link_status = 1; 1436 em_update_link_status(adapter); 1437 1438 /* Deal with TX cruft when link lost */ 1439 em_tx_purge(adapter); 1440 1441 callout_reset(&adapter->timer, hz, em_timer, adapter); 1442 } 1443 1444 if (reg_icr & E1000_ICR_RXO) 1445 adapter->rx_overruns++; 1446 1447 logif(intr_end); 1448 } 1449 1450 static void 1451 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1452 { 1453 struct adapter *adapter = ifp->if_softc; 1454 u_char fiber_type = IFM_1000_SX; 1455 1456 ASSERT_SERIALIZED(ifp->if_serializer); 1457 1458 em_update_link_status(adapter); 1459 1460 ifmr->ifm_status = IFM_AVALID; 1461 ifmr->ifm_active = IFM_ETHER; 1462 1463 if (!adapter->link_active) 1464 return; 1465 1466 ifmr->ifm_status |= IFM_ACTIVE; 1467 1468 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 1469 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 1470 if (adapter->hw.mac.type == e1000_82545) 1471 fiber_type = IFM_1000_LX; 1472 ifmr->ifm_active |= fiber_type | IFM_FDX; 1473 } else { 1474 switch (adapter->link_speed) { 1475 case 10: 1476 ifmr->ifm_active |= IFM_10_T; 1477 break; 1478 case 100: 1479 ifmr->ifm_active |= IFM_100_TX; 1480 break; 1481 1482 case 1000: 1483 ifmr->ifm_active |= IFM_1000_T; 1484 break; 1485 } 1486 if (adapter->link_duplex == FULL_DUPLEX) 1487 ifmr->ifm_active |= IFM_FDX; 1488 else 1489 ifmr->ifm_active |= IFM_HDX; 1490 } 1491 } 1492 1493 static int 1494 em_media_change(struct ifnet *ifp) 1495 { 1496 struct adapter *adapter = ifp->if_softc; 1497 struct ifmedia *ifm = &adapter->media; 1498 1499 ASSERT_SERIALIZED(ifp->if_serializer); 1500 1501 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1502 return (EINVAL); 1503 1504 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1505 case IFM_AUTO: 1506 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1507 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1508 break; 1509 1510 case IFM_1000_LX: 1511 case IFM_1000_SX: 1512 case IFM_1000_T: 1513 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1514 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1515 break; 1516 1517 case IFM_100_TX: 1518 adapter->hw.mac.autoneg = FALSE; 1519 adapter->hw.phy.autoneg_advertised = 0; 1520 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1521 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1522 else 1523 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1524 break; 1525 1526 case IFM_10_T: 1527 adapter->hw.mac.autoneg = FALSE; 1528 adapter->hw.phy.autoneg_advertised = 0; 1529 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1530 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1531 else 1532 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1533 break; 1534 1535 default: 1536 if_printf(ifp, "Unsupported media type\n"); 1537 break; 1538 } 1539 1540 /* 1541 * As the speed/duplex settings my have changed we need to 1542 * reset the PHY. 1543 */ 1544 adapter->hw.phy.reset_disable = FALSE; 1545 1546 em_init(adapter); 1547 1548 return (0); 1549 } 1550 1551 static int 1552 em_encap(struct adapter *adapter, struct mbuf **m_headp) 1553 { 1554 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1555 bus_dmamap_t map; 1556 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1557 struct e1000_tx_desc *ctxd = NULL; 1558 struct mbuf *m_head = *m_headp; 1559 uint32_t txd_upper, txd_lower, txd_used, cmd = 0; 1560 int maxsegs, nsegs, i, j, first, last = 0, error; 1561 1562 if (m_head->m_len < EM_TXCSUM_MINHL && 1563 (m_head->m_flags & EM_CSUM_FEATURES)) { 1564 /* 1565 * Make sure that ethernet header and ip.ip_hl are in 1566 * contiguous memory, since if TXCSUM is enabled, later 1567 * TX context descriptor's setup need to access ip.ip_hl. 1568 */ 1569 error = em_txcsum_pullup(adapter, m_headp); 1570 if (error) { 1571 KKASSERT(*m_headp == NULL); 1572 return error; 1573 } 1574 m_head = *m_headp; 1575 } 1576 1577 txd_upper = txd_lower = 0; 1578 txd_used = 0; 1579 1580 /* 1581 * Capture the first descriptor index, this descriptor 1582 * will have the index of the EOP which is the only one 1583 * that now gets a DONE bit writeback. 1584 */ 1585 first = adapter->next_avail_tx_desc; 1586 tx_buffer = &adapter->tx_buffer_area[first]; 1587 tx_buffer_mapped = tx_buffer; 1588 map = tx_buffer->map; 1589 1590 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED; 1591 KASSERT(maxsegs >= adapter->spare_tx_desc, 1592 ("not enough spare TX desc")); 1593 if (adapter->pcix_82544) { 1594 /* Half it; see the comment in em_attach() */ 1595 maxsegs >>= 1; 1596 } 1597 if (maxsegs > EM_MAX_SCATTER) 1598 maxsegs = EM_MAX_SCATTER; 1599 1600 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp, 1601 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1602 if (error) { 1603 if (error == ENOBUFS) 1604 adapter->mbuf_alloc_failed++; 1605 else 1606 adapter->no_tx_dma_setup++; 1607 1608 m_freem(*m_headp); 1609 *m_headp = NULL; 1610 return error; 1611 } 1612 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1613 1614 m_head = *m_headp; 1615 adapter->tx_nsegs += nsegs; 1616 1617 if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) { 1618 /* TX csum offloading will consume one TX desc */ 1619 adapter->tx_nsegs += em_txcsum(adapter, m_head, 1620 &txd_upper, &txd_lower); 1621 } 1622 i = adapter->next_avail_tx_desc; 1623 1624 /* Set up our transmit descriptors */ 1625 for (j = 0; j < nsegs; j++) { 1626 /* If adapter is 82544 and on PCIX bus */ 1627 if(adapter->pcix_82544) { 1628 DESC_ARRAY desc_array; 1629 uint32_t array_elements, counter; 1630 1631 /* 1632 * Check the Address and Length combination and 1633 * split the data accordingly 1634 */ 1635 array_elements = em_82544_fill_desc(segs[j].ds_addr, 1636 segs[j].ds_len, &desc_array); 1637 for (counter = 0; counter < array_elements; counter++) { 1638 KKASSERT(txd_used < adapter->num_tx_desc_avail); 1639 1640 tx_buffer = &adapter->tx_buffer_area[i]; 1641 ctxd = &adapter->tx_desc_base[i]; 1642 1643 ctxd->buffer_addr = htole64( 1644 desc_array.descriptor[counter].address); 1645 ctxd->lower.data = htole32( 1646 E1000_TXD_CMD_IFCS | txd_lower | 1647 desc_array.descriptor[counter].length); 1648 ctxd->upper.data = htole32(txd_upper); 1649 1650 last = i; 1651 if (++i == adapter->num_tx_desc) 1652 i = 0; 1653 1654 txd_used++; 1655 } 1656 } else { 1657 tx_buffer = &adapter->tx_buffer_area[i]; 1658 ctxd = &adapter->tx_desc_base[i]; 1659 1660 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1661 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1662 txd_lower | segs[j].ds_len); 1663 ctxd->upper.data = htole32(txd_upper); 1664 1665 last = i; 1666 if (++i == adapter->num_tx_desc) 1667 i = 0; 1668 } 1669 } 1670 1671 adapter->next_avail_tx_desc = i; 1672 if (adapter->pcix_82544) { 1673 KKASSERT(adapter->num_tx_desc_avail > txd_used); 1674 adapter->num_tx_desc_avail -= txd_used; 1675 } else { 1676 KKASSERT(adapter->num_tx_desc_avail > nsegs); 1677 adapter->num_tx_desc_avail -= nsegs; 1678 } 1679 1680 /* Handle VLAN tag */ 1681 if (m_head->m_flags & M_VLANTAG) { 1682 /* Set the vlan id. */ 1683 ctxd->upper.fields.special = 1684 htole16(m_head->m_pkthdr.ether_vlantag); 1685 1686 /* Tell hardware to add tag */ 1687 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1688 } 1689 1690 tx_buffer->m_head = m_head; 1691 tx_buffer_mapped->map = tx_buffer->map; 1692 tx_buffer->map = map; 1693 1694 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) { 1695 adapter->tx_nsegs = 0; 1696 1697 /* 1698 * Report Status (RS) is turned on 1699 * every tx_int_nsegs descriptors. 1700 */ 1701 cmd = E1000_TXD_CMD_RS; 1702 1703 /* 1704 * Keep track of the descriptor, which will 1705 * be written back by hardware. 1706 */ 1707 adapter->tx_dd[adapter->tx_dd_tail] = last; 1708 EM_INC_TXDD_IDX(adapter->tx_dd_tail); 1709 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head); 1710 } 1711 1712 /* 1713 * Last Descriptor of Packet needs End Of Packet (EOP) 1714 */ 1715 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1716 1717 /* 1718 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000 1719 * that this frame is available to transmit. 1720 */ 1721 if (adapter->hw.mac.type == e1000_82547 && 1722 adapter->link_duplex == HALF_DUPLEX) { 1723 em_82547_move_tail_serialized(adapter); 1724 } else { 1725 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 1726 if (adapter->hw.mac.type == e1000_82547) { 1727 em_82547_update_fifo_head(adapter, 1728 m_head->m_pkthdr.len); 1729 } 1730 } 1731 return (0); 1732 } 1733 1734 /* 1735 * 82547 workaround to avoid controller hang in half-duplex environment. 1736 * The workaround is to avoid queuing a large packet that would span 1737 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1738 * in this case. We do that only when FIFO is quiescent. 1739 */ 1740 static void 1741 em_82547_move_tail_serialized(struct adapter *adapter) 1742 { 1743 struct e1000_tx_desc *tx_desc; 1744 uint16_t hw_tdt, sw_tdt, length = 0; 1745 bool eop = 0; 1746 1747 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer); 1748 1749 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 1750 sw_tdt = adapter->next_avail_tx_desc; 1751 1752 while (hw_tdt != sw_tdt) { 1753 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1754 length += tx_desc->lower.flags.length; 1755 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1756 if (++hw_tdt == adapter->num_tx_desc) 1757 hw_tdt = 0; 1758 1759 if (eop) { 1760 if (em_82547_fifo_workaround(adapter, length)) { 1761 adapter->tx_fifo_wrk_cnt++; 1762 callout_reset(&adapter->tx_fifo_timer, 1, 1763 em_82547_move_tail, adapter); 1764 break; 1765 } 1766 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 1767 em_82547_update_fifo_head(adapter, length); 1768 length = 0; 1769 } 1770 } 1771 } 1772 1773 static void 1774 em_82547_move_tail(void *xsc) 1775 { 1776 struct adapter *adapter = xsc; 1777 struct ifnet *ifp = &adapter->arpcom.ac_if; 1778 1779 lwkt_serialize_enter(ifp->if_serializer); 1780 em_82547_move_tail_serialized(adapter); 1781 lwkt_serialize_exit(ifp->if_serializer); 1782 } 1783 1784 static int 1785 em_82547_fifo_workaround(struct adapter *adapter, int len) 1786 { 1787 int fifo_space, fifo_pkt_len; 1788 1789 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1790 1791 if (adapter->link_duplex == HALF_DUPLEX) { 1792 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 1793 1794 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1795 if (em_82547_tx_fifo_reset(adapter)) 1796 return (0); 1797 else 1798 return (1); 1799 } 1800 } 1801 return (0); 1802 } 1803 1804 static void 1805 em_82547_update_fifo_head(struct adapter *adapter, int len) 1806 { 1807 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1808 1809 /* tx_fifo_head is always 16 byte aligned */ 1810 adapter->tx_fifo_head += fifo_pkt_len; 1811 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) 1812 adapter->tx_fifo_head -= adapter->tx_fifo_size; 1813 } 1814 1815 static int 1816 em_82547_tx_fifo_reset(struct adapter *adapter) 1817 { 1818 uint32_t tctl; 1819 1820 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1821 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 1822 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 1823 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 1824 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 1825 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 1826 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 1827 /* Disable TX unit */ 1828 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 1829 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 1830 tctl & ~E1000_TCTL_EN); 1831 1832 /* Reset FIFO pointers */ 1833 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 1834 adapter->tx_head_addr); 1835 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 1836 adapter->tx_head_addr); 1837 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 1838 adapter->tx_head_addr); 1839 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 1840 adapter->tx_head_addr); 1841 1842 /* Re-enable TX unit */ 1843 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 1844 E1000_WRITE_FLUSH(&adapter->hw); 1845 1846 adapter->tx_fifo_head = 0; 1847 adapter->tx_fifo_reset_cnt++; 1848 1849 return (TRUE); 1850 } else { 1851 return (FALSE); 1852 } 1853 } 1854 1855 static void 1856 em_set_promisc(struct adapter *adapter) 1857 { 1858 struct ifnet *ifp = &adapter->arpcom.ac_if; 1859 uint32_t reg_rctl; 1860 1861 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1862 1863 if (ifp->if_flags & IFF_PROMISC) { 1864 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1865 /* Turn this on if you want to see bad packets */ 1866 if (em_debug_sbp) 1867 reg_rctl |= E1000_RCTL_SBP; 1868 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1869 } else if (ifp->if_flags & IFF_ALLMULTI) { 1870 reg_rctl |= E1000_RCTL_MPE; 1871 reg_rctl &= ~E1000_RCTL_UPE; 1872 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1873 } 1874 } 1875 1876 static void 1877 em_disable_promisc(struct adapter *adapter) 1878 { 1879 uint32_t reg_rctl; 1880 1881 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1882 1883 reg_rctl &= ~E1000_RCTL_UPE; 1884 reg_rctl &= ~E1000_RCTL_MPE; 1885 reg_rctl &= ~E1000_RCTL_SBP; 1886 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1887 } 1888 1889 static void 1890 em_set_multi(struct adapter *adapter) 1891 { 1892 struct ifnet *ifp = &adapter->arpcom.ac_if; 1893 struct ifmultiaddr *ifma; 1894 uint32_t reg_rctl = 0; 1895 uint8_t *mta; 1896 int mcnt = 0; 1897 1898 mta = adapter->mta; 1899 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1900 1901 if (adapter->hw.mac.type == e1000_82542 && 1902 adapter->hw.revision_id == E1000_REVISION_2) { 1903 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1904 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1905 e1000_pci_clear_mwi(&adapter->hw); 1906 reg_rctl |= E1000_RCTL_RST; 1907 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1908 msec_delay(5); 1909 } 1910 1911 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1912 if (ifma->ifma_addr->sa_family != AF_LINK) 1913 continue; 1914 1915 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1916 break; 1917 1918 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1919 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1920 mcnt++; 1921 } 1922 1923 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1924 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1925 reg_rctl |= E1000_RCTL_MPE; 1926 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1927 } else { 1928 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1929 } 1930 1931 if (adapter->hw.mac.type == e1000_82542 && 1932 adapter->hw.revision_id == E1000_REVISION_2) { 1933 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1934 reg_rctl &= ~E1000_RCTL_RST; 1935 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1936 msec_delay(5); 1937 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1938 e1000_pci_set_mwi(&adapter->hw); 1939 } 1940 } 1941 1942 /* 1943 * This routine checks for link status and updates statistics. 1944 */ 1945 static void 1946 em_timer(void *xsc) 1947 { 1948 struct adapter *adapter = xsc; 1949 struct ifnet *ifp = &adapter->arpcom.ac_if; 1950 1951 lwkt_serialize_enter(ifp->if_serializer); 1952 1953 em_update_link_status(adapter); 1954 em_update_stats(adapter); 1955 1956 /* Reset LAA into RAR[0] on 82571 */ 1957 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 1958 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1959 1960 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1961 em_print_hw_stats(adapter); 1962 1963 em_smartspeed(adapter); 1964 1965 callout_reset(&adapter->timer, hz, em_timer, adapter); 1966 1967 lwkt_serialize_exit(ifp->if_serializer); 1968 } 1969 1970 static void 1971 em_update_link_status(struct adapter *adapter) 1972 { 1973 struct e1000_hw *hw = &adapter->hw; 1974 struct ifnet *ifp = &adapter->arpcom.ac_if; 1975 device_t dev = adapter->dev; 1976 uint32_t link_check = 0; 1977 1978 /* Get the cached link value or read phy for real */ 1979 switch (hw->phy.media_type) { 1980 case e1000_media_type_copper: 1981 if (hw->mac.get_link_status) { 1982 /* Do the work to read phy */ 1983 e1000_check_for_link(hw); 1984 link_check = !hw->mac.get_link_status; 1985 if (link_check) /* ESB2 fix */ 1986 e1000_cfg_on_link_up(hw); 1987 } else { 1988 link_check = TRUE; 1989 } 1990 break; 1991 1992 case e1000_media_type_fiber: 1993 e1000_check_for_link(hw); 1994 link_check = 1995 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 1996 break; 1997 1998 case e1000_media_type_internal_serdes: 1999 e1000_check_for_link(hw); 2000 link_check = adapter->hw.mac.serdes_has_link; 2001 break; 2002 2003 case e1000_media_type_unknown: 2004 default: 2005 break; 2006 } 2007 2008 /* Now check for a transition */ 2009 if (link_check && adapter->link_active == 0) { 2010 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 2011 &adapter->link_duplex); 2012 2013 /* 2014 * Check if we should enable/disable SPEED_MODE bit on 2015 * 82571/82572 2016 */ 2017 if (adapter->link_speed != SPEED_1000 && 2018 (hw->mac.type == e1000_82571 || 2019 hw->mac.type == e1000_82572)) { 2020 int tarc0; 2021 2022 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2023 tarc0 &= ~SPEED_MODE_BIT; 2024 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2025 } 2026 if (bootverbose) { 2027 device_printf(dev, "Link is up %d Mbps %s\n", 2028 adapter->link_speed, 2029 ((adapter->link_duplex == FULL_DUPLEX) ? 2030 "Full Duplex" : "Half Duplex")); 2031 } 2032 adapter->link_active = 1; 2033 adapter->smartspeed = 0; 2034 ifp->if_baudrate = adapter->link_speed * 1000000; 2035 ifp->if_link_state = LINK_STATE_UP; 2036 if_link_state_change(ifp); 2037 } else if (!link_check && adapter->link_active == 1) { 2038 ifp->if_baudrate = adapter->link_speed = 0; 2039 adapter->link_duplex = 0; 2040 if (bootverbose) 2041 device_printf(dev, "Link is Down\n"); 2042 adapter->link_active = 0; 2043 #if 0 2044 /* Link down, disable watchdog */ 2045 if->if_timer = 0; 2046 #endif 2047 ifp->if_link_state = LINK_STATE_DOWN; 2048 if_link_state_change(ifp); 2049 } 2050 } 2051 2052 static void 2053 em_stop(struct adapter *adapter) 2054 { 2055 struct ifnet *ifp = &adapter->arpcom.ac_if; 2056 int i; 2057 2058 ASSERT_SERIALIZED(ifp->if_serializer); 2059 2060 em_disable_intr(adapter); 2061 2062 callout_stop(&adapter->timer); 2063 callout_stop(&adapter->tx_fifo_timer); 2064 2065 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2066 ifp->if_timer = 0; 2067 2068 e1000_reset_hw(&adapter->hw); 2069 if (adapter->hw.mac.type >= e1000_82544) 2070 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2071 2072 for (i = 0; i < adapter->num_tx_desc; i++) { 2073 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i]; 2074 2075 if (tx_buffer->m_head != NULL) { 2076 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 2077 m_freem(tx_buffer->m_head); 2078 tx_buffer->m_head = NULL; 2079 } 2080 } 2081 2082 for (i = 0; i < adapter->num_rx_desc; i++) { 2083 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i]; 2084 2085 if (rx_buffer->m_head != NULL) { 2086 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 2087 m_freem(rx_buffer->m_head); 2088 rx_buffer->m_head = NULL; 2089 } 2090 } 2091 2092 if (adapter->fmp != NULL) 2093 m_freem(adapter->fmp); 2094 adapter->fmp = NULL; 2095 adapter->lmp = NULL; 2096 2097 adapter->csum_flags = 0; 2098 adapter->csum_ehlen = 0; 2099 adapter->csum_iphlen = 0; 2100 2101 adapter->tx_dd_head = 0; 2102 adapter->tx_dd_tail = 0; 2103 adapter->tx_nsegs = 0; 2104 } 2105 2106 static int 2107 em_get_hw_info(struct adapter *adapter) 2108 { 2109 device_t dev = adapter->dev; 2110 2111 /* Save off the information about this board */ 2112 adapter->hw.vendor_id = pci_get_vendor(dev); 2113 adapter->hw.device_id = pci_get_device(dev); 2114 adapter->hw.revision_id = pci_get_revid(dev); 2115 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev); 2116 adapter->hw.subsystem_device_id = pci_get_subdevice(dev); 2117 2118 /* Do Shared Code Init and Setup */ 2119 if (e1000_set_mac_type(&adapter->hw)) 2120 return ENXIO; 2121 return 0; 2122 } 2123 2124 static int 2125 em_alloc_pci_res(struct adapter *adapter) 2126 { 2127 device_t dev = adapter->dev; 2128 u_int intr_flags; 2129 int val, rid, msi_enable; 2130 2131 /* Enable bus mastering */ 2132 pci_enable_busmaster(dev); 2133 2134 adapter->memory_rid = EM_BAR_MEM; 2135 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2136 &adapter->memory_rid, RF_ACTIVE); 2137 if (adapter->memory == NULL) { 2138 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2139 return (ENXIO); 2140 } 2141 adapter->osdep.mem_bus_space_tag = 2142 rman_get_bustag(adapter->memory); 2143 adapter->osdep.mem_bus_space_handle = 2144 rman_get_bushandle(adapter->memory); 2145 2146 /* XXX This is quite goofy, it is not actually used */ 2147 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2148 2149 /* Only older adapters use IO mapping */ 2150 if (adapter->hw.mac.type > e1000_82543 && 2151 adapter->hw.mac.type < e1000_82571) { 2152 /* Figure our where our IO BAR is ? */ 2153 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) { 2154 val = pci_read_config(dev, rid, 4); 2155 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2156 adapter->io_rid = rid; 2157 break; 2158 } 2159 rid += 4; 2160 /* check for 64bit BAR */ 2161 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2162 rid += 4; 2163 } 2164 if (rid >= PCIR_CARDBUSCIS) { 2165 device_printf(dev, "Unable to locate IO BAR\n"); 2166 return (ENXIO); 2167 } 2168 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2169 &adapter->io_rid, RF_ACTIVE); 2170 if (adapter->ioport == NULL) { 2171 device_printf(dev, "Unable to allocate bus resource: " 2172 "ioport\n"); 2173 return (ENXIO); 2174 } 2175 adapter->hw.io_base = 0; 2176 adapter->osdep.io_bus_space_tag = 2177 rman_get_bustag(adapter->ioport); 2178 adapter->osdep.io_bus_space_handle = 2179 rman_get_bushandle(adapter->ioport); 2180 } 2181 2182 /* 2183 * Don't enable MSI on PCI/PCI-X chips, see: 2184 * 82540EP and 82545GM specification update 2185 * 2186 * Don't enable MSI on 82571/82572, see: 2187 * 82571EB/82572EI specification update 2188 */ 2189 msi_enable = em_msi_enable; 2190 if (msi_enable && 2191 (!pci_is_pcie(dev) || 2192 adapter->hw.mac.type == e1000_82571 || 2193 adapter->hw.mac.type == e1000_82572)) 2194 msi_enable = 0; 2195 2196 adapter->intr_type = pci_alloc_1intr(dev, msi_enable, 2197 &adapter->intr_rid, &intr_flags); 2198 2199 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 2200 &adapter->intr_rid, intr_flags); 2201 if (adapter->intr_res == NULL) { 2202 device_printf(dev, "Unable to allocate bus resource: " 2203 "interrupt\n"); 2204 return (ENXIO); 2205 } 2206 2207 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2208 adapter->hw.back = &adapter->osdep; 2209 return (0); 2210 } 2211 2212 static void 2213 em_free_pci_res(struct adapter *adapter) 2214 { 2215 device_t dev = adapter->dev; 2216 2217 if (adapter->intr_res != NULL) { 2218 bus_release_resource(dev, SYS_RES_IRQ, 2219 adapter->intr_rid, adapter->intr_res); 2220 } 2221 2222 if (adapter->intr_type == PCI_INTR_TYPE_MSI) 2223 pci_release_msi(dev); 2224 2225 if (adapter->memory != NULL) { 2226 bus_release_resource(dev, SYS_RES_MEMORY, 2227 adapter->memory_rid, adapter->memory); 2228 } 2229 2230 if (adapter->flash != NULL) { 2231 bus_release_resource(dev, SYS_RES_MEMORY, 2232 adapter->flash_rid, adapter->flash); 2233 } 2234 2235 if (adapter->ioport != NULL) { 2236 bus_release_resource(dev, SYS_RES_IOPORT, 2237 adapter->io_rid, adapter->ioport); 2238 } 2239 } 2240 2241 static int 2242 em_reset(struct adapter *adapter) 2243 { 2244 device_t dev = adapter->dev; 2245 uint16_t rx_buffer_size; 2246 2247 /* When hardware is reset, fifo_head is also reset */ 2248 adapter->tx_fifo_head = 0; 2249 2250 /* Set up smart power down as default off on newer adapters. */ 2251 if (!em_smart_pwr_down && 2252 (adapter->hw.mac.type == e1000_82571 || 2253 adapter->hw.mac.type == e1000_82572)) { 2254 uint16_t phy_tmp = 0; 2255 2256 /* Speed up time to link by disabling smart power down. */ 2257 e1000_read_phy_reg(&adapter->hw, 2258 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2259 phy_tmp &= ~IGP02E1000_PM_SPD; 2260 e1000_write_phy_reg(&adapter->hw, 2261 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2262 } 2263 2264 /* 2265 * These parameters control the automatic generation (Tx) and 2266 * response (Rx) to Ethernet PAUSE frames. 2267 * - High water mark should allow for at least two frames to be 2268 * received after sending an XOFF. 2269 * - Low water mark works best when it is very near the high water mark. 2270 * This allows the receiver to restart by sending XON when it has 2271 * drained a bit. Here we use an arbitary value of 1500 which will 2272 * restart after one full frame is pulled from the buffer. There 2273 * could be several smaller frames in the buffer and if so they will 2274 * not trigger the XON until their total number reduces the buffer 2275 * by 1500. 2276 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2277 */ 2278 rx_buffer_size = 2279 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10; 2280 2281 adapter->hw.fc.high_water = rx_buffer_size - 2282 roundup2(adapter->max_frame_size, 1024); 2283 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 2284 2285 if (adapter->hw.mac.type == e1000_80003es2lan) 2286 adapter->hw.fc.pause_time = 0xFFFF; 2287 else 2288 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 2289 2290 adapter->hw.fc.send_xon = TRUE; 2291 2292 adapter->hw.fc.requested_mode = e1000_fc_full; 2293 2294 /* Workaround: no TX flow ctrl for PCH */ 2295 if (adapter->hw.mac.type == e1000_pchlan) 2296 adapter->hw.fc.requested_mode = e1000_fc_rx_pause; 2297 2298 /* Override - settings for PCH2LAN, ya its magic :) */ 2299 if (adapter->hw.mac.type == e1000_pch2lan) { 2300 adapter->hw.fc.high_water = 0x5C20; 2301 adapter->hw.fc.low_water = 0x5048; 2302 adapter->hw.fc.pause_time = 0x0650; 2303 adapter->hw.fc.refresh_time = 0x0400; 2304 2305 /* Jumbos need adjusted PBA */ 2306 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) 2307 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12); 2308 else 2309 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26); 2310 } 2311 2312 /* Issue a global reset */ 2313 e1000_reset_hw(&adapter->hw); 2314 if (adapter->hw.mac.type >= e1000_82544) 2315 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2316 em_disable_aspm(adapter); 2317 2318 if (e1000_init_hw(&adapter->hw) < 0) { 2319 device_printf(dev, "Hardware Initialization Failed\n"); 2320 return (EIO); 2321 } 2322 2323 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 2324 e1000_get_phy_info(&adapter->hw); 2325 e1000_check_for_link(&adapter->hw); 2326 2327 return (0); 2328 } 2329 2330 static void 2331 em_setup_ifp(struct adapter *adapter) 2332 { 2333 struct ifnet *ifp = &adapter->arpcom.ac_if; 2334 2335 if_initname(ifp, device_get_name(adapter->dev), 2336 device_get_unit(adapter->dev)); 2337 ifp->if_softc = adapter; 2338 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2339 ifp->if_init = em_init; 2340 ifp->if_ioctl = em_ioctl; 2341 ifp->if_start = em_start; 2342 #ifdef DEVICE_POLLING 2343 ifp->if_poll = em_poll; 2344 #endif 2345 ifp->if_watchdog = em_watchdog; 2346 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1); 2347 ifq_set_ready(&ifp->if_snd); 2348 2349 ether_ifattach(ifp, adapter->hw.mac.addr, NULL); 2350 2351 if (adapter->hw.mac.type >= e1000_82543) 2352 ifp->if_capabilities = IFCAP_HWCSUM; 2353 2354 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2355 ifp->if_capenable = ifp->if_capabilities; 2356 2357 if (ifp->if_capenable & IFCAP_TXCSUM) 2358 ifp->if_hwassist = EM_CSUM_FEATURES; 2359 2360 /* 2361 * Tell the upper layer(s) we support long frames. 2362 */ 2363 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2364 2365 /* 2366 * Specify the media types supported by this adapter and register 2367 * callbacks to update media and link information 2368 */ 2369 ifmedia_init(&adapter->media, IFM_IMASK, 2370 em_media_change, em_media_status); 2371 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2372 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2373 u_char fiber_type = IFM_1000_SX; /* default type */ 2374 2375 if (adapter->hw.mac.type == e1000_82545) 2376 fiber_type = IFM_1000_LX; 2377 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2378 0, NULL); 2379 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2380 } else { 2381 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2382 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2383 0, NULL); 2384 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2385 0, NULL); 2386 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2387 0, NULL); 2388 if (adapter->hw.phy.type != e1000_phy_ife) { 2389 ifmedia_add(&adapter->media, 2390 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2391 ifmedia_add(&adapter->media, 2392 IFM_ETHER | IFM_1000_T, 0, NULL); 2393 } 2394 } 2395 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2396 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2397 } 2398 2399 2400 /* 2401 * Workaround for SmartSpeed on 82541 and 82547 controllers 2402 */ 2403 static void 2404 em_smartspeed(struct adapter *adapter) 2405 { 2406 uint16_t phy_tmp; 2407 2408 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp || 2409 adapter->hw.mac.autoneg == 0 || 2410 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2411 return; 2412 2413 if (adapter->smartspeed == 0) { 2414 /* 2415 * If Master/Slave config fault is asserted twice, 2416 * we assume back-to-back 2417 */ 2418 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2419 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2420 return; 2421 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2422 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2423 e1000_read_phy_reg(&adapter->hw, 2424 PHY_1000T_CTRL, &phy_tmp); 2425 if (phy_tmp & CR_1000T_MS_ENABLE) { 2426 phy_tmp &= ~CR_1000T_MS_ENABLE; 2427 e1000_write_phy_reg(&adapter->hw, 2428 PHY_1000T_CTRL, phy_tmp); 2429 adapter->smartspeed++; 2430 if (adapter->hw.mac.autoneg && 2431 !e1000_phy_setup_autoneg(&adapter->hw) && 2432 !e1000_read_phy_reg(&adapter->hw, 2433 PHY_CONTROL, &phy_tmp)) { 2434 phy_tmp |= MII_CR_AUTO_NEG_EN | 2435 MII_CR_RESTART_AUTO_NEG; 2436 e1000_write_phy_reg(&adapter->hw, 2437 PHY_CONTROL, phy_tmp); 2438 } 2439 } 2440 } 2441 return; 2442 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2443 /* If still no link, perhaps using 2/3 pair cable */ 2444 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2445 phy_tmp |= CR_1000T_MS_ENABLE; 2446 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2447 if (adapter->hw.mac.autoneg && 2448 !e1000_phy_setup_autoneg(&adapter->hw) && 2449 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2450 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2451 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2452 } 2453 } 2454 2455 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2456 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2457 adapter->smartspeed = 0; 2458 } 2459 2460 static int 2461 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2462 struct em_dma_alloc *dma) 2463 { 2464 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag, 2465 EM_DBA_ALIGN, size, BUS_DMA_WAITOK, 2466 &dma->dma_tag, &dma->dma_map, 2467 &dma->dma_paddr); 2468 if (dma->dma_vaddr == NULL) 2469 return ENOMEM; 2470 else 2471 return 0; 2472 } 2473 2474 static void 2475 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2476 { 2477 if (dma->dma_tag == NULL) 2478 return; 2479 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2480 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2481 bus_dma_tag_destroy(dma->dma_tag); 2482 } 2483 2484 static int 2485 em_create_tx_ring(struct adapter *adapter) 2486 { 2487 device_t dev = adapter->dev; 2488 struct em_buffer *tx_buffer; 2489 int error, i; 2490 2491 adapter->tx_buffer_area = 2492 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc, 2493 M_DEVBUF, M_WAITOK | M_ZERO); 2494 2495 /* 2496 * Create DMA tags for tx buffers 2497 */ 2498 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 2499 1, 0, /* alignment, bounds */ 2500 BUS_SPACE_MAXADDR, /* lowaddr */ 2501 BUS_SPACE_MAXADDR, /* highaddr */ 2502 NULL, NULL, /* filter, filterarg */ 2503 EM_TSO_SIZE, /* maxsize */ 2504 EM_MAX_SCATTER, /* nsegments */ 2505 EM_MAX_SEGSIZE, /* maxsegsize */ 2506 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2507 BUS_DMA_ONEBPAGE, /* flags */ 2508 &adapter->txtag); 2509 if (error) { 2510 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2511 kfree(adapter->tx_buffer_area, M_DEVBUF); 2512 adapter->tx_buffer_area = NULL; 2513 return error; 2514 } 2515 2516 /* 2517 * Create DMA maps for tx buffers 2518 */ 2519 for (i = 0; i < adapter->num_tx_desc; i++) { 2520 tx_buffer = &adapter->tx_buffer_area[i]; 2521 2522 error = bus_dmamap_create(adapter->txtag, 2523 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2524 &tx_buffer->map); 2525 if (error) { 2526 device_printf(dev, "Unable to create TX DMA map\n"); 2527 em_destroy_tx_ring(adapter, i); 2528 return error; 2529 } 2530 } 2531 return (0); 2532 } 2533 2534 static void 2535 em_init_tx_ring(struct adapter *adapter) 2536 { 2537 /* Clear the old ring contents */ 2538 bzero(adapter->tx_desc_base, 2539 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 2540 2541 /* Reset state */ 2542 adapter->next_avail_tx_desc = 0; 2543 adapter->next_tx_to_clean = 0; 2544 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2545 } 2546 2547 static void 2548 em_init_tx_unit(struct adapter *adapter) 2549 { 2550 uint32_t tctl, tarc, tipg = 0; 2551 uint64_t bus_addr; 2552 2553 /* Setup the Base and Length of the Tx Descriptor Ring */ 2554 bus_addr = adapter->txdma.dma_paddr; 2555 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 2556 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 2557 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 2558 (uint32_t)(bus_addr >> 32)); 2559 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 2560 (uint32_t)bus_addr); 2561 /* Setup the HW Tx Head and Tail descriptor pointers */ 2562 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 2563 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 2564 2565 /* Set the default values for the Tx Inter Packet Gap timer */ 2566 switch (adapter->hw.mac.type) { 2567 case e1000_82542: 2568 tipg = DEFAULT_82542_TIPG_IPGT; 2569 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2570 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2571 break; 2572 2573 case e1000_80003es2lan: 2574 tipg = DEFAULT_82543_TIPG_IPGR1; 2575 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2576 E1000_TIPG_IPGR2_SHIFT; 2577 break; 2578 2579 default: 2580 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2581 adapter->hw.phy.media_type == 2582 e1000_media_type_internal_serdes) 2583 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2584 else 2585 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2586 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2587 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2588 break; 2589 } 2590 2591 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2592 2593 /* NOTE: 0 is not allowed for TIDV */ 2594 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1); 2595 if(adapter->hw.mac.type >= e1000_82540) 2596 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0); 2597 2598 if (adapter->hw.mac.type == e1000_82571 || 2599 adapter->hw.mac.type == e1000_82572) { 2600 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2601 tarc |= SPEED_MODE_BIT; 2602 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2603 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2604 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2605 tarc |= 1; 2606 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2607 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2608 tarc |= 1; 2609 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2610 } 2611 2612 /* Program the Transmit Control Register */ 2613 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2614 tctl &= ~E1000_TCTL_CT; 2615 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2616 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2617 2618 if (adapter->hw.mac.type >= e1000_82571) 2619 tctl |= E1000_TCTL_MULR; 2620 2621 /* This write will effectively turn on the transmit unit. */ 2622 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2623 } 2624 2625 static void 2626 em_destroy_tx_ring(struct adapter *adapter, int ndesc) 2627 { 2628 struct em_buffer *tx_buffer; 2629 int i; 2630 2631 if (adapter->tx_buffer_area == NULL) 2632 return; 2633 2634 for (i = 0; i < ndesc; i++) { 2635 tx_buffer = &adapter->tx_buffer_area[i]; 2636 2637 KKASSERT(tx_buffer->m_head == NULL); 2638 bus_dmamap_destroy(adapter->txtag, tx_buffer->map); 2639 } 2640 bus_dma_tag_destroy(adapter->txtag); 2641 2642 kfree(adapter->tx_buffer_area, M_DEVBUF); 2643 adapter->tx_buffer_area = NULL; 2644 } 2645 2646 /* 2647 * The offload context needs to be set when we transfer the first 2648 * packet of a particular protocol (TCP/UDP). This routine has been 2649 * enhanced to deal with inserted VLAN headers. 2650 * 2651 * If the new packet's ether header length, ip header length and 2652 * csum offloading type are same as the previous packet, we should 2653 * avoid allocating a new csum context descriptor; mainly to take 2654 * advantage of the pipeline effect of the TX data read request. 2655 * 2656 * This function returns number of TX descrptors allocated for 2657 * csum context. 2658 */ 2659 static int 2660 em_txcsum(struct adapter *adapter, struct mbuf *mp, 2661 uint32_t *txd_upper, uint32_t *txd_lower) 2662 { 2663 struct e1000_context_desc *TXD; 2664 struct em_buffer *tx_buffer; 2665 struct ether_vlan_header *eh; 2666 struct ip *ip; 2667 int curr_txd, ehdrlen, csum_flags; 2668 uint32_t cmd, hdr_len, ip_hlen; 2669 uint16_t etype; 2670 2671 /* 2672 * Determine where frame payload starts. 2673 * Jump over vlan headers if already present, 2674 * helpful for QinQ too. 2675 */ 2676 KASSERT(mp->m_len >= ETHER_HDR_LEN, 2677 ("em_txcsum_pullup is not called (eh)?")); 2678 eh = mtod(mp, struct ether_vlan_header *); 2679 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2680 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN, 2681 ("em_txcsum_pullup is not called (evh)?")); 2682 etype = ntohs(eh->evl_proto); 2683 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN; 2684 } else { 2685 etype = ntohs(eh->evl_encap_proto); 2686 ehdrlen = ETHER_HDR_LEN; 2687 } 2688 2689 /* 2690 * We only support TCP/UDP for IPv4 for the moment. 2691 * TODO: Support SCTP too when it hits the tree. 2692 */ 2693 if (etype != ETHERTYPE_IP) 2694 return 0; 2695 2696 KASSERT(mp->m_len >= ehdrlen + EM_IPVHL_SIZE, 2697 ("em_txcsum_pullup is not called (eh+ip_vhl)?")); 2698 2699 /* NOTE: We could only safely access ip.ip_vhl part */ 2700 ip = (struct ip *)(mp->m_data + ehdrlen); 2701 ip_hlen = ip->ip_hl << 2; 2702 2703 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES; 2704 2705 if (adapter->csum_ehlen == ehdrlen && 2706 adapter->csum_iphlen == ip_hlen && 2707 adapter->csum_flags == csum_flags) { 2708 /* 2709 * Same csum offload context as the previous packets; 2710 * just return. 2711 */ 2712 *txd_upper = adapter->csum_txd_upper; 2713 *txd_lower = adapter->csum_txd_lower; 2714 return 0; 2715 } 2716 2717 /* 2718 * Setup a new csum offload context. 2719 */ 2720 2721 curr_txd = adapter->next_avail_tx_desc; 2722 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 2723 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 2724 2725 cmd = 0; 2726 2727 /* Setup of IP header checksum. */ 2728 if (csum_flags & CSUM_IP) { 2729 /* 2730 * Start offset for header checksum calculation. 2731 * End offset for header checksum calculation. 2732 * Offset of place to put the checksum. 2733 */ 2734 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2735 TXD->lower_setup.ip_fields.ipcse = 2736 htole16(ehdrlen + ip_hlen - 1); 2737 TXD->lower_setup.ip_fields.ipcso = 2738 ehdrlen + offsetof(struct ip, ip_sum); 2739 cmd |= E1000_TXD_CMD_IP; 2740 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2741 } 2742 hdr_len = ehdrlen + ip_hlen; 2743 2744 if (csum_flags & CSUM_TCP) { 2745 /* 2746 * Start offset for payload checksum calculation. 2747 * End offset for payload checksum calculation. 2748 * Offset of place to put the checksum. 2749 */ 2750 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2751 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2752 TXD->upper_setup.tcp_fields.tucso = 2753 hdr_len + offsetof(struct tcphdr, th_sum); 2754 cmd |= E1000_TXD_CMD_TCP; 2755 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2756 } else if (csum_flags & CSUM_UDP) { 2757 /* 2758 * Start offset for header checksum calculation. 2759 * End offset for header checksum calculation. 2760 * Offset of place to put the checksum. 2761 */ 2762 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2763 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2764 TXD->upper_setup.tcp_fields.tucso = 2765 hdr_len + offsetof(struct udphdr, uh_sum); 2766 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2767 } 2768 2769 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2770 E1000_TXD_DTYP_D; /* Data descr */ 2771 2772 /* Save the information for this csum offloading context */ 2773 adapter->csum_ehlen = ehdrlen; 2774 adapter->csum_iphlen = ip_hlen; 2775 adapter->csum_flags = csum_flags; 2776 adapter->csum_txd_upper = *txd_upper; 2777 adapter->csum_txd_lower = *txd_lower; 2778 2779 TXD->tcp_seg_setup.data = htole32(0); 2780 TXD->cmd_and_length = 2781 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2782 2783 if (++curr_txd == adapter->num_tx_desc) 2784 curr_txd = 0; 2785 2786 KKASSERT(adapter->num_tx_desc_avail > 0); 2787 adapter->num_tx_desc_avail--; 2788 2789 adapter->next_avail_tx_desc = curr_txd; 2790 return 1; 2791 } 2792 2793 static int 2794 em_txcsum_pullup(struct adapter *adapter, struct mbuf **m0) 2795 { 2796 struct mbuf *m = *m0; 2797 struct ether_header *eh; 2798 int len; 2799 2800 adapter->tx_csum_try_pullup++; 2801 2802 len = ETHER_HDR_LEN + EM_IPVHL_SIZE; 2803 2804 if (__predict_false(!M_WRITABLE(m))) { 2805 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2806 adapter->tx_csum_drop1++; 2807 m_freem(m); 2808 *m0 = NULL; 2809 return ENOBUFS; 2810 } 2811 eh = mtod(m, struct ether_header *); 2812 2813 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2814 len += EVL_ENCAPLEN; 2815 2816 if (m->m_len < len) { 2817 adapter->tx_csum_drop2++; 2818 m_freem(m); 2819 *m0 = NULL; 2820 return ENOBUFS; 2821 } 2822 return 0; 2823 } 2824 2825 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2826 adapter->tx_csum_pullup1++; 2827 m = m_pullup(m, ETHER_HDR_LEN); 2828 if (m == NULL) { 2829 adapter->tx_csum_pullup1_failed++; 2830 *m0 = NULL; 2831 return ENOBUFS; 2832 } 2833 *m0 = m; 2834 } 2835 eh = mtod(m, struct ether_header *); 2836 2837 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2838 len += EVL_ENCAPLEN; 2839 2840 if (m->m_len < len) { 2841 adapter->tx_csum_pullup2++; 2842 m = m_pullup(m, len); 2843 if (m == NULL) { 2844 adapter->tx_csum_pullup2_failed++; 2845 *m0 = NULL; 2846 return ENOBUFS; 2847 } 2848 *m0 = m; 2849 } 2850 return 0; 2851 } 2852 2853 static void 2854 em_txeof(struct adapter *adapter) 2855 { 2856 struct ifnet *ifp = &adapter->arpcom.ac_if; 2857 struct em_buffer *tx_buffer; 2858 int first, num_avail; 2859 2860 if (adapter->tx_dd_head == adapter->tx_dd_tail) 2861 return; 2862 2863 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2864 return; 2865 2866 num_avail = adapter->num_tx_desc_avail; 2867 first = adapter->next_tx_to_clean; 2868 2869 while (adapter->tx_dd_head != adapter->tx_dd_tail) { 2870 struct e1000_tx_desc *tx_desc; 2871 int dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2872 2873 tx_desc = &adapter->tx_desc_base[dd_idx]; 2874 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2875 EM_INC_TXDD_IDX(adapter->tx_dd_head); 2876 2877 if (++dd_idx == adapter->num_tx_desc) 2878 dd_idx = 0; 2879 2880 while (first != dd_idx) { 2881 logif(pkt_txclean); 2882 2883 num_avail++; 2884 2885 tx_buffer = &adapter->tx_buffer_area[first]; 2886 if (tx_buffer->m_head) { 2887 ifp->if_opackets++; 2888 bus_dmamap_unload(adapter->txtag, 2889 tx_buffer->map); 2890 m_freem(tx_buffer->m_head); 2891 tx_buffer->m_head = NULL; 2892 } 2893 2894 if (++first == adapter->num_tx_desc) 2895 first = 0; 2896 } 2897 } else { 2898 break; 2899 } 2900 } 2901 adapter->next_tx_to_clean = first; 2902 adapter->num_tx_desc_avail = num_avail; 2903 2904 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 2905 adapter->tx_dd_head = 0; 2906 adapter->tx_dd_tail = 0; 2907 } 2908 2909 if (!EM_IS_OACTIVE(adapter)) { 2910 ifp->if_flags &= ~IFF_OACTIVE; 2911 2912 /* All clean, turn off the timer */ 2913 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2914 ifp->if_timer = 0; 2915 } 2916 } 2917 2918 static void 2919 em_tx_collect(struct adapter *adapter) 2920 { 2921 struct ifnet *ifp = &adapter->arpcom.ac_if; 2922 struct em_buffer *tx_buffer; 2923 int tdh, first, num_avail, dd_idx = -1; 2924 2925 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2926 return; 2927 2928 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0)); 2929 if (tdh == adapter->next_tx_to_clean) 2930 return; 2931 2932 if (adapter->tx_dd_head != adapter->tx_dd_tail) 2933 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2934 2935 num_avail = adapter->num_tx_desc_avail; 2936 first = adapter->next_tx_to_clean; 2937 2938 while (first != tdh) { 2939 logif(pkt_txclean); 2940 2941 num_avail++; 2942 2943 tx_buffer = &adapter->tx_buffer_area[first]; 2944 if (tx_buffer->m_head) { 2945 ifp->if_opackets++; 2946 bus_dmamap_unload(adapter->txtag, 2947 tx_buffer->map); 2948 m_freem(tx_buffer->m_head); 2949 tx_buffer->m_head = NULL; 2950 } 2951 2952 if (first == dd_idx) { 2953 EM_INC_TXDD_IDX(adapter->tx_dd_head); 2954 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 2955 adapter->tx_dd_head = 0; 2956 adapter->tx_dd_tail = 0; 2957 dd_idx = -1; 2958 } else { 2959 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2960 } 2961 } 2962 2963 if (++first == adapter->num_tx_desc) 2964 first = 0; 2965 } 2966 adapter->next_tx_to_clean = first; 2967 adapter->num_tx_desc_avail = num_avail; 2968 2969 if (!EM_IS_OACTIVE(adapter)) { 2970 ifp->if_flags &= ~IFF_OACTIVE; 2971 2972 /* All clean, turn off the timer */ 2973 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2974 ifp->if_timer = 0; 2975 } 2976 } 2977 2978 /* 2979 * When Link is lost sometimes there is work still in the TX ring 2980 * which will result in a watchdog, rather than allow that do an 2981 * attempted cleanup and then reinit here. Note that this has been 2982 * seens mostly with fiber adapters. 2983 */ 2984 static void 2985 em_tx_purge(struct adapter *adapter) 2986 { 2987 struct ifnet *ifp = &adapter->arpcom.ac_if; 2988 2989 if (!adapter->link_active && ifp->if_timer) { 2990 em_tx_collect(adapter); 2991 if (ifp->if_timer) { 2992 if_printf(ifp, "Link lost, TX pending, reinit\n"); 2993 ifp->if_timer = 0; 2994 em_init(adapter); 2995 } 2996 } 2997 } 2998 2999 static int 3000 em_newbuf(struct adapter *adapter, int i, int init) 3001 { 3002 struct mbuf *m; 3003 bus_dma_segment_t seg; 3004 bus_dmamap_t map; 3005 struct em_buffer *rx_buffer; 3006 int error, nseg; 3007 3008 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 3009 if (m == NULL) { 3010 adapter->mbuf_cluster_failed++; 3011 if (init) { 3012 if_printf(&adapter->arpcom.ac_if, 3013 "Unable to allocate RX mbuf\n"); 3014 } 3015 return (ENOBUFS); 3016 } 3017 m->m_len = m->m_pkthdr.len = MCLBYTES; 3018 3019 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN) 3020 m_adj(m, ETHER_ALIGN); 3021 3022 error = bus_dmamap_load_mbuf_segment(adapter->rxtag, 3023 adapter->rx_sparemap, m, 3024 &seg, 1, &nseg, BUS_DMA_NOWAIT); 3025 if (error) { 3026 m_freem(m); 3027 if (init) { 3028 if_printf(&adapter->arpcom.ac_if, 3029 "Unable to load RX mbuf\n"); 3030 } 3031 return (error); 3032 } 3033 3034 rx_buffer = &adapter->rx_buffer_area[i]; 3035 if (rx_buffer->m_head != NULL) 3036 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 3037 3038 map = rx_buffer->map; 3039 rx_buffer->map = adapter->rx_sparemap; 3040 adapter->rx_sparemap = map; 3041 3042 rx_buffer->m_head = m; 3043 3044 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr); 3045 return (0); 3046 } 3047 3048 static int 3049 em_create_rx_ring(struct adapter *adapter) 3050 { 3051 device_t dev = adapter->dev; 3052 struct em_buffer *rx_buffer; 3053 int i, error; 3054 3055 adapter->rx_buffer_area = 3056 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc, 3057 M_DEVBUF, M_WAITOK | M_ZERO); 3058 3059 /* 3060 * Create DMA tag for rx buffers 3061 */ 3062 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 3063 1, 0, /* alignment, bounds */ 3064 BUS_SPACE_MAXADDR, /* lowaddr */ 3065 BUS_SPACE_MAXADDR, /* highaddr */ 3066 NULL, NULL, /* filter, filterarg */ 3067 MCLBYTES, /* maxsize */ 3068 1, /* nsegments */ 3069 MCLBYTES, /* maxsegsize */ 3070 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 3071 &adapter->rxtag); 3072 if (error) { 3073 device_printf(dev, "Unable to allocate RX DMA tag\n"); 3074 kfree(adapter->rx_buffer_area, M_DEVBUF); 3075 adapter->rx_buffer_area = NULL; 3076 return error; 3077 } 3078 3079 /* 3080 * Create spare DMA map for rx buffers 3081 */ 3082 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3083 &adapter->rx_sparemap); 3084 if (error) { 3085 device_printf(dev, "Unable to create spare RX DMA map\n"); 3086 bus_dma_tag_destroy(adapter->rxtag); 3087 kfree(adapter->rx_buffer_area, M_DEVBUF); 3088 adapter->rx_buffer_area = NULL; 3089 return error; 3090 } 3091 3092 /* 3093 * Create DMA maps for rx buffers 3094 */ 3095 for (i = 0; i < adapter->num_rx_desc; i++) { 3096 rx_buffer = &adapter->rx_buffer_area[i]; 3097 3098 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3099 &rx_buffer->map); 3100 if (error) { 3101 device_printf(dev, "Unable to create RX DMA map\n"); 3102 em_destroy_rx_ring(adapter, i); 3103 return error; 3104 } 3105 } 3106 return (0); 3107 } 3108 3109 static int 3110 em_init_rx_ring(struct adapter *adapter) 3111 { 3112 int i, error; 3113 3114 /* Reset descriptor ring */ 3115 bzero(adapter->rx_desc_base, 3116 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 3117 3118 /* Allocate new ones. */ 3119 for (i = 0; i < adapter->num_rx_desc; i++) { 3120 error = em_newbuf(adapter, i, 1); 3121 if (error) 3122 return (error); 3123 } 3124 3125 /* Setup our descriptor pointers */ 3126 adapter->next_rx_desc_to_check = 0; 3127 3128 return (0); 3129 } 3130 3131 static void 3132 em_init_rx_unit(struct adapter *adapter) 3133 { 3134 struct ifnet *ifp = &adapter->arpcom.ac_if; 3135 uint64_t bus_addr; 3136 uint32_t rctl; 3137 3138 /* 3139 * Make sure receives are disabled while setting 3140 * up the descriptor ring 3141 */ 3142 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3143 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3144 3145 if (adapter->hw.mac.type >= e1000_82540) { 3146 uint32_t itr; 3147 3148 /* 3149 * Set the interrupt throttling rate. Value is calculated 3150 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 3151 */ 3152 if (adapter->int_throttle_ceil) 3153 itr = 1000000000 / 256 / adapter->int_throttle_ceil; 3154 else 3155 itr = 0; 3156 em_set_itr(adapter, itr); 3157 } 3158 3159 /* Disable accelerated ackknowledge */ 3160 if (adapter->hw.mac.type == e1000_82574) { 3161 E1000_WRITE_REG(&adapter->hw, 3162 E1000_RFCTL, E1000_RFCTL_ACK_DIS); 3163 } 3164 3165 /* Receive Checksum Offload for TCP and UDP */ 3166 if (ifp->if_capenable & IFCAP_RXCSUM) { 3167 uint32_t rxcsum; 3168 3169 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 3170 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3171 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum); 3172 } 3173 3174 /* 3175 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3176 * long latencies are observed, like Lenovo X60. This 3177 * change eliminates the problem, but since having positive 3178 * values in RDTR is a known source of problems on other 3179 * platforms another solution is being sought. 3180 */ 3181 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) { 3182 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573); 3183 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573); 3184 } 3185 3186 /* 3187 * Setup the Base and Length of the Rx Descriptor Ring 3188 */ 3189 bus_addr = adapter->rxdma.dma_paddr; 3190 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 3191 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 3192 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 3193 (uint32_t)(bus_addr >> 32)); 3194 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 3195 (uint32_t)bus_addr); 3196 3197 /* 3198 * Setup the HW Rx Head and Tail Descriptor Pointers 3199 */ 3200 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 3201 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 3202 3203 /* Set early receive threshold on appropriate hw */ 3204 if (((adapter->hw.mac.type == e1000_ich9lan) || 3205 (adapter->hw.mac.type == e1000_pch2lan) || 3206 (adapter->hw.mac.type == e1000_ich10lan)) && 3207 (ifp->if_mtu > ETHERMTU)) { 3208 uint32_t rxdctl; 3209 3210 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0)); 3211 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3); 3212 E1000_WRITE_REG(&adapter->hw, E1000_ERT, 0x100 | (1 << 13)); 3213 } 3214 3215 if (adapter->hw.mac.type == e1000_pch2lan) { 3216 if (ifp->if_mtu > ETHERMTU) 3217 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE); 3218 else 3219 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE); 3220 } 3221 3222 /* Setup the Receive Control Register */ 3223 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3224 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3225 E1000_RCTL_RDMTS_HALF | 3226 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3227 3228 /* Make sure VLAN Filters are off */ 3229 rctl &= ~E1000_RCTL_VFE; 3230 3231 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 3232 rctl |= E1000_RCTL_SBP; 3233 else 3234 rctl &= ~E1000_RCTL_SBP; 3235 3236 switch (adapter->rx_buffer_len) { 3237 default: 3238 case 2048: 3239 rctl |= E1000_RCTL_SZ_2048; 3240 break; 3241 3242 case 4096: 3243 rctl |= E1000_RCTL_SZ_4096 | 3244 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3245 break; 3246 3247 case 8192: 3248 rctl |= E1000_RCTL_SZ_8192 | 3249 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3250 break; 3251 3252 case 16384: 3253 rctl |= E1000_RCTL_SZ_16384 | 3254 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3255 break; 3256 } 3257 3258 if (ifp->if_mtu > ETHERMTU) 3259 rctl |= E1000_RCTL_LPE; 3260 else 3261 rctl &= ~E1000_RCTL_LPE; 3262 3263 /* Enable Receives */ 3264 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3265 } 3266 3267 static void 3268 em_destroy_rx_ring(struct adapter *adapter, int ndesc) 3269 { 3270 struct em_buffer *rx_buffer; 3271 int i; 3272 3273 if (adapter->rx_buffer_area == NULL) 3274 return; 3275 3276 for (i = 0; i < ndesc; i++) { 3277 rx_buffer = &adapter->rx_buffer_area[i]; 3278 3279 KKASSERT(rx_buffer->m_head == NULL); 3280 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map); 3281 } 3282 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 3283 bus_dma_tag_destroy(adapter->rxtag); 3284 3285 kfree(adapter->rx_buffer_area, M_DEVBUF); 3286 adapter->rx_buffer_area = NULL; 3287 } 3288 3289 static void 3290 em_rxeof(struct adapter *adapter, int count) 3291 { 3292 struct ifnet *ifp = &adapter->arpcom.ac_if; 3293 uint8_t status, accept_frame = 0, eop = 0; 3294 uint16_t len, desc_len, prev_len_adj; 3295 struct e1000_rx_desc *current_desc; 3296 struct mbuf *mp; 3297 int i; 3298 3299 i = adapter->next_rx_desc_to_check; 3300 current_desc = &adapter->rx_desc_base[i]; 3301 3302 if (!(current_desc->status & E1000_RXD_STAT_DD)) 3303 return; 3304 3305 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) { 3306 struct mbuf *m = NULL; 3307 3308 logif(pkt_receive); 3309 3310 mp = adapter->rx_buffer_area[i].m_head; 3311 3312 /* 3313 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3314 * needs to access the last received byte in the mbuf. 3315 */ 3316 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3317 BUS_DMASYNC_POSTREAD); 3318 3319 accept_frame = 1; 3320 prev_len_adj = 0; 3321 desc_len = le16toh(current_desc->length); 3322 status = current_desc->status; 3323 if (status & E1000_RXD_STAT_EOP) { 3324 count--; 3325 eop = 1; 3326 if (desc_len < ETHER_CRC_LEN) { 3327 len = 0; 3328 prev_len_adj = ETHER_CRC_LEN - desc_len; 3329 } else { 3330 len = desc_len - ETHER_CRC_LEN; 3331 } 3332 } else { 3333 eop = 0; 3334 len = desc_len; 3335 } 3336 3337 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3338 uint8_t last_byte; 3339 uint32_t pkt_len = desc_len; 3340 3341 if (adapter->fmp != NULL) 3342 pkt_len += adapter->fmp->m_pkthdr.len; 3343 3344 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3345 if (TBI_ACCEPT(&adapter->hw, status, 3346 current_desc->errors, pkt_len, last_byte, 3347 adapter->min_frame_size, adapter->max_frame_size)) { 3348 e1000_tbi_adjust_stats_82543(&adapter->hw, 3349 &adapter->stats, pkt_len, 3350 adapter->hw.mac.addr, 3351 adapter->max_frame_size); 3352 if (len > 0) 3353 len--; 3354 } else { 3355 accept_frame = 0; 3356 } 3357 } 3358 3359 if (accept_frame) { 3360 if (em_newbuf(adapter, i, 0) != 0) { 3361 ifp->if_iqdrops++; 3362 goto discard; 3363 } 3364 3365 /* Assign correct length to the current fragment */ 3366 mp->m_len = len; 3367 3368 if (adapter->fmp == NULL) { 3369 mp->m_pkthdr.len = len; 3370 adapter->fmp = mp; /* Store the first mbuf */ 3371 adapter->lmp = mp; 3372 } else { 3373 /* 3374 * Chain mbuf's together 3375 */ 3376 3377 /* 3378 * Adjust length of previous mbuf in chain if 3379 * we received less than 4 bytes in the last 3380 * descriptor. 3381 */ 3382 if (prev_len_adj > 0) { 3383 adapter->lmp->m_len -= prev_len_adj; 3384 adapter->fmp->m_pkthdr.len -= 3385 prev_len_adj; 3386 } 3387 adapter->lmp->m_next = mp; 3388 adapter->lmp = adapter->lmp->m_next; 3389 adapter->fmp->m_pkthdr.len += len; 3390 } 3391 3392 if (eop) { 3393 adapter->fmp->m_pkthdr.rcvif = ifp; 3394 ifp->if_ipackets++; 3395 3396 if (ifp->if_capenable & IFCAP_RXCSUM) { 3397 em_rxcsum(adapter, current_desc, 3398 adapter->fmp); 3399 } 3400 3401 if (status & E1000_RXD_STAT_VP) { 3402 adapter->fmp->m_pkthdr.ether_vlantag = 3403 (le16toh(current_desc->special) & 3404 E1000_RXD_SPC_VLAN_MASK); 3405 adapter->fmp->m_flags |= M_VLANTAG; 3406 } 3407 m = adapter->fmp; 3408 adapter->fmp = NULL; 3409 adapter->lmp = NULL; 3410 } 3411 } else { 3412 ifp->if_ierrors++; 3413 discard: 3414 #ifdef foo 3415 /* Reuse loaded DMA map and just update mbuf chain */ 3416 mp = adapter->rx_buffer_area[i].m_head; 3417 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 3418 mp->m_data = mp->m_ext.ext_buf; 3419 mp->m_next = NULL; 3420 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 3421 m_adj(mp, ETHER_ALIGN); 3422 #endif 3423 if (adapter->fmp != NULL) { 3424 m_freem(adapter->fmp); 3425 adapter->fmp = NULL; 3426 adapter->lmp = NULL; 3427 } 3428 m = NULL; 3429 } 3430 3431 /* Zero out the receive descriptors status. */ 3432 current_desc->status = 0; 3433 3434 if (m != NULL) 3435 ifp->if_input(ifp, m); 3436 3437 /* Advance our pointers to the next descriptor. */ 3438 if (++i == adapter->num_rx_desc) 3439 i = 0; 3440 current_desc = &adapter->rx_desc_base[i]; 3441 } 3442 adapter->next_rx_desc_to_check = i; 3443 3444 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3445 if (--i < 0) 3446 i = adapter->num_rx_desc - 1; 3447 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 3448 } 3449 3450 static void 3451 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc, 3452 struct mbuf *mp) 3453 { 3454 /* 82543 or newer only */ 3455 if (adapter->hw.mac.type < e1000_82543 || 3456 /* Ignore Checksum bit is set */ 3457 (rx_desc->status & E1000_RXD_STAT_IXSM)) 3458 return; 3459 3460 if ((rx_desc->status & E1000_RXD_STAT_IPCS) && 3461 !(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3462 /* IP Checksum Good */ 3463 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 3464 } 3465 3466 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) && 3467 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3468 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3469 CSUM_PSEUDO_HDR | 3470 CSUM_FRAG_NOT_CHECKED; 3471 mp->m_pkthdr.csum_data = htons(0xffff); 3472 } 3473 } 3474 3475 static void 3476 em_enable_intr(struct adapter *adapter) 3477 { 3478 uint32_t ims_mask = IMS_ENABLE_MASK; 3479 3480 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer); 3481 3482 #if 0 3483 /* XXX MSIX */ 3484 if (adapter->hw.mac.type == e1000_82574) { 3485 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK); 3486 ims_mask |= EM_MSIX_MASK; 3487 } 3488 #endif 3489 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask); 3490 } 3491 3492 static void 3493 em_disable_intr(struct adapter *adapter) 3494 { 3495 uint32_t clear = 0xffffffff; 3496 3497 /* 3498 * The first version of 82542 had an errata where when link was forced 3499 * it would stay up even up even if the cable was disconnected. 3500 * Sequence errors were used to detect the disconnect and then the 3501 * driver would unforce the link. This code in the in the ISR. For 3502 * this to work correctly the Sequence error interrupt had to be 3503 * enabled all the time. 3504 */ 3505 if (adapter->hw.mac.type == e1000_82542 && 3506 adapter->hw.revision_id == E1000_REVISION_2) 3507 clear &= ~E1000_ICR_RXSEQ; 3508 else if (adapter->hw.mac.type == e1000_82574) 3509 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0); 3510 3511 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear); 3512 3513 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer); 3514 } 3515 3516 /* 3517 * Bit of a misnomer, what this really means is 3518 * to enable OS management of the system... aka 3519 * to disable special hardware management features 3520 */ 3521 static void 3522 em_get_mgmt(struct adapter *adapter) 3523 { 3524 /* A shared code workaround */ 3525 #define E1000_82542_MANC2H E1000_MANC2H 3526 if (adapter->has_manage) { 3527 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3528 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3529 3530 /* disable hardware interception of ARP */ 3531 manc &= ~(E1000_MANC_ARP_EN); 3532 3533 /* enable receiving management packets to the host */ 3534 if (adapter->hw.mac.type >= e1000_82571) { 3535 manc |= E1000_MANC_EN_MNG2HOST; 3536 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3537 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3538 manc2h |= E1000_MNG2HOST_PORT_623; 3539 manc2h |= E1000_MNG2HOST_PORT_664; 3540 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3541 } 3542 3543 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3544 } 3545 } 3546 3547 /* 3548 * Give control back to hardware management 3549 * controller if there is one. 3550 */ 3551 static void 3552 em_rel_mgmt(struct adapter *adapter) 3553 { 3554 if (adapter->has_manage) { 3555 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3556 3557 /* re-enable hardware interception of ARP */ 3558 manc |= E1000_MANC_ARP_EN; 3559 3560 if (adapter->hw.mac.type >= e1000_82571) 3561 manc &= ~E1000_MANC_EN_MNG2HOST; 3562 3563 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3564 } 3565 } 3566 3567 /* 3568 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3569 * For ASF and Pass Through versions of f/w this means that 3570 * the driver is loaded. For AMT version (only with 82573) 3571 * of the f/w this means that the network i/f is open. 3572 */ 3573 static void 3574 em_get_hw_control(struct adapter *adapter) 3575 { 3576 /* Let firmware know the driver has taken over */ 3577 if (adapter->hw.mac.type == e1000_82573) { 3578 uint32_t swsm; 3579 3580 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3581 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3582 swsm | E1000_SWSM_DRV_LOAD); 3583 } else { 3584 uint32_t ctrl_ext; 3585 3586 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3587 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3588 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3589 } 3590 adapter->control_hw = 1; 3591 } 3592 3593 /* 3594 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3595 * For ASF and Pass Through versions of f/w this means that the 3596 * driver is no longer loaded. For AMT version (only with 82573) 3597 * of the f/w this means that the network i/f is closed. 3598 */ 3599 static void 3600 em_rel_hw_control(struct adapter *adapter) 3601 { 3602 if (!adapter->control_hw) 3603 return; 3604 adapter->control_hw = 0; 3605 3606 /* Let firmware taken over control of h/w */ 3607 if (adapter->hw.mac.type == e1000_82573) { 3608 uint32_t swsm; 3609 3610 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3611 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3612 swsm & ~E1000_SWSM_DRV_LOAD); 3613 } else { 3614 uint32_t ctrl_ext; 3615 3616 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3617 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3618 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3619 } 3620 } 3621 3622 static int 3623 em_is_valid_eaddr(const uint8_t *addr) 3624 { 3625 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3626 3627 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3628 return (FALSE); 3629 3630 return (TRUE); 3631 } 3632 3633 /* 3634 * Enable PCI Wake On Lan capability 3635 */ 3636 void 3637 em_enable_wol(device_t dev) 3638 { 3639 uint16_t cap, status; 3640 uint8_t id; 3641 3642 /* First find the capabilities pointer*/ 3643 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3644 3645 /* Read the PM Capabilities */ 3646 id = pci_read_config(dev, cap, 1); 3647 if (id != PCIY_PMG) /* Something wrong */ 3648 return; 3649 3650 /* 3651 * OK, we have the power capabilities, 3652 * so now get the status register 3653 */ 3654 cap += PCIR_POWER_STATUS; 3655 status = pci_read_config(dev, cap, 2); 3656 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3657 pci_write_config(dev, cap, status, 2); 3658 } 3659 3660 3661 /* 3662 * 82544 Coexistence issue workaround. 3663 * There are 2 issues. 3664 * 1. Transmit Hang issue. 3665 * To detect this issue, following equation can be used... 3666 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3667 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3668 * 3669 * 2. DAC issue. 3670 * To detect this issue, following equation can be used... 3671 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3672 * If SUM[3:0] is in between 9 to c, we will have this issue. 3673 * 3674 * WORKAROUND: 3675 * Make sure we do not have ending address 3676 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3677 */ 3678 static uint32_t 3679 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array) 3680 { 3681 uint32_t safe_terminator; 3682 3683 /* 3684 * Since issue is sensitive to length and address. 3685 * Let us first check the address... 3686 */ 3687 if (length <= 4) { 3688 desc_array->descriptor[0].address = address; 3689 desc_array->descriptor[0].length = length; 3690 desc_array->elements = 1; 3691 return (desc_array->elements); 3692 } 3693 3694 safe_terminator = 3695 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3696 3697 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3698 if (safe_terminator == 0 || 3699 (safe_terminator > 4 && safe_terminator < 9) || 3700 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 3701 desc_array->descriptor[0].address = address; 3702 desc_array->descriptor[0].length = length; 3703 desc_array->elements = 1; 3704 return (desc_array->elements); 3705 } 3706 3707 desc_array->descriptor[0].address = address; 3708 desc_array->descriptor[0].length = length - 4; 3709 desc_array->descriptor[1].address = address + (length - 4); 3710 desc_array->descriptor[1].length = 4; 3711 desc_array->elements = 2; 3712 return (desc_array->elements); 3713 } 3714 3715 static void 3716 em_update_stats(struct adapter *adapter) 3717 { 3718 struct ifnet *ifp = &adapter->arpcom.ac_if; 3719 3720 if (adapter->hw.phy.media_type == e1000_media_type_copper || 3721 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3722 adapter->stats.symerrs += 3723 E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3724 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3725 } 3726 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3727 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3728 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3729 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3730 3731 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3732 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3733 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3734 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3735 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3736 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3737 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3738 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3739 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3740 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3741 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3742 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3743 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3744 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3745 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3746 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3747 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3748 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3749 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3750 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3751 3752 /* For the 64-bit byte counters the low dword must be read first. */ 3753 /* Both registers clear on the read of the high dword */ 3754 3755 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 3756 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 3757 3758 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3759 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3760 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3761 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3762 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3763 3764 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3765 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3766 3767 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3768 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3769 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3770 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3771 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3772 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3773 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3774 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3775 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3776 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3777 3778 if (adapter->hw.mac.type >= e1000_82543) { 3779 adapter->stats.algnerrc += 3780 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3781 adapter->stats.rxerrc += 3782 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3783 adapter->stats.tncrs += 3784 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3785 adapter->stats.cexterr += 3786 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3787 adapter->stats.tsctc += 3788 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3789 adapter->stats.tsctfc += 3790 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3791 } 3792 3793 ifp->if_collisions = adapter->stats.colc; 3794 3795 /* Rx Errors */ 3796 ifp->if_ierrors = 3797 adapter->dropped_pkts + adapter->stats.rxerrc + 3798 adapter->stats.crcerrs + adapter->stats.algnerrc + 3799 adapter->stats.ruc + adapter->stats.roc + 3800 adapter->stats.mpc + adapter->stats.cexterr; 3801 3802 /* Tx Errors */ 3803 ifp->if_oerrors = 3804 adapter->stats.ecol + adapter->stats.latecol + 3805 adapter->watchdog_events; 3806 } 3807 3808 static void 3809 em_print_debug_info(struct adapter *adapter) 3810 { 3811 device_t dev = adapter->dev; 3812 uint8_t *hw_addr = adapter->hw.hw_addr; 3813 3814 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3815 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3816 E1000_READ_REG(&adapter->hw, E1000_CTRL), 3817 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 3818 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3819 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3820 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 3821 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3822 adapter->hw.fc.high_water, 3823 adapter->hw.fc.low_water); 3824 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3825 E1000_READ_REG(&adapter->hw, E1000_TIDV), 3826 E1000_READ_REG(&adapter->hw, E1000_TADV)); 3827 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3828 E1000_READ_REG(&adapter->hw, E1000_RDTR), 3829 E1000_READ_REG(&adapter->hw, E1000_RADV)); 3830 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3831 (long long)adapter->tx_fifo_wrk_cnt, 3832 (long long)adapter->tx_fifo_reset_cnt); 3833 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3834 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 3835 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 3836 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3837 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 3838 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 3839 device_printf(dev, "Num Tx descriptors avail = %d\n", 3840 adapter->num_tx_desc_avail); 3841 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3842 adapter->no_tx_desc_avail1); 3843 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3844 adapter->no_tx_desc_avail2); 3845 device_printf(dev, "Std mbuf failed = %ld\n", 3846 adapter->mbuf_alloc_failed); 3847 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3848 adapter->mbuf_cluster_failed); 3849 device_printf(dev, "Driver dropped packets = %ld\n", 3850 adapter->dropped_pkts); 3851 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3852 adapter->no_tx_dma_setup); 3853 3854 device_printf(dev, "TXCSUM try pullup = %lu\n", 3855 adapter->tx_csum_try_pullup); 3856 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n", 3857 adapter->tx_csum_pullup1); 3858 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n", 3859 adapter->tx_csum_pullup1_failed); 3860 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n", 3861 adapter->tx_csum_pullup2); 3862 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n", 3863 adapter->tx_csum_pullup2_failed); 3864 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n", 3865 adapter->tx_csum_drop1); 3866 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n", 3867 adapter->tx_csum_drop2); 3868 } 3869 3870 static void 3871 em_print_hw_stats(struct adapter *adapter) 3872 { 3873 device_t dev = adapter->dev; 3874 3875 device_printf(dev, "Excessive collisions = %lld\n", 3876 (long long)adapter->stats.ecol); 3877 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3878 device_printf(dev, "Symbol errors = %lld\n", 3879 (long long)adapter->stats.symerrs); 3880 #endif 3881 device_printf(dev, "Sequence errors = %lld\n", 3882 (long long)adapter->stats.sec); 3883 device_printf(dev, "Defer count = %lld\n", 3884 (long long)adapter->stats.dc); 3885 device_printf(dev, "Missed Packets = %lld\n", 3886 (long long)adapter->stats.mpc); 3887 device_printf(dev, "Receive No Buffers = %lld\n", 3888 (long long)adapter->stats.rnbc); 3889 /* RLEC is inaccurate on some hardware, calculate our own. */ 3890 device_printf(dev, "Receive Length Errors = %lld\n", 3891 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 3892 device_printf(dev, "Receive errors = %lld\n", 3893 (long long)adapter->stats.rxerrc); 3894 device_printf(dev, "Crc errors = %lld\n", 3895 (long long)adapter->stats.crcerrs); 3896 device_printf(dev, "Alignment errors = %lld\n", 3897 (long long)adapter->stats.algnerrc); 3898 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3899 (long long)adapter->stats.cexterr); 3900 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 3901 device_printf(dev, "watchdog timeouts = %ld\n", 3902 adapter->watchdog_events); 3903 device_printf(dev, "XON Rcvd = %lld\n", 3904 (long long)adapter->stats.xonrxc); 3905 device_printf(dev, "XON Xmtd = %lld\n", 3906 (long long)adapter->stats.xontxc); 3907 device_printf(dev, "XOFF Rcvd = %lld\n", 3908 (long long)adapter->stats.xoffrxc); 3909 device_printf(dev, "XOFF Xmtd = %lld\n", 3910 (long long)adapter->stats.xofftxc); 3911 device_printf(dev, "Good Packets Rcvd = %lld\n", 3912 (long long)adapter->stats.gprc); 3913 device_printf(dev, "Good Packets Xmtd = %lld\n", 3914 (long long)adapter->stats.gptc); 3915 } 3916 3917 static void 3918 em_print_nvm_info(struct adapter *adapter) 3919 { 3920 uint16_t eeprom_data; 3921 int i, j, row = 0; 3922 3923 /* Its a bit crude, but it gets the job done */ 3924 kprintf("\nInterface EEPROM Dump:\n"); 3925 kprintf("Offset\n0x0000 "); 3926 for (i = 0, j = 0; i < 32; i++, j++) { 3927 if (j == 8) { /* Make the offset block */ 3928 j = 0; ++row; 3929 kprintf("\n0x00%x0 ",row); 3930 } 3931 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 3932 kprintf("%04x ", eeprom_data); 3933 } 3934 kprintf("\n"); 3935 } 3936 3937 static int 3938 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3939 { 3940 struct adapter *adapter; 3941 struct ifnet *ifp; 3942 int error, result; 3943 3944 result = -1; 3945 error = sysctl_handle_int(oidp, &result, 0, req); 3946 if (error || !req->newptr) 3947 return (error); 3948 3949 adapter = (struct adapter *)arg1; 3950 ifp = &adapter->arpcom.ac_if; 3951 3952 lwkt_serialize_enter(ifp->if_serializer); 3953 3954 if (result == 1) 3955 em_print_debug_info(adapter); 3956 3957 /* 3958 * This value will cause a hex dump of the 3959 * first 32 16-bit words of the EEPROM to 3960 * the screen. 3961 */ 3962 if (result == 2) 3963 em_print_nvm_info(adapter); 3964 3965 lwkt_serialize_exit(ifp->if_serializer); 3966 3967 return (error); 3968 } 3969 3970 static int 3971 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 3972 { 3973 int error, result; 3974 3975 result = -1; 3976 error = sysctl_handle_int(oidp, &result, 0, req); 3977 if (error || !req->newptr) 3978 return (error); 3979 3980 if (result == 1) { 3981 struct adapter *adapter = (struct adapter *)arg1; 3982 struct ifnet *ifp = &adapter->arpcom.ac_if; 3983 3984 lwkt_serialize_enter(ifp->if_serializer); 3985 em_print_hw_stats(adapter); 3986 lwkt_serialize_exit(ifp->if_serializer); 3987 } 3988 return (error); 3989 } 3990 3991 static void 3992 em_add_sysctl(struct adapter *adapter) 3993 { 3994 sysctl_ctx_init(&adapter->sysctl_ctx); 3995 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx, 3996 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 3997 device_get_nameunit(adapter->dev), 3998 CTLFLAG_RD, 0, ""); 3999 if (adapter->sysctl_tree == NULL) { 4000 device_printf(adapter->dev, "can't add sysctl node\n"); 4001 } else { 4002 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4003 SYSCTL_CHILDREN(adapter->sysctl_tree), 4004 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4005 em_sysctl_debug_info, "I", "Debug Information"); 4006 4007 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4008 SYSCTL_CHILDREN(adapter->sysctl_tree), 4009 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4010 em_sysctl_stats, "I", "Statistics"); 4011 4012 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4013 SYSCTL_CHILDREN(adapter->sysctl_tree), 4014 OID_AUTO, "rxd", CTLFLAG_RD, 4015 &adapter->num_rx_desc, 0, NULL); 4016 SYSCTL_ADD_INT(&adapter->sysctl_ctx, 4017 SYSCTL_CHILDREN(adapter->sysctl_tree), 4018 OID_AUTO, "txd", CTLFLAG_RD, 4019 &adapter->num_tx_desc, 0, NULL); 4020 4021 if (adapter->hw.mac.type >= e1000_82540) { 4022 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4023 SYSCTL_CHILDREN(adapter->sysctl_tree), 4024 OID_AUTO, "int_throttle_ceil", 4025 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4026 em_sysctl_int_throttle, "I", 4027 "interrupt throttling rate"); 4028 } 4029 SYSCTL_ADD_PROC(&adapter->sysctl_ctx, 4030 SYSCTL_CHILDREN(adapter->sysctl_tree), 4031 OID_AUTO, "int_tx_nsegs", 4032 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4033 em_sysctl_int_tx_nsegs, "I", 4034 "# segments per TX interrupt"); 4035 } 4036 } 4037 4038 static int 4039 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 4040 { 4041 struct adapter *adapter = (void *)arg1; 4042 struct ifnet *ifp = &adapter->arpcom.ac_if; 4043 int error, throttle; 4044 4045 throttle = adapter->int_throttle_ceil; 4046 error = sysctl_handle_int(oidp, &throttle, 0, req); 4047 if (error || req->newptr == NULL) 4048 return error; 4049 if (throttle < 0 || throttle > 1000000000 / 256) 4050 return EINVAL; 4051 4052 if (throttle) { 4053 /* 4054 * Set the interrupt throttling rate in 256ns increments, 4055 * recalculate sysctl value assignment to get exact frequency. 4056 */ 4057 throttle = 1000000000 / 256 / throttle; 4058 4059 /* Upper 16bits of ITR is reserved and should be zero */ 4060 if (throttle & 0xffff0000) 4061 return EINVAL; 4062 } 4063 4064 lwkt_serialize_enter(ifp->if_serializer); 4065 4066 if (throttle) 4067 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 4068 else 4069 adapter->int_throttle_ceil = 0; 4070 4071 if (ifp->if_flags & IFF_RUNNING) 4072 em_set_itr(adapter, throttle); 4073 4074 lwkt_serialize_exit(ifp->if_serializer); 4075 4076 if (bootverbose) { 4077 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 4078 adapter->int_throttle_ceil); 4079 } 4080 return 0; 4081 } 4082 4083 static int 4084 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 4085 { 4086 struct adapter *adapter = (void *)arg1; 4087 struct ifnet *ifp = &adapter->arpcom.ac_if; 4088 int error, segs; 4089 4090 segs = adapter->tx_int_nsegs; 4091 error = sysctl_handle_int(oidp, &segs, 0, req); 4092 if (error || req->newptr == NULL) 4093 return error; 4094 if (segs <= 0) 4095 return EINVAL; 4096 4097 lwkt_serialize_enter(ifp->if_serializer); 4098 4099 /* 4100 * Don't allow int_tx_nsegs to become: 4101 * o Less the oact_tx_desc 4102 * o Too large that no TX desc will cause TX interrupt to 4103 * be generated (OACTIVE will never recover) 4104 * o Too small that will cause tx_dd[] overflow 4105 */ 4106 if (segs < adapter->oact_tx_desc || 4107 segs >= adapter->num_tx_desc - adapter->oact_tx_desc || 4108 segs < adapter->num_tx_desc / EM_TXDD_SAFE) { 4109 error = EINVAL; 4110 } else { 4111 error = 0; 4112 adapter->tx_int_nsegs = segs; 4113 } 4114 4115 lwkt_serialize_exit(ifp->if_serializer); 4116 4117 return error; 4118 } 4119 4120 static void 4121 em_set_itr(struct adapter *adapter, uint32_t itr) 4122 { 4123 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr); 4124 if (adapter->hw.mac.type == e1000_82574) { 4125 int i; 4126 4127 /* 4128 * When using MSIX interrupts we need to 4129 * throttle using the EITR register 4130 */ 4131 for (i = 0; i < 4; ++i) { 4132 E1000_WRITE_REG(&adapter->hw, 4133 E1000_EITR_82574(i), itr); 4134 } 4135 } 4136 } 4137 4138 static void 4139 em_disable_aspm(struct adapter *adapter) 4140 { 4141 uint16_t link_cap, link_ctrl, disable; 4142 uint8_t pcie_ptr, reg; 4143 device_t dev = adapter->dev; 4144 4145 switch (adapter->hw.mac.type) { 4146 case e1000_82571: 4147 case e1000_82572: 4148 case e1000_82573: 4149 /* 4150 * 82573 specification update 4151 * #8 disable L0s 4152 * #41 disable L1 4153 * 4154 * 82571/82572 specification update 4155 # #13 disable L1 4156 * #68 disable L0s 4157 */ 4158 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 4159 break; 4160 4161 case e1000_82574: 4162 case e1000_82583: 4163 /* 4164 * 82574 specification update #20 4165 * 82583 specification update #9 4166 * 4167 * There is no need to disable L1 4168 */ 4169 disable = PCIEM_LNKCTL_ASPM_L0S; 4170 break; 4171 4172 default: 4173 return; 4174 } 4175 4176 pcie_ptr = pci_get_pciecap_ptr(dev); 4177 if (pcie_ptr == 0) 4178 return; 4179 4180 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 4181 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 4182 return; 4183 4184 if (bootverbose) { 4185 if_printf(&adapter->arpcom.ac_if, 4186 "disable ASPM %#02x\n", disable); 4187 } 4188 4189 reg = pcie_ptr + PCIER_LINKCTRL; 4190 link_ctrl = pci_read_config(dev, reg, 2); 4191 link_ctrl &= ~disable; 4192 pci_write_config(dev, reg, link_ctrl, 2); 4193 } 4194