1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2014, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 */ 67 /* 68 * SERIALIZATION API RULES: 69 * 70 * - We must call lwkt_serialize_handler_enable() prior to enabling the 71 * hardware interrupt and lwkt_serialize_handler_disable() after disabling 72 * the hardware interrupt in order to avoid handler execution races from 73 * scheduled interrupt threads. 74 */ 75 76 #include "opt_ifpoll.h" 77 78 #include <sys/param.h> 79 #include <sys/bus.h> 80 #include <sys/endian.h> 81 #include <sys/interrupt.h> 82 #include <sys/kernel.h> 83 #include <sys/ktr.h> 84 #include <sys/malloc.h> 85 #include <sys/mbuf.h> 86 #include <sys/proc.h> 87 #include <sys/rman.h> 88 #include <sys/serialize.h> 89 #include <sys/socket.h> 90 #include <sys/sockio.h> 91 #include <sys/sysctl.h> 92 #include <sys/systm.h> 93 94 #include <net/bpf.h> 95 #include <net/ethernet.h> 96 #include <net/if.h> 97 #include <net/if_arp.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_poll.h> 101 #include <net/ifq_var.h> 102 #include <net/vlan/if_vlan_var.h> 103 #include <net/vlan/if_vlan_ether.h> 104 105 #include <netinet/ip.h> 106 #include <netinet/tcp.h> 107 #include <netinet/udp.h> 108 109 #include <bus/pci/pcivar.h> 110 #include <bus/pci/pcireg.h> 111 112 #include <dev/netif/ig_hal/e1000_api.h> 113 #include <dev/netif/ig_hal/e1000_82571.h> 114 #include <dev/netif/em/if_em.h> 115 116 #define DEBUG_HW 0 117 118 #define EM_NAME "Intel(R) PRO/1000 Network Connection " 119 #define EM_VER " 7.4.2" 120 121 #define _EM_DEVICE(id, ret) \ 122 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER } 123 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100) 124 #define EM_DEVICE(id) _EM_DEVICE(id, 0) 125 #define EM_DEVICE_NULL { 0, 0, 0, NULL } 126 127 static const struct em_vendor_info em_vendor_info_array[] = { 128 EM_DEVICE(82540EM), 129 EM_DEVICE(82540EM_LOM), 130 EM_DEVICE(82540EP), 131 EM_DEVICE(82540EP_LOM), 132 EM_DEVICE(82540EP_LP), 133 134 EM_DEVICE(82541EI), 135 EM_DEVICE(82541ER), 136 EM_DEVICE(82541ER_LOM), 137 EM_DEVICE(82541EI_MOBILE), 138 EM_DEVICE(82541GI), 139 EM_DEVICE(82541GI_LF), 140 EM_DEVICE(82541GI_MOBILE), 141 142 EM_DEVICE(82542), 143 144 EM_DEVICE(82543GC_FIBER), 145 EM_DEVICE(82543GC_COPPER), 146 147 EM_DEVICE(82544EI_COPPER), 148 EM_DEVICE(82544EI_FIBER), 149 EM_DEVICE(82544GC_COPPER), 150 EM_DEVICE(82544GC_LOM), 151 152 EM_DEVICE(82545EM_COPPER), 153 EM_DEVICE(82545EM_FIBER), 154 EM_DEVICE(82545GM_COPPER), 155 EM_DEVICE(82545GM_FIBER), 156 EM_DEVICE(82545GM_SERDES), 157 158 EM_DEVICE(82546EB_COPPER), 159 EM_DEVICE(82546EB_FIBER), 160 EM_DEVICE(82546EB_QUAD_COPPER), 161 EM_DEVICE(82546GB_COPPER), 162 EM_DEVICE(82546GB_FIBER), 163 EM_DEVICE(82546GB_SERDES), 164 EM_DEVICE(82546GB_PCIE), 165 EM_DEVICE(82546GB_QUAD_COPPER), 166 EM_DEVICE(82546GB_QUAD_COPPER_KSP3), 167 168 EM_DEVICE(82547EI), 169 EM_DEVICE(82547EI_MOBILE), 170 EM_DEVICE(82547GI), 171 172 EM_EMX_DEVICE(82571EB_COPPER), 173 EM_EMX_DEVICE(82571EB_FIBER), 174 EM_EMX_DEVICE(82571EB_SERDES), 175 EM_EMX_DEVICE(82571EB_SERDES_DUAL), 176 EM_EMX_DEVICE(82571EB_SERDES_QUAD), 177 EM_EMX_DEVICE(82571EB_QUAD_COPPER), 178 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP), 179 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP), 180 EM_EMX_DEVICE(82571EB_QUAD_FIBER), 181 EM_EMX_DEVICE(82571PT_QUAD_COPPER), 182 183 EM_EMX_DEVICE(82572EI_COPPER), 184 EM_EMX_DEVICE(82572EI_FIBER), 185 EM_EMX_DEVICE(82572EI_SERDES), 186 EM_EMX_DEVICE(82572EI), 187 188 EM_EMX_DEVICE(82573E), 189 EM_EMX_DEVICE(82573E_IAMT), 190 EM_EMX_DEVICE(82573L), 191 192 EM_DEVICE(82583V), 193 194 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT), 195 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT), 196 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT), 197 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT), 198 199 EM_DEVICE(ICH8_IGP_M_AMT), 200 EM_DEVICE(ICH8_IGP_AMT), 201 EM_DEVICE(ICH8_IGP_C), 202 EM_DEVICE(ICH8_IFE), 203 EM_DEVICE(ICH8_IFE_GT), 204 EM_DEVICE(ICH8_IFE_G), 205 EM_DEVICE(ICH8_IGP_M), 206 EM_DEVICE(ICH8_82567V_3), 207 208 EM_DEVICE(ICH9_IGP_M_AMT), 209 EM_DEVICE(ICH9_IGP_AMT), 210 EM_DEVICE(ICH9_IGP_C), 211 EM_DEVICE(ICH9_IGP_M), 212 EM_DEVICE(ICH9_IGP_M_V), 213 EM_DEVICE(ICH9_IFE), 214 EM_DEVICE(ICH9_IFE_GT), 215 EM_DEVICE(ICH9_IFE_G), 216 EM_DEVICE(ICH9_BM), 217 218 EM_EMX_DEVICE(82574L), 219 EM_EMX_DEVICE(82574LA), 220 221 EM_DEVICE(ICH10_R_BM_LM), 222 EM_DEVICE(ICH10_R_BM_LF), 223 EM_DEVICE(ICH10_R_BM_V), 224 EM_DEVICE(ICH10_D_BM_LM), 225 EM_DEVICE(ICH10_D_BM_LF), 226 EM_DEVICE(ICH10_D_BM_V), 227 228 EM_DEVICE(PCH_M_HV_LM), 229 EM_DEVICE(PCH_M_HV_LC), 230 EM_DEVICE(PCH_D_HV_DM), 231 EM_DEVICE(PCH_D_HV_DC), 232 233 EM_DEVICE(PCH2_LV_LM), 234 EM_DEVICE(PCH2_LV_V), 235 236 EM_EMX_DEVICE(PCH_LPT_I217_LM), 237 EM_EMX_DEVICE(PCH_LPT_I217_V), 238 EM_EMX_DEVICE(PCH_LPTLP_I218_LM), 239 EM_EMX_DEVICE(PCH_LPTLP_I218_V), 240 EM_EMX_DEVICE(PCH_I218_LM2), 241 EM_EMX_DEVICE(PCH_I218_V2), 242 EM_EMX_DEVICE(PCH_I218_LM3), 243 EM_EMX_DEVICE(PCH_I218_V3), 244 245 /* required last entry */ 246 EM_DEVICE_NULL 247 }; 248 249 static int em_probe(device_t); 250 static int em_attach(device_t); 251 static int em_detach(device_t); 252 static int em_shutdown(device_t); 253 static int em_suspend(device_t); 254 static int em_resume(device_t); 255 256 static void em_init(void *); 257 static void em_stop(struct adapter *); 258 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 259 static void em_start(struct ifnet *, struct ifaltq_subque *); 260 #ifdef IFPOLL_ENABLE 261 static void em_npoll(struct ifnet *, struct ifpoll_info *); 262 static void em_npoll_compat(struct ifnet *, void *, int); 263 #endif 264 static void em_watchdog(struct ifnet *); 265 static void em_media_status(struct ifnet *, struct ifmediareq *); 266 static int em_media_change(struct ifnet *); 267 static void em_timer(void *); 268 269 static void em_intr(void *); 270 static void em_intr_mask(void *); 271 static void em_intr_body(struct adapter *, boolean_t); 272 static void em_rxeof(struct adapter *, int); 273 static void em_txeof(struct adapter *); 274 static void em_tx_collect(struct adapter *); 275 static void em_tx_purge(struct adapter *); 276 static void em_enable_intr(struct adapter *); 277 static void em_disable_intr(struct adapter *); 278 279 static int em_dma_malloc(struct adapter *, bus_size_t, 280 struct em_dma_alloc *); 281 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 282 static void em_init_tx_ring(struct adapter *); 283 static int em_init_rx_ring(struct adapter *); 284 static int em_create_tx_ring(struct adapter *); 285 static int em_create_rx_ring(struct adapter *); 286 static void em_destroy_tx_ring(struct adapter *, int); 287 static void em_destroy_rx_ring(struct adapter *, int); 288 static int em_newbuf(struct adapter *, int, int); 289 static int em_encap(struct adapter *, struct mbuf **, int *, int *); 290 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *, 291 struct mbuf *); 292 static int em_txcsum(struct adapter *, struct mbuf *, 293 uint32_t *, uint32_t *); 294 static int em_tso_pullup(struct adapter *, struct mbuf **); 295 static int em_tso_setup(struct adapter *, struct mbuf *, 296 uint32_t *, uint32_t *); 297 298 static int em_get_hw_info(struct adapter *); 299 static int em_is_valid_eaddr(const uint8_t *); 300 static int em_alloc_pci_res(struct adapter *); 301 static void em_free_pci_res(struct adapter *); 302 static int em_reset(struct adapter *); 303 static void em_setup_ifp(struct adapter *); 304 static void em_init_tx_unit(struct adapter *); 305 static void em_init_rx_unit(struct adapter *); 306 static void em_update_stats(struct adapter *); 307 static void em_set_promisc(struct adapter *); 308 static void em_disable_promisc(struct adapter *); 309 static void em_set_multi(struct adapter *); 310 static void em_update_link_status(struct adapter *); 311 static void em_smartspeed(struct adapter *); 312 static void em_set_itr(struct adapter *, uint32_t); 313 static void em_disable_aspm(struct adapter *); 314 315 /* Hardware workarounds */ 316 static int em_82547_fifo_workaround(struct adapter *, int); 317 static void em_82547_update_fifo_head(struct adapter *, int); 318 static int em_82547_tx_fifo_reset(struct adapter *); 319 static void em_82547_move_tail(void *); 320 static void em_82547_move_tail_serialized(struct adapter *); 321 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY); 322 323 static void em_print_debug_info(struct adapter *); 324 static void em_print_nvm_info(struct adapter *); 325 static void em_print_hw_stats(struct adapter *); 326 327 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 328 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 329 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 330 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 331 static void em_add_sysctl(struct adapter *adapter); 332 333 /* Management and WOL Support */ 334 static void em_get_mgmt(struct adapter *); 335 static void em_rel_mgmt(struct adapter *); 336 static void em_get_hw_control(struct adapter *); 337 static void em_rel_hw_control(struct adapter *); 338 static void em_enable_wol(device_t); 339 340 static device_method_t em_methods[] = { 341 /* Device interface */ 342 DEVMETHOD(device_probe, em_probe), 343 DEVMETHOD(device_attach, em_attach), 344 DEVMETHOD(device_detach, em_detach), 345 DEVMETHOD(device_shutdown, em_shutdown), 346 DEVMETHOD(device_suspend, em_suspend), 347 DEVMETHOD(device_resume, em_resume), 348 DEVMETHOD_END 349 }; 350 351 static driver_t em_driver = { 352 "em", 353 em_methods, 354 sizeof(struct adapter), 355 }; 356 357 static devclass_t em_devclass; 358 359 DECLARE_DUMMY_MODULE(if_em); 360 MODULE_DEPEND(em, ig_hal, 1, 1, 1); 361 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL); 362 363 /* 364 * Tunables 365 */ 366 static int em_int_throttle_ceil = EM_DEFAULT_ITR; 367 static int em_rxd = EM_DEFAULT_RXD; 368 static int em_txd = EM_DEFAULT_TXD; 369 static int em_smart_pwr_down = 0; 370 371 /* Controls whether promiscuous also shows bad packets */ 372 static int em_debug_sbp = FALSE; 373 374 static int em_82573_workaround = 1; 375 static int em_msi_enable = 1; 376 377 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil); 378 TUNABLE_INT("hw.em.rxd", &em_rxd); 379 TUNABLE_INT("hw.em.txd", &em_txd); 380 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 381 TUNABLE_INT("hw.em.sbp", &em_debug_sbp); 382 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround); 383 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable); 384 385 /* Global used in WOL setup with multiport cards */ 386 static int em_global_quad_port_a = 0; 387 388 /* Set this to one to display debug statistics */ 389 static int em_display_debug_stats = 0; 390 391 #if !defined(KTR_IF_EM) 392 #define KTR_IF_EM KTR_ALL 393 #endif 394 KTR_INFO_MASTER(if_em); 395 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin"); 396 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end"); 397 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet"); 398 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet"); 399 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean"); 400 #define logif(name) KTR_LOG(if_em_ ## name) 401 402 static int 403 em_probe(device_t dev) 404 { 405 const struct em_vendor_info *ent; 406 uint16_t vid, did; 407 408 vid = pci_get_vendor(dev); 409 did = pci_get_device(dev); 410 411 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) { 412 if (vid == ent->vendor_id && did == ent->device_id) { 413 device_set_desc(dev, ent->desc); 414 device_set_async_attach(dev, TRUE); 415 return (ent->ret); 416 } 417 } 418 return (ENXIO); 419 } 420 421 static int 422 em_attach(device_t dev) 423 { 424 struct adapter *adapter = device_get_softc(dev); 425 struct ifnet *ifp = &adapter->arpcom.ac_if; 426 int tsize, rsize; 427 int error = 0; 428 uint16_t eeprom_data, device_id, apme_mask; 429 driver_intr_t *intr_func; 430 431 adapter->dev = adapter->osdep.dev = dev; 432 433 callout_init_mp(&adapter->timer); 434 callout_init_mp(&adapter->tx_fifo_timer); 435 436 ifmedia_init(&adapter->media, IFM_IMASK, 437 em_media_change, em_media_status); 438 439 /* Determine hardware and mac info */ 440 error = em_get_hw_info(adapter); 441 if (error) { 442 device_printf(dev, "Identify hardware failed\n"); 443 goto fail; 444 } 445 446 /* Setup PCI resources */ 447 error = em_alloc_pci_res(adapter); 448 if (error) { 449 device_printf(dev, "Allocation of PCI resources failed\n"); 450 goto fail; 451 } 452 453 /* 454 * For ICH8 and family we need to map the flash memory, 455 * and this must happen after the MAC is identified. 456 */ 457 if (adapter->hw.mac.type == e1000_ich8lan || 458 adapter->hw.mac.type == e1000_ich9lan || 459 adapter->hw.mac.type == e1000_ich10lan || 460 adapter->hw.mac.type == e1000_pchlan || 461 adapter->hw.mac.type == e1000_pch2lan || 462 adapter->hw.mac.type == e1000_pch_lpt) { 463 adapter->flash_rid = EM_BAR_FLASH; 464 465 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 466 &adapter->flash_rid, RF_ACTIVE); 467 if (adapter->flash == NULL) { 468 device_printf(dev, "Mapping of Flash failed\n"); 469 error = ENXIO; 470 goto fail; 471 } 472 adapter->osdep.flash_bus_space_tag = 473 rman_get_bustag(adapter->flash); 474 adapter->osdep.flash_bus_space_handle = 475 rman_get_bushandle(adapter->flash); 476 477 /* 478 * This is used in the shared code 479 * XXX this goof is actually not used. 480 */ 481 adapter->hw.flash_address = (uint8_t *)adapter->flash; 482 } 483 484 switch (adapter->hw.mac.type) { 485 case e1000_82571: 486 case e1000_82572: 487 case e1000_pch_lpt: 488 /* 489 * Pullup extra 4bytes into the first data segment for 490 * TSO, see: 491 * 82571/82572 specification update errata #7 492 * 493 * Same applies to I217 (and maybe I218). 494 * 495 * NOTE: 496 * 4bytes instead of 2bytes, which are mentioned in the 497 * errata, are pulled; mainly to keep rest of the data 498 * properly aligned. 499 */ 500 adapter->flags |= EM_FLAG_TSO_PULLEX; 501 /* FALL THROUGH */ 502 503 default: 504 if (pci_is_pcie(dev)) 505 adapter->flags |= EM_FLAG_TSO; 506 break; 507 } 508 509 /* Do Shared Code initialization */ 510 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 511 device_printf(dev, "Setup of Shared code failed\n"); 512 error = ENXIO; 513 goto fail; 514 } 515 516 e1000_get_bus_info(&adapter->hw); 517 518 /* 519 * Validate number of transmit and receive descriptors. It 520 * must not exceed hardware maximum, and must be multiple 521 * of E1000_DBA_ALIGN. 522 */ 523 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 || 524 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 525 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 526 em_txd < EM_MIN_TXD) { 527 if (adapter->hw.mac.type < e1000_82544) 528 adapter->num_tx_desc = EM_MAX_TXD_82543; 529 else 530 adapter->num_tx_desc = EM_DEFAULT_TXD; 531 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 532 adapter->num_tx_desc, em_txd); 533 } else { 534 adapter->num_tx_desc = em_txd; 535 } 536 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 || 537 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 538 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 539 em_rxd < EM_MIN_RXD) { 540 if (adapter->hw.mac.type < e1000_82544) 541 adapter->num_rx_desc = EM_MAX_RXD_82543; 542 else 543 adapter->num_rx_desc = EM_DEFAULT_RXD; 544 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 545 adapter->num_rx_desc, em_rxd); 546 } else { 547 adapter->num_rx_desc = em_rxd; 548 } 549 550 adapter->hw.mac.autoneg = DO_AUTO_NEG; 551 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 552 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 553 adapter->rx_buffer_len = MCLBYTES; 554 555 /* 556 * Interrupt throttle rate 557 */ 558 if (em_int_throttle_ceil == 0) { 559 adapter->int_throttle_ceil = 0; 560 } else { 561 int throttle = em_int_throttle_ceil; 562 563 if (throttle < 0) 564 throttle = EM_DEFAULT_ITR; 565 566 /* Recalculate the tunable value to get the exact frequency. */ 567 throttle = 1000000000 / 256 / throttle; 568 569 /* Upper 16bits of ITR is reserved and should be zero */ 570 if (throttle & 0xffff0000) 571 throttle = 1000000000 / 256 / EM_DEFAULT_ITR; 572 573 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 574 } 575 576 e1000_init_script_state_82541(&adapter->hw, TRUE); 577 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 578 579 /* Copper options */ 580 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 581 adapter->hw.phy.mdix = AUTO_ALL_MODES; 582 adapter->hw.phy.disable_polarity_correction = FALSE; 583 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 584 } 585 586 /* Set the frame limits assuming standard ethernet sized frames. */ 587 adapter->hw.mac.max_frame_size = 588 ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 589 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN; 590 591 /* This controls when hardware reports transmit completion status. */ 592 adapter->hw.mac.report_tx_early = 1; 593 594 /* 595 * Create top level busdma tag 596 */ 597 error = bus_dma_tag_create(NULL, 1, 0, 598 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 599 NULL, NULL, 600 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 601 0, &adapter->parent_dtag); 602 if (error) { 603 device_printf(dev, "could not create top level DMA tag\n"); 604 goto fail; 605 } 606 607 /* 608 * Allocate Transmit Descriptor ring 609 */ 610 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 611 EM_DBA_ALIGN); 612 error = em_dma_malloc(adapter, tsize, &adapter->txdma); 613 if (error) { 614 device_printf(dev, "Unable to allocate tx_desc memory\n"); 615 goto fail; 616 } 617 adapter->tx_desc_base = adapter->txdma.dma_vaddr; 618 619 /* 620 * Allocate Receive Descriptor ring 621 */ 622 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 623 EM_DBA_ALIGN); 624 error = em_dma_malloc(adapter, rsize, &adapter->rxdma); 625 if (error) { 626 device_printf(dev, "Unable to allocate rx_desc memory\n"); 627 goto fail; 628 } 629 adapter->rx_desc_base = adapter->rxdma.dma_vaddr; 630 631 /* Allocate multicast array memory. */ 632 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES, 633 M_DEVBUF, M_WAITOK); 634 635 /* Indicate SOL/IDER usage */ 636 if (e1000_check_reset_block(&adapter->hw)) { 637 device_printf(dev, 638 "PHY reset is blocked due to SOL/IDER session.\n"); 639 } 640 641 /* Disable EEE */ 642 adapter->hw.dev_spec.ich8lan.eee_disable = 1; 643 644 /* 645 * Start from a known state, this is important in reading the 646 * nvm and mac from that. 647 */ 648 e1000_reset_hw(&adapter->hw); 649 650 /* Make sure we have a good EEPROM before we read from it */ 651 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 652 /* 653 * Some PCI-E parts fail the first check due to 654 * the link being in sleep state, call it again, 655 * if it fails a second time its a real issue. 656 */ 657 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 658 device_printf(dev, 659 "The EEPROM Checksum Is Not Valid\n"); 660 error = EIO; 661 goto fail; 662 } 663 } 664 665 /* Copy the permanent MAC address out of the EEPROM */ 666 if (e1000_read_mac_addr(&adapter->hw) < 0) { 667 device_printf(dev, "EEPROM read error while reading MAC" 668 " address\n"); 669 error = EIO; 670 goto fail; 671 } 672 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) { 673 device_printf(dev, "Invalid MAC address\n"); 674 error = EIO; 675 goto fail; 676 } 677 678 /* Disable ULP support */ 679 e1000_disable_ulp_lpt_lp(&adapter->hw, TRUE); 680 681 /* Allocate transmit descriptors and buffers */ 682 error = em_create_tx_ring(adapter); 683 if (error) { 684 device_printf(dev, "Could not setup transmit structures\n"); 685 goto fail; 686 } 687 688 /* Allocate receive descriptors and buffers */ 689 error = em_create_rx_ring(adapter); 690 if (error) { 691 device_printf(dev, "Could not setup receive structures\n"); 692 goto fail; 693 } 694 695 /* Manually turn off all interrupts */ 696 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 697 698 /* Determine if we have to control management hardware */ 699 if (e1000_enable_mng_pass_thru(&adapter->hw)) 700 adapter->flags |= EM_FLAG_HAS_MGMT; 701 702 /* 703 * Setup Wake-on-Lan 704 */ 705 apme_mask = EM_EEPROM_APME; 706 eeprom_data = 0; 707 switch (adapter->hw.mac.type) { 708 case e1000_82542: 709 case e1000_82543: 710 break; 711 712 case e1000_82573: 713 case e1000_82583: 714 adapter->flags |= EM_FLAG_HAS_AMT; 715 /* FALL THROUGH */ 716 717 case e1000_82546: 718 case e1000_82546_rev_3: 719 case e1000_82571: 720 case e1000_82572: 721 case e1000_80003es2lan: 722 if (adapter->hw.bus.func == 1) { 723 e1000_read_nvm(&adapter->hw, 724 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 725 } else { 726 e1000_read_nvm(&adapter->hw, 727 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 728 } 729 break; 730 731 case e1000_ich8lan: 732 case e1000_ich9lan: 733 case e1000_ich10lan: 734 case e1000_pchlan: 735 case e1000_pch2lan: 736 apme_mask = E1000_WUC_APME; 737 adapter->flags |= EM_FLAG_HAS_AMT; 738 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 739 break; 740 741 default: 742 e1000_read_nvm(&adapter->hw, 743 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 744 break; 745 } 746 if (eeprom_data & apme_mask) 747 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 748 749 /* 750 * We have the eeprom settings, now apply the special cases 751 * where the eeprom may be wrong or the board won't support 752 * wake on lan on a particular port 753 */ 754 device_id = pci_get_device(dev); 755 switch (device_id) { 756 case E1000_DEV_ID_82546GB_PCIE: 757 adapter->wol = 0; 758 break; 759 760 case E1000_DEV_ID_82546EB_FIBER: 761 case E1000_DEV_ID_82546GB_FIBER: 762 case E1000_DEV_ID_82571EB_FIBER: 763 /* 764 * Wake events only supported on port A for dual fiber 765 * regardless of eeprom setting 766 */ 767 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 768 E1000_STATUS_FUNC_1) 769 adapter->wol = 0; 770 break; 771 772 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 773 case E1000_DEV_ID_82571EB_QUAD_COPPER: 774 case E1000_DEV_ID_82571EB_QUAD_FIBER: 775 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 776 /* if quad port adapter, disable WoL on all but port A */ 777 if (em_global_quad_port_a != 0) 778 adapter->wol = 0; 779 /* Reset for multiple quad port adapters */ 780 if (++em_global_quad_port_a == 4) 781 em_global_quad_port_a = 0; 782 break; 783 } 784 785 /* XXX disable wol */ 786 adapter->wol = 0; 787 788 /* Setup OS specific network interface */ 789 em_setup_ifp(adapter); 790 791 /* Add sysctl tree, must after em_setup_ifp() */ 792 em_add_sysctl(adapter); 793 794 #ifdef IFPOLL_ENABLE 795 /* Polling setup */ 796 ifpoll_compat_setup(&adapter->npoll, 797 device_get_sysctl_ctx(dev), device_get_sysctl_tree(dev), 798 device_get_unit(dev), ifp->if_serializer); 799 #endif 800 801 /* Reset the hardware */ 802 error = em_reset(adapter); 803 if (error) { 804 /* 805 * Some 82573 parts fail the first reset, call it again, 806 * if it fails a second time its a real issue. 807 */ 808 error = em_reset(adapter); 809 if (error) { 810 device_printf(dev, "Unable to reset the hardware\n"); 811 ether_ifdetach(ifp); 812 goto fail; 813 } 814 } 815 816 /* Initialize statistics */ 817 em_update_stats(adapter); 818 819 adapter->hw.mac.get_link_status = 1; 820 em_update_link_status(adapter); 821 822 /* Do we need workaround for 82544 PCI-X adapter? */ 823 if (adapter->hw.bus.type == e1000_bus_type_pcix && 824 adapter->hw.mac.type == e1000_82544) 825 adapter->pcix_82544 = TRUE; 826 else 827 adapter->pcix_82544 = FALSE; 828 829 if (adapter->pcix_82544) { 830 /* 831 * 82544 on PCI-X may split one TX segment 832 * into two TX descs, so we double its number 833 * of spare TX desc here. 834 */ 835 adapter->spare_tx_desc = 2 * EM_TX_SPARE; 836 } else { 837 adapter->spare_tx_desc = EM_TX_SPARE; 838 } 839 if (adapter->flags & EM_FLAG_TSO) 840 adapter->spare_tx_desc = EM_TX_SPARE_TSO; 841 adapter->tx_wreg_nsegs = EM_DEFAULT_TXWREG; 842 843 /* 844 * Keep following relationship between spare_tx_desc, oact_tx_desc 845 * and tx_int_nsegs: 846 * (spare_tx_desc + EM_TX_RESERVED) <= 847 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs 848 */ 849 adapter->oact_tx_desc = adapter->num_tx_desc / 8; 850 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX) 851 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX; 852 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED) 853 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED; 854 855 adapter->tx_int_nsegs = adapter->num_tx_desc / 16; 856 if (adapter->tx_int_nsegs < adapter->oact_tx_desc) 857 adapter->tx_int_nsegs = adapter->oact_tx_desc; 858 859 /* Non-AMT based hardware can now take control from firmware */ 860 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 861 EM_FLAG_HAS_MGMT && adapter->hw.mac.type >= e1000_82571) 862 em_get_hw_control(adapter); 863 864 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 865 866 /* 867 * Missing Interrupt Following ICR read: 868 * 869 * 82571/82572 specification update errata #76 870 * 82573 specification update errata #31 871 * 82574 specification update errata #12 872 * 82583 specification update errata #4 873 */ 874 intr_func = em_intr; 875 if ((adapter->flags & EM_FLAG_SHARED_INTR) && 876 (adapter->hw.mac.type == e1000_82571 || 877 adapter->hw.mac.type == e1000_82572 || 878 adapter->hw.mac.type == e1000_82573 || 879 adapter->hw.mac.type == e1000_82574 || 880 adapter->hw.mac.type == e1000_82583)) 881 intr_func = em_intr_mask; 882 883 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE, 884 intr_func, adapter, &adapter->intr_tag, 885 ifp->if_serializer); 886 if (error) { 887 device_printf(dev, "Failed to register interrupt handler"); 888 ether_ifdetach(ifp); 889 goto fail; 890 } 891 return (0); 892 fail: 893 em_detach(dev); 894 return (error); 895 } 896 897 static int 898 em_detach(device_t dev) 899 { 900 struct adapter *adapter = device_get_softc(dev); 901 902 if (device_is_attached(dev)) { 903 struct ifnet *ifp = &adapter->arpcom.ac_if; 904 905 lwkt_serialize_enter(ifp->if_serializer); 906 907 em_stop(adapter); 908 909 e1000_phy_hw_reset(&adapter->hw); 910 911 em_rel_mgmt(adapter); 912 em_rel_hw_control(adapter); 913 914 if (adapter->wol) { 915 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 916 E1000_WUC_PME_EN); 917 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 918 em_enable_wol(dev); 919 } 920 921 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag); 922 923 lwkt_serialize_exit(ifp->if_serializer); 924 925 ether_ifdetach(ifp); 926 } else if (adapter->memory != NULL) { 927 em_rel_hw_control(adapter); 928 } 929 930 ifmedia_removeall(&adapter->media); 931 bus_generic_detach(dev); 932 933 em_free_pci_res(adapter); 934 935 em_destroy_tx_ring(adapter, adapter->num_tx_desc); 936 em_destroy_rx_ring(adapter, adapter->num_rx_desc); 937 938 /* Free Transmit Descriptor ring */ 939 if (adapter->tx_desc_base) 940 em_dma_free(adapter, &adapter->txdma); 941 942 /* Free Receive Descriptor ring */ 943 if (adapter->rx_desc_base) 944 em_dma_free(adapter, &adapter->rxdma); 945 946 /* Free top level busdma tag */ 947 if (adapter->parent_dtag != NULL) 948 bus_dma_tag_destroy(adapter->parent_dtag); 949 950 if (adapter->mta != NULL) 951 kfree(adapter->mta, M_DEVBUF); 952 953 return (0); 954 } 955 956 static int 957 em_shutdown(device_t dev) 958 { 959 return em_suspend(dev); 960 } 961 962 static int 963 em_suspend(device_t dev) 964 { 965 struct adapter *adapter = device_get_softc(dev); 966 struct ifnet *ifp = &adapter->arpcom.ac_if; 967 968 lwkt_serialize_enter(ifp->if_serializer); 969 970 em_stop(adapter); 971 972 em_rel_mgmt(adapter); 973 em_rel_hw_control(adapter); 974 975 if (adapter->wol) { 976 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 977 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 978 em_enable_wol(dev); 979 } 980 981 lwkt_serialize_exit(ifp->if_serializer); 982 983 return bus_generic_suspend(dev); 984 } 985 986 static int 987 em_resume(device_t dev) 988 { 989 struct adapter *adapter = device_get_softc(dev); 990 struct ifnet *ifp = &adapter->arpcom.ac_if; 991 992 lwkt_serialize_enter(ifp->if_serializer); 993 994 if (adapter->hw.mac.type == e1000_pch2lan) 995 e1000_resume_workarounds_pchlan(&adapter->hw); 996 997 em_init(adapter); 998 em_get_mgmt(adapter); 999 if_devstart(ifp); 1000 1001 lwkt_serialize_exit(ifp->if_serializer); 1002 1003 return bus_generic_resume(dev); 1004 } 1005 1006 static void 1007 em_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1008 { 1009 struct adapter *adapter = ifp->if_softc; 1010 struct mbuf *m_head; 1011 int idx = -1, nsegs = 0; 1012 1013 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1014 ASSERT_SERIALIZED(ifp->if_serializer); 1015 1016 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1017 return; 1018 1019 if (!adapter->link_active) { 1020 ifq_purge(&ifp->if_snd); 1021 return; 1022 } 1023 1024 while (!ifq_is_empty(&ifp->if_snd)) { 1025 /* Now do we at least have a minimal? */ 1026 if (EM_IS_OACTIVE(adapter)) { 1027 em_tx_collect(adapter); 1028 if (EM_IS_OACTIVE(adapter)) { 1029 ifq_set_oactive(&ifp->if_snd); 1030 adapter->no_tx_desc_avail1++; 1031 break; 1032 } 1033 } 1034 1035 logif(pkt_txqueue); 1036 m_head = ifq_dequeue(&ifp->if_snd); 1037 if (m_head == NULL) 1038 break; 1039 1040 if (em_encap(adapter, &m_head, &nsegs, &idx)) { 1041 IFNET_STAT_INC(ifp, oerrors, 1); 1042 em_tx_collect(adapter); 1043 continue; 1044 } 1045 1046 /* 1047 * TX interrupt are aggressively aggregated, so increasing 1048 * opackets at TX interrupt time will make the opackets 1049 * statistics vastly inaccurate; we do the opackets increment 1050 * now. 1051 */ 1052 IFNET_STAT_INC(ifp, opackets, 1); 1053 1054 if (nsegs >= adapter->tx_wreg_nsegs && idx >= 0) { 1055 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1056 nsegs = 0; 1057 idx = -1; 1058 } 1059 1060 /* Send a copy of the frame to the BPF listener */ 1061 ETHER_BPF_MTAP(ifp, m_head); 1062 1063 /* Set timeout in case hardware has problems transmitting. */ 1064 ifp->if_timer = EM_TX_TIMEOUT; 1065 } 1066 if (idx >= 0) 1067 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx); 1068 } 1069 1070 static int 1071 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1072 { 1073 struct adapter *adapter = ifp->if_softc; 1074 struct ifreq *ifr = (struct ifreq *)data; 1075 uint16_t eeprom_data = 0; 1076 int max_frame_size, mask, reinit; 1077 int error = 0; 1078 1079 ASSERT_SERIALIZED(ifp->if_serializer); 1080 1081 switch (command) { 1082 case SIOCSIFMTU: 1083 switch (adapter->hw.mac.type) { 1084 case e1000_82573: 1085 /* 1086 * 82573 only supports jumbo frames 1087 * if ASPM is disabled. 1088 */ 1089 e1000_read_nvm(&adapter->hw, 1090 NVM_INIT_3GIO_3, 1, &eeprom_data); 1091 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1092 max_frame_size = ETHER_MAX_LEN; 1093 break; 1094 } 1095 /* FALL THROUGH */ 1096 1097 /* Limit Jumbo Frame size */ 1098 case e1000_82571: 1099 case e1000_82572: 1100 case e1000_ich9lan: 1101 case e1000_ich10lan: 1102 case e1000_pch2lan: 1103 case e1000_pch_lpt: 1104 case e1000_82574: 1105 case e1000_82583: 1106 case e1000_80003es2lan: 1107 max_frame_size = 9234; 1108 break; 1109 1110 case e1000_pchlan: 1111 max_frame_size = 4096; 1112 break; 1113 1114 /* Adapters that do not support jumbo frames */ 1115 case e1000_82542: 1116 case e1000_ich8lan: 1117 max_frame_size = ETHER_MAX_LEN; 1118 break; 1119 1120 default: 1121 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1122 break; 1123 } 1124 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1125 ETHER_CRC_LEN) { 1126 error = EINVAL; 1127 break; 1128 } 1129 1130 ifp->if_mtu = ifr->ifr_mtu; 1131 adapter->hw.mac.max_frame_size = 1132 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1133 1134 if (ifp->if_flags & IFF_RUNNING) 1135 em_init(adapter); 1136 break; 1137 1138 case SIOCSIFFLAGS: 1139 if (ifp->if_flags & IFF_UP) { 1140 if ((ifp->if_flags & IFF_RUNNING)) { 1141 if ((ifp->if_flags ^ adapter->if_flags) & 1142 (IFF_PROMISC | IFF_ALLMULTI)) { 1143 em_disable_promisc(adapter); 1144 em_set_promisc(adapter); 1145 } 1146 } else { 1147 em_init(adapter); 1148 } 1149 } else if (ifp->if_flags & IFF_RUNNING) { 1150 em_stop(adapter); 1151 } 1152 adapter->if_flags = ifp->if_flags; 1153 break; 1154 1155 case SIOCADDMULTI: 1156 case SIOCDELMULTI: 1157 if (ifp->if_flags & IFF_RUNNING) { 1158 em_disable_intr(adapter); 1159 em_set_multi(adapter); 1160 if (adapter->hw.mac.type == e1000_82542 && 1161 adapter->hw.revision_id == E1000_REVISION_2) 1162 em_init_rx_unit(adapter); 1163 #ifdef IFPOLL_ENABLE 1164 if (!(ifp->if_flags & IFF_NPOLLING)) 1165 #endif 1166 em_enable_intr(adapter); 1167 } 1168 break; 1169 1170 case SIOCSIFMEDIA: 1171 /* Check SOL/IDER usage */ 1172 if (e1000_check_reset_block(&adapter->hw)) { 1173 device_printf(adapter->dev, "Media change is" 1174 " blocked due to SOL/IDER session.\n"); 1175 break; 1176 } 1177 /* FALL THROUGH */ 1178 1179 case SIOCGIFMEDIA: 1180 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1181 break; 1182 1183 case SIOCSIFCAP: 1184 reinit = 0; 1185 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1186 if (mask & IFCAP_RXCSUM) { 1187 ifp->if_capenable ^= IFCAP_RXCSUM; 1188 reinit = 1; 1189 } 1190 if (mask & IFCAP_TXCSUM) { 1191 ifp->if_capenable ^= IFCAP_TXCSUM; 1192 if (ifp->if_capenable & IFCAP_TXCSUM) 1193 ifp->if_hwassist |= EM_CSUM_FEATURES; 1194 else 1195 ifp->if_hwassist &= ~EM_CSUM_FEATURES; 1196 } 1197 if (mask & IFCAP_TSO) { 1198 ifp->if_capenable ^= IFCAP_TSO; 1199 if (ifp->if_capenable & IFCAP_TSO) 1200 ifp->if_hwassist |= CSUM_TSO; 1201 else 1202 ifp->if_hwassist &= ~CSUM_TSO; 1203 } 1204 if (mask & IFCAP_VLAN_HWTAGGING) { 1205 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1206 reinit = 1; 1207 } 1208 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1209 em_init(adapter); 1210 break; 1211 1212 default: 1213 error = ether_ioctl(ifp, command, data); 1214 break; 1215 } 1216 return (error); 1217 } 1218 1219 static void 1220 em_watchdog(struct ifnet *ifp) 1221 { 1222 struct adapter *adapter = ifp->if_softc; 1223 1224 ASSERT_SERIALIZED(ifp->if_serializer); 1225 1226 /* 1227 * The timer is set to 5 every time start queues a packet. 1228 * Then txeof keeps resetting it as long as it cleans at 1229 * least one descriptor. 1230 * Finally, anytime all descriptors are clean the timer is 1231 * set to 0. 1232 */ 1233 1234 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1235 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) { 1236 /* 1237 * If we reach here, all TX jobs are completed and 1238 * the TX engine should have been idled for some time. 1239 * We don't need to call if_devstart() here. 1240 */ 1241 ifq_clr_oactive(&ifp->if_snd); 1242 ifp->if_timer = 0; 1243 return; 1244 } 1245 1246 /* 1247 * If we are in this routine because of pause frames, then 1248 * don't reset the hardware. 1249 */ 1250 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1251 E1000_STATUS_TXOFF) { 1252 ifp->if_timer = EM_TX_TIMEOUT; 1253 return; 1254 } 1255 1256 if (e1000_check_for_link(&adapter->hw) == 0) 1257 if_printf(ifp, "watchdog timeout -- resetting\n"); 1258 1259 IFNET_STAT_INC(ifp, oerrors, 1); 1260 adapter->watchdog_events++; 1261 1262 em_init(adapter); 1263 1264 if (!ifq_is_empty(&ifp->if_snd)) 1265 if_devstart(ifp); 1266 } 1267 1268 static void 1269 em_init(void *xsc) 1270 { 1271 struct adapter *adapter = xsc; 1272 struct ifnet *ifp = &adapter->arpcom.ac_if; 1273 device_t dev = adapter->dev; 1274 1275 ASSERT_SERIALIZED(ifp->if_serializer); 1276 1277 em_stop(adapter); 1278 1279 /* Get the latest mac address, User can use a LAA */ 1280 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN); 1281 1282 /* Put the address into the Receive Address Array */ 1283 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1284 1285 /* 1286 * With the 82571 adapter, RAR[0] may be overwritten 1287 * when the other port is reset, we make a duplicate 1288 * in RAR[14] for that eventuality, this assures 1289 * the interface continues to function. 1290 */ 1291 if (adapter->hw.mac.type == e1000_82571) { 1292 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1293 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1294 E1000_RAR_ENTRIES - 1); 1295 } 1296 1297 /* Reset the hardware */ 1298 if (em_reset(adapter)) { 1299 device_printf(dev, "Unable to reset the hardware\n"); 1300 /* XXX em_stop()? */ 1301 return; 1302 } 1303 em_update_link_status(adapter); 1304 1305 /* Setup VLAN support, basic and offload if available */ 1306 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1307 1308 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1309 uint32_t ctrl; 1310 1311 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1312 ctrl |= E1000_CTRL_VME; 1313 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1314 } 1315 1316 /* Configure for OS presence */ 1317 em_get_mgmt(adapter); 1318 1319 /* Prepare transmit descriptors and buffers */ 1320 em_init_tx_ring(adapter); 1321 em_init_tx_unit(adapter); 1322 1323 /* Setup Multicast table */ 1324 em_set_multi(adapter); 1325 1326 /* Prepare receive descriptors and buffers */ 1327 if (em_init_rx_ring(adapter)) { 1328 device_printf(dev, "Could not setup receive structures\n"); 1329 em_stop(adapter); 1330 return; 1331 } 1332 em_init_rx_unit(adapter); 1333 1334 /* Don't lose promiscuous settings */ 1335 em_set_promisc(adapter); 1336 1337 ifp->if_flags |= IFF_RUNNING; 1338 ifq_clr_oactive(&ifp->if_snd); 1339 1340 callout_reset(&adapter->timer, hz, em_timer, adapter); 1341 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1342 1343 /* MSI/X configuration for 82574 */ 1344 if (adapter->hw.mac.type == e1000_82574) { 1345 int tmp; 1346 1347 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1348 tmp |= E1000_CTRL_EXT_PBA_CLR; 1349 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1350 /* 1351 * XXX MSIX 1352 * Set the IVAR - interrupt vector routing. 1353 * Each nibble represents a vector, high bit 1354 * is enable, other 3 bits are the MSIX table 1355 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1356 * Link (other) to 2, hence the magic number. 1357 */ 1358 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908); 1359 } 1360 1361 #ifdef IFPOLL_ENABLE 1362 /* 1363 * Only enable interrupts if we are not polling, make sure 1364 * they are off otherwise. 1365 */ 1366 if (ifp->if_flags & IFF_NPOLLING) 1367 em_disable_intr(adapter); 1368 else 1369 #endif /* IFPOLL_ENABLE */ 1370 em_enable_intr(adapter); 1371 1372 /* AMT based hardware can now take control from firmware */ 1373 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) == 1374 (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT) && 1375 adapter->hw.mac.type >= e1000_82571) 1376 em_get_hw_control(adapter); 1377 } 1378 1379 #ifdef IFPOLL_ENABLE 1380 1381 static void 1382 em_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 1383 { 1384 struct adapter *adapter = ifp->if_softc; 1385 1386 ASSERT_SERIALIZED(ifp->if_serializer); 1387 1388 if (adapter->npoll.ifpc_stcount-- == 0) { 1389 uint32_t reg_icr; 1390 1391 adapter->npoll.ifpc_stcount = adapter->npoll.ifpc_stfrac; 1392 1393 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1394 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1395 callout_stop(&adapter->timer); 1396 adapter->hw.mac.get_link_status = 1; 1397 em_update_link_status(adapter); 1398 callout_reset(&adapter->timer, hz, em_timer, adapter); 1399 } 1400 } 1401 1402 em_rxeof(adapter, count); 1403 em_txeof(adapter); 1404 1405 if (!ifq_is_empty(&ifp->if_snd)) 1406 if_devstart(ifp); 1407 } 1408 1409 static void 1410 em_npoll(struct ifnet *ifp, struct ifpoll_info *info) 1411 { 1412 struct adapter *adapter = ifp->if_softc; 1413 1414 ASSERT_SERIALIZED(ifp->if_serializer); 1415 1416 if (info != NULL) { 1417 int cpuid = adapter->npoll.ifpc_cpuid; 1418 1419 info->ifpi_rx[cpuid].poll_func = em_npoll_compat; 1420 info->ifpi_rx[cpuid].arg = NULL; 1421 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 1422 1423 if (ifp->if_flags & IFF_RUNNING) 1424 em_disable_intr(adapter); 1425 ifq_set_cpuid(&ifp->if_snd, cpuid); 1426 } else { 1427 if (ifp->if_flags & IFF_RUNNING) 1428 em_enable_intr(adapter); 1429 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res)); 1430 } 1431 } 1432 1433 #endif /* IFPOLL_ENABLE */ 1434 1435 static void 1436 em_intr(void *xsc) 1437 { 1438 em_intr_body(xsc, TRUE); 1439 } 1440 1441 static void 1442 em_intr_body(struct adapter *adapter, boolean_t chk_asserted) 1443 { 1444 struct ifnet *ifp = &adapter->arpcom.ac_if; 1445 uint32_t reg_icr; 1446 1447 logif(intr_beg); 1448 ASSERT_SERIALIZED(ifp->if_serializer); 1449 1450 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1451 1452 if (chk_asserted && 1453 ((adapter->hw.mac.type >= e1000_82571 && 1454 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1455 reg_icr == 0)) { 1456 logif(intr_end); 1457 return; 1458 } 1459 1460 /* 1461 * XXX: some laptops trigger several spurious interrupts 1462 * on em(4) when in the resume cycle. The ICR register 1463 * reports all-ones value in this case. Processing such 1464 * interrupts would lead to a freeze. I don't know why. 1465 */ 1466 if (reg_icr == 0xffffffff) { 1467 logif(intr_end); 1468 return; 1469 } 1470 1471 if (ifp->if_flags & IFF_RUNNING) { 1472 if (reg_icr & 1473 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) 1474 em_rxeof(adapter, -1); 1475 if (reg_icr & E1000_ICR_TXDW) { 1476 em_txeof(adapter); 1477 if (!ifq_is_empty(&ifp->if_snd)) 1478 if_devstart(ifp); 1479 } 1480 } 1481 1482 /* Link status change */ 1483 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1484 callout_stop(&adapter->timer); 1485 adapter->hw.mac.get_link_status = 1; 1486 em_update_link_status(adapter); 1487 1488 /* Deal with TX cruft when link lost */ 1489 em_tx_purge(adapter); 1490 1491 callout_reset(&adapter->timer, hz, em_timer, adapter); 1492 } 1493 1494 if (reg_icr & E1000_ICR_RXO) 1495 adapter->rx_overruns++; 1496 1497 logif(intr_end); 1498 } 1499 1500 static void 1501 em_intr_mask(void *xsc) 1502 { 1503 struct adapter *adapter = xsc; 1504 1505 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 1506 /* 1507 * NOTE: 1508 * ICR.INT_ASSERTED bit will never be set if IMS is 0, 1509 * so don't check it. 1510 */ 1511 em_intr_body(adapter, FALSE); 1512 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK); 1513 } 1514 1515 static void 1516 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1517 { 1518 struct adapter *adapter = ifp->if_softc; 1519 u_char fiber_type = IFM_1000_SX; 1520 1521 ASSERT_SERIALIZED(ifp->if_serializer); 1522 1523 em_update_link_status(adapter); 1524 1525 ifmr->ifm_status = IFM_AVALID; 1526 ifmr->ifm_active = IFM_ETHER; 1527 1528 if (!adapter->link_active) 1529 return; 1530 1531 ifmr->ifm_status |= IFM_ACTIVE; 1532 1533 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 1534 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 1535 if (adapter->hw.mac.type == e1000_82545) 1536 fiber_type = IFM_1000_LX; 1537 ifmr->ifm_active |= fiber_type | IFM_FDX; 1538 } else { 1539 switch (adapter->link_speed) { 1540 case 10: 1541 ifmr->ifm_active |= IFM_10_T; 1542 break; 1543 case 100: 1544 ifmr->ifm_active |= IFM_100_TX; 1545 break; 1546 1547 case 1000: 1548 ifmr->ifm_active |= IFM_1000_T; 1549 break; 1550 } 1551 if (adapter->link_duplex == FULL_DUPLEX) 1552 ifmr->ifm_active |= IFM_FDX; 1553 else 1554 ifmr->ifm_active |= IFM_HDX; 1555 } 1556 } 1557 1558 static int 1559 em_media_change(struct ifnet *ifp) 1560 { 1561 struct adapter *adapter = ifp->if_softc; 1562 struct ifmedia *ifm = &adapter->media; 1563 1564 ASSERT_SERIALIZED(ifp->if_serializer); 1565 1566 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1567 return (EINVAL); 1568 1569 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1570 case IFM_AUTO: 1571 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1572 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1573 break; 1574 1575 case IFM_1000_LX: 1576 case IFM_1000_SX: 1577 case IFM_1000_T: 1578 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1579 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1580 break; 1581 1582 case IFM_100_TX: 1583 adapter->hw.mac.autoneg = FALSE; 1584 adapter->hw.phy.autoneg_advertised = 0; 1585 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1586 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1587 else 1588 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1589 break; 1590 1591 case IFM_10_T: 1592 adapter->hw.mac.autoneg = FALSE; 1593 adapter->hw.phy.autoneg_advertised = 0; 1594 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1595 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1596 else 1597 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1598 break; 1599 1600 default: 1601 if_printf(ifp, "Unsupported media type\n"); 1602 break; 1603 } 1604 1605 em_init(adapter); 1606 1607 return (0); 1608 } 1609 1610 static int 1611 em_encap(struct adapter *adapter, struct mbuf **m_headp, 1612 int *segs_used, int *idx) 1613 { 1614 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1615 bus_dmamap_t map; 1616 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1617 struct e1000_tx_desc *ctxd = NULL; 1618 struct mbuf *m_head = *m_headp; 1619 uint32_t txd_upper, txd_lower, txd_used, cmd = 0; 1620 int maxsegs, nsegs, i, j, first, last = 0, error; 1621 1622 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1623 error = em_tso_pullup(adapter, m_headp); 1624 if (error) 1625 return error; 1626 m_head = *m_headp; 1627 } 1628 1629 txd_upper = txd_lower = 0; 1630 txd_used = 0; 1631 1632 /* 1633 * Capture the first descriptor index, this descriptor 1634 * will have the index of the EOP which is the only one 1635 * that now gets a DONE bit writeback. 1636 */ 1637 first = adapter->next_avail_tx_desc; 1638 tx_buffer = &adapter->tx_buffer_area[first]; 1639 tx_buffer_mapped = tx_buffer; 1640 map = tx_buffer->map; 1641 1642 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED; 1643 KASSERT(maxsegs >= adapter->spare_tx_desc, 1644 ("not enough spare TX desc")); 1645 if (adapter->pcix_82544) { 1646 /* Half it; see the comment in em_attach() */ 1647 maxsegs >>= 1; 1648 } 1649 if (maxsegs > EM_MAX_SCATTER) 1650 maxsegs = EM_MAX_SCATTER; 1651 1652 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp, 1653 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1654 if (error) { 1655 if (error == ENOBUFS) 1656 adapter->mbuf_alloc_failed++; 1657 else 1658 adapter->no_tx_dma_setup++; 1659 1660 m_freem(*m_headp); 1661 *m_headp = NULL; 1662 return error; 1663 } 1664 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1665 1666 m_head = *m_headp; 1667 adapter->tx_nsegs += nsegs; 1668 *segs_used += nsegs; 1669 1670 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1671 /* TSO will consume one TX desc */ 1672 i = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower); 1673 adapter->tx_nsegs += i; 1674 *segs_used += i; 1675 } else if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) { 1676 /* TX csum offloading will consume one TX desc */ 1677 i = em_txcsum(adapter, m_head, &txd_upper, &txd_lower); 1678 adapter->tx_nsegs += i; 1679 *segs_used += i; 1680 } 1681 1682 /* Handle VLAN tag */ 1683 if (m_head->m_flags & M_VLANTAG) { 1684 /* Set the vlan id. */ 1685 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16); 1686 /* Tell hardware to add tag */ 1687 txd_lower |= htole32(E1000_TXD_CMD_VLE); 1688 } 1689 1690 i = adapter->next_avail_tx_desc; 1691 1692 /* Set up our transmit descriptors */ 1693 for (j = 0; j < nsegs; j++) { 1694 /* If adapter is 82544 and on PCIX bus */ 1695 if(adapter->pcix_82544) { 1696 DESC_ARRAY desc_array; 1697 uint32_t array_elements, counter; 1698 1699 /* 1700 * Check the Address and Length combination and 1701 * split the data accordingly 1702 */ 1703 array_elements = em_82544_fill_desc(segs[j].ds_addr, 1704 segs[j].ds_len, &desc_array); 1705 for (counter = 0; counter < array_elements; counter++) { 1706 KKASSERT(txd_used < adapter->num_tx_desc_avail); 1707 1708 tx_buffer = &adapter->tx_buffer_area[i]; 1709 ctxd = &adapter->tx_desc_base[i]; 1710 1711 ctxd->buffer_addr = htole64( 1712 desc_array.descriptor[counter].address); 1713 ctxd->lower.data = htole32( 1714 E1000_TXD_CMD_IFCS | txd_lower | 1715 desc_array.descriptor[counter].length); 1716 ctxd->upper.data = htole32(txd_upper); 1717 1718 last = i; 1719 if (++i == adapter->num_tx_desc) 1720 i = 0; 1721 1722 txd_used++; 1723 } 1724 } else { 1725 tx_buffer = &adapter->tx_buffer_area[i]; 1726 ctxd = &adapter->tx_desc_base[i]; 1727 1728 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1729 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1730 txd_lower | segs[j].ds_len); 1731 ctxd->upper.data = htole32(txd_upper); 1732 1733 last = i; 1734 if (++i == adapter->num_tx_desc) 1735 i = 0; 1736 } 1737 } 1738 1739 adapter->next_avail_tx_desc = i; 1740 if (adapter->pcix_82544) { 1741 KKASSERT(adapter->num_tx_desc_avail > txd_used); 1742 adapter->num_tx_desc_avail -= txd_used; 1743 } else { 1744 KKASSERT(adapter->num_tx_desc_avail > nsegs); 1745 adapter->num_tx_desc_avail -= nsegs; 1746 } 1747 1748 tx_buffer->m_head = m_head; 1749 tx_buffer_mapped->map = tx_buffer->map; 1750 tx_buffer->map = map; 1751 1752 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) { 1753 adapter->tx_nsegs = 0; 1754 1755 /* 1756 * Report Status (RS) is turned on 1757 * every tx_int_nsegs descriptors. 1758 */ 1759 cmd = E1000_TXD_CMD_RS; 1760 1761 /* 1762 * Keep track of the descriptor, which will 1763 * be written back by hardware. 1764 */ 1765 adapter->tx_dd[adapter->tx_dd_tail] = last; 1766 EM_INC_TXDD_IDX(adapter->tx_dd_tail); 1767 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head); 1768 } 1769 1770 /* 1771 * Last Descriptor of Packet needs End Of Packet (EOP) 1772 */ 1773 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1774 1775 if (adapter->hw.mac.type == e1000_82547) { 1776 /* 1777 * Advance the Transmit Descriptor Tail (TDT), this tells the 1778 * E1000 that this frame is available to transmit. 1779 */ 1780 if (adapter->link_duplex == HALF_DUPLEX) { 1781 em_82547_move_tail_serialized(adapter); 1782 } else { 1783 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 1784 em_82547_update_fifo_head(adapter, 1785 m_head->m_pkthdr.len); 1786 } 1787 } else { 1788 /* 1789 * Defer TDT updating, until enough descriptors are setup 1790 */ 1791 *idx = i; 1792 } 1793 return (0); 1794 } 1795 1796 /* 1797 * 82547 workaround to avoid controller hang in half-duplex environment. 1798 * The workaround is to avoid queuing a large packet that would span 1799 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1800 * in this case. We do that only when FIFO is quiescent. 1801 */ 1802 static void 1803 em_82547_move_tail_serialized(struct adapter *adapter) 1804 { 1805 struct e1000_tx_desc *tx_desc; 1806 uint16_t hw_tdt, sw_tdt, length = 0; 1807 bool eop = 0; 1808 1809 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer); 1810 1811 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 1812 sw_tdt = adapter->next_avail_tx_desc; 1813 1814 while (hw_tdt != sw_tdt) { 1815 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1816 length += tx_desc->lower.flags.length; 1817 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1818 if (++hw_tdt == adapter->num_tx_desc) 1819 hw_tdt = 0; 1820 1821 if (eop) { 1822 if (em_82547_fifo_workaround(adapter, length)) { 1823 adapter->tx_fifo_wrk_cnt++; 1824 callout_reset(&adapter->tx_fifo_timer, 1, 1825 em_82547_move_tail, adapter); 1826 break; 1827 } 1828 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 1829 em_82547_update_fifo_head(adapter, length); 1830 length = 0; 1831 } 1832 } 1833 } 1834 1835 static void 1836 em_82547_move_tail(void *xsc) 1837 { 1838 struct adapter *adapter = xsc; 1839 struct ifnet *ifp = &adapter->arpcom.ac_if; 1840 1841 lwkt_serialize_enter(ifp->if_serializer); 1842 em_82547_move_tail_serialized(adapter); 1843 lwkt_serialize_exit(ifp->if_serializer); 1844 } 1845 1846 static int 1847 em_82547_fifo_workaround(struct adapter *adapter, int len) 1848 { 1849 int fifo_space, fifo_pkt_len; 1850 1851 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1852 1853 if (adapter->link_duplex == HALF_DUPLEX) { 1854 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 1855 1856 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1857 if (em_82547_tx_fifo_reset(adapter)) 1858 return (0); 1859 else 1860 return (1); 1861 } 1862 } 1863 return (0); 1864 } 1865 1866 static void 1867 em_82547_update_fifo_head(struct adapter *adapter, int len) 1868 { 1869 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1870 1871 /* tx_fifo_head is always 16 byte aligned */ 1872 adapter->tx_fifo_head += fifo_pkt_len; 1873 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) 1874 adapter->tx_fifo_head -= adapter->tx_fifo_size; 1875 } 1876 1877 static int 1878 em_82547_tx_fifo_reset(struct adapter *adapter) 1879 { 1880 uint32_t tctl; 1881 1882 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 1883 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 1884 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 1885 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 1886 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 1887 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 1888 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 1889 /* Disable TX unit */ 1890 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 1891 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 1892 tctl & ~E1000_TCTL_EN); 1893 1894 /* Reset FIFO pointers */ 1895 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 1896 adapter->tx_head_addr); 1897 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 1898 adapter->tx_head_addr); 1899 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 1900 adapter->tx_head_addr); 1901 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 1902 adapter->tx_head_addr); 1903 1904 /* Re-enable TX unit */ 1905 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 1906 E1000_WRITE_FLUSH(&adapter->hw); 1907 1908 adapter->tx_fifo_head = 0; 1909 adapter->tx_fifo_reset_cnt++; 1910 1911 return (TRUE); 1912 } else { 1913 return (FALSE); 1914 } 1915 } 1916 1917 static void 1918 em_set_promisc(struct adapter *adapter) 1919 { 1920 struct ifnet *ifp = &adapter->arpcom.ac_if; 1921 uint32_t reg_rctl; 1922 1923 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1924 1925 if (ifp->if_flags & IFF_PROMISC) { 1926 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1927 /* Turn this on if you want to see bad packets */ 1928 if (em_debug_sbp) 1929 reg_rctl |= E1000_RCTL_SBP; 1930 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1931 } else if (ifp->if_flags & IFF_ALLMULTI) { 1932 reg_rctl |= E1000_RCTL_MPE; 1933 reg_rctl &= ~E1000_RCTL_UPE; 1934 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1935 } 1936 } 1937 1938 static void 1939 em_disable_promisc(struct adapter *adapter) 1940 { 1941 uint32_t reg_rctl; 1942 1943 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1944 1945 reg_rctl &= ~E1000_RCTL_UPE; 1946 reg_rctl &= ~E1000_RCTL_MPE; 1947 reg_rctl &= ~E1000_RCTL_SBP; 1948 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1949 } 1950 1951 static void 1952 em_set_multi(struct adapter *adapter) 1953 { 1954 struct ifnet *ifp = &adapter->arpcom.ac_if; 1955 struct ifmultiaddr *ifma; 1956 uint32_t reg_rctl = 0; 1957 uint8_t *mta; 1958 int mcnt = 0; 1959 1960 mta = adapter->mta; 1961 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1962 1963 if (adapter->hw.mac.type == e1000_82542 && 1964 adapter->hw.revision_id == E1000_REVISION_2) { 1965 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1966 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1967 e1000_pci_clear_mwi(&adapter->hw); 1968 reg_rctl |= E1000_RCTL_RST; 1969 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1970 msec_delay(5); 1971 } 1972 1973 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1974 if (ifma->ifma_addr->sa_family != AF_LINK) 1975 continue; 1976 1977 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1978 break; 1979 1980 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1981 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1982 mcnt++; 1983 } 1984 1985 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1986 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1987 reg_rctl |= E1000_RCTL_MPE; 1988 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1989 } else { 1990 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1991 } 1992 1993 if (adapter->hw.mac.type == e1000_82542 && 1994 adapter->hw.revision_id == E1000_REVISION_2) { 1995 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1996 reg_rctl &= ~E1000_RCTL_RST; 1997 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1998 msec_delay(5); 1999 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2000 e1000_pci_set_mwi(&adapter->hw); 2001 } 2002 } 2003 2004 /* 2005 * This routine checks for link status and updates statistics. 2006 */ 2007 static void 2008 em_timer(void *xsc) 2009 { 2010 struct adapter *adapter = xsc; 2011 struct ifnet *ifp = &adapter->arpcom.ac_if; 2012 2013 lwkt_serialize_enter(ifp->if_serializer); 2014 2015 em_update_link_status(adapter); 2016 em_update_stats(adapter); 2017 2018 /* Reset LAA into RAR[0] on 82571 */ 2019 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 2020 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 2021 2022 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 2023 em_print_hw_stats(adapter); 2024 2025 em_smartspeed(adapter); 2026 2027 callout_reset(&adapter->timer, hz, em_timer, adapter); 2028 2029 lwkt_serialize_exit(ifp->if_serializer); 2030 } 2031 2032 static void 2033 em_update_link_status(struct adapter *adapter) 2034 { 2035 struct e1000_hw *hw = &adapter->hw; 2036 struct ifnet *ifp = &adapter->arpcom.ac_if; 2037 device_t dev = adapter->dev; 2038 uint32_t link_check = 0; 2039 2040 /* Get the cached link value or read phy for real */ 2041 switch (hw->phy.media_type) { 2042 case e1000_media_type_copper: 2043 if (hw->mac.get_link_status) { 2044 /* Do the work to read phy */ 2045 e1000_check_for_link(hw); 2046 link_check = !hw->mac.get_link_status; 2047 if (link_check) /* ESB2 fix */ 2048 e1000_cfg_on_link_up(hw); 2049 } else { 2050 link_check = TRUE; 2051 } 2052 break; 2053 2054 case e1000_media_type_fiber: 2055 e1000_check_for_link(hw); 2056 link_check = 2057 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 2058 break; 2059 2060 case e1000_media_type_internal_serdes: 2061 e1000_check_for_link(hw); 2062 link_check = adapter->hw.mac.serdes_has_link; 2063 break; 2064 2065 case e1000_media_type_unknown: 2066 default: 2067 break; 2068 } 2069 2070 /* Now check for a transition */ 2071 if (link_check && adapter->link_active == 0) { 2072 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 2073 &adapter->link_duplex); 2074 2075 /* 2076 * Check if we should enable/disable SPEED_MODE bit on 2077 * 82571/82572 2078 */ 2079 if (adapter->link_speed != SPEED_1000 && 2080 (hw->mac.type == e1000_82571 || 2081 hw->mac.type == e1000_82572)) { 2082 int tarc0; 2083 2084 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2085 tarc0 &= ~SPEED_MODE_BIT; 2086 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2087 } 2088 if (bootverbose) { 2089 device_printf(dev, "Link is up %d Mbps %s\n", 2090 adapter->link_speed, 2091 ((adapter->link_duplex == FULL_DUPLEX) ? 2092 "Full Duplex" : "Half Duplex")); 2093 } 2094 adapter->link_active = 1; 2095 adapter->smartspeed = 0; 2096 ifp->if_baudrate = adapter->link_speed * 1000000; 2097 ifp->if_link_state = LINK_STATE_UP; 2098 if_link_state_change(ifp); 2099 } else if (!link_check && adapter->link_active == 1) { 2100 ifp->if_baudrate = adapter->link_speed = 0; 2101 adapter->link_duplex = 0; 2102 if (bootverbose) 2103 device_printf(dev, "Link is Down\n"); 2104 adapter->link_active = 0; 2105 #if 0 2106 /* Link down, disable watchdog */ 2107 if->if_timer = 0; 2108 #endif 2109 ifp->if_link_state = LINK_STATE_DOWN; 2110 if_link_state_change(ifp); 2111 } 2112 } 2113 2114 static void 2115 em_stop(struct adapter *adapter) 2116 { 2117 struct ifnet *ifp = &adapter->arpcom.ac_if; 2118 int i; 2119 2120 ASSERT_SERIALIZED(ifp->if_serializer); 2121 2122 em_disable_intr(adapter); 2123 2124 callout_stop(&adapter->timer); 2125 callout_stop(&adapter->tx_fifo_timer); 2126 2127 ifp->if_flags &= ~IFF_RUNNING; 2128 ifq_clr_oactive(&ifp->if_snd); 2129 ifp->if_timer = 0; 2130 2131 e1000_reset_hw(&adapter->hw); 2132 if (adapter->hw.mac.type >= e1000_82544) 2133 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2134 2135 for (i = 0; i < adapter->num_tx_desc; i++) { 2136 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i]; 2137 2138 if (tx_buffer->m_head != NULL) { 2139 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 2140 m_freem(tx_buffer->m_head); 2141 tx_buffer->m_head = NULL; 2142 } 2143 } 2144 2145 for (i = 0; i < adapter->num_rx_desc; i++) { 2146 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i]; 2147 2148 if (rx_buffer->m_head != NULL) { 2149 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 2150 m_freem(rx_buffer->m_head); 2151 rx_buffer->m_head = NULL; 2152 } 2153 } 2154 2155 if (adapter->fmp != NULL) 2156 m_freem(adapter->fmp); 2157 adapter->fmp = NULL; 2158 adapter->lmp = NULL; 2159 2160 adapter->csum_flags = 0; 2161 adapter->csum_lhlen = 0; 2162 adapter->csum_iphlen = 0; 2163 adapter->csum_thlen = 0; 2164 adapter->csum_mss = 0; 2165 adapter->csum_pktlen = 0; 2166 2167 adapter->tx_dd_head = 0; 2168 adapter->tx_dd_tail = 0; 2169 adapter->tx_nsegs = 0; 2170 } 2171 2172 static int 2173 em_get_hw_info(struct adapter *adapter) 2174 { 2175 device_t dev = adapter->dev; 2176 2177 /* Save off the information about this board */ 2178 adapter->hw.vendor_id = pci_get_vendor(dev); 2179 adapter->hw.device_id = pci_get_device(dev); 2180 adapter->hw.revision_id = pci_get_revid(dev); 2181 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev); 2182 adapter->hw.subsystem_device_id = pci_get_subdevice(dev); 2183 2184 /* Do Shared Code Init and Setup */ 2185 if (e1000_set_mac_type(&adapter->hw)) 2186 return ENXIO; 2187 return 0; 2188 } 2189 2190 static int 2191 em_alloc_pci_res(struct adapter *adapter) 2192 { 2193 device_t dev = adapter->dev; 2194 u_int intr_flags; 2195 int val, rid, msi_enable; 2196 2197 /* Enable bus mastering */ 2198 pci_enable_busmaster(dev); 2199 2200 adapter->memory_rid = EM_BAR_MEM; 2201 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2202 &adapter->memory_rid, RF_ACTIVE); 2203 if (adapter->memory == NULL) { 2204 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2205 return (ENXIO); 2206 } 2207 adapter->osdep.mem_bus_space_tag = 2208 rman_get_bustag(adapter->memory); 2209 adapter->osdep.mem_bus_space_handle = 2210 rman_get_bushandle(adapter->memory); 2211 2212 /* XXX This is quite goofy, it is not actually used */ 2213 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2214 2215 /* Only older adapters use IO mapping */ 2216 if (adapter->hw.mac.type > e1000_82543 && 2217 adapter->hw.mac.type < e1000_82571) { 2218 /* Figure our where our IO BAR is ? */ 2219 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) { 2220 val = pci_read_config(dev, rid, 4); 2221 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2222 adapter->io_rid = rid; 2223 break; 2224 } 2225 rid += 4; 2226 /* check for 64bit BAR */ 2227 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2228 rid += 4; 2229 } 2230 if (rid >= PCIR_CARDBUSCIS) { 2231 device_printf(dev, "Unable to locate IO BAR\n"); 2232 return (ENXIO); 2233 } 2234 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2235 &adapter->io_rid, RF_ACTIVE); 2236 if (adapter->ioport == NULL) { 2237 device_printf(dev, "Unable to allocate bus resource: " 2238 "ioport\n"); 2239 return (ENXIO); 2240 } 2241 adapter->hw.io_base = 0; 2242 adapter->osdep.io_bus_space_tag = 2243 rman_get_bustag(adapter->ioport); 2244 adapter->osdep.io_bus_space_handle = 2245 rman_get_bushandle(adapter->ioport); 2246 } 2247 2248 /* 2249 * Don't enable MSI-X on 82574, see: 2250 * 82574 specification update errata #15 2251 * 2252 * Don't enable MSI on PCI/PCI-X chips, see: 2253 * 82540 specification update errata #6 2254 * 82545 specification update errata #4 2255 * 2256 * Don't enable MSI on 82571/82572, see: 2257 * 82571/82572 specification update errata #63 2258 */ 2259 msi_enable = em_msi_enable; 2260 if (msi_enable && 2261 (!pci_is_pcie(dev) || 2262 adapter->hw.mac.type == e1000_82571 || 2263 adapter->hw.mac.type == e1000_82572)) 2264 msi_enable = 0; 2265 2266 adapter->intr_type = pci_alloc_1intr(dev, msi_enable, 2267 &adapter->intr_rid, &intr_flags); 2268 2269 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) { 2270 int unshared; 2271 2272 unshared = device_getenv_int(dev, "irq.unshared", 0); 2273 if (!unshared) { 2274 adapter->flags |= EM_FLAG_SHARED_INTR; 2275 if (bootverbose) 2276 device_printf(dev, "IRQ shared\n"); 2277 } else { 2278 intr_flags &= ~RF_SHAREABLE; 2279 if (bootverbose) 2280 device_printf(dev, "IRQ unshared\n"); 2281 } 2282 } 2283 2284 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 2285 &adapter->intr_rid, intr_flags); 2286 if (adapter->intr_res == NULL) { 2287 device_printf(dev, "Unable to allocate bus resource: " 2288 "interrupt\n"); 2289 return (ENXIO); 2290 } 2291 2292 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2293 adapter->hw.back = &adapter->osdep; 2294 return (0); 2295 } 2296 2297 static void 2298 em_free_pci_res(struct adapter *adapter) 2299 { 2300 device_t dev = adapter->dev; 2301 2302 if (adapter->intr_res != NULL) { 2303 bus_release_resource(dev, SYS_RES_IRQ, 2304 adapter->intr_rid, adapter->intr_res); 2305 } 2306 2307 if (adapter->intr_type == PCI_INTR_TYPE_MSI) 2308 pci_release_msi(dev); 2309 2310 if (adapter->memory != NULL) { 2311 bus_release_resource(dev, SYS_RES_MEMORY, 2312 adapter->memory_rid, adapter->memory); 2313 } 2314 2315 if (adapter->flash != NULL) { 2316 bus_release_resource(dev, SYS_RES_MEMORY, 2317 adapter->flash_rid, adapter->flash); 2318 } 2319 2320 if (adapter->ioport != NULL) { 2321 bus_release_resource(dev, SYS_RES_IOPORT, 2322 adapter->io_rid, adapter->ioport); 2323 } 2324 } 2325 2326 static int 2327 em_reset(struct adapter *adapter) 2328 { 2329 device_t dev = adapter->dev; 2330 uint16_t rx_buffer_size; 2331 uint32_t pba; 2332 2333 /* When hardware is reset, fifo_head is also reset */ 2334 adapter->tx_fifo_head = 0; 2335 2336 /* Set up smart power down as default off on newer adapters. */ 2337 if (!em_smart_pwr_down && 2338 (adapter->hw.mac.type == e1000_82571 || 2339 adapter->hw.mac.type == e1000_82572)) { 2340 uint16_t phy_tmp = 0; 2341 2342 /* Speed up time to link by disabling smart power down. */ 2343 e1000_read_phy_reg(&adapter->hw, 2344 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2345 phy_tmp &= ~IGP02E1000_PM_SPD; 2346 e1000_write_phy_reg(&adapter->hw, 2347 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2348 } 2349 2350 /* 2351 * Packet Buffer Allocation (PBA) 2352 * Writing PBA sets the receive portion of the buffer 2353 * the remainder is used for the transmit buffer. 2354 * 2355 * Devices before the 82547 had a Packet Buffer of 64K. 2356 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 2357 * After the 82547 the buffer was reduced to 40K. 2358 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 2359 * Note: default does not leave enough room for Jumbo Frame >10k. 2360 */ 2361 switch (adapter->hw.mac.type) { 2362 case e1000_82547: 2363 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 2364 if (adapter->hw.mac.max_frame_size > 8192) 2365 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2366 else 2367 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2368 adapter->tx_fifo_head = 0; 2369 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 2370 adapter->tx_fifo_size = 2371 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 2372 break; 2373 2374 /* Total Packet Buffer on these is 48K */ 2375 case e1000_82571: 2376 case e1000_82572: 2377 case e1000_80003es2lan: 2378 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2379 break; 2380 2381 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2382 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2383 break; 2384 2385 case e1000_82574: 2386 case e1000_82583: 2387 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2388 break; 2389 2390 case e1000_ich8lan: 2391 pba = E1000_PBA_8K; 2392 break; 2393 2394 case e1000_ich9lan: 2395 case e1000_ich10lan: 2396 #define E1000_PBA_10K 0x000A 2397 pba = E1000_PBA_10K; 2398 break; 2399 2400 case e1000_pchlan: 2401 case e1000_pch2lan: 2402 case e1000_pch_lpt: 2403 pba = E1000_PBA_26K; 2404 break; 2405 2406 default: 2407 /* Devices before 82547 had a Packet Buffer of 64K. */ 2408 if (adapter->hw.mac.max_frame_size > 8192) 2409 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2410 else 2411 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2412 } 2413 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2414 2415 /* 2416 * These parameters control the automatic generation (Tx) and 2417 * response (Rx) to Ethernet PAUSE frames. 2418 * - High water mark should allow for at least two frames to be 2419 * received after sending an XOFF. 2420 * - Low water mark works best when it is very near the high water mark. 2421 * This allows the receiver to restart by sending XON when it has 2422 * drained a bit. Here we use an arbitary value of 1500 which will 2423 * restart after one full frame is pulled from the buffer. There 2424 * could be several smaller frames in the buffer and if so they will 2425 * not trigger the XON until their total number reduces the buffer 2426 * by 1500. 2427 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2428 */ 2429 rx_buffer_size = 2430 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10; 2431 2432 adapter->hw.fc.high_water = rx_buffer_size - 2433 roundup2(adapter->hw.mac.max_frame_size, 1024); 2434 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 2435 2436 if (adapter->hw.mac.type == e1000_80003es2lan) 2437 adapter->hw.fc.pause_time = 0xFFFF; 2438 else 2439 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 2440 2441 adapter->hw.fc.send_xon = TRUE; 2442 2443 adapter->hw.fc.requested_mode = e1000_fc_full; 2444 2445 /* 2446 * Device specific overrides/settings 2447 */ 2448 switch (adapter->hw.mac.type) { 2449 case e1000_pchlan: 2450 /* Workaround: no TX flow ctrl for PCH */ 2451 adapter->hw.fc.requested_mode = e1000_fc_rx_pause; 2452 adapter->hw.fc.pause_time = 0xFFFF; /* override */ 2453 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) { 2454 adapter->hw.fc.high_water = 0x3500; 2455 adapter->hw.fc.low_water = 0x1500; 2456 } else { 2457 adapter->hw.fc.high_water = 0x5000; 2458 adapter->hw.fc.low_water = 0x3000; 2459 } 2460 adapter->hw.fc.refresh_time = 0x1000; 2461 break; 2462 2463 case e1000_pch2lan: 2464 case e1000_pch_lpt: 2465 adapter->hw.fc.high_water = 0x5C20; 2466 adapter->hw.fc.low_water = 0x5048; 2467 adapter->hw.fc.pause_time = 0x0650; 2468 adapter->hw.fc.refresh_time = 0x0400; 2469 /* Jumbos need adjusted PBA */ 2470 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) 2471 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12); 2472 else 2473 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26); 2474 break; 2475 2476 case e1000_ich9lan: 2477 case e1000_ich10lan: 2478 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) { 2479 adapter->hw.fc.high_water = 0x2800; 2480 adapter->hw.fc.low_water = 2481 adapter->hw.fc.high_water - 8; 2482 break; 2483 } 2484 /* FALL THROUGH */ 2485 default: 2486 if (adapter->hw.mac.type == e1000_80003es2lan) 2487 adapter->hw.fc.pause_time = 0xFFFF; 2488 break; 2489 } 2490 2491 /* Issue a global reset */ 2492 e1000_reset_hw(&adapter->hw); 2493 if (adapter->hw.mac.type >= e1000_82544) 2494 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2495 em_disable_aspm(adapter); 2496 2497 if (e1000_init_hw(&adapter->hw) < 0) { 2498 device_printf(dev, "Hardware Initialization Failed\n"); 2499 return (EIO); 2500 } 2501 2502 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 2503 e1000_get_phy_info(&adapter->hw); 2504 e1000_check_for_link(&adapter->hw); 2505 2506 return (0); 2507 } 2508 2509 static void 2510 em_setup_ifp(struct adapter *adapter) 2511 { 2512 struct ifnet *ifp = &adapter->arpcom.ac_if; 2513 2514 if_initname(ifp, device_get_name(adapter->dev), 2515 device_get_unit(adapter->dev)); 2516 ifp->if_softc = adapter; 2517 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2518 ifp->if_init = em_init; 2519 ifp->if_ioctl = em_ioctl; 2520 ifp->if_start = em_start; 2521 #ifdef IFPOLL_ENABLE 2522 ifp->if_npoll = em_npoll; 2523 #endif 2524 ifp->if_watchdog = em_watchdog; 2525 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1); 2526 ifq_set_ready(&ifp->if_snd); 2527 2528 ether_ifattach(ifp, adapter->hw.mac.addr, NULL); 2529 2530 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2531 if (adapter->hw.mac.type >= e1000_82543) 2532 ifp->if_capabilities |= IFCAP_HWCSUM; 2533 if (adapter->flags & EM_FLAG_TSO) 2534 ifp->if_capabilities |= IFCAP_TSO; 2535 ifp->if_capenable = ifp->if_capabilities; 2536 2537 if (ifp->if_capenable & IFCAP_TXCSUM) 2538 ifp->if_hwassist |= EM_CSUM_FEATURES; 2539 if (ifp->if_capenable & IFCAP_TSO) 2540 ifp->if_hwassist |= CSUM_TSO; 2541 2542 /* 2543 * Tell the upper layer(s) we support long frames. 2544 */ 2545 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2546 2547 /* 2548 * Specify the media types supported by this adapter and register 2549 * callbacks to update media and link information 2550 */ 2551 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2552 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2553 u_char fiber_type = IFM_1000_SX; /* default type */ 2554 2555 if (adapter->hw.mac.type == e1000_82545) 2556 fiber_type = IFM_1000_LX; 2557 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2558 0, NULL); 2559 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2560 } else { 2561 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2562 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2563 0, NULL); 2564 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2565 0, NULL); 2566 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2567 0, NULL); 2568 if (adapter->hw.phy.type != e1000_phy_ife) { 2569 ifmedia_add(&adapter->media, 2570 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2571 ifmedia_add(&adapter->media, 2572 IFM_ETHER | IFM_1000_T, 0, NULL); 2573 } 2574 } 2575 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2576 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2577 } 2578 2579 2580 /* 2581 * Workaround for SmartSpeed on 82541 and 82547 controllers 2582 */ 2583 static void 2584 em_smartspeed(struct adapter *adapter) 2585 { 2586 uint16_t phy_tmp; 2587 2588 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp || 2589 adapter->hw.mac.autoneg == 0 || 2590 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2591 return; 2592 2593 if (adapter->smartspeed == 0) { 2594 /* 2595 * If Master/Slave config fault is asserted twice, 2596 * we assume back-to-back 2597 */ 2598 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2599 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2600 return; 2601 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2602 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2603 e1000_read_phy_reg(&adapter->hw, 2604 PHY_1000T_CTRL, &phy_tmp); 2605 if (phy_tmp & CR_1000T_MS_ENABLE) { 2606 phy_tmp &= ~CR_1000T_MS_ENABLE; 2607 e1000_write_phy_reg(&adapter->hw, 2608 PHY_1000T_CTRL, phy_tmp); 2609 adapter->smartspeed++; 2610 if (adapter->hw.mac.autoneg && 2611 !e1000_phy_setup_autoneg(&adapter->hw) && 2612 !e1000_read_phy_reg(&adapter->hw, 2613 PHY_CONTROL, &phy_tmp)) { 2614 phy_tmp |= MII_CR_AUTO_NEG_EN | 2615 MII_CR_RESTART_AUTO_NEG; 2616 e1000_write_phy_reg(&adapter->hw, 2617 PHY_CONTROL, phy_tmp); 2618 } 2619 } 2620 } 2621 return; 2622 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2623 /* If still no link, perhaps using 2/3 pair cable */ 2624 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2625 phy_tmp |= CR_1000T_MS_ENABLE; 2626 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2627 if (adapter->hw.mac.autoneg && 2628 !e1000_phy_setup_autoneg(&adapter->hw) && 2629 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2630 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2631 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2632 } 2633 } 2634 2635 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2636 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2637 adapter->smartspeed = 0; 2638 } 2639 2640 static int 2641 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2642 struct em_dma_alloc *dma) 2643 { 2644 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag, 2645 EM_DBA_ALIGN, size, BUS_DMA_WAITOK, 2646 &dma->dma_tag, &dma->dma_map, 2647 &dma->dma_paddr); 2648 if (dma->dma_vaddr == NULL) 2649 return ENOMEM; 2650 else 2651 return 0; 2652 } 2653 2654 static void 2655 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2656 { 2657 if (dma->dma_tag == NULL) 2658 return; 2659 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2660 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2661 bus_dma_tag_destroy(dma->dma_tag); 2662 } 2663 2664 static int 2665 em_create_tx_ring(struct adapter *adapter) 2666 { 2667 device_t dev = adapter->dev; 2668 struct em_buffer *tx_buffer; 2669 int error, i; 2670 2671 adapter->tx_buffer_area = 2672 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc, 2673 M_DEVBUF, M_WAITOK | M_ZERO); 2674 2675 /* 2676 * Create DMA tags for tx buffers 2677 */ 2678 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 2679 1, 0, /* alignment, bounds */ 2680 BUS_SPACE_MAXADDR, /* lowaddr */ 2681 BUS_SPACE_MAXADDR, /* highaddr */ 2682 NULL, NULL, /* filter, filterarg */ 2683 EM_TSO_SIZE, /* maxsize */ 2684 EM_MAX_SCATTER, /* nsegments */ 2685 PAGE_SIZE, /* maxsegsize */ 2686 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2687 BUS_DMA_ONEBPAGE, /* flags */ 2688 &adapter->txtag); 2689 if (error) { 2690 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2691 kfree(adapter->tx_buffer_area, M_DEVBUF); 2692 adapter->tx_buffer_area = NULL; 2693 return error; 2694 } 2695 2696 /* 2697 * Create DMA maps for tx buffers 2698 */ 2699 for (i = 0; i < adapter->num_tx_desc; i++) { 2700 tx_buffer = &adapter->tx_buffer_area[i]; 2701 2702 error = bus_dmamap_create(adapter->txtag, 2703 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2704 &tx_buffer->map); 2705 if (error) { 2706 device_printf(dev, "Unable to create TX DMA map\n"); 2707 em_destroy_tx_ring(adapter, i); 2708 return error; 2709 } 2710 } 2711 return (0); 2712 } 2713 2714 static void 2715 em_init_tx_ring(struct adapter *adapter) 2716 { 2717 /* Clear the old ring contents */ 2718 bzero(adapter->tx_desc_base, 2719 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 2720 2721 /* Reset state */ 2722 adapter->next_avail_tx_desc = 0; 2723 adapter->next_tx_to_clean = 0; 2724 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2725 } 2726 2727 static void 2728 em_init_tx_unit(struct adapter *adapter) 2729 { 2730 uint32_t tctl, tarc, tipg = 0; 2731 uint64_t bus_addr; 2732 2733 /* Setup the Base and Length of the Tx Descriptor Ring */ 2734 bus_addr = adapter->txdma.dma_paddr; 2735 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 2736 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 2737 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 2738 (uint32_t)(bus_addr >> 32)); 2739 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 2740 (uint32_t)bus_addr); 2741 /* Setup the HW Tx Head and Tail descriptor pointers */ 2742 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 2743 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 2744 2745 /* Set the default values for the Tx Inter Packet Gap timer */ 2746 switch (adapter->hw.mac.type) { 2747 case e1000_82542: 2748 tipg = DEFAULT_82542_TIPG_IPGT; 2749 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2750 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2751 break; 2752 2753 case e1000_80003es2lan: 2754 tipg = DEFAULT_82543_TIPG_IPGR1; 2755 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2756 E1000_TIPG_IPGR2_SHIFT; 2757 break; 2758 2759 default: 2760 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2761 adapter->hw.phy.media_type == 2762 e1000_media_type_internal_serdes) 2763 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2764 else 2765 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2766 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2767 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2768 break; 2769 } 2770 2771 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2772 2773 /* NOTE: 0 is not allowed for TIDV */ 2774 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1); 2775 if(adapter->hw.mac.type >= e1000_82540) 2776 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0); 2777 2778 if (adapter->hw.mac.type == e1000_82571 || 2779 adapter->hw.mac.type == e1000_82572) { 2780 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2781 tarc |= SPEED_MODE_BIT; 2782 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2783 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2784 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2785 tarc |= 1; 2786 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2787 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2788 tarc |= 1; 2789 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2790 } 2791 2792 /* Program the Transmit Control Register */ 2793 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2794 tctl &= ~E1000_TCTL_CT; 2795 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2796 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2797 2798 if (adapter->hw.mac.type >= e1000_82571) 2799 tctl |= E1000_TCTL_MULR; 2800 2801 /* This write will effectively turn on the transmit unit. */ 2802 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2803 2804 if (adapter->hw.mac.type == e1000_82571 || 2805 adapter->hw.mac.type == e1000_82572 || 2806 adapter->hw.mac.type == e1000_80003es2lan) { 2807 /* Bit 28 of TARC1 must be cleared when MULR is enabled */ 2808 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2809 tarc &= ~(1 << 28); 2810 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2811 } 2812 } 2813 2814 static void 2815 em_destroy_tx_ring(struct adapter *adapter, int ndesc) 2816 { 2817 struct em_buffer *tx_buffer; 2818 int i; 2819 2820 if (adapter->tx_buffer_area == NULL) 2821 return; 2822 2823 for (i = 0; i < ndesc; i++) { 2824 tx_buffer = &adapter->tx_buffer_area[i]; 2825 2826 KKASSERT(tx_buffer->m_head == NULL); 2827 bus_dmamap_destroy(adapter->txtag, tx_buffer->map); 2828 } 2829 bus_dma_tag_destroy(adapter->txtag); 2830 2831 kfree(adapter->tx_buffer_area, M_DEVBUF); 2832 adapter->tx_buffer_area = NULL; 2833 } 2834 2835 /* 2836 * The offload context needs to be set when we transfer the first 2837 * packet of a particular protocol (TCP/UDP). This routine has been 2838 * enhanced to deal with inserted VLAN headers. 2839 * 2840 * If the new packet's ether header length, ip header length and 2841 * csum offloading type are same as the previous packet, we should 2842 * avoid allocating a new csum context descriptor; mainly to take 2843 * advantage of the pipeline effect of the TX data read request. 2844 * 2845 * This function returns number of TX descrptors allocated for 2846 * csum context. 2847 */ 2848 static int 2849 em_txcsum(struct adapter *adapter, struct mbuf *mp, 2850 uint32_t *txd_upper, uint32_t *txd_lower) 2851 { 2852 struct e1000_context_desc *TXD; 2853 int curr_txd, ehdrlen, csum_flags; 2854 uint32_t cmd, hdr_len, ip_hlen; 2855 2856 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES; 2857 ip_hlen = mp->m_pkthdr.csum_iphlen; 2858 ehdrlen = mp->m_pkthdr.csum_lhlen; 2859 2860 if (adapter->csum_lhlen == ehdrlen && 2861 adapter->csum_iphlen == ip_hlen && 2862 adapter->csum_flags == csum_flags) { 2863 /* 2864 * Same csum offload context as the previous packets; 2865 * just return. 2866 */ 2867 *txd_upper = adapter->csum_txd_upper; 2868 *txd_lower = adapter->csum_txd_lower; 2869 return 0; 2870 } 2871 2872 /* 2873 * Setup a new csum offload context. 2874 */ 2875 2876 curr_txd = adapter->next_avail_tx_desc; 2877 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 2878 2879 cmd = 0; 2880 2881 /* Setup of IP header checksum. */ 2882 if (csum_flags & CSUM_IP) { 2883 /* 2884 * Start offset for header checksum calculation. 2885 * End offset for header checksum calculation. 2886 * Offset of place to put the checksum. 2887 */ 2888 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2889 TXD->lower_setup.ip_fields.ipcse = 2890 htole16(ehdrlen + ip_hlen - 1); 2891 TXD->lower_setup.ip_fields.ipcso = 2892 ehdrlen + offsetof(struct ip, ip_sum); 2893 cmd |= E1000_TXD_CMD_IP; 2894 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2895 } 2896 hdr_len = ehdrlen + ip_hlen; 2897 2898 if (csum_flags & CSUM_TCP) { 2899 /* 2900 * Start offset for payload checksum calculation. 2901 * End offset for payload checksum calculation. 2902 * Offset of place to put the checksum. 2903 */ 2904 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2905 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2906 TXD->upper_setup.tcp_fields.tucso = 2907 hdr_len + offsetof(struct tcphdr, th_sum); 2908 cmd |= E1000_TXD_CMD_TCP; 2909 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2910 } else if (csum_flags & CSUM_UDP) { 2911 /* 2912 * Start offset for header checksum calculation. 2913 * End offset for header checksum calculation. 2914 * Offset of place to put the checksum. 2915 */ 2916 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2917 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2918 TXD->upper_setup.tcp_fields.tucso = 2919 hdr_len + offsetof(struct udphdr, uh_sum); 2920 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2921 } 2922 2923 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2924 E1000_TXD_DTYP_D; /* Data descr */ 2925 2926 /* Save the information for this csum offloading context */ 2927 adapter->csum_lhlen = ehdrlen; 2928 adapter->csum_iphlen = ip_hlen; 2929 adapter->csum_flags = csum_flags; 2930 adapter->csum_txd_upper = *txd_upper; 2931 adapter->csum_txd_lower = *txd_lower; 2932 2933 TXD->tcp_seg_setup.data = htole32(0); 2934 TXD->cmd_and_length = 2935 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2936 2937 if (++curr_txd == adapter->num_tx_desc) 2938 curr_txd = 0; 2939 2940 KKASSERT(adapter->num_tx_desc_avail > 0); 2941 adapter->num_tx_desc_avail--; 2942 2943 adapter->next_avail_tx_desc = curr_txd; 2944 return 1; 2945 } 2946 2947 static void 2948 em_txeof(struct adapter *adapter) 2949 { 2950 struct ifnet *ifp = &adapter->arpcom.ac_if; 2951 struct em_buffer *tx_buffer; 2952 int first, num_avail; 2953 2954 if (adapter->tx_dd_head == adapter->tx_dd_tail) 2955 return; 2956 2957 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 2958 return; 2959 2960 num_avail = adapter->num_tx_desc_avail; 2961 first = adapter->next_tx_to_clean; 2962 2963 while (adapter->tx_dd_head != adapter->tx_dd_tail) { 2964 struct e1000_tx_desc *tx_desc; 2965 int dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 2966 2967 tx_desc = &adapter->tx_desc_base[dd_idx]; 2968 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2969 EM_INC_TXDD_IDX(adapter->tx_dd_head); 2970 2971 if (++dd_idx == adapter->num_tx_desc) 2972 dd_idx = 0; 2973 2974 while (first != dd_idx) { 2975 logif(pkt_txclean); 2976 2977 num_avail++; 2978 2979 tx_buffer = &adapter->tx_buffer_area[first]; 2980 if (tx_buffer->m_head) { 2981 bus_dmamap_unload(adapter->txtag, 2982 tx_buffer->map); 2983 m_freem(tx_buffer->m_head); 2984 tx_buffer->m_head = NULL; 2985 } 2986 2987 if (++first == adapter->num_tx_desc) 2988 first = 0; 2989 } 2990 } else { 2991 break; 2992 } 2993 } 2994 adapter->next_tx_to_clean = first; 2995 adapter->num_tx_desc_avail = num_avail; 2996 2997 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 2998 adapter->tx_dd_head = 0; 2999 adapter->tx_dd_tail = 0; 3000 } 3001 3002 if (!EM_IS_OACTIVE(adapter)) { 3003 ifq_clr_oactive(&ifp->if_snd); 3004 3005 /* All clean, turn off the timer */ 3006 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3007 ifp->if_timer = 0; 3008 } 3009 } 3010 3011 static void 3012 em_tx_collect(struct adapter *adapter) 3013 { 3014 struct ifnet *ifp = &adapter->arpcom.ac_if; 3015 struct em_buffer *tx_buffer; 3016 int tdh, first, num_avail, dd_idx = -1; 3017 3018 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3019 return; 3020 3021 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0)); 3022 if (tdh == adapter->next_tx_to_clean) 3023 return; 3024 3025 if (adapter->tx_dd_head != adapter->tx_dd_tail) 3026 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3027 3028 num_avail = adapter->num_tx_desc_avail; 3029 first = adapter->next_tx_to_clean; 3030 3031 while (first != tdh) { 3032 logif(pkt_txclean); 3033 3034 num_avail++; 3035 3036 tx_buffer = &adapter->tx_buffer_area[first]; 3037 if (tx_buffer->m_head) { 3038 bus_dmamap_unload(adapter->txtag, 3039 tx_buffer->map); 3040 m_freem(tx_buffer->m_head); 3041 tx_buffer->m_head = NULL; 3042 } 3043 3044 if (first == dd_idx) { 3045 EM_INC_TXDD_IDX(adapter->tx_dd_head); 3046 if (adapter->tx_dd_head == adapter->tx_dd_tail) { 3047 adapter->tx_dd_head = 0; 3048 adapter->tx_dd_tail = 0; 3049 dd_idx = -1; 3050 } else { 3051 dd_idx = adapter->tx_dd[adapter->tx_dd_head]; 3052 } 3053 } 3054 3055 if (++first == adapter->num_tx_desc) 3056 first = 0; 3057 } 3058 adapter->next_tx_to_clean = first; 3059 adapter->num_tx_desc_avail = num_avail; 3060 3061 if (!EM_IS_OACTIVE(adapter)) { 3062 ifq_clr_oactive(&ifp->if_snd); 3063 3064 /* All clean, turn off the timer */ 3065 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3066 ifp->if_timer = 0; 3067 } 3068 } 3069 3070 /* 3071 * When Link is lost sometimes there is work still in the TX ring 3072 * which will result in a watchdog, rather than allow that do an 3073 * attempted cleanup and then reinit here. Note that this has been 3074 * seens mostly with fiber adapters. 3075 */ 3076 static void 3077 em_tx_purge(struct adapter *adapter) 3078 { 3079 struct ifnet *ifp = &adapter->arpcom.ac_if; 3080 3081 if (!adapter->link_active && ifp->if_timer) { 3082 em_tx_collect(adapter); 3083 if (ifp->if_timer) { 3084 if_printf(ifp, "Link lost, TX pending, reinit\n"); 3085 ifp->if_timer = 0; 3086 em_init(adapter); 3087 } 3088 } 3089 } 3090 3091 static int 3092 em_newbuf(struct adapter *adapter, int i, int init) 3093 { 3094 struct mbuf *m; 3095 bus_dma_segment_t seg; 3096 bus_dmamap_t map; 3097 struct em_buffer *rx_buffer; 3098 int error, nseg; 3099 3100 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 3101 if (m == NULL) { 3102 adapter->mbuf_cluster_failed++; 3103 if (init) { 3104 if_printf(&adapter->arpcom.ac_if, 3105 "Unable to allocate RX mbuf\n"); 3106 } 3107 return (ENOBUFS); 3108 } 3109 m->m_len = m->m_pkthdr.len = MCLBYTES; 3110 3111 if (adapter->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN) 3112 m_adj(m, ETHER_ALIGN); 3113 3114 error = bus_dmamap_load_mbuf_segment(adapter->rxtag, 3115 adapter->rx_sparemap, m, 3116 &seg, 1, &nseg, BUS_DMA_NOWAIT); 3117 if (error) { 3118 m_freem(m); 3119 if (init) { 3120 if_printf(&adapter->arpcom.ac_if, 3121 "Unable to load RX mbuf\n"); 3122 } 3123 return (error); 3124 } 3125 3126 rx_buffer = &adapter->rx_buffer_area[i]; 3127 if (rx_buffer->m_head != NULL) 3128 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 3129 3130 map = rx_buffer->map; 3131 rx_buffer->map = adapter->rx_sparemap; 3132 adapter->rx_sparemap = map; 3133 3134 rx_buffer->m_head = m; 3135 3136 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr); 3137 return (0); 3138 } 3139 3140 static int 3141 em_create_rx_ring(struct adapter *adapter) 3142 { 3143 device_t dev = adapter->dev; 3144 struct em_buffer *rx_buffer; 3145 int i, error; 3146 3147 adapter->rx_buffer_area = 3148 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc, 3149 M_DEVBUF, M_WAITOK | M_ZERO); 3150 3151 /* 3152 * Create DMA tag for rx buffers 3153 */ 3154 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */ 3155 1, 0, /* alignment, bounds */ 3156 BUS_SPACE_MAXADDR, /* lowaddr */ 3157 BUS_SPACE_MAXADDR, /* highaddr */ 3158 NULL, NULL, /* filter, filterarg */ 3159 MCLBYTES, /* maxsize */ 3160 1, /* nsegments */ 3161 MCLBYTES, /* maxsegsize */ 3162 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 3163 &adapter->rxtag); 3164 if (error) { 3165 device_printf(dev, "Unable to allocate RX DMA tag\n"); 3166 kfree(adapter->rx_buffer_area, M_DEVBUF); 3167 adapter->rx_buffer_area = NULL; 3168 return error; 3169 } 3170 3171 /* 3172 * Create spare DMA map for rx buffers 3173 */ 3174 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3175 &adapter->rx_sparemap); 3176 if (error) { 3177 device_printf(dev, "Unable to create spare RX DMA map\n"); 3178 bus_dma_tag_destroy(adapter->rxtag); 3179 kfree(adapter->rx_buffer_area, M_DEVBUF); 3180 adapter->rx_buffer_area = NULL; 3181 return error; 3182 } 3183 3184 /* 3185 * Create DMA maps for rx buffers 3186 */ 3187 for (i = 0; i < adapter->num_rx_desc; i++) { 3188 rx_buffer = &adapter->rx_buffer_area[i]; 3189 3190 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK, 3191 &rx_buffer->map); 3192 if (error) { 3193 device_printf(dev, "Unable to create RX DMA map\n"); 3194 em_destroy_rx_ring(adapter, i); 3195 return error; 3196 } 3197 } 3198 return (0); 3199 } 3200 3201 static int 3202 em_init_rx_ring(struct adapter *adapter) 3203 { 3204 int i, error; 3205 3206 /* Reset descriptor ring */ 3207 bzero(adapter->rx_desc_base, 3208 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 3209 3210 /* Allocate new ones. */ 3211 for (i = 0; i < adapter->num_rx_desc; i++) { 3212 error = em_newbuf(adapter, i, 1); 3213 if (error) 3214 return (error); 3215 } 3216 3217 /* Setup our descriptor pointers */ 3218 adapter->next_rx_desc_to_check = 0; 3219 3220 return (0); 3221 } 3222 3223 static void 3224 em_init_rx_unit(struct adapter *adapter) 3225 { 3226 struct ifnet *ifp = &adapter->arpcom.ac_if; 3227 uint64_t bus_addr; 3228 uint32_t rctl; 3229 3230 /* 3231 * Make sure receives are disabled while setting 3232 * up the descriptor ring 3233 */ 3234 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3235 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3236 3237 if (adapter->hw.mac.type >= e1000_82540) { 3238 uint32_t itr; 3239 3240 /* 3241 * Set the interrupt throttling rate. Value is calculated 3242 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 3243 */ 3244 if (adapter->int_throttle_ceil) 3245 itr = 1000000000 / 256 / adapter->int_throttle_ceil; 3246 else 3247 itr = 0; 3248 em_set_itr(adapter, itr); 3249 } 3250 3251 /* Disable accelerated ackknowledge */ 3252 if (adapter->hw.mac.type == e1000_82574) { 3253 E1000_WRITE_REG(&adapter->hw, 3254 E1000_RFCTL, E1000_RFCTL_ACK_DIS); 3255 } 3256 3257 /* Receive Checksum Offload for TCP and UDP */ 3258 if (ifp->if_capenable & IFCAP_RXCSUM) { 3259 uint32_t rxcsum; 3260 3261 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 3262 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3263 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum); 3264 } 3265 3266 /* 3267 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3268 * long latencies are observed, like Lenovo X60. This 3269 * change eliminates the problem, but since having positive 3270 * values in RDTR is a known source of problems on other 3271 * platforms another solution is being sought. 3272 */ 3273 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) { 3274 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573); 3275 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573); 3276 } 3277 3278 /* 3279 * Setup the Base and Length of the Rx Descriptor Ring 3280 */ 3281 bus_addr = adapter->rxdma.dma_paddr; 3282 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 3283 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 3284 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 3285 (uint32_t)(bus_addr >> 32)); 3286 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 3287 (uint32_t)bus_addr); 3288 3289 /* 3290 * Setup the HW Rx Head and Tail Descriptor Pointers 3291 */ 3292 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 3293 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 3294 3295 /* Set PTHRESH for improved jumbo performance */ 3296 if (((adapter->hw.mac.type == e1000_ich9lan) || 3297 (adapter->hw.mac.type == e1000_pch2lan) || 3298 (adapter->hw.mac.type == e1000_ich10lan)) && 3299 (ifp->if_mtu > ETHERMTU)) { 3300 uint32_t rxdctl; 3301 3302 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0)); 3303 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3); 3304 } 3305 3306 if (adapter->hw.mac.type >= e1000_pch2lan) { 3307 if (ifp->if_mtu > ETHERMTU) 3308 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE); 3309 else 3310 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE); 3311 } 3312 3313 /* Setup the Receive Control Register */ 3314 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3315 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3316 E1000_RCTL_RDMTS_HALF | 3317 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3318 3319 /* Make sure VLAN Filters are off */ 3320 rctl &= ~E1000_RCTL_VFE; 3321 3322 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 3323 rctl |= E1000_RCTL_SBP; 3324 else 3325 rctl &= ~E1000_RCTL_SBP; 3326 3327 switch (adapter->rx_buffer_len) { 3328 default: 3329 case 2048: 3330 rctl |= E1000_RCTL_SZ_2048; 3331 break; 3332 3333 case 4096: 3334 rctl |= E1000_RCTL_SZ_4096 | 3335 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3336 break; 3337 3338 case 8192: 3339 rctl |= E1000_RCTL_SZ_8192 | 3340 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3341 break; 3342 3343 case 16384: 3344 rctl |= E1000_RCTL_SZ_16384 | 3345 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3346 break; 3347 } 3348 3349 if (ifp->if_mtu > ETHERMTU) 3350 rctl |= E1000_RCTL_LPE; 3351 else 3352 rctl &= ~E1000_RCTL_LPE; 3353 3354 /* Enable Receives */ 3355 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3356 } 3357 3358 static void 3359 em_destroy_rx_ring(struct adapter *adapter, int ndesc) 3360 { 3361 struct em_buffer *rx_buffer; 3362 int i; 3363 3364 if (adapter->rx_buffer_area == NULL) 3365 return; 3366 3367 for (i = 0; i < ndesc; i++) { 3368 rx_buffer = &adapter->rx_buffer_area[i]; 3369 3370 KKASSERT(rx_buffer->m_head == NULL); 3371 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map); 3372 } 3373 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 3374 bus_dma_tag_destroy(adapter->rxtag); 3375 3376 kfree(adapter->rx_buffer_area, M_DEVBUF); 3377 adapter->rx_buffer_area = NULL; 3378 } 3379 3380 static void 3381 em_rxeof(struct adapter *adapter, int count) 3382 { 3383 struct ifnet *ifp = &adapter->arpcom.ac_if; 3384 uint8_t status, accept_frame = 0, eop = 0; 3385 uint16_t len, desc_len, prev_len_adj; 3386 struct e1000_rx_desc *current_desc; 3387 struct mbuf *mp; 3388 int i; 3389 3390 i = adapter->next_rx_desc_to_check; 3391 current_desc = &adapter->rx_desc_base[i]; 3392 3393 if (!(current_desc->status & E1000_RXD_STAT_DD)) 3394 return; 3395 3396 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) { 3397 struct mbuf *m = NULL; 3398 3399 logif(pkt_receive); 3400 3401 mp = adapter->rx_buffer_area[i].m_head; 3402 3403 /* 3404 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3405 * needs to access the last received byte in the mbuf. 3406 */ 3407 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3408 BUS_DMASYNC_POSTREAD); 3409 3410 accept_frame = 1; 3411 prev_len_adj = 0; 3412 desc_len = le16toh(current_desc->length); 3413 status = current_desc->status; 3414 if (status & E1000_RXD_STAT_EOP) { 3415 count--; 3416 eop = 1; 3417 if (desc_len < ETHER_CRC_LEN) { 3418 len = 0; 3419 prev_len_adj = ETHER_CRC_LEN - desc_len; 3420 } else { 3421 len = desc_len - ETHER_CRC_LEN; 3422 } 3423 } else { 3424 eop = 0; 3425 len = desc_len; 3426 } 3427 3428 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3429 uint8_t last_byte; 3430 uint32_t pkt_len = desc_len; 3431 3432 if (adapter->fmp != NULL) 3433 pkt_len += adapter->fmp->m_pkthdr.len; 3434 3435 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3436 if (TBI_ACCEPT(&adapter->hw, status, 3437 current_desc->errors, pkt_len, last_byte, 3438 adapter->min_frame_size, 3439 adapter->hw.mac.max_frame_size)) { 3440 e1000_tbi_adjust_stats_82543(&adapter->hw, 3441 &adapter->stats, pkt_len, 3442 adapter->hw.mac.addr, 3443 adapter->hw.mac.max_frame_size); 3444 if (len > 0) 3445 len--; 3446 } else { 3447 accept_frame = 0; 3448 } 3449 } 3450 3451 if (accept_frame) { 3452 if (em_newbuf(adapter, i, 0) != 0) { 3453 IFNET_STAT_INC(ifp, iqdrops, 1); 3454 goto discard; 3455 } 3456 3457 /* Assign correct length to the current fragment */ 3458 mp->m_len = len; 3459 3460 if (adapter->fmp == NULL) { 3461 mp->m_pkthdr.len = len; 3462 adapter->fmp = mp; /* Store the first mbuf */ 3463 adapter->lmp = mp; 3464 } else { 3465 /* 3466 * Chain mbuf's together 3467 */ 3468 3469 /* 3470 * Adjust length of previous mbuf in chain if 3471 * we received less than 4 bytes in the last 3472 * descriptor. 3473 */ 3474 if (prev_len_adj > 0) { 3475 adapter->lmp->m_len -= prev_len_adj; 3476 adapter->fmp->m_pkthdr.len -= 3477 prev_len_adj; 3478 } 3479 adapter->lmp->m_next = mp; 3480 adapter->lmp = adapter->lmp->m_next; 3481 adapter->fmp->m_pkthdr.len += len; 3482 } 3483 3484 if (eop) { 3485 adapter->fmp->m_pkthdr.rcvif = ifp; 3486 IFNET_STAT_INC(ifp, ipackets, 1); 3487 3488 if (ifp->if_capenable & IFCAP_RXCSUM) { 3489 em_rxcsum(adapter, current_desc, 3490 adapter->fmp); 3491 } 3492 3493 if (status & E1000_RXD_STAT_VP) { 3494 adapter->fmp->m_pkthdr.ether_vlantag = 3495 (le16toh(current_desc->special) & 3496 E1000_RXD_SPC_VLAN_MASK); 3497 adapter->fmp->m_flags |= M_VLANTAG; 3498 } 3499 m = adapter->fmp; 3500 adapter->fmp = NULL; 3501 adapter->lmp = NULL; 3502 } 3503 } else { 3504 IFNET_STAT_INC(ifp, ierrors, 1); 3505 discard: 3506 #ifdef foo 3507 /* Reuse loaded DMA map and just update mbuf chain */ 3508 mp = adapter->rx_buffer_area[i].m_head; 3509 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 3510 mp->m_data = mp->m_ext.ext_buf; 3511 mp->m_next = NULL; 3512 if (adapter->hw.mac.max_frame_size <= 3513 (MCLBYTES - ETHER_ALIGN)) 3514 m_adj(mp, ETHER_ALIGN); 3515 #endif 3516 if (adapter->fmp != NULL) { 3517 m_freem(adapter->fmp); 3518 adapter->fmp = NULL; 3519 adapter->lmp = NULL; 3520 } 3521 m = NULL; 3522 } 3523 3524 /* Zero out the receive descriptors status. */ 3525 current_desc->status = 0; 3526 3527 if (m != NULL) 3528 ifp->if_input(ifp, m, NULL, -1); 3529 3530 /* Advance our pointers to the next descriptor. */ 3531 if (++i == adapter->num_rx_desc) 3532 i = 0; 3533 current_desc = &adapter->rx_desc_base[i]; 3534 } 3535 adapter->next_rx_desc_to_check = i; 3536 3537 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3538 if (--i < 0) 3539 i = adapter->num_rx_desc - 1; 3540 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 3541 } 3542 3543 static void 3544 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc, 3545 struct mbuf *mp) 3546 { 3547 /* 82543 or newer only */ 3548 if (adapter->hw.mac.type < e1000_82543 || 3549 /* Ignore Checksum bit is set */ 3550 (rx_desc->status & E1000_RXD_STAT_IXSM)) 3551 return; 3552 3553 if ((rx_desc->status & E1000_RXD_STAT_IPCS) && 3554 !(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3555 /* IP Checksum Good */ 3556 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 3557 } 3558 3559 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) && 3560 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3561 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3562 CSUM_PSEUDO_HDR | 3563 CSUM_FRAG_NOT_CHECKED; 3564 mp->m_pkthdr.csum_data = htons(0xffff); 3565 } 3566 } 3567 3568 static void 3569 em_enable_intr(struct adapter *adapter) 3570 { 3571 uint32_t ims_mask = IMS_ENABLE_MASK; 3572 3573 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer); 3574 3575 #if 0 3576 /* XXX MSIX */ 3577 if (adapter->hw.mac.type == e1000_82574) { 3578 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK); 3579 ims_mask |= EM_MSIX_MASK; 3580 } 3581 #endif 3582 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask); 3583 } 3584 3585 static void 3586 em_disable_intr(struct adapter *adapter) 3587 { 3588 uint32_t clear = 0xffffffff; 3589 3590 /* 3591 * The first version of 82542 had an errata where when link was forced 3592 * it would stay up even up even if the cable was disconnected. 3593 * Sequence errors were used to detect the disconnect and then the 3594 * driver would unforce the link. This code in the in the ISR. For 3595 * this to work correctly the Sequence error interrupt had to be 3596 * enabled all the time. 3597 */ 3598 if (adapter->hw.mac.type == e1000_82542 && 3599 adapter->hw.revision_id == E1000_REVISION_2) 3600 clear &= ~E1000_ICR_RXSEQ; 3601 else if (adapter->hw.mac.type == e1000_82574) 3602 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0); 3603 3604 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear); 3605 3606 adapter->npoll.ifpc_stcount = 0; 3607 3608 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer); 3609 } 3610 3611 /* 3612 * Bit of a misnomer, what this really means is 3613 * to enable OS management of the system... aka 3614 * to disable special hardware management features 3615 */ 3616 static void 3617 em_get_mgmt(struct adapter *adapter) 3618 { 3619 /* A shared code workaround */ 3620 #define E1000_82542_MANC2H E1000_MANC2H 3621 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3622 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3623 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3624 3625 /* disable hardware interception of ARP */ 3626 manc &= ~(E1000_MANC_ARP_EN); 3627 3628 /* enable receiving management packets to the host */ 3629 if (adapter->hw.mac.type >= e1000_82571) { 3630 manc |= E1000_MANC_EN_MNG2HOST; 3631 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3632 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3633 manc2h |= E1000_MNG2HOST_PORT_623; 3634 manc2h |= E1000_MNG2HOST_PORT_664; 3635 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3636 } 3637 3638 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3639 } 3640 } 3641 3642 /* 3643 * Give control back to hardware management 3644 * controller if there is one. 3645 */ 3646 static void 3647 em_rel_mgmt(struct adapter *adapter) 3648 { 3649 if (adapter->flags & EM_FLAG_HAS_MGMT) { 3650 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3651 3652 /* re-enable hardware interception of ARP */ 3653 manc |= E1000_MANC_ARP_EN; 3654 3655 if (adapter->hw.mac.type >= e1000_82571) 3656 manc &= ~E1000_MANC_EN_MNG2HOST; 3657 3658 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3659 } 3660 } 3661 3662 /* 3663 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3664 * For ASF and Pass Through versions of f/w this means that 3665 * the driver is loaded. For AMT version (only with 82573) 3666 * of the f/w this means that the network i/f is open. 3667 */ 3668 static void 3669 em_get_hw_control(struct adapter *adapter) 3670 { 3671 /* Let firmware know the driver has taken over */ 3672 if (adapter->hw.mac.type == e1000_82573) { 3673 uint32_t swsm; 3674 3675 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3676 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3677 swsm | E1000_SWSM_DRV_LOAD); 3678 } else { 3679 uint32_t ctrl_ext; 3680 3681 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3682 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3683 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3684 } 3685 adapter->flags |= EM_FLAG_HW_CTRL; 3686 } 3687 3688 /* 3689 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3690 * For ASF and Pass Through versions of f/w this means that the 3691 * driver is no longer loaded. For AMT version (only with 82573) 3692 * of the f/w this means that the network i/f is closed. 3693 */ 3694 static void 3695 em_rel_hw_control(struct adapter *adapter) 3696 { 3697 if ((adapter->flags & EM_FLAG_HW_CTRL) == 0) 3698 return; 3699 adapter->flags &= ~EM_FLAG_HW_CTRL; 3700 3701 /* Let firmware taken over control of h/w */ 3702 if (adapter->hw.mac.type == e1000_82573) { 3703 uint32_t swsm; 3704 3705 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3706 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3707 swsm & ~E1000_SWSM_DRV_LOAD); 3708 } else { 3709 uint32_t ctrl_ext; 3710 3711 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3712 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3713 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3714 } 3715 } 3716 3717 static int 3718 em_is_valid_eaddr(const uint8_t *addr) 3719 { 3720 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3721 3722 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3723 return (FALSE); 3724 3725 return (TRUE); 3726 } 3727 3728 /* 3729 * Enable PCI Wake On Lan capability 3730 */ 3731 void 3732 em_enable_wol(device_t dev) 3733 { 3734 uint16_t cap, status; 3735 uint8_t id; 3736 3737 /* First find the capabilities pointer*/ 3738 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3739 3740 /* Read the PM Capabilities */ 3741 id = pci_read_config(dev, cap, 1); 3742 if (id != PCIY_PMG) /* Something wrong */ 3743 return; 3744 3745 /* 3746 * OK, we have the power capabilities, 3747 * so now get the status register 3748 */ 3749 cap += PCIR_POWER_STATUS; 3750 status = pci_read_config(dev, cap, 2); 3751 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3752 pci_write_config(dev, cap, status, 2); 3753 } 3754 3755 3756 /* 3757 * 82544 Coexistence issue workaround. 3758 * There are 2 issues. 3759 * 1. Transmit Hang issue. 3760 * To detect this issue, following equation can be used... 3761 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3762 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3763 * 3764 * 2. DAC issue. 3765 * To detect this issue, following equation can be used... 3766 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3767 * If SUM[3:0] is in between 9 to c, we will have this issue. 3768 * 3769 * WORKAROUND: 3770 * Make sure we do not have ending address 3771 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3772 */ 3773 static uint32_t 3774 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array) 3775 { 3776 uint32_t safe_terminator; 3777 3778 /* 3779 * Since issue is sensitive to length and address. 3780 * Let us first check the address... 3781 */ 3782 if (length <= 4) { 3783 desc_array->descriptor[0].address = address; 3784 desc_array->descriptor[0].length = length; 3785 desc_array->elements = 1; 3786 return (desc_array->elements); 3787 } 3788 3789 safe_terminator = 3790 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF); 3791 3792 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3793 if (safe_terminator == 0 || 3794 (safe_terminator > 4 && safe_terminator < 9) || 3795 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 3796 desc_array->descriptor[0].address = address; 3797 desc_array->descriptor[0].length = length; 3798 desc_array->elements = 1; 3799 return (desc_array->elements); 3800 } 3801 3802 desc_array->descriptor[0].address = address; 3803 desc_array->descriptor[0].length = length - 4; 3804 desc_array->descriptor[1].address = address + (length - 4); 3805 desc_array->descriptor[1].length = 4; 3806 desc_array->elements = 2; 3807 return (desc_array->elements); 3808 } 3809 3810 static void 3811 em_update_stats(struct adapter *adapter) 3812 { 3813 struct ifnet *ifp = &adapter->arpcom.ac_if; 3814 3815 if (adapter->hw.phy.media_type == e1000_media_type_copper || 3816 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3817 adapter->stats.symerrs += 3818 E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3819 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3820 } 3821 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3822 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3823 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3824 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3825 3826 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3827 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3828 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3829 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3830 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3831 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3832 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3833 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3834 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3835 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3836 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3837 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3838 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3839 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3840 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3841 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3842 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3843 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3844 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3845 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3846 3847 /* For the 64-bit byte counters the low dword must be read first. */ 3848 /* Both registers clear on the read of the high dword */ 3849 3850 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 3851 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 3852 3853 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3854 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3855 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3856 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3857 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3858 3859 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3860 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3861 3862 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3863 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3864 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3865 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3866 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3867 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3868 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3869 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3870 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3871 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3872 3873 if (adapter->hw.mac.type >= e1000_82543) { 3874 adapter->stats.algnerrc += 3875 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3876 adapter->stats.rxerrc += 3877 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3878 adapter->stats.tncrs += 3879 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3880 adapter->stats.cexterr += 3881 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3882 adapter->stats.tsctc += 3883 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3884 adapter->stats.tsctfc += 3885 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3886 } 3887 3888 IFNET_STAT_SET(ifp, collisions, adapter->stats.colc); 3889 3890 /* Rx Errors */ 3891 IFNET_STAT_SET(ifp, ierrors, 3892 adapter->dropped_pkts + adapter->stats.rxerrc + 3893 adapter->stats.crcerrs + adapter->stats.algnerrc + 3894 adapter->stats.ruc + adapter->stats.roc + 3895 adapter->stats.mpc + adapter->stats.cexterr); 3896 3897 /* Tx Errors */ 3898 IFNET_STAT_SET(ifp, oerrors, 3899 adapter->stats.ecol + adapter->stats.latecol + 3900 adapter->watchdog_events); 3901 } 3902 3903 static void 3904 em_print_debug_info(struct adapter *adapter) 3905 { 3906 device_t dev = adapter->dev; 3907 uint8_t *hw_addr = adapter->hw.hw_addr; 3908 3909 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3910 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3911 E1000_READ_REG(&adapter->hw, E1000_CTRL), 3912 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 3913 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3914 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3915 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 3916 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3917 adapter->hw.fc.high_water, 3918 adapter->hw.fc.low_water); 3919 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3920 E1000_READ_REG(&adapter->hw, E1000_TIDV), 3921 E1000_READ_REG(&adapter->hw, E1000_TADV)); 3922 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3923 E1000_READ_REG(&adapter->hw, E1000_RDTR), 3924 E1000_READ_REG(&adapter->hw, E1000_RADV)); 3925 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3926 (long long)adapter->tx_fifo_wrk_cnt, 3927 (long long)adapter->tx_fifo_reset_cnt); 3928 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3929 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 3930 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 3931 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3932 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 3933 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 3934 device_printf(dev, "Num Tx descriptors avail = %d\n", 3935 adapter->num_tx_desc_avail); 3936 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3937 adapter->no_tx_desc_avail1); 3938 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3939 adapter->no_tx_desc_avail2); 3940 device_printf(dev, "Std mbuf failed = %ld\n", 3941 adapter->mbuf_alloc_failed); 3942 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3943 adapter->mbuf_cluster_failed); 3944 device_printf(dev, "Driver dropped packets = %ld\n", 3945 adapter->dropped_pkts); 3946 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3947 adapter->no_tx_dma_setup); 3948 } 3949 3950 static void 3951 em_print_hw_stats(struct adapter *adapter) 3952 { 3953 device_t dev = adapter->dev; 3954 3955 device_printf(dev, "Excessive collisions = %lld\n", 3956 (long long)adapter->stats.ecol); 3957 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3958 device_printf(dev, "Symbol errors = %lld\n", 3959 (long long)adapter->stats.symerrs); 3960 #endif 3961 device_printf(dev, "Sequence errors = %lld\n", 3962 (long long)adapter->stats.sec); 3963 device_printf(dev, "Defer count = %lld\n", 3964 (long long)adapter->stats.dc); 3965 device_printf(dev, "Missed Packets = %lld\n", 3966 (long long)adapter->stats.mpc); 3967 device_printf(dev, "Receive No Buffers = %lld\n", 3968 (long long)adapter->stats.rnbc); 3969 /* RLEC is inaccurate on some hardware, calculate our own. */ 3970 device_printf(dev, "Receive Length Errors = %lld\n", 3971 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 3972 device_printf(dev, "Receive errors = %lld\n", 3973 (long long)adapter->stats.rxerrc); 3974 device_printf(dev, "Crc errors = %lld\n", 3975 (long long)adapter->stats.crcerrs); 3976 device_printf(dev, "Alignment errors = %lld\n", 3977 (long long)adapter->stats.algnerrc); 3978 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3979 (long long)adapter->stats.cexterr); 3980 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 3981 device_printf(dev, "watchdog timeouts = %ld\n", 3982 adapter->watchdog_events); 3983 device_printf(dev, "XON Rcvd = %lld\n", 3984 (long long)adapter->stats.xonrxc); 3985 device_printf(dev, "XON Xmtd = %lld\n", 3986 (long long)adapter->stats.xontxc); 3987 device_printf(dev, "XOFF Rcvd = %lld\n", 3988 (long long)adapter->stats.xoffrxc); 3989 device_printf(dev, "XOFF Xmtd = %lld\n", 3990 (long long)adapter->stats.xofftxc); 3991 device_printf(dev, "Good Packets Rcvd = %lld\n", 3992 (long long)adapter->stats.gprc); 3993 device_printf(dev, "Good Packets Xmtd = %lld\n", 3994 (long long)adapter->stats.gptc); 3995 } 3996 3997 static void 3998 em_print_nvm_info(struct adapter *adapter) 3999 { 4000 uint16_t eeprom_data; 4001 int i, j, row = 0; 4002 4003 /* Its a bit crude, but it gets the job done */ 4004 kprintf("\nInterface EEPROM Dump:\n"); 4005 kprintf("Offset\n0x0000 "); 4006 for (i = 0, j = 0; i < 32; i++, j++) { 4007 if (j == 8) { /* Make the offset block */ 4008 j = 0; ++row; 4009 kprintf("\n0x00%x0 ",row); 4010 } 4011 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4012 kprintf("%04x ", eeprom_data); 4013 } 4014 kprintf("\n"); 4015 } 4016 4017 static int 4018 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4019 { 4020 struct adapter *adapter; 4021 struct ifnet *ifp; 4022 int error, result; 4023 4024 result = -1; 4025 error = sysctl_handle_int(oidp, &result, 0, req); 4026 if (error || !req->newptr) 4027 return (error); 4028 4029 adapter = (struct adapter *)arg1; 4030 ifp = &adapter->arpcom.ac_if; 4031 4032 lwkt_serialize_enter(ifp->if_serializer); 4033 4034 if (result == 1) 4035 em_print_debug_info(adapter); 4036 4037 /* 4038 * This value will cause a hex dump of the 4039 * first 32 16-bit words of the EEPROM to 4040 * the screen. 4041 */ 4042 if (result == 2) 4043 em_print_nvm_info(adapter); 4044 4045 lwkt_serialize_exit(ifp->if_serializer); 4046 4047 return (error); 4048 } 4049 4050 static int 4051 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 4052 { 4053 int error, result; 4054 4055 result = -1; 4056 error = sysctl_handle_int(oidp, &result, 0, req); 4057 if (error || !req->newptr) 4058 return (error); 4059 4060 if (result == 1) { 4061 struct adapter *adapter = (struct adapter *)arg1; 4062 struct ifnet *ifp = &adapter->arpcom.ac_if; 4063 4064 lwkt_serialize_enter(ifp->if_serializer); 4065 em_print_hw_stats(adapter); 4066 lwkt_serialize_exit(ifp->if_serializer); 4067 } 4068 return (error); 4069 } 4070 4071 static void 4072 em_add_sysctl(struct adapter *adapter) 4073 { 4074 struct sysctl_ctx_list *ctx; 4075 struct sysctl_oid *tree; 4076 4077 ctx = device_get_sysctl_ctx(adapter->dev); 4078 tree = device_get_sysctl_tree(adapter->dev); 4079 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 4080 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4081 em_sysctl_debug_info, "I", "Debug Information"); 4082 4083 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 4084 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4085 em_sysctl_stats, "I", "Statistics"); 4086 4087 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 4088 OID_AUTO, "rxd", CTLFLAG_RD, 4089 &adapter->num_rx_desc, 0, NULL); 4090 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 4091 OID_AUTO, "txd", CTLFLAG_RD, 4092 &adapter->num_tx_desc, 0, NULL); 4093 4094 if (adapter->hw.mac.type >= e1000_82540) { 4095 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 4096 OID_AUTO, "int_throttle_ceil", 4097 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4098 em_sysctl_int_throttle, "I", 4099 "interrupt throttling rate"); 4100 } 4101 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), 4102 OID_AUTO, "int_tx_nsegs", 4103 CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 4104 em_sysctl_int_tx_nsegs, "I", 4105 "# segments per TX interrupt"); 4106 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), 4107 OID_AUTO, "wreg_tx_nsegs", CTLFLAG_RW, 4108 &adapter->tx_wreg_nsegs, 0, 4109 "# segments before write to hardware register"); 4110 } 4111 4112 static int 4113 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 4114 { 4115 struct adapter *adapter = (void *)arg1; 4116 struct ifnet *ifp = &adapter->arpcom.ac_if; 4117 int error, throttle; 4118 4119 throttle = adapter->int_throttle_ceil; 4120 error = sysctl_handle_int(oidp, &throttle, 0, req); 4121 if (error || req->newptr == NULL) 4122 return error; 4123 if (throttle < 0 || throttle > 1000000000 / 256) 4124 return EINVAL; 4125 4126 if (throttle) { 4127 /* 4128 * Set the interrupt throttling rate in 256ns increments, 4129 * recalculate sysctl value assignment to get exact frequency. 4130 */ 4131 throttle = 1000000000 / 256 / throttle; 4132 4133 /* Upper 16bits of ITR is reserved and should be zero */ 4134 if (throttle & 0xffff0000) 4135 return EINVAL; 4136 } 4137 4138 lwkt_serialize_enter(ifp->if_serializer); 4139 4140 if (throttle) 4141 adapter->int_throttle_ceil = 1000000000 / 256 / throttle; 4142 else 4143 adapter->int_throttle_ceil = 0; 4144 4145 if (ifp->if_flags & IFF_RUNNING) 4146 em_set_itr(adapter, throttle); 4147 4148 lwkt_serialize_exit(ifp->if_serializer); 4149 4150 if (bootverbose) { 4151 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 4152 adapter->int_throttle_ceil); 4153 } 4154 return 0; 4155 } 4156 4157 static int 4158 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 4159 { 4160 struct adapter *adapter = (void *)arg1; 4161 struct ifnet *ifp = &adapter->arpcom.ac_if; 4162 int error, segs; 4163 4164 segs = adapter->tx_int_nsegs; 4165 error = sysctl_handle_int(oidp, &segs, 0, req); 4166 if (error || req->newptr == NULL) 4167 return error; 4168 if (segs <= 0) 4169 return EINVAL; 4170 4171 lwkt_serialize_enter(ifp->if_serializer); 4172 4173 /* 4174 * Don't allow int_tx_nsegs to become: 4175 * o Less the oact_tx_desc 4176 * o Too large that no TX desc will cause TX interrupt to 4177 * be generated (OACTIVE will never recover) 4178 * o Too small that will cause tx_dd[] overflow 4179 */ 4180 if (segs < adapter->oact_tx_desc || 4181 segs >= adapter->num_tx_desc - adapter->oact_tx_desc || 4182 segs < adapter->num_tx_desc / EM_TXDD_SAFE) { 4183 error = EINVAL; 4184 } else { 4185 error = 0; 4186 adapter->tx_int_nsegs = segs; 4187 } 4188 4189 lwkt_serialize_exit(ifp->if_serializer); 4190 4191 return error; 4192 } 4193 4194 static void 4195 em_set_itr(struct adapter *adapter, uint32_t itr) 4196 { 4197 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr); 4198 if (adapter->hw.mac.type == e1000_82574) { 4199 int i; 4200 4201 /* 4202 * When using MSIX interrupts we need to 4203 * throttle using the EITR register 4204 */ 4205 for (i = 0; i < 4; ++i) { 4206 E1000_WRITE_REG(&adapter->hw, 4207 E1000_EITR_82574(i), itr); 4208 } 4209 } 4210 } 4211 4212 static void 4213 em_disable_aspm(struct adapter *adapter) 4214 { 4215 uint16_t link_cap, link_ctrl, disable; 4216 uint8_t pcie_ptr, reg; 4217 device_t dev = adapter->dev; 4218 4219 switch (adapter->hw.mac.type) { 4220 case e1000_82571: 4221 case e1000_82572: 4222 case e1000_82573: 4223 /* 4224 * 82573 specification update 4225 * errata #8 disable L0s 4226 * errata #41 disable L1 4227 * 4228 * 82571/82572 specification update 4229 # errata #13 disable L1 4230 * errata #68 disable L0s 4231 */ 4232 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 4233 break; 4234 4235 case e1000_82574: 4236 case e1000_82583: 4237 /* 4238 * 82574 specification update errata #20 4239 * 82583 specification update errata #9 4240 * 4241 * There is no need to disable L1 4242 */ 4243 disable = PCIEM_LNKCTL_ASPM_L0S; 4244 break; 4245 4246 default: 4247 return; 4248 } 4249 4250 pcie_ptr = pci_get_pciecap_ptr(dev); 4251 if (pcie_ptr == 0) 4252 return; 4253 4254 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 4255 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 4256 return; 4257 4258 if (bootverbose) { 4259 if_printf(&adapter->arpcom.ac_if, 4260 "disable ASPM %#02x\n", disable); 4261 } 4262 4263 reg = pcie_ptr + PCIER_LINKCTRL; 4264 link_ctrl = pci_read_config(dev, reg, 2); 4265 link_ctrl &= ~disable; 4266 pci_write_config(dev, reg, link_ctrl, 2); 4267 } 4268 4269 static int 4270 em_tso_pullup(struct adapter *adapter, struct mbuf **mp) 4271 { 4272 int iphlen, hoff, thoff, ex = 0; 4273 struct mbuf *m; 4274 struct ip *ip; 4275 4276 m = *mp; 4277 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 4278 4279 iphlen = m->m_pkthdr.csum_iphlen; 4280 thoff = m->m_pkthdr.csum_thlen; 4281 hoff = m->m_pkthdr.csum_lhlen; 4282 4283 KASSERT(iphlen > 0, ("invalid ip hlen")); 4284 KASSERT(thoff > 0, ("invalid tcp hlen")); 4285 KASSERT(hoff > 0, ("invalid ether hlen")); 4286 4287 if (adapter->flags & EM_FLAG_TSO_PULLEX) 4288 ex = 4; 4289 4290 if (m->m_len < hoff + iphlen + thoff + ex) { 4291 m = m_pullup(m, hoff + iphlen + thoff + ex); 4292 if (m == NULL) { 4293 *mp = NULL; 4294 return ENOBUFS; 4295 } 4296 *mp = m; 4297 } 4298 ip = mtodoff(m, struct ip *, hoff); 4299 ip->ip_len = 0; 4300 4301 return 0; 4302 } 4303 4304 static int 4305 em_tso_setup(struct adapter *adapter, struct mbuf *mp, 4306 uint32_t *txd_upper, uint32_t *txd_lower) 4307 { 4308 struct e1000_context_desc *TXD; 4309 int hoff, iphlen, thoff, hlen; 4310 int mss, pktlen, curr_txd; 4311 4312 iphlen = mp->m_pkthdr.csum_iphlen; 4313 thoff = mp->m_pkthdr.csum_thlen; 4314 hoff = mp->m_pkthdr.csum_lhlen; 4315 mss = mp->m_pkthdr.tso_segsz; 4316 pktlen = mp->m_pkthdr.len; 4317 4318 if (adapter->csum_flags == CSUM_TSO && 4319 adapter->csum_iphlen == iphlen && 4320 adapter->csum_lhlen == hoff && 4321 adapter->csum_thlen == thoff && 4322 adapter->csum_mss == mss && 4323 adapter->csum_pktlen == pktlen) { 4324 *txd_upper = adapter->csum_txd_upper; 4325 *txd_lower = adapter->csum_txd_lower; 4326 return 0; 4327 } 4328 hlen = hoff + iphlen + thoff; 4329 4330 /* 4331 * Setup a new TSO context. 4332 */ 4333 4334 curr_txd = adapter->next_avail_tx_desc; 4335 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd]; 4336 4337 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 4338 E1000_TXD_DTYP_D | /* Data descr type */ 4339 E1000_TXD_CMD_TSE; /* Do TSE on this packet */ 4340 4341 /* IP and/or TCP header checksum calculation and insertion. */ 4342 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 4343 4344 /* 4345 * Start offset for header checksum calculation. 4346 * End offset for header checksum calculation. 4347 * Offset of place put the checksum. 4348 */ 4349 TXD->lower_setup.ip_fields.ipcss = hoff; 4350 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1); 4351 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum); 4352 4353 /* 4354 * Start offset for payload checksum calculation. 4355 * End offset for payload checksum calculation. 4356 * Offset of place to put the checksum. 4357 */ 4358 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen; 4359 TXD->upper_setup.tcp_fields.tucse = 0; 4360 TXD->upper_setup.tcp_fields.tucso = 4361 hoff + iphlen + offsetof(struct tcphdr, th_sum); 4362 4363 /* 4364 * Payload size per packet w/o any headers. 4365 * Length of all headers up to payload. 4366 */ 4367 TXD->tcp_seg_setup.fields.mss = htole16(mss); 4368 TXD->tcp_seg_setup.fields.hdr_len = hlen; 4369 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS | 4370 E1000_TXD_CMD_DEXT | /* Extended descr */ 4371 E1000_TXD_CMD_TSE | /* TSE context */ 4372 E1000_TXD_CMD_IP | /* Do IP csum */ 4373 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 4374 (pktlen - hlen)); /* Total len */ 4375 4376 /* Save the information for this TSO context */ 4377 adapter->csum_flags = CSUM_TSO; 4378 adapter->csum_lhlen = hoff; 4379 adapter->csum_iphlen = iphlen; 4380 adapter->csum_thlen = thoff; 4381 adapter->csum_mss = mss; 4382 adapter->csum_pktlen = pktlen; 4383 adapter->csum_txd_upper = *txd_upper; 4384 adapter->csum_txd_lower = *txd_lower; 4385 4386 if (++curr_txd == adapter->num_tx_desc) 4387 curr_txd = 0; 4388 4389 KKASSERT(adapter->num_tx_desc_avail > 0); 4390 adapter->num_tx_desc_avail--; 4391 4392 adapter->next_avail_tx_desc = curr_txd; 4393 return 1; 4394 } 4395