1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.35 2005/06/20 15:10:40 joerg Exp $ 34 */ 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 48 * Accton EN1217 (www.accton.com) 49 * Conexant LANfinity (www.conexant.com) 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/sysctl.h> 99 #include <sys/thread2.h> 100 101 #include <net/if.h> 102 #include <net/ifq_var.h> 103 #include <net/if_arp.h> 104 #include <net/ethernet.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/vlan/if_vlan_var.h> 109 110 #include <net/bpf.h> 111 112 #include <vm/vm.h> /* for vtophys */ 113 #include <vm/pmap.h> /* for vtophys */ 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include "../mii_layer/mii.h" 122 #include "../mii_layer/miivar.h" 123 124 #include <bus/pci/pcireg.h> 125 #include <bus/pci/pcivar.h> 126 127 #define DC_USEIOSPACE 128 129 #include "if_dcreg.h" 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 /* 135 * Various supported device vendors/types and their names. 136 */ 137 static struct dc_type dc_devs[] = { 138 { DC_VENDORID_DEC, DC_DEVICEID_21143, 139 "Intel 21143 10/100BaseTX" }, 140 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 141 "Davicom DM9009 10/100BaseTX" }, 142 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 143 "Davicom DM9100 10/100BaseTX" }, 144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 145 "Davicom DM9102 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 147 "Davicom DM9102A 10/100BaseTX" }, 148 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 149 "ADMtek AL981 10/100BaseTX" }, 150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 151 "ADMtek AN985 10/100BaseTX" }, 152 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 153 "ASIX AX88140A 10/100BaseTX" }, 154 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 155 "ASIX AX88141 10/100BaseTX" }, 156 { DC_VENDORID_MX, DC_DEVICEID_98713, 157 "Macronix 98713 10/100BaseTX" }, 158 { DC_VENDORID_MX, DC_DEVICEID_98713, 159 "Macronix 98713A 10/100BaseTX" }, 160 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 161 "Compex RL100-TX 10/100BaseTX" }, 162 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 163 "Compex RL100-TX 10/100BaseTX" }, 164 { DC_VENDORID_MX, DC_DEVICEID_987x5, 165 "Macronix 98715/98715A 10/100BaseTX" }, 166 { DC_VENDORID_MX, DC_DEVICEID_987x5, 167 "Macronix 98715AEC-C 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_987x5, 169 "Macronix 98725 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_98727, 171 "Macronix 98727/98732 10/100BaseTX" }, 172 { DC_VENDORID_LO, DC_DEVICEID_82C115, 173 "LC82C115 PNIC II 10/100BaseTX" }, 174 { DC_VENDORID_LO, DC_DEVICEID_82C168, 175 "82c168 PNIC 10/100BaseTX" }, 176 { DC_VENDORID_LO, DC_DEVICEID_82C168, 177 "82c169 PNIC 10/100BaseTX" }, 178 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 179 "Accton EN1217 10/100BaseTX" }, 180 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 181 "Accton EN2242 MiniPCI 10/100BaseTX" }, 182 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 183 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 184 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 185 "3Com OfficeConnect 10/100B" }, 186 { 0, 0, NULL } 187 }; 188 189 static int dc_probe (device_t); 190 static int dc_attach (device_t); 191 static int dc_detach (device_t); 192 static int dc_suspend (device_t); 193 static int dc_resume (device_t); 194 static void dc_acpi (device_t); 195 static struct dc_type *dc_devtype (device_t); 196 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 197 static int dc_encap (struct dc_softc *, struct mbuf *, 198 u_int32_t *); 199 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 200 static int dc_rx_resync (struct dc_softc *); 201 static void dc_rxeof (struct dc_softc *); 202 static void dc_txeof (struct dc_softc *); 203 static void dc_tick (void *); 204 static void dc_tx_underrun (struct dc_softc *); 205 static void dc_intr (void *); 206 static void dc_start (struct ifnet *); 207 static int dc_ioctl (struct ifnet *, u_long, caddr_t, 208 struct ucred *); 209 #ifdef DEVICE_POLLING 210 static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd, 211 int count); 212 #endif 213 static void dc_init (void *); 214 static void dc_stop (struct dc_softc *); 215 static void dc_watchdog (struct ifnet *); 216 static void dc_shutdown (device_t); 217 static int dc_ifmedia_upd (struct ifnet *); 218 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 219 220 static void dc_delay (struct dc_softc *); 221 static void dc_eeprom_idle (struct dc_softc *); 222 static void dc_eeprom_putbyte (struct dc_softc *, int); 223 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 224 static void dc_eeprom_getword_pnic 225 (struct dc_softc *, int, u_int16_t *); 226 static void dc_eeprom_width (struct dc_softc *); 227 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, 228 int, int); 229 230 static void dc_mii_writebit (struct dc_softc *, int); 231 static int dc_mii_readbit (struct dc_softc *); 232 static void dc_mii_sync (struct dc_softc *); 233 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 234 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 235 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 236 static int dc_miibus_readreg (device_t, int, int); 237 static int dc_miibus_writereg (device_t, int, int, int); 238 static void dc_miibus_statchg (device_t); 239 static void dc_miibus_mediainit (device_t); 240 241 static u_int32_t dc_crc_mask (struct dc_softc *); 242 static void dc_setcfg (struct dc_softc *, int); 243 static void dc_setfilt_21143 (struct dc_softc *); 244 static void dc_setfilt_asix (struct dc_softc *); 245 static void dc_setfilt_admtek (struct dc_softc *); 246 247 static void dc_setfilt (struct dc_softc *); 248 249 static void dc_reset (struct dc_softc *); 250 static int dc_list_rx_init (struct dc_softc *); 251 static int dc_list_tx_init (struct dc_softc *); 252 253 static void dc_read_srom (struct dc_softc *, int); 254 static void dc_parse_21143_srom (struct dc_softc *); 255 static void dc_decode_leaf_sia (struct dc_softc *, 256 struct dc_eblock_sia *); 257 static void dc_decode_leaf_mii (struct dc_softc *, 258 struct dc_eblock_mii *); 259 static void dc_decode_leaf_sym (struct dc_softc *, 260 struct dc_eblock_sym *); 261 static void dc_apply_fixup (struct dc_softc *, int); 262 263 #ifdef DC_USEIOSPACE 264 #define DC_RES SYS_RES_IOPORT 265 #define DC_RID DC_PCI_CFBIO 266 #else 267 #define DC_RES SYS_RES_MEMORY 268 #define DC_RID DC_PCI_CFBMA 269 #endif 270 271 static device_method_t dc_methods[] = { 272 /* Device interface */ 273 DEVMETHOD(device_probe, dc_probe), 274 DEVMETHOD(device_attach, dc_attach), 275 DEVMETHOD(device_detach, dc_detach), 276 DEVMETHOD(device_suspend, dc_suspend), 277 DEVMETHOD(device_resume, dc_resume), 278 DEVMETHOD(device_shutdown, dc_shutdown), 279 280 /* bus interface */ 281 DEVMETHOD(bus_print_child, bus_generic_print_child), 282 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 283 284 /* MII interface */ 285 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 286 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 287 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 288 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 289 290 { 0, 0 } 291 }; 292 293 static driver_t dc_driver = { 294 "dc", 295 dc_methods, 296 sizeof(struct dc_softc) 297 }; 298 299 static devclass_t dc_devclass; 300 301 #ifdef __i386__ 302 static int dc_quick=1; 303 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 304 &dc_quick,0,"do not mdevget in dc driver"); 305 #endif 306 307 DECLARE_DUMMY_MODULE(if_dc); 308 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 309 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 310 311 #define DC_SETBIT(sc, reg, x) \ 312 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 313 314 #define DC_CLRBIT(sc, reg, x) \ 315 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 316 317 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 318 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 319 320 static void dc_delay(sc) 321 struct dc_softc *sc; 322 { 323 int idx; 324 325 for (idx = (300 / 33) + 1; idx > 0; idx--) 326 CSR_READ_4(sc, DC_BUSCTL); 327 } 328 329 static void dc_eeprom_width(sc) 330 struct dc_softc *sc; 331 { 332 int i; 333 334 /* Force EEPROM to idle state. */ 335 dc_eeprom_idle(sc); 336 337 /* Enter EEPROM access mode. */ 338 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 339 dc_delay(sc); 340 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 341 dc_delay(sc); 342 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 343 dc_delay(sc); 344 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 345 dc_delay(sc); 346 347 for (i = 3; i--;) { 348 if (6 & (1 << i)) 349 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 350 else 351 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 352 dc_delay(sc); 353 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 354 dc_delay(sc); 355 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 356 dc_delay(sc); 357 } 358 359 for (i = 1; i <= 12; i++) { 360 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 361 dc_delay(sc); 362 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 363 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 364 dc_delay(sc); 365 break; 366 } 367 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 368 dc_delay(sc); 369 } 370 371 /* Turn off EEPROM access mode. */ 372 dc_eeprom_idle(sc); 373 374 if (i < 4 || i > 12) 375 sc->dc_romwidth = 6; 376 else 377 sc->dc_romwidth = i; 378 379 /* Enter EEPROM access mode. */ 380 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 381 dc_delay(sc); 382 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 383 dc_delay(sc); 384 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 385 dc_delay(sc); 386 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 387 dc_delay(sc); 388 389 /* Turn off EEPROM access mode. */ 390 dc_eeprom_idle(sc); 391 } 392 393 static void dc_eeprom_idle(sc) 394 struct dc_softc *sc; 395 { 396 int i; 397 398 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 399 dc_delay(sc); 400 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 401 dc_delay(sc); 402 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 403 dc_delay(sc); 404 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 405 dc_delay(sc); 406 407 for (i = 0; i < 25; i++) { 408 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 409 dc_delay(sc); 410 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 411 dc_delay(sc); 412 } 413 414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 415 dc_delay(sc); 416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 417 dc_delay(sc); 418 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 419 420 return; 421 } 422 423 /* 424 * Send a read command and address to the EEPROM, check for ACK. 425 */ 426 static void dc_eeprom_putbyte(sc, addr) 427 struct dc_softc *sc; 428 int addr; 429 { 430 int d, i; 431 432 d = DC_EECMD_READ >> 6; 433 for (i = 3; i--; ) { 434 if (d & (1 << i)) 435 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 436 else 437 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 438 dc_delay(sc); 439 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 440 dc_delay(sc); 441 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 442 dc_delay(sc); 443 } 444 445 /* 446 * Feed in each bit and strobe the clock. 447 */ 448 for (i = sc->dc_romwidth; i--;) { 449 if (addr & (1 << i)) { 450 SIO_SET(DC_SIO_EE_DATAIN); 451 } else { 452 SIO_CLR(DC_SIO_EE_DATAIN); 453 } 454 dc_delay(sc); 455 SIO_SET(DC_SIO_EE_CLK); 456 dc_delay(sc); 457 SIO_CLR(DC_SIO_EE_CLK); 458 dc_delay(sc); 459 } 460 461 return; 462 } 463 464 /* 465 * Read a word of data stored in the EEPROM at address 'addr.' 466 * The PNIC 82c168/82c169 has its own non-standard way to read 467 * the EEPROM. 468 */ 469 static void dc_eeprom_getword_pnic(sc, addr, dest) 470 struct dc_softc *sc; 471 int addr; 472 u_int16_t *dest; 473 { 474 int i; 475 u_int32_t r; 476 477 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 478 479 for (i = 0; i < DC_TIMEOUT; i++) { 480 DELAY(1); 481 r = CSR_READ_4(sc, DC_SIO); 482 if (!(r & DC_PN_SIOCTL_BUSY)) { 483 *dest = (u_int16_t)(r & 0xFFFF); 484 return; 485 } 486 } 487 488 return; 489 } 490 491 /* 492 * Read a word of data stored in the EEPROM at address 'addr.' 493 */ 494 static void dc_eeprom_getword(sc, addr, dest) 495 struct dc_softc *sc; 496 int addr; 497 u_int16_t *dest; 498 { 499 int i; 500 u_int16_t word = 0; 501 502 /* Force EEPROM to idle state. */ 503 dc_eeprom_idle(sc); 504 505 /* Enter EEPROM access mode. */ 506 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 507 dc_delay(sc); 508 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 509 dc_delay(sc); 510 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 511 dc_delay(sc); 512 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 513 dc_delay(sc); 514 515 /* 516 * Send address of word we want to read. 517 */ 518 dc_eeprom_putbyte(sc, addr); 519 520 /* 521 * Start reading bits from EEPROM. 522 */ 523 for (i = 0x8000; i; i >>= 1) { 524 SIO_SET(DC_SIO_EE_CLK); 525 dc_delay(sc); 526 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 527 word |= i; 528 dc_delay(sc); 529 SIO_CLR(DC_SIO_EE_CLK); 530 dc_delay(sc); 531 } 532 533 /* Turn off EEPROM access mode. */ 534 dc_eeprom_idle(sc); 535 536 *dest = word; 537 538 return; 539 } 540 541 /* 542 * Read a sequence of words from the EEPROM. 543 */ 544 static void dc_read_eeprom(sc, dest, off, cnt, swap) 545 struct dc_softc *sc; 546 caddr_t dest; 547 int off; 548 int cnt; 549 int swap; 550 { 551 int i; 552 u_int16_t word = 0, *ptr; 553 554 for (i = 0; i < cnt; i++) { 555 if (DC_IS_PNIC(sc)) 556 dc_eeprom_getword_pnic(sc, off + i, &word); 557 else 558 dc_eeprom_getword(sc, off + i, &word); 559 ptr = (u_int16_t *)(dest + (i * 2)); 560 if (swap) 561 *ptr = ntohs(word); 562 else 563 *ptr = word; 564 } 565 566 return; 567 } 568 569 /* 570 * The following two routines are taken from the Macronix 98713 571 * Application Notes pp.19-21. 572 */ 573 /* 574 * Write a bit to the MII bus. 575 */ 576 static void dc_mii_writebit(sc, bit) 577 struct dc_softc *sc; 578 int bit; 579 { 580 if (bit) 581 CSR_WRITE_4(sc, DC_SIO, 582 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 583 else 584 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 585 586 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 587 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 588 589 return; 590 } 591 592 /* 593 * Read a bit from the MII bus. 594 */ 595 static int dc_mii_readbit(sc) 596 struct dc_softc *sc; 597 { 598 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 599 CSR_READ_4(sc, DC_SIO); 600 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 601 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 602 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 603 return(1); 604 605 return(0); 606 } 607 608 /* 609 * Sync the PHYs by setting data bit and strobing the clock 32 times. 610 */ 611 static void dc_mii_sync(sc) 612 struct dc_softc *sc; 613 { 614 int i; 615 616 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 617 618 for (i = 0; i < 32; i++) 619 dc_mii_writebit(sc, 1); 620 621 return; 622 } 623 624 /* 625 * Clock a series of bits through the MII. 626 */ 627 static void dc_mii_send(sc, bits, cnt) 628 struct dc_softc *sc; 629 u_int32_t bits; 630 int cnt; 631 { 632 int i; 633 634 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 635 dc_mii_writebit(sc, bits & i); 636 } 637 638 /* 639 * Read an PHY register through the MII. 640 */ 641 static int dc_mii_readreg(sc, frame) 642 struct dc_softc *sc; 643 struct dc_mii_frame *frame; 644 645 { 646 int ack, i; 647 648 crit_enter(); 649 650 /* 651 * Set up frame for RX. 652 */ 653 frame->mii_stdelim = DC_MII_STARTDELIM; 654 frame->mii_opcode = DC_MII_READOP; 655 frame->mii_turnaround = 0; 656 frame->mii_data = 0; 657 658 /* 659 * Sync the PHYs. 660 */ 661 dc_mii_sync(sc); 662 663 /* 664 * Send command/address info. 665 */ 666 dc_mii_send(sc, frame->mii_stdelim, 2); 667 dc_mii_send(sc, frame->mii_opcode, 2); 668 dc_mii_send(sc, frame->mii_phyaddr, 5); 669 dc_mii_send(sc, frame->mii_regaddr, 5); 670 671 #ifdef notdef 672 /* Idle bit */ 673 dc_mii_writebit(sc, 1); 674 dc_mii_writebit(sc, 0); 675 #endif 676 677 /* Check for ack */ 678 ack = dc_mii_readbit(sc); 679 680 /* 681 * Now try reading data bits. If the ack failed, we still 682 * need to clock through 16 cycles to keep the PHY(s) in sync. 683 */ 684 if (ack) { 685 for(i = 0; i < 16; i++) { 686 dc_mii_readbit(sc); 687 } 688 goto fail; 689 } 690 691 for (i = 0x8000; i; i >>= 1) { 692 if (!ack) { 693 if (dc_mii_readbit(sc)) 694 frame->mii_data |= i; 695 } 696 } 697 698 fail: 699 700 dc_mii_writebit(sc, 0); 701 dc_mii_writebit(sc, 0); 702 703 crit_exit(); 704 705 if (ack) 706 return(1); 707 return(0); 708 } 709 710 /* 711 * Write to a PHY register through the MII. 712 */ 713 static int dc_mii_writereg(sc, frame) 714 struct dc_softc *sc; 715 struct dc_mii_frame *frame; 716 717 { 718 crit_enter(); 719 720 /* 721 * Set up frame for TX. 722 */ 723 724 frame->mii_stdelim = DC_MII_STARTDELIM; 725 frame->mii_opcode = DC_MII_WRITEOP; 726 frame->mii_turnaround = DC_MII_TURNAROUND; 727 728 /* 729 * Sync the PHYs. 730 */ 731 dc_mii_sync(sc); 732 733 dc_mii_send(sc, frame->mii_stdelim, 2); 734 dc_mii_send(sc, frame->mii_opcode, 2); 735 dc_mii_send(sc, frame->mii_phyaddr, 5); 736 dc_mii_send(sc, frame->mii_regaddr, 5); 737 dc_mii_send(sc, frame->mii_turnaround, 2); 738 dc_mii_send(sc, frame->mii_data, 16); 739 740 /* Idle bit. */ 741 dc_mii_writebit(sc, 0); 742 dc_mii_writebit(sc, 0); 743 744 crit_exit(); 745 746 return(0); 747 } 748 749 static int dc_miibus_readreg(dev, phy, reg) 750 device_t dev; 751 int phy, reg; 752 { 753 struct dc_mii_frame frame; 754 struct dc_softc *sc; 755 int i, rval, phy_reg = 0; 756 757 sc = device_get_softc(dev); 758 bzero((char *)&frame, sizeof(frame)); 759 760 /* 761 * Note: both the AL981 and AN985 have internal PHYs, 762 * however the AL981 provides direct access to the PHY 763 * registers while the AN985 uses a serial MII interface. 764 * The AN985's MII interface is also buggy in that you 765 * can read from any MII address (0 to 31), but only address 1 766 * behaves normally. To deal with both cases, we pretend 767 * that the PHY is at MII address 1. 768 */ 769 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 770 return(0); 771 772 /* 773 * Note: the ukphy probes of the RS7112 report a PHY at 774 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 775 * so we only respond to correct one. 776 */ 777 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 778 return(0); 779 780 if (sc->dc_pmode != DC_PMODE_MII) { 781 if (phy == (MII_NPHY - 1)) { 782 switch(reg) { 783 case MII_BMSR: 784 /* 785 * Fake something to make the probe 786 * code think there's a PHY here. 787 */ 788 return(BMSR_MEDIAMASK); 789 break; 790 case MII_PHYIDR1: 791 if (DC_IS_PNIC(sc)) 792 return(DC_VENDORID_LO); 793 return(DC_VENDORID_DEC); 794 break; 795 case MII_PHYIDR2: 796 if (DC_IS_PNIC(sc)) 797 return(DC_DEVICEID_82C168); 798 return(DC_DEVICEID_21143); 799 break; 800 default: 801 return(0); 802 break; 803 } 804 } else 805 return(0); 806 } 807 808 if (DC_IS_PNIC(sc)) { 809 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 810 (phy << 23) | (reg << 18)); 811 for (i = 0; i < DC_TIMEOUT; i++) { 812 DELAY(1); 813 rval = CSR_READ_4(sc, DC_PN_MII); 814 if (!(rval & DC_PN_MII_BUSY)) { 815 rval &= 0xFFFF; 816 return(rval == 0xFFFF ? 0 : rval); 817 } 818 } 819 return(0); 820 } 821 822 if (DC_IS_COMET(sc)) { 823 switch(reg) { 824 case MII_BMCR: 825 phy_reg = DC_AL_BMCR; 826 break; 827 case MII_BMSR: 828 phy_reg = DC_AL_BMSR; 829 break; 830 case MII_PHYIDR1: 831 phy_reg = DC_AL_VENID; 832 break; 833 case MII_PHYIDR2: 834 phy_reg = DC_AL_DEVID; 835 break; 836 case MII_ANAR: 837 phy_reg = DC_AL_ANAR; 838 break; 839 case MII_ANLPAR: 840 phy_reg = DC_AL_LPAR; 841 break; 842 case MII_ANER: 843 phy_reg = DC_AL_ANER; 844 break; 845 default: 846 if_printf(&sc->arpcom.ac_if, 847 "phy_read: bad phy register %x\n", reg); 848 return(0); 849 break; 850 } 851 852 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 853 854 if (rval == 0xFFFF) 855 return(0); 856 return(rval); 857 } 858 859 frame.mii_phyaddr = phy; 860 frame.mii_regaddr = reg; 861 if (sc->dc_type == DC_TYPE_98713) { 862 phy_reg = CSR_READ_4(sc, DC_NETCFG); 863 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 864 } 865 dc_mii_readreg(sc, &frame); 866 if (sc->dc_type == DC_TYPE_98713) 867 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 868 869 return(frame.mii_data); 870 } 871 872 static int dc_miibus_writereg(dev, phy, reg, data) 873 device_t dev; 874 int phy, reg, data; 875 { 876 struct dc_softc *sc; 877 struct dc_mii_frame frame; 878 int i, phy_reg = 0; 879 880 sc = device_get_softc(dev); 881 bzero((char *)&frame, sizeof(frame)); 882 883 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 884 return(0); 885 886 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 887 return(0); 888 889 if (DC_IS_PNIC(sc)) { 890 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 891 (phy << 23) | (reg << 10) | data); 892 for (i = 0; i < DC_TIMEOUT; i++) { 893 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 894 break; 895 } 896 return(0); 897 } 898 899 if (DC_IS_COMET(sc)) { 900 switch(reg) { 901 case MII_BMCR: 902 phy_reg = DC_AL_BMCR; 903 break; 904 case MII_BMSR: 905 phy_reg = DC_AL_BMSR; 906 break; 907 case MII_PHYIDR1: 908 phy_reg = DC_AL_VENID; 909 break; 910 case MII_PHYIDR2: 911 phy_reg = DC_AL_DEVID; 912 break; 913 case MII_ANAR: 914 phy_reg = DC_AL_ANAR; 915 break; 916 case MII_ANLPAR: 917 phy_reg = DC_AL_LPAR; 918 break; 919 case MII_ANER: 920 phy_reg = DC_AL_ANER; 921 break; 922 default: 923 if_printf(&sc->arpcom.ac_if, 924 "phy_write: bad phy register %x\n", reg); 925 return(0); 926 break; 927 } 928 929 CSR_WRITE_4(sc, phy_reg, data); 930 return(0); 931 } 932 933 frame.mii_phyaddr = phy; 934 frame.mii_regaddr = reg; 935 frame.mii_data = data; 936 937 if (sc->dc_type == DC_TYPE_98713) { 938 phy_reg = CSR_READ_4(sc, DC_NETCFG); 939 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 940 } 941 dc_mii_writereg(sc, &frame); 942 if (sc->dc_type == DC_TYPE_98713) 943 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 944 945 return(0); 946 } 947 948 static void dc_miibus_statchg(dev) 949 device_t dev; 950 { 951 struct dc_softc *sc; 952 struct mii_data *mii; 953 struct ifmedia *ifm; 954 955 sc = device_get_softc(dev); 956 if (DC_IS_ADMTEK(sc)) 957 return; 958 959 mii = device_get_softc(sc->dc_miibus); 960 ifm = &mii->mii_media; 961 if (DC_IS_DAVICOM(sc) && 962 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 963 dc_setcfg(sc, ifm->ifm_media); 964 sc->dc_if_media = ifm->ifm_media; 965 } else { 966 dc_setcfg(sc, mii->mii_media_active); 967 sc->dc_if_media = mii->mii_media_active; 968 } 969 970 return; 971 } 972 973 /* 974 * Special support for DM9102A cards with HomePNA PHYs. Note: 975 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 976 * to be impossible to talk to the management interface of the DM9801 977 * PHY (its MDIO pin is not connected to anything). Consequently, 978 * the driver has to just 'know' about the additional mode and deal 979 * with it itself. *sigh* 980 */ 981 static void dc_miibus_mediainit(dev) 982 device_t dev; 983 { 984 struct dc_softc *sc; 985 struct mii_data *mii; 986 struct ifmedia *ifm; 987 int rev; 988 989 rev = pci_get_revid(dev); 990 991 sc = device_get_softc(dev); 992 mii = device_get_softc(sc->dc_miibus); 993 ifm = &mii->mii_media; 994 995 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 996 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 997 998 return; 999 } 1000 1001 #define DC_BITS_512 9 1002 #define DC_BITS_128 7 1003 #define DC_BITS_64 6 1004 1005 static u_int32_t 1006 dc_crc_mask(struct dc_softc *sc) 1007 { 1008 /* 1009 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1010 * chips is only 128 bits wide. 1011 */ 1012 if (sc->dc_flags & DC_128BIT_HASH) 1013 return ((1 << DC_BITS_128) - 1); 1014 1015 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1016 if (sc->dc_flags & DC_64BIT_HASH) 1017 return ((1 << DC_BITS_64) - 1); 1018 1019 return ((1 << DC_BITS_512) - 1); 1020 } 1021 1022 /* 1023 * 21143-style RX filter setup routine. Filter programming is done by 1024 * downloading a special setup frame into the TX engine. 21143, Macronix, 1025 * PNIC, PNIC II and Davicom chips are programmed this way. 1026 * 1027 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1028 * address (our node address) and a 512-bit hash filter for multicast 1029 * frames. We also sneak the broadcast address into the hash filter since 1030 * we need that too. 1031 */ 1032 void dc_setfilt_21143(sc) 1033 struct dc_softc *sc; 1034 { 1035 struct dc_desc *sframe; 1036 u_int32_t h, crc_mask, *sp; 1037 struct ifmultiaddr *ifma; 1038 struct ifnet *ifp; 1039 int i; 1040 1041 ifp = &sc->arpcom.ac_if; 1042 1043 i = sc->dc_cdata.dc_tx_prod; 1044 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1045 sc->dc_cdata.dc_tx_cnt++; 1046 sframe = &sc->dc_ldata->dc_tx_list[i]; 1047 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1048 bzero((char *)sp, DC_SFRAME_LEN); 1049 1050 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1051 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1052 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1053 1054 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1055 1056 /* If we want promiscuous mode, set the allframes bit. */ 1057 if (ifp->if_flags & IFF_PROMISC) 1058 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1059 else 1060 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1061 1062 if (ifp->if_flags & IFF_ALLMULTI) 1063 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1064 else 1065 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1066 1067 crc_mask = dc_crc_mask(sc); 1068 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1069 if (ifma->ifma_addr->sa_family != AF_LINK) 1070 continue; 1071 h = ether_crc32_le( 1072 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1073 ETHER_ADDR_LEN) & crc_mask; 1074 sp[h >> 4] |= 1 << (h & 0xF); 1075 } 1076 1077 if (ifp->if_flags & IFF_BROADCAST) { 1078 h = ether_crc32_le(ifp->if_broadcastaddr, 1079 ETHER_ADDR_LEN) & crc_mask; 1080 sp[h >> 4] |= 1 << (h & 0xF); 1081 } 1082 1083 /* Set our MAC address */ 1084 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1085 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1086 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1087 1088 sframe->dc_status = DC_TXSTAT_OWN; 1089 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1090 1091 /* 1092 * The PNIC takes an exceedingly long time to process its 1093 * setup frame; wait 10ms after posting the setup frame 1094 * before proceeding, just so it has time to swallow its 1095 * medicine. 1096 */ 1097 DELAY(10000); 1098 1099 ifp->if_timer = 5; 1100 1101 return; 1102 } 1103 1104 void dc_setfilt_admtek(sc) 1105 struct dc_softc *sc; 1106 { 1107 struct ifnet *ifp; 1108 int h = 0; 1109 u_int32_t crc_mask; 1110 u_int32_t hashes[2] = { 0, 0 }; 1111 struct ifmultiaddr *ifma; 1112 1113 ifp = &sc->arpcom.ac_if; 1114 1115 /* Init our MAC address */ 1116 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1117 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1118 1119 /* If we want promiscuous mode, set the allframes bit. */ 1120 if (ifp->if_flags & IFF_PROMISC) 1121 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1122 else 1123 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1124 1125 if (ifp->if_flags & IFF_ALLMULTI) 1126 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1127 else 1128 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1129 1130 /* first, zot all the existing hash bits */ 1131 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1132 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1133 1134 /* 1135 * If we're already in promisc or allmulti mode, we 1136 * don't have to bother programming the multicast filter. 1137 */ 1138 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1139 return; 1140 1141 /* now program new ones */ 1142 if (DC_IS_CENTAUR(sc)) 1143 crc_mask = dc_crc_mask(sc); 1144 else 1145 crc_mask = 0x3f; 1146 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1147 if (ifma->ifma_addr->sa_family != AF_LINK) 1148 continue; 1149 if (DC_IS_CENTAUR(sc)) { 1150 h = ether_crc32_le( 1151 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1152 ETHER_ADDR_LEN) & crc_mask; 1153 } else { 1154 h = ether_crc32_be( 1155 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1156 ETHER_ADDR_LEN); 1157 h = (h >> 26) & crc_mask; 1158 } 1159 if (h < 32) 1160 hashes[0] |= (1 << h); 1161 else 1162 hashes[1] |= (1 << (h - 32)); 1163 } 1164 1165 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1166 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1167 1168 return; 1169 } 1170 1171 void dc_setfilt_asix(sc) 1172 struct dc_softc *sc; 1173 { 1174 struct ifnet *ifp; 1175 int h = 0; 1176 u_int32_t hashes[2] = { 0, 0 }; 1177 struct ifmultiaddr *ifma; 1178 1179 ifp = &sc->arpcom.ac_if; 1180 1181 /* Init our MAC address */ 1182 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1183 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1184 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1185 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1186 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1187 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1188 1189 /* If we want promiscuous mode, set the allframes bit. */ 1190 if (ifp->if_flags & IFF_PROMISC) 1191 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1192 else 1193 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1194 1195 if (ifp->if_flags & IFF_ALLMULTI) 1196 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1197 else 1198 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1199 1200 /* 1201 * The ASIX chip has a special bit to enable reception 1202 * of broadcast frames. 1203 */ 1204 if (ifp->if_flags & IFF_BROADCAST) 1205 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1206 else 1207 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1208 1209 /* first, zot all the existing hash bits */ 1210 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1211 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1212 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1213 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1214 1215 /* 1216 * If we're already in promisc or allmulti mode, we 1217 * don't have to bother programming the multicast filter. 1218 */ 1219 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1220 return; 1221 1222 /* now program new ones */ 1223 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1224 if (ifma->ifma_addr->sa_family != AF_LINK) 1225 continue; 1226 h = ether_crc32_be( 1227 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1228 ETHER_ADDR_LEN); 1229 h = (h >> 26) & 0x3f; 1230 if (h < 32) 1231 hashes[0] |= (1 << h); 1232 else 1233 hashes[1] |= (1 << (h - 32)); 1234 } 1235 1236 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1237 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1238 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1239 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1240 1241 return; 1242 } 1243 1244 static void dc_setfilt(sc) 1245 struct dc_softc *sc; 1246 { 1247 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1248 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1249 dc_setfilt_21143(sc); 1250 1251 if (DC_IS_ASIX(sc)) 1252 dc_setfilt_asix(sc); 1253 1254 if (DC_IS_ADMTEK(sc)) 1255 dc_setfilt_admtek(sc); 1256 1257 return; 1258 } 1259 1260 /* 1261 * In order to fiddle with the 1262 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1263 * first have to put the transmit and/or receive logic in the idle state. 1264 */ 1265 static void dc_setcfg(sc, media) 1266 struct dc_softc *sc; 1267 int media; 1268 { 1269 int i, restart = 0; 1270 u_int32_t isr; 1271 1272 if (IFM_SUBTYPE(media) == IFM_NONE) 1273 return; 1274 1275 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1276 restart = 1; 1277 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1278 1279 for (i = 0; i < DC_TIMEOUT; i++) { 1280 isr = CSR_READ_4(sc, DC_ISR); 1281 if (isr & DC_ISR_TX_IDLE || 1282 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1283 break; 1284 DELAY(10); 1285 } 1286 1287 if (i == DC_TIMEOUT) { 1288 if_printf(&sc->arpcom.ac_if, 1289 "failed to force tx and rx to idle state\n"); 1290 } 1291 } 1292 1293 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1294 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1295 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1296 if (sc->dc_pmode == DC_PMODE_MII) { 1297 int watchdogreg; 1298 1299 if (DC_IS_INTEL(sc)) { 1300 /* there's a write enable bit here that reads as 1 */ 1301 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1302 watchdogreg &= ~DC_WDOG_CTLWREN; 1303 watchdogreg |= DC_WDOG_JABBERDIS; 1304 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1305 } else { 1306 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1307 } 1308 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1309 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1310 if (sc->dc_type == DC_TYPE_98713) 1311 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1312 DC_NETCFG_SCRAMBLER)); 1313 if (!DC_IS_DAVICOM(sc)) 1314 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1315 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1316 if (DC_IS_INTEL(sc)) 1317 dc_apply_fixup(sc, IFM_AUTO); 1318 } else { 1319 if (DC_IS_PNIC(sc)) { 1320 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1321 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1322 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1323 } 1324 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1325 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1326 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1327 if (DC_IS_INTEL(sc)) 1328 dc_apply_fixup(sc, 1329 (media & IFM_GMASK) == IFM_FDX ? 1330 IFM_100_TX|IFM_FDX : IFM_100_TX); 1331 } 1332 } 1333 1334 if (IFM_SUBTYPE(media) == IFM_10_T) { 1335 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1336 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1337 if (sc->dc_pmode == DC_PMODE_MII) { 1338 int watchdogreg; 1339 1340 /* there's a write enable bit here that reads as 1 */ 1341 if (DC_IS_INTEL(sc)) { 1342 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1343 watchdogreg &= ~DC_WDOG_CTLWREN; 1344 watchdogreg |= DC_WDOG_JABBERDIS; 1345 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1346 } else { 1347 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1348 } 1349 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1350 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1351 if (sc->dc_type == DC_TYPE_98713) 1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1353 if (!DC_IS_DAVICOM(sc)) 1354 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1355 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1356 if (DC_IS_INTEL(sc)) 1357 dc_apply_fixup(sc, IFM_AUTO); 1358 } else { 1359 if (DC_IS_PNIC(sc)) { 1360 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1361 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1362 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1363 } 1364 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1365 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1366 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1367 if (DC_IS_INTEL(sc)) { 1368 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1369 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1370 if ((media & IFM_GMASK) == IFM_FDX) 1371 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1372 else 1373 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1374 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1375 DC_CLRBIT(sc, DC_10BTCTRL, 1376 DC_TCTL_AUTONEGENBL); 1377 dc_apply_fixup(sc, 1378 (media & IFM_GMASK) == IFM_FDX ? 1379 IFM_10_T|IFM_FDX : IFM_10_T); 1380 DELAY(20000); 1381 } 1382 } 1383 } 1384 1385 /* 1386 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1387 * PHY and we want HomePNA mode, set the portsel bit to turn 1388 * on the external MII port. 1389 */ 1390 if (DC_IS_DAVICOM(sc)) { 1391 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1392 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1393 sc->dc_link = 1; 1394 } else { 1395 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1396 } 1397 } 1398 1399 if ((media & IFM_GMASK) == IFM_FDX) { 1400 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1401 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1402 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1403 } else { 1404 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1405 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1406 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1407 } 1408 1409 if (restart) 1410 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1411 1412 return; 1413 } 1414 1415 static void dc_reset(sc) 1416 struct dc_softc *sc; 1417 { 1418 int i; 1419 1420 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1421 1422 for (i = 0; i < DC_TIMEOUT; i++) { 1423 DELAY(10); 1424 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1425 break; 1426 } 1427 1428 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) { 1429 DELAY(10000); 1430 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1431 i = 0; 1432 } 1433 1434 if (i == DC_TIMEOUT) 1435 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 1436 1437 /* Wait a little while for the chip to get its brains in order. */ 1438 DELAY(1000); 1439 1440 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1441 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1442 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1443 1444 /* 1445 * Bring the SIA out of reset. In some cases, it looks 1446 * like failing to unreset the SIA soon enough gets it 1447 * into a state where it will never come out of reset 1448 * until we reset the whole chip again. 1449 */ 1450 if (DC_IS_INTEL(sc)) { 1451 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1452 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1453 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1454 } 1455 1456 return; 1457 } 1458 1459 static struct dc_type *dc_devtype(dev) 1460 device_t dev; 1461 { 1462 struct dc_type *t; 1463 u_int32_t rev; 1464 1465 t = dc_devs; 1466 1467 while(t->dc_name != NULL) { 1468 if ((pci_get_vendor(dev) == t->dc_vid) && 1469 (pci_get_device(dev) == t->dc_did)) { 1470 /* Check the PCI revision */ 1471 rev = pci_get_revid(dev); 1472 if (t->dc_did == DC_DEVICEID_98713 && 1473 rev >= DC_REVISION_98713A) 1474 t++; 1475 if (t->dc_did == DC_DEVICEID_98713_CP && 1476 rev >= DC_REVISION_98713A) 1477 t++; 1478 if (t->dc_did == DC_DEVICEID_987x5 && 1479 rev >= DC_REVISION_98715AEC_C) 1480 t++; 1481 if (t->dc_did == DC_DEVICEID_987x5 && 1482 rev >= DC_REVISION_98725) 1483 t++; 1484 if (t->dc_did == DC_DEVICEID_AX88140A && 1485 rev >= DC_REVISION_88141) 1486 t++; 1487 if (t->dc_did == DC_DEVICEID_82C168 && 1488 rev >= DC_REVISION_82C169) 1489 t++; 1490 if (t->dc_did == DC_DEVICEID_DM9102 && 1491 rev >= DC_REVISION_DM9102A) 1492 t++; 1493 return(t); 1494 } 1495 t++; 1496 } 1497 1498 return(NULL); 1499 } 1500 1501 /* 1502 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1503 * IDs against our list and return a device name if we find a match. 1504 * We do a little bit of extra work to identify the exact type of 1505 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1506 * but different revision IDs. The same is true for 98715/98715A 1507 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1508 * cases, the exact chip revision affects driver behavior. 1509 */ 1510 static int dc_probe(dev) 1511 device_t dev; 1512 { 1513 struct dc_type *t; 1514 1515 t = dc_devtype(dev); 1516 1517 if (t != NULL) { 1518 device_set_desc(dev, t->dc_name); 1519 return(0); 1520 } 1521 1522 return(ENXIO); 1523 } 1524 1525 static void dc_acpi(dev) 1526 device_t dev; 1527 { 1528 u_int32_t r, cptr; 1529 1530 /* Find the location of the capabilities block */ 1531 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1532 1533 r = pci_read_config(dev, cptr, 4) & 0xFF; 1534 if (r == 0x01) { 1535 1536 r = pci_read_config(dev, cptr + 4, 4); 1537 if (r & DC_PSTATE_D3) { 1538 u_int32_t iobase, membase, irq; 1539 struct dc_softc *sc; 1540 1541 /* Save important PCI config data. */ 1542 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1543 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1544 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1545 1546 sc = device_get_softc(dev); 1547 /* Reset the power state. */ 1548 if_printf(&sc->arpcom.ac_if, 1549 "chip is in D%d power mode " 1550 "-- setting to D0\n", r & DC_PSTATE_D3); 1551 r &= 0xFFFFFFFC; 1552 pci_write_config(dev, cptr + 4, r, 4); 1553 1554 /* Restore PCI config data. */ 1555 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1556 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1557 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1558 } 1559 } 1560 } 1561 1562 static void dc_apply_fixup(sc, media) 1563 struct dc_softc *sc; 1564 int media; 1565 { 1566 struct dc_mediainfo *m; 1567 u_int8_t *p; 1568 int i; 1569 u_int32_t reg; 1570 1571 m = sc->dc_mi; 1572 1573 while (m != NULL) { 1574 if (m->dc_media == media) 1575 break; 1576 m = m->dc_next; 1577 } 1578 1579 if (m == NULL) 1580 return; 1581 1582 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1583 reg = (p[0] | (p[1] << 8)) << 16; 1584 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1585 } 1586 1587 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1588 reg = (p[0] | (p[1] << 8)) << 16; 1589 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1590 } 1591 1592 return; 1593 } 1594 1595 static void dc_decode_leaf_sia(sc, l) 1596 struct dc_softc *sc; 1597 struct dc_eblock_sia *l; 1598 { 1599 struct dc_mediainfo *m; 1600 1601 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1602 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1603 m->dc_media = IFM_10_T; 1604 1605 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1606 m->dc_media = IFM_10_T|IFM_FDX; 1607 1608 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1609 m->dc_media = IFM_10_2; 1610 1611 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1612 m->dc_media = IFM_10_5; 1613 1614 m->dc_gp_len = 2; 1615 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1616 1617 m->dc_next = sc->dc_mi; 1618 sc->dc_mi = m; 1619 1620 sc->dc_pmode = DC_PMODE_SIA; 1621 1622 return; 1623 } 1624 1625 static void dc_decode_leaf_sym(sc, l) 1626 struct dc_softc *sc; 1627 struct dc_eblock_sym *l; 1628 { 1629 struct dc_mediainfo *m; 1630 1631 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1632 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1633 m->dc_media = IFM_100_TX; 1634 1635 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1636 m->dc_media = IFM_100_TX|IFM_FDX; 1637 1638 m->dc_gp_len = 2; 1639 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1640 1641 m->dc_next = sc->dc_mi; 1642 sc->dc_mi = m; 1643 1644 sc->dc_pmode = DC_PMODE_SYM; 1645 1646 return; 1647 } 1648 1649 static void dc_decode_leaf_mii(sc, l) 1650 struct dc_softc *sc; 1651 struct dc_eblock_mii *l; 1652 { 1653 u_int8_t *p; 1654 struct dc_mediainfo *m; 1655 1656 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1657 /* We abuse IFM_AUTO to represent MII. */ 1658 m->dc_media = IFM_AUTO; 1659 m->dc_gp_len = l->dc_gpr_len; 1660 1661 p = (u_int8_t *)l; 1662 p += sizeof(struct dc_eblock_mii); 1663 m->dc_gp_ptr = p; 1664 p += 2 * l->dc_gpr_len; 1665 m->dc_reset_len = *p; 1666 p++; 1667 m->dc_reset_ptr = p; 1668 1669 m->dc_next = sc->dc_mi; 1670 sc->dc_mi = m; 1671 1672 return; 1673 } 1674 1675 static void dc_read_srom(sc, bits) 1676 struct dc_softc *sc; 1677 int bits; 1678 { 1679 int size; 1680 1681 size = 2 << bits; 1682 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT); 1683 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1684 } 1685 1686 static void dc_parse_21143_srom(sc) 1687 struct dc_softc *sc; 1688 { 1689 struct dc_leaf_hdr *lhdr; 1690 struct dc_eblock_hdr *hdr; 1691 int i, loff; 1692 char *ptr; 1693 int have_mii; 1694 1695 have_mii = 0; 1696 loff = sc->dc_srom[27]; 1697 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1698 1699 ptr = (char *)lhdr; 1700 ptr += sizeof(struct dc_leaf_hdr) - 1; 1701 /* 1702 * Look if we got a MII media block. 1703 */ 1704 for (i = 0; i < lhdr->dc_mcnt; i++) { 1705 hdr = (struct dc_eblock_hdr *)ptr; 1706 if (hdr->dc_type == DC_EBLOCK_MII) 1707 have_mii++; 1708 1709 ptr += (hdr->dc_len & 0x7F); 1710 ptr++; 1711 } 1712 1713 /* 1714 * Do the same thing again. Only use SIA and SYM media 1715 * blocks if no MII media block is available. 1716 */ 1717 ptr = (char *)lhdr; 1718 ptr += sizeof(struct dc_leaf_hdr) - 1; 1719 for (i = 0; i < lhdr->dc_mcnt; i++) { 1720 hdr = (struct dc_eblock_hdr *)ptr; 1721 switch(hdr->dc_type) { 1722 case DC_EBLOCK_MII: 1723 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1724 break; 1725 case DC_EBLOCK_SIA: 1726 if (! have_mii) 1727 dc_decode_leaf_sia(sc, 1728 (struct dc_eblock_sia *)hdr); 1729 break; 1730 case DC_EBLOCK_SYM: 1731 if (! have_mii) 1732 dc_decode_leaf_sym(sc, 1733 (struct dc_eblock_sym *)hdr); 1734 break; 1735 default: 1736 /* Don't care. Yet. */ 1737 break; 1738 } 1739 ptr += (hdr->dc_len & 0x7F); 1740 ptr++; 1741 } 1742 1743 return; 1744 } 1745 1746 /* 1747 * Attach the interface. Allocate softc structures, do ifmedia 1748 * setup and ethernet/BPF attach. 1749 */ 1750 static int dc_attach(dev) 1751 device_t dev; 1752 { 1753 int tmp = 0; 1754 u_char eaddr[ETHER_ADDR_LEN]; 1755 u_int32_t command; 1756 struct dc_softc *sc; 1757 struct ifnet *ifp; 1758 u_int32_t revision; 1759 int error = 0, rid, mac_offset; 1760 1761 sc = device_get_softc(dev); 1762 callout_init(&sc->dc_stat_timer); 1763 1764 ifp = &sc->arpcom.ac_if; 1765 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1766 1767 /* 1768 * Handle power management nonsense. 1769 */ 1770 dc_acpi(dev); 1771 1772 /* 1773 * Map control/status registers. 1774 */ 1775 pci_enable_busmaster(dev); 1776 1777 rid = DC_RID; 1778 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1779 1780 if (sc->dc_res == NULL) { 1781 device_printf(dev, "couldn't map ports/memory\n"); 1782 error = ENXIO; 1783 goto fail; 1784 } 1785 1786 sc->dc_btag = rman_get_bustag(sc->dc_res); 1787 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1788 1789 /* Allocate interrupt */ 1790 rid = 0; 1791 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1792 RF_SHAREABLE | RF_ACTIVE); 1793 1794 if (sc->dc_irq == NULL) { 1795 device_printf(dev, "couldn't map interrupt\n"); 1796 error = ENXIO; 1797 goto fail; 1798 } 1799 1800 /* Need this info to decide on a chip type. */ 1801 sc->dc_info = dc_devtype(dev); 1802 revision = pci_get_revid(dev); 1803 1804 /* Get the eeprom width, but PNIC has diff eeprom */ 1805 if (sc->dc_info->dc_did != DC_DEVICEID_82C168) 1806 dc_eeprom_width(sc); 1807 1808 switch(sc->dc_info->dc_did) { 1809 case DC_DEVICEID_21143: 1810 sc->dc_type = DC_TYPE_21143; 1811 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1812 sc->dc_flags |= DC_REDUCED_MII_POLL; 1813 /* Save EEPROM contents so we can parse them later. */ 1814 dc_read_srom(sc, sc->dc_romwidth); 1815 break; 1816 case DC_DEVICEID_DM9009: 1817 case DC_DEVICEID_DM9100: 1818 case DC_DEVICEID_DM9102: 1819 sc->dc_type = DC_TYPE_DM9102; 1820 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1821 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1822 sc->dc_pmode = DC_PMODE_MII; 1823 /* Increase the latency timer value. */ 1824 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1825 command &= 0xFFFF00FF; 1826 command |= 0x00008000; 1827 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1828 break; 1829 case DC_DEVICEID_AL981: 1830 sc->dc_type = DC_TYPE_AL981; 1831 sc->dc_flags |= DC_TX_USE_TX_INTR; 1832 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1833 sc->dc_pmode = DC_PMODE_MII; 1834 dc_read_srom(sc, sc->dc_romwidth); 1835 break; 1836 case DC_DEVICEID_AN985: 1837 case DC_DEVICEID_EN2242: 1838 case DC_DEVICEID_3CSOHOB: 1839 sc->dc_type = DC_TYPE_AN985; 1840 sc->dc_flags |= DC_64BIT_HASH; 1841 sc->dc_flags |= DC_TX_USE_TX_INTR; 1842 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1843 sc->dc_pmode = DC_PMODE_MII; 1844 dc_read_srom(sc, sc->dc_romwidth); 1845 break; 1846 case DC_DEVICEID_98713: 1847 case DC_DEVICEID_98713_CP: 1848 if (revision < DC_REVISION_98713A) { 1849 sc->dc_type = DC_TYPE_98713; 1850 } 1851 if (revision >= DC_REVISION_98713A) { 1852 sc->dc_type = DC_TYPE_98713A; 1853 sc->dc_flags |= DC_21143_NWAY; 1854 } 1855 sc->dc_flags |= DC_REDUCED_MII_POLL; 1856 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1857 break; 1858 case DC_DEVICEID_987x5: 1859 case DC_DEVICEID_EN1217: 1860 /* 1861 * Macronix MX98715AEC-C/D/E parts have only a 1862 * 128-bit hash table. We need to deal with these 1863 * in the same manner as the PNIC II so that we 1864 * get the right number of bits out of the 1865 * CRC routine. 1866 */ 1867 if (revision >= DC_REVISION_98715AEC_C && 1868 revision < DC_REVISION_98725) 1869 sc->dc_flags |= DC_128BIT_HASH; 1870 sc->dc_type = DC_TYPE_987x5; 1871 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1872 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1873 break; 1874 case DC_DEVICEID_98727: 1875 sc->dc_type = DC_TYPE_987x5; 1876 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1877 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1878 break; 1879 case DC_DEVICEID_82C115: 1880 sc->dc_type = DC_TYPE_PNICII; 1881 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1882 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1883 break; 1884 case DC_DEVICEID_82C168: 1885 sc->dc_type = DC_TYPE_PNIC; 1886 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1887 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1888 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK); 1889 if (revision < DC_REVISION_82C169) 1890 sc->dc_pmode = DC_PMODE_SYM; 1891 break; 1892 case DC_DEVICEID_AX88140A: 1893 sc->dc_type = DC_TYPE_ASIX; 1894 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1895 sc->dc_flags |= DC_REDUCED_MII_POLL; 1896 sc->dc_pmode = DC_PMODE_MII; 1897 break; 1898 case DC_DEVICEID_RS7112: 1899 sc->dc_type = DC_TYPE_CONEXANT; 1900 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1901 sc->dc_flags |= DC_REDUCED_MII_POLL; 1902 sc->dc_pmode = DC_PMODE_MII; 1903 dc_read_srom(sc, sc->dc_romwidth); 1904 break; 1905 default: 1906 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 1907 break; 1908 } 1909 1910 /* Save the cache line size. */ 1911 if (DC_IS_DAVICOM(sc)) 1912 sc->dc_cachesize = 0; 1913 else 1914 sc->dc_cachesize = pci_read_config(dev, 1915 DC_PCI_CFLT, 4) & 0xFF; 1916 1917 /* Reset the adapter. */ 1918 dc_reset(sc); 1919 1920 /* Take 21143 out of snooze mode */ 1921 if (DC_IS_INTEL(sc)) { 1922 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1923 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1924 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1925 } 1926 1927 /* 1928 * Try to learn something about the supported media. 1929 * We know that ASIX and ADMtek and Davicom devices 1930 * will *always* be using MII media, so that's a no-brainer. 1931 * The tricky ones are the Macronix/PNIC II and the 1932 * Intel 21143. 1933 */ 1934 if (DC_IS_INTEL(sc)) 1935 dc_parse_21143_srom(sc); 1936 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1937 if (sc->dc_type == DC_TYPE_98713) 1938 sc->dc_pmode = DC_PMODE_MII; 1939 else 1940 sc->dc_pmode = DC_PMODE_SYM; 1941 } else if (!sc->dc_pmode) 1942 sc->dc_pmode = DC_PMODE_MII; 1943 1944 /* 1945 * Get station address from the EEPROM. 1946 */ 1947 switch(sc->dc_type) { 1948 case DC_TYPE_98713: 1949 case DC_TYPE_98713A: 1950 case DC_TYPE_987x5: 1951 case DC_TYPE_PNICII: 1952 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1953 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1954 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1955 break; 1956 case DC_TYPE_PNIC: 1957 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1958 break; 1959 case DC_TYPE_DM9102: 1960 case DC_TYPE_21143: 1961 case DC_TYPE_ASIX: 1962 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1963 break; 1964 case DC_TYPE_AL981: 1965 case DC_TYPE_AN985: 1966 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 1967 ETHER_ADDR_LEN); 1968 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1969 break; 1970 case DC_TYPE_CONEXANT: 1971 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 1972 break; 1973 default: 1974 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1975 break; 1976 } 1977 1978 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1979 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1980 1981 if (sc->dc_ldata == NULL) { 1982 device_printf(dev, "no memory for list buffers!\n"); 1983 error = ENXIO; 1984 goto fail; 1985 } 1986 1987 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1988 1989 ifp->if_softc = sc; 1990 ifp->if_mtu = ETHERMTU; 1991 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1992 ifp->if_ioctl = dc_ioctl; 1993 ifp->if_start = dc_start; 1994 #ifdef DEVICE_POLLING 1995 ifp->if_poll = dc_poll; 1996 #endif 1997 ifp->if_watchdog = dc_watchdog; 1998 ifp->if_init = dc_init; 1999 ifp->if_baudrate = 10000000; 2000 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2001 ifq_set_ready(&ifp->if_snd); 2002 2003 /* 2004 * Do MII setup. If this is a 21143, check for a PHY on the 2005 * MII bus after applying any necessary fixups to twiddle the 2006 * GPIO bits. If we don't end up finding a PHY, restore the 2007 * old selection (SIA only or SIA/SYM) and attach the dcphy 2008 * driver instead. 2009 */ 2010 if (DC_IS_INTEL(sc)) { 2011 dc_apply_fixup(sc, IFM_AUTO); 2012 tmp = sc->dc_pmode; 2013 sc->dc_pmode = DC_PMODE_MII; 2014 } 2015 2016 error = mii_phy_probe(dev, &sc->dc_miibus, 2017 dc_ifmedia_upd, dc_ifmedia_sts); 2018 2019 if (error && DC_IS_INTEL(sc)) { 2020 sc->dc_pmode = tmp; 2021 if (sc->dc_pmode != DC_PMODE_SIA) 2022 sc->dc_pmode = DC_PMODE_SYM; 2023 sc->dc_flags |= DC_21143_NWAY; 2024 mii_phy_probe(dev, &sc->dc_miibus, 2025 dc_ifmedia_upd, dc_ifmedia_sts); 2026 /* 2027 * For non-MII cards, we need to have the 21143 2028 * drive the LEDs. Except there are some systems 2029 * like the NEC VersaPro NoteBook PC which have no 2030 * LEDs, and twiddling these bits has adverse effects 2031 * on them. (I.e. you suddenly can't get a link.) 2032 */ 2033 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2034 sc->dc_flags |= DC_TULIP_LEDS; 2035 error = 0; 2036 } 2037 2038 if (error) { 2039 device_printf(dev, "MII without any PHY!\n"); 2040 error = ENXIO; 2041 goto fail; 2042 } 2043 2044 /* 2045 * Call MI attach routine. 2046 */ 2047 ether_ifattach(ifp, eaddr); 2048 2049 if (DC_IS_ADMTEK(sc)) { 2050 /* 2051 * Set automatic TX underrun recovery for the ADMtek chips 2052 */ 2053 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2054 } 2055 2056 /* 2057 * Tell the upper layer(s) we support long frames. 2058 */ 2059 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2060 2061 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 2062 dc_intr, sc, &sc->dc_intrhand, NULL); 2063 if (error) { 2064 ether_ifdetach(ifp); 2065 device_printf(dev, "couldn't set up irq\n"); 2066 goto fail; 2067 } 2068 2069 return(0); 2070 2071 fail: 2072 dc_detach(dev); 2073 return(error); 2074 } 2075 2076 static int dc_detach(dev) 2077 device_t dev; 2078 { 2079 struct dc_softc *sc = device_get_softc(dev); 2080 struct ifnet *ifp = &sc->arpcom.ac_if; 2081 struct dc_mediainfo *m; 2082 2083 crit_enter(); 2084 2085 if (device_is_attached(dev)) { 2086 dc_stop(sc); 2087 ether_ifdetach(ifp); 2088 } 2089 2090 if (sc->dc_miibus) 2091 device_delete_child(dev, sc->dc_miibus); 2092 bus_generic_detach(dev); 2093 2094 if (sc->dc_intrhand) 2095 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2096 2097 crit_exit(); 2098 2099 if (sc->dc_irq) 2100 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2101 if (sc->dc_res) 2102 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2103 2104 if (sc->dc_ldata) 2105 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2106 if (sc->dc_pnic_rx_buf != NULL) 2107 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2108 2109 while(sc->dc_mi != NULL) { 2110 m = sc->dc_mi->dc_next; 2111 free(sc->dc_mi, M_DEVBUF); 2112 sc->dc_mi = m; 2113 } 2114 2115 if (sc->dc_srom) 2116 free(sc->dc_srom, M_DEVBUF); 2117 2118 return(0); 2119 } 2120 2121 /* 2122 * Initialize the transmit descriptors. 2123 */ 2124 static int dc_list_tx_init(sc) 2125 struct dc_softc *sc; 2126 { 2127 struct dc_chain_data *cd; 2128 struct dc_list_data *ld; 2129 int i; 2130 2131 cd = &sc->dc_cdata; 2132 ld = sc->dc_ldata; 2133 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2134 if (i == (DC_TX_LIST_CNT - 1)) { 2135 ld->dc_tx_list[i].dc_next = 2136 vtophys(&ld->dc_tx_list[0]); 2137 } else { 2138 ld->dc_tx_list[i].dc_next = 2139 vtophys(&ld->dc_tx_list[i + 1]); 2140 } 2141 cd->dc_tx_chain[i] = NULL; 2142 ld->dc_tx_list[i].dc_data = 0; 2143 ld->dc_tx_list[i].dc_ctl = 0; 2144 } 2145 2146 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2147 2148 return(0); 2149 } 2150 2151 2152 /* 2153 * Initialize the RX descriptors and allocate mbufs for them. Note that 2154 * we arrange the descriptors in a closed ring, so that the last descriptor 2155 * points back to the first. 2156 */ 2157 static int dc_list_rx_init(sc) 2158 struct dc_softc *sc; 2159 { 2160 struct dc_chain_data *cd; 2161 struct dc_list_data *ld; 2162 int i; 2163 2164 cd = &sc->dc_cdata; 2165 ld = sc->dc_ldata; 2166 2167 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2168 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2169 return(ENOBUFS); 2170 if (i == (DC_RX_LIST_CNT - 1)) { 2171 ld->dc_rx_list[i].dc_next = 2172 vtophys(&ld->dc_rx_list[0]); 2173 } else { 2174 ld->dc_rx_list[i].dc_next = 2175 vtophys(&ld->dc_rx_list[i + 1]); 2176 } 2177 } 2178 2179 cd->dc_rx_prod = 0; 2180 2181 return(0); 2182 } 2183 2184 /* 2185 * Initialize an RX descriptor and attach an MBUF cluster. 2186 */ 2187 static int dc_newbuf(sc, i, m) 2188 struct dc_softc *sc; 2189 int i; 2190 struct mbuf *m; 2191 { 2192 struct mbuf *m_new = NULL; 2193 struct dc_desc *c; 2194 2195 c = &sc->dc_ldata->dc_rx_list[i]; 2196 2197 if (m == NULL) { 2198 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2199 if (m_new == NULL) 2200 return (ENOBUFS); 2201 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2202 } else { 2203 m_new = m; 2204 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2205 m_new->m_data = m_new->m_ext.ext_buf; 2206 } 2207 2208 m_adj(m_new, sizeof(u_int64_t)); 2209 2210 /* 2211 * If this is a PNIC chip, zero the buffer. This is part 2212 * of the workaround for the receive bug in the 82c168 and 2213 * 82c169 chips. 2214 */ 2215 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2216 bzero((char *)mtod(m_new, char *), m_new->m_len); 2217 2218 sc->dc_cdata.dc_rx_chain[i] = m_new; 2219 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2220 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2221 c->dc_status = DC_RXSTAT_OWN; 2222 2223 return(0); 2224 } 2225 2226 /* 2227 * Grrrrr. 2228 * The PNIC chip has a terrible bug in it that manifests itself during 2229 * periods of heavy activity. The exact mode of failure if difficult to 2230 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2231 * will happen on slow machines. The bug is that sometimes instead of 2232 * uploading one complete frame during reception, it uploads what looks 2233 * like the entire contents of its FIFO memory. The frame we want is at 2234 * the end of the whole mess, but we never know exactly how much data has 2235 * been uploaded, so salvaging the frame is hard. 2236 * 2237 * There is only one way to do it reliably, and it's disgusting. 2238 * Here's what we know: 2239 * 2240 * - We know there will always be somewhere between one and three extra 2241 * descriptors uploaded. 2242 * 2243 * - We know the desired received frame will always be at the end of the 2244 * total data upload. 2245 * 2246 * - We know the size of the desired received frame because it will be 2247 * provided in the length field of the status word in the last descriptor. 2248 * 2249 * Here's what we do: 2250 * 2251 * - When we allocate buffers for the receive ring, we bzero() them. 2252 * This means that we know that the buffer contents should be all 2253 * zeros, except for data uploaded by the chip. 2254 * 2255 * - We also force the PNIC chip to upload frames that include the 2256 * ethernet CRC at the end. 2257 * 2258 * - We gather all of the bogus frame data into a single buffer. 2259 * 2260 * - We then position a pointer at the end of this buffer and scan 2261 * backwards until we encounter the first non-zero byte of data. 2262 * This is the end of the received frame. We know we will encounter 2263 * some data at the end of the frame because the CRC will always be 2264 * there, so even if the sender transmits a packet of all zeros, 2265 * we won't be fooled. 2266 * 2267 * - We know the size of the actual received frame, so we subtract 2268 * that value from the current pointer location. This brings us 2269 * to the start of the actual received packet. 2270 * 2271 * - We copy this into an mbuf and pass it on, along with the actual 2272 * frame length. 2273 * 2274 * The performance hit is tremendous, but it beats dropping frames all 2275 * the time. 2276 */ 2277 2278 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2279 static void dc_pnic_rx_bug_war(sc, idx) 2280 struct dc_softc *sc; 2281 int idx; 2282 { 2283 struct dc_desc *cur_rx; 2284 struct dc_desc *c = NULL; 2285 struct mbuf *m = NULL; 2286 unsigned char *ptr; 2287 int i, total_len; 2288 u_int32_t rxstat = 0; 2289 2290 i = sc->dc_pnic_rx_bug_save; 2291 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2292 ptr = sc->dc_pnic_rx_buf; 2293 bzero(ptr, DC_RXLEN * 5); 2294 2295 /* Copy all the bytes from the bogus buffers. */ 2296 while (1) { 2297 c = &sc->dc_ldata->dc_rx_list[i]; 2298 rxstat = c->dc_status; 2299 m = sc->dc_cdata.dc_rx_chain[i]; 2300 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2301 ptr += DC_RXLEN; 2302 /* If this is the last buffer, break out. */ 2303 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2304 break; 2305 dc_newbuf(sc, i, m); 2306 DC_INC(i, DC_RX_LIST_CNT); 2307 } 2308 2309 /* Find the length of the actual receive frame. */ 2310 total_len = DC_RXBYTES(rxstat); 2311 2312 /* Scan backwards until we hit a non-zero byte. */ 2313 while(*ptr == 0x00) 2314 ptr--; 2315 2316 /* Round off. */ 2317 if ((uintptr_t)(ptr) & 0x3) 2318 ptr -= 1; 2319 2320 /* Now find the start of the frame. */ 2321 ptr -= total_len; 2322 if (ptr < sc->dc_pnic_rx_buf) 2323 ptr = sc->dc_pnic_rx_buf; 2324 2325 /* 2326 * Now copy the salvaged frame to the last mbuf and fake up 2327 * the status word to make it look like a successful 2328 * frame reception. 2329 */ 2330 dc_newbuf(sc, i, m); 2331 bcopy(ptr, mtod(m, char *), total_len); 2332 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2333 2334 return; 2335 } 2336 2337 /* 2338 * This routine searches the RX ring for dirty descriptors in the 2339 * event that the rxeof routine falls out of sync with the chip's 2340 * current descriptor pointer. This may happen sometimes as a result 2341 * of a "no RX buffer available" condition that happens when the chip 2342 * consumes all of the RX buffers before the driver has a chance to 2343 * process the RX ring. This routine may need to be called more than 2344 * once to bring the driver back in sync with the chip, however we 2345 * should still be getting RX DONE interrupts to drive the search 2346 * for new packets in the RX ring, so we should catch up eventually. 2347 */ 2348 static int dc_rx_resync(sc) 2349 struct dc_softc *sc; 2350 { 2351 int i, pos; 2352 struct dc_desc *cur_rx; 2353 2354 pos = sc->dc_cdata.dc_rx_prod; 2355 2356 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2357 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2358 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2359 break; 2360 DC_INC(pos, DC_RX_LIST_CNT); 2361 } 2362 2363 /* If the ring really is empty, then just return. */ 2364 if (i == DC_RX_LIST_CNT) 2365 return(0); 2366 2367 /* We've fallen behing the chip: catch it. */ 2368 sc->dc_cdata.dc_rx_prod = pos; 2369 2370 return(EAGAIN); 2371 } 2372 2373 /* 2374 * A frame has been uploaded: pass the resulting mbuf chain up to 2375 * the higher level protocols. 2376 */ 2377 static void dc_rxeof(sc) 2378 struct dc_softc *sc; 2379 { 2380 struct mbuf *m; 2381 struct ifnet *ifp; 2382 struct dc_desc *cur_rx; 2383 int i, total_len = 0; 2384 u_int32_t rxstat; 2385 2386 ifp = &sc->arpcom.ac_if; 2387 i = sc->dc_cdata.dc_rx_prod; 2388 2389 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2390 2391 #ifdef DEVICE_POLLING 2392 if (ifp->if_flags & IFF_POLLING) { 2393 if (sc->rxcycles <= 0) 2394 break; 2395 sc->rxcycles--; 2396 } 2397 #endif /* DEVICE_POLLING */ 2398 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2399 rxstat = cur_rx->dc_status; 2400 m = sc->dc_cdata.dc_rx_chain[i]; 2401 total_len = DC_RXBYTES(rxstat); 2402 2403 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2404 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2405 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2406 sc->dc_pnic_rx_bug_save = i; 2407 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2408 DC_INC(i, DC_RX_LIST_CNT); 2409 continue; 2410 } 2411 dc_pnic_rx_bug_war(sc, i); 2412 rxstat = cur_rx->dc_status; 2413 total_len = DC_RXBYTES(rxstat); 2414 } 2415 } 2416 2417 sc->dc_cdata.dc_rx_chain[i] = NULL; 2418 2419 /* 2420 * If an error occurs, update stats, clear the 2421 * status word and leave the mbuf cluster in place: 2422 * it should simply get re-used next time this descriptor 2423 * comes up in the ring. However, don't report long 2424 * frames as errors since they could be vlans 2425 */ 2426 if ((rxstat & DC_RXSTAT_RXERR)){ 2427 if (!(rxstat & DC_RXSTAT_GIANT) || 2428 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2429 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2430 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2431 ifp->if_ierrors++; 2432 if (rxstat & DC_RXSTAT_COLLSEEN) 2433 ifp->if_collisions++; 2434 dc_newbuf(sc, i, m); 2435 if (rxstat & DC_RXSTAT_CRCERR) { 2436 DC_INC(i, DC_RX_LIST_CNT); 2437 continue; 2438 } else { 2439 dc_init(sc); 2440 return; 2441 } 2442 } 2443 } 2444 2445 /* No errors; receive the packet. */ 2446 total_len -= ETHER_CRC_LEN; 2447 2448 #ifdef __i386__ 2449 /* 2450 * On the x86 we do not have alignment problems, so try to 2451 * allocate a new buffer for the receive ring, and pass up 2452 * the one where the packet is already, saving the expensive 2453 * copy done in m_devget(). 2454 * If we are on an architecture with alignment problems, or 2455 * if the allocation fails, then use m_devget and leave the 2456 * existing buffer in the receive ring. 2457 */ 2458 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2459 m->m_pkthdr.rcvif = ifp; 2460 m->m_pkthdr.len = m->m_len = total_len; 2461 DC_INC(i, DC_RX_LIST_CNT); 2462 } else 2463 #endif 2464 { 2465 struct mbuf *m0; 2466 2467 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2468 total_len + ETHER_ALIGN, 0, ifp, NULL); 2469 dc_newbuf(sc, i, m); 2470 DC_INC(i, DC_RX_LIST_CNT); 2471 if (m0 == NULL) { 2472 ifp->if_ierrors++; 2473 continue; 2474 } 2475 m_adj(m0, ETHER_ALIGN); 2476 m = m0; 2477 } 2478 2479 ifp->if_ipackets++; 2480 (*ifp->if_input)(ifp, m); 2481 } 2482 2483 sc->dc_cdata.dc_rx_prod = i; 2484 } 2485 2486 /* 2487 * A frame was downloaded to the chip. It's safe for us to clean up 2488 * the list buffers. 2489 */ 2490 2491 static void 2492 dc_txeof(sc) 2493 struct dc_softc *sc; 2494 { 2495 struct dc_desc *cur_tx = NULL; 2496 struct ifnet *ifp; 2497 int idx; 2498 2499 ifp = &sc->arpcom.ac_if; 2500 2501 /* 2502 * Go through our tx list and free mbufs for those 2503 * frames that have been transmitted. 2504 */ 2505 idx = sc->dc_cdata.dc_tx_cons; 2506 while(idx != sc->dc_cdata.dc_tx_prod) { 2507 u_int32_t txstat; 2508 2509 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2510 txstat = cur_tx->dc_status; 2511 2512 if (txstat & DC_TXSTAT_OWN) 2513 break; 2514 2515 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2516 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2517 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2518 /* 2519 * Yes, the PNIC is so brain damaged 2520 * that it will sometimes generate a TX 2521 * underrun error while DMAing the RX 2522 * filter setup frame. If we detect this, 2523 * we have to send the setup frame again, 2524 * or else the filter won't be programmed 2525 * correctly. 2526 */ 2527 if (DC_IS_PNIC(sc)) { 2528 if (txstat & DC_TXSTAT_ERRSUM) 2529 dc_setfilt(sc); 2530 } 2531 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2532 } 2533 sc->dc_cdata.dc_tx_cnt--; 2534 DC_INC(idx, DC_TX_LIST_CNT); 2535 continue; 2536 } 2537 2538 if (DC_IS_CONEXANT(sc)) { 2539 /* 2540 * For some reason Conexant chips like 2541 * setting the CARRLOST flag even when 2542 * the carrier is there. In CURRENT we 2543 * have the same problem for Xircom 2544 * cards ! 2545 */ 2546 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2547 sc->dc_pmode == DC_PMODE_MII && 2548 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2549 DC_TXSTAT_NOCARRIER))) 2550 txstat &= ~DC_TXSTAT_ERRSUM; 2551 } else { 2552 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2553 sc->dc_pmode == DC_PMODE_MII && 2554 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2555 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2556 txstat &= ~DC_TXSTAT_ERRSUM; 2557 } 2558 2559 if (txstat & DC_TXSTAT_ERRSUM) { 2560 ifp->if_oerrors++; 2561 if (txstat & DC_TXSTAT_EXCESSCOLL) 2562 ifp->if_collisions++; 2563 if (txstat & DC_TXSTAT_LATECOLL) 2564 ifp->if_collisions++; 2565 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2566 dc_init(sc); 2567 return; 2568 } 2569 } 2570 2571 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2572 2573 ifp->if_opackets++; 2574 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2575 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2576 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2577 } 2578 2579 sc->dc_cdata.dc_tx_cnt--; 2580 DC_INC(idx, DC_TX_LIST_CNT); 2581 } 2582 2583 if (idx != sc->dc_cdata.dc_tx_cons) { 2584 /* some buffers have been freed */ 2585 sc->dc_cdata.dc_tx_cons = idx; 2586 ifp->if_flags &= ~IFF_OACTIVE; 2587 } 2588 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2589 2590 return; 2591 } 2592 2593 static void dc_tick(xsc) 2594 void *xsc; 2595 { 2596 struct dc_softc *sc = xsc; 2597 struct ifnet *ifp = &sc->arpcom.ac_if; 2598 struct mii_data *mii; 2599 u_int32_t r; 2600 2601 crit_enter(); 2602 2603 mii = device_get_softc(sc->dc_miibus); 2604 2605 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2606 if (sc->dc_flags & DC_21143_NWAY) { 2607 r = CSR_READ_4(sc, DC_10BTSTAT); 2608 if (IFM_SUBTYPE(mii->mii_media_active) == 2609 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2610 sc->dc_link = 0; 2611 mii_mediachg(mii); 2612 } 2613 if (IFM_SUBTYPE(mii->mii_media_active) == 2614 IFM_10_T && (r & DC_TSTAT_LS10)) { 2615 sc->dc_link = 0; 2616 mii_mediachg(mii); 2617 } 2618 if (sc->dc_link == 0) 2619 mii_tick(mii); 2620 } else { 2621 r = CSR_READ_4(sc, DC_ISR); 2622 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2623 sc->dc_cdata.dc_tx_cnt == 0) 2624 mii_tick(mii); 2625 if (!(mii->mii_media_status & IFM_ACTIVE)) 2626 sc->dc_link = 0; 2627 } 2628 } else 2629 mii_tick(mii); 2630 2631 /* 2632 * When the init routine completes, we expect to be able to send 2633 * packets right away, and in fact the network code will send a 2634 * gratuitous ARP the moment the init routine marks the interface 2635 * as running. However, even though the MAC may have been initialized, 2636 * there may be a delay of a few seconds before the PHY completes 2637 * autonegotiation and the link is brought up. Any transmissions 2638 * made during that delay will be lost. Dealing with this is tricky: 2639 * we can't just pause in the init routine while waiting for the 2640 * PHY to come ready since that would bring the whole system to 2641 * a screeching halt for several seconds. 2642 * 2643 * What we do here is prevent the TX start routine from sending 2644 * any packets until a link has been established. After the 2645 * interface has been initialized, the tick routine will poll 2646 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2647 * that time, packets will stay in the send queue, and once the 2648 * link comes up, they will be flushed out to the wire. 2649 */ 2650 if (!sc->dc_link) { 2651 mii_pollstat(mii); 2652 if (mii->mii_media_status & IFM_ACTIVE && 2653 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2654 sc->dc_link++; 2655 if (!ifq_is_empty(&ifp->if_snd)) 2656 dc_start(ifp); 2657 } 2658 } 2659 2660 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2661 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc); 2662 else 2663 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 2664 2665 crit_exit(); 2666 } 2667 2668 /* 2669 * A transmit underrun has occurred. Back off the transmit threshold, 2670 * or switch to store and forward mode if we have to. 2671 */ 2672 static void dc_tx_underrun(sc) 2673 struct dc_softc *sc; 2674 { 2675 u_int32_t isr; 2676 int i; 2677 2678 if (DC_IS_DAVICOM(sc)) 2679 dc_init(sc); 2680 2681 if (DC_IS_INTEL(sc)) { 2682 /* 2683 * The real 21143 requires that the transmitter be idle 2684 * in order to change the transmit threshold or store 2685 * and forward state. 2686 */ 2687 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2688 2689 for (i = 0; i < DC_TIMEOUT; i++) { 2690 isr = CSR_READ_4(sc, DC_ISR); 2691 if (isr & DC_ISR_TX_IDLE) 2692 break; 2693 DELAY(10); 2694 } 2695 if (i == DC_TIMEOUT) { 2696 if_printf(&sc->arpcom.ac_if, 2697 "failed to force tx to idle state\n"); 2698 dc_init(sc); 2699 } 2700 } 2701 2702 if_printf(&sc->arpcom.ac_if, "TX underrun -- "); 2703 sc->dc_txthresh += DC_TXTHRESH_INC; 2704 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2705 printf("using store and forward mode\n"); 2706 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2707 } else { 2708 printf("increasing TX threshold\n"); 2709 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2710 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2711 } 2712 2713 if (DC_IS_INTEL(sc)) 2714 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2715 2716 return; 2717 } 2718 2719 #ifdef DEVICE_POLLING 2720 2721 static void 2722 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2723 { 2724 struct dc_softc *sc = ifp->if_softc; 2725 u_int32_t status; 2726 2727 switch(cmd) { 2728 case POLL_REGISTER: 2729 /* Disable interrupts */ 2730 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2731 break; 2732 case POLL_DEREGISTER: 2733 /* Re-enable interrupts. */ 2734 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2735 break; 2736 case POLL_ONLY: 2737 sc->rxcycles = count; 2738 dc_rxeof(sc); 2739 dc_txeof(sc); 2740 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2741 dc_start(ifp); 2742 break; 2743 case POLL_AND_CHECK_STATUS: 2744 sc->rxcycles = count; 2745 dc_rxeof(sc); 2746 dc_txeof(sc); 2747 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2748 dc_start(ifp); 2749 status = CSR_READ_4(sc, DC_ISR); 2750 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2751 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2752 DC_ISR_BUS_ERR); 2753 if (!status) 2754 break; 2755 /* ack what we have */ 2756 CSR_WRITE_4(sc, DC_ISR, status); 2757 2758 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2759 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2760 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2761 2762 if (dc_rx_resync(sc)) 2763 dc_rxeof(sc); 2764 } 2765 /* restart transmit unit if necessary */ 2766 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2767 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2768 2769 if (status & DC_ISR_TX_UNDERRUN) 2770 dc_tx_underrun(sc); 2771 2772 if (status & DC_ISR_BUS_ERR) { 2773 if_printf(ifp, "dc_poll: bus error\n"); 2774 dc_reset(sc); 2775 dc_init(sc); 2776 } 2777 break; 2778 } 2779 } 2780 #endif /* DEVICE_POLLING */ 2781 2782 static void dc_intr(arg) 2783 void *arg; 2784 { 2785 struct dc_softc *sc; 2786 struct ifnet *ifp; 2787 u_int32_t status; 2788 2789 sc = arg; 2790 2791 if (sc->suspended) { 2792 return; 2793 } 2794 2795 ifp = &sc->arpcom.ac_if; 2796 2797 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2798 return ; 2799 2800 /* Suppress unwanted interrupts */ 2801 if (!(ifp->if_flags & IFF_UP)) { 2802 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2803 dc_stop(sc); 2804 return; 2805 } 2806 2807 /* Disable interrupts. */ 2808 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2809 2810 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2811 2812 CSR_WRITE_4(sc, DC_ISR, status); 2813 2814 if (status & DC_ISR_RX_OK) { 2815 int curpkts; 2816 curpkts = ifp->if_ipackets; 2817 dc_rxeof(sc); 2818 if (curpkts == ifp->if_ipackets) { 2819 while(dc_rx_resync(sc)) 2820 dc_rxeof(sc); 2821 } 2822 } 2823 2824 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2825 dc_txeof(sc); 2826 2827 if (status & DC_ISR_TX_IDLE) { 2828 dc_txeof(sc); 2829 if (sc->dc_cdata.dc_tx_cnt) { 2830 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2831 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2832 } 2833 } 2834 2835 if (status & DC_ISR_TX_UNDERRUN) 2836 dc_tx_underrun(sc); 2837 2838 if ((status & DC_ISR_RX_WATDOGTIMEO) 2839 || (status & DC_ISR_RX_NOBUF)) { 2840 int curpkts; 2841 curpkts = ifp->if_ipackets; 2842 dc_rxeof(sc); 2843 if (curpkts == ifp->if_ipackets) { 2844 while(dc_rx_resync(sc)) 2845 dc_rxeof(sc); 2846 } 2847 } 2848 2849 if (status & DC_ISR_BUS_ERR) { 2850 dc_reset(sc); 2851 dc_init(sc); 2852 } 2853 } 2854 2855 /* Re-enable interrupts. */ 2856 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2857 2858 if (!ifq_is_empty(&ifp->if_snd)) 2859 dc_start(ifp); 2860 2861 return; 2862 } 2863 2864 /* 2865 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2866 * pointers to the fragment pointers. 2867 */ 2868 static int dc_encap(sc, m_head, txidx) 2869 struct dc_softc *sc; 2870 struct mbuf *m_head; 2871 u_int32_t *txidx; 2872 { 2873 struct dc_desc *f = NULL; 2874 struct mbuf *m; 2875 int frag, cur, cnt = 0; 2876 2877 /* 2878 * Start packing the mbufs in this chain into 2879 * the fragment pointers. Stop when we run out 2880 * of fragments or hit the end of the mbuf chain. 2881 */ 2882 m = m_head; 2883 cur = frag = *txidx; 2884 2885 for (m = m_head; m != NULL; m = m->m_next) { 2886 if (m->m_len != 0) { 2887 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2888 if (*txidx != sc->dc_cdata.dc_tx_prod && 2889 frag == (DC_TX_LIST_CNT - 1)) 2890 return(ENOBUFS); 2891 } 2892 if ((DC_TX_LIST_CNT - 2893 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2894 return(ENOBUFS); 2895 2896 f = &sc->dc_ldata->dc_tx_list[frag]; 2897 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2898 if (cnt == 0) { 2899 f->dc_status = 0; 2900 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2901 } else 2902 f->dc_status = DC_TXSTAT_OWN; 2903 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2904 cur = frag; 2905 DC_INC(frag, DC_TX_LIST_CNT); 2906 cnt++; 2907 } 2908 } 2909 2910 if (m != NULL) 2911 return(ENOBUFS); 2912 2913 sc->dc_cdata.dc_tx_cnt += cnt; 2914 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2915 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2916 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2917 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2918 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2919 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2920 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2921 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2922 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2923 *txidx = frag; 2924 2925 return(0); 2926 } 2927 2928 /* 2929 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2930 * to the mbuf data regions directly in the transmit lists. We also save a 2931 * copy of the pointers since the transmit list fragment pointers are 2932 * physical addresses. 2933 */ 2934 2935 static void dc_start(ifp) 2936 struct ifnet *ifp; 2937 { 2938 struct dc_softc *sc; 2939 struct mbuf *m_head = NULL, *m_new; 2940 int did_defrag, idx; 2941 2942 sc = ifp->if_softc; 2943 2944 if (!sc->dc_link) 2945 return; 2946 2947 if (ifp->if_flags & IFF_OACTIVE) 2948 return; 2949 2950 idx = sc->dc_cdata.dc_tx_prod; 2951 2952 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2953 did_defrag = 0; 2954 m_head = ifq_poll(&ifp->if_snd); 2955 if (m_head == NULL) 2956 break; 2957 2958 if (sc->dc_flags & DC_TX_COALESCE && 2959 m_head->m_next != NULL) { 2960 /* 2961 * Check first if coalescing allows us to queue 2962 * the packet. We don't want to loose it if 2963 * the TX queue is full. 2964 */ 2965 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 2966 idx != sc->dc_cdata.dc_tx_prod && 2967 idx == (DC_TX_LIST_CNT - 1)) { 2968 ifp->if_flags |= IFF_OACTIVE; 2969 break; 2970 } 2971 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) { 2972 ifp->if_flags |= IFF_OACTIVE; 2973 break; 2974 } 2975 2976 /* only coalesce if have >1 mbufs */ 2977 m_new = m_defrag_nofree(m_head, MB_DONTWAIT); 2978 if (m_new == NULL) { 2979 ifp->if_flags |= IFF_OACTIVE; 2980 break; 2981 } 2982 m_freem(m_head); 2983 m_head = m_new; 2984 did_defrag = 1; 2985 } 2986 2987 if (dc_encap(sc, m_head, &idx)) { 2988 if (did_defrag) { 2989 m_freem(m_head); 2990 m_new = ifq_dequeue(&ifp->if_snd); 2991 m_freem(m_new); 2992 } 2993 ifp->if_flags |= IFF_OACTIVE; 2994 break; 2995 } 2996 2997 m_new = ifq_dequeue(&ifp->if_snd); 2998 if (did_defrag) 2999 m_freem(m_new); 3000 3001 /* 3002 * If there's a BPF listener, bounce a copy of this frame 3003 * to him. 3004 */ 3005 BPF_MTAP(ifp, m_head); 3006 3007 if (sc->dc_flags & DC_TX_ONE) { 3008 ifp->if_flags |= IFF_OACTIVE; 3009 break; 3010 } 3011 } 3012 3013 /* Transmit */ 3014 sc->dc_cdata.dc_tx_prod = idx; 3015 if (!(sc->dc_flags & DC_TX_POLL)) 3016 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3017 3018 /* 3019 * Set a timeout in case the chip goes out to lunch. 3020 */ 3021 ifp->if_timer = 5; 3022 3023 return; 3024 } 3025 3026 static void dc_init(xsc) 3027 void *xsc; 3028 { 3029 struct dc_softc *sc = xsc; 3030 struct ifnet *ifp = &sc->arpcom.ac_if; 3031 struct mii_data *mii; 3032 3033 crit_enter(); 3034 3035 mii = device_get_softc(sc->dc_miibus); 3036 3037 /* 3038 * Cancel pending I/O and free all RX/TX buffers. 3039 */ 3040 dc_stop(sc); 3041 dc_reset(sc); 3042 3043 /* 3044 * Set cache alignment and burst length. 3045 */ 3046 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3047 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3048 else 3049 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3050 /* 3051 * Evenly share the bus between receive and transmit process. 3052 */ 3053 if (DC_IS_INTEL(sc)) 3054 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3055 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3056 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3057 } else { 3058 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3059 } 3060 if (sc->dc_flags & DC_TX_POLL) 3061 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3062 switch(sc->dc_cachesize) { 3063 case 32: 3064 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3065 break; 3066 case 16: 3067 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3068 break; 3069 case 8: 3070 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3071 break; 3072 case 0: 3073 default: 3074 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3075 break; 3076 } 3077 3078 if (sc->dc_flags & DC_TX_STORENFWD) 3079 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3080 else { 3081 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3082 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3083 } else { 3084 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3085 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3086 } 3087 } 3088 3089 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3090 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3091 3092 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3093 /* 3094 * The app notes for the 98713 and 98715A say that 3095 * in order to have the chips operate properly, a magic 3096 * number must be written to CSR16. Macronix does not 3097 * document the meaning of these bits so there's no way 3098 * to know exactly what they do. The 98713 has a magic 3099 * number all its own; the rest all use a different one. 3100 */ 3101 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3102 if (sc->dc_type == DC_TYPE_98713) 3103 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3104 else 3105 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3106 } 3107 3108 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3109 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3110 3111 /* Init circular RX list. */ 3112 if (dc_list_rx_init(sc) == ENOBUFS) { 3113 if_printf(ifp, "initialization failed: no " 3114 "memory for rx buffers\n"); 3115 dc_stop(sc); 3116 crit_exit(); 3117 return; 3118 } 3119 3120 /* 3121 * Init tx descriptors. 3122 */ 3123 dc_list_tx_init(sc); 3124 3125 /* 3126 * Load the address of the RX list. 3127 */ 3128 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3129 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3130 3131 /* 3132 * Enable interrupts. 3133 */ 3134 #ifdef DEVICE_POLLING 3135 /* 3136 * ... but only if we are not polling, and make sure they are off in 3137 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3138 * after a reset. 3139 */ 3140 if (ifp->if_flags & IFF_POLLING) 3141 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3142 else 3143 #endif 3144 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3145 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3146 3147 /* Enable transmitter. */ 3148 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3149 3150 /* 3151 * If this is an Intel 21143 and we're not using the 3152 * MII port, program the LED control pins so we get 3153 * link and activity indications. 3154 */ 3155 if (sc->dc_flags & DC_TULIP_LEDS) { 3156 CSR_WRITE_4(sc, DC_WATCHDOG, 3157 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3158 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3159 } 3160 3161 /* 3162 * Load the RX/multicast filter. We do this sort of late 3163 * because the filter programming scheme on the 21143 and 3164 * some clones requires DMAing a setup frame via the TX 3165 * engine, and we need the transmitter enabled for that. 3166 */ 3167 dc_setfilt(sc); 3168 3169 /* Enable receiver. */ 3170 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3171 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3172 3173 mii_mediachg(mii); 3174 dc_setcfg(sc, sc->dc_if_media); 3175 3176 ifp->if_flags |= IFF_RUNNING; 3177 ifp->if_flags &= ~IFF_OACTIVE; 3178 3179 crit_exit(); 3180 3181 /* Don't start the ticker if this is a homePNA link. */ 3182 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3183 sc->dc_link = 1; 3184 else { 3185 if (sc->dc_flags & DC_21143_NWAY) 3186 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc); 3187 else 3188 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 3189 } 3190 3191 return; 3192 } 3193 3194 /* 3195 * Set media options. 3196 */ 3197 static int dc_ifmedia_upd(ifp) 3198 struct ifnet *ifp; 3199 { 3200 struct dc_softc *sc; 3201 struct mii_data *mii; 3202 struct ifmedia *ifm; 3203 3204 sc = ifp->if_softc; 3205 mii = device_get_softc(sc->dc_miibus); 3206 mii_mediachg(mii); 3207 ifm = &mii->mii_media; 3208 3209 if (DC_IS_DAVICOM(sc) && 3210 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3211 dc_setcfg(sc, ifm->ifm_media); 3212 else 3213 sc->dc_link = 0; 3214 3215 return(0); 3216 } 3217 3218 /* 3219 * Report current media status. 3220 */ 3221 static void dc_ifmedia_sts(ifp, ifmr) 3222 struct ifnet *ifp; 3223 struct ifmediareq *ifmr; 3224 { 3225 struct dc_softc *sc; 3226 struct mii_data *mii; 3227 struct ifmedia *ifm; 3228 3229 sc = ifp->if_softc; 3230 mii = device_get_softc(sc->dc_miibus); 3231 mii_pollstat(mii); 3232 ifm = &mii->mii_media; 3233 if (DC_IS_DAVICOM(sc)) { 3234 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3235 ifmr->ifm_active = ifm->ifm_media; 3236 ifmr->ifm_status = 0; 3237 return; 3238 } 3239 } 3240 ifmr->ifm_active = mii->mii_media_active; 3241 ifmr->ifm_status = mii->mii_media_status; 3242 3243 return; 3244 } 3245 3246 static int dc_ioctl(ifp, command, data, cr) 3247 struct ifnet *ifp; 3248 u_long command; 3249 caddr_t data; 3250 struct ucred *cr; 3251 { 3252 struct dc_softc *sc = ifp->if_softc; 3253 struct ifreq *ifr = (struct ifreq *) data; 3254 struct mii_data *mii; 3255 int error = 0; 3256 3257 crit_enter(); 3258 3259 switch(command) { 3260 case SIOCSIFFLAGS: 3261 if (ifp->if_flags & IFF_UP) { 3262 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3263 (IFF_PROMISC | IFF_ALLMULTI); 3264 if (ifp->if_flags & IFF_RUNNING) { 3265 if (need_setfilt) 3266 dc_setfilt(sc); 3267 } else { 3268 sc->dc_txthresh = 0; 3269 dc_init(sc); 3270 } 3271 } else { 3272 if (ifp->if_flags & IFF_RUNNING) 3273 dc_stop(sc); 3274 } 3275 sc->dc_if_flags = ifp->if_flags; 3276 error = 0; 3277 break; 3278 case SIOCADDMULTI: 3279 case SIOCDELMULTI: 3280 dc_setfilt(sc); 3281 error = 0; 3282 break; 3283 case SIOCGIFMEDIA: 3284 case SIOCSIFMEDIA: 3285 mii = device_get_softc(sc->dc_miibus); 3286 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3287 break; 3288 default: 3289 error = ether_ioctl(ifp, command, data); 3290 break; 3291 } 3292 3293 crit_exit(); 3294 3295 return(error); 3296 } 3297 3298 static void dc_watchdog(ifp) 3299 struct ifnet *ifp; 3300 { 3301 struct dc_softc *sc; 3302 3303 sc = ifp->if_softc; 3304 3305 ifp->if_oerrors++; 3306 if_printf(ifp, "watchdog timeout\n"); 3307 3308 dc_stop(sc); 3309 dc_reset(sc); 3310 dc_init(sc); 3311 3312 if (!ifq_is_empty(&ifp->if_snd)) 3313 dc_start(ifp); 3314 3315 return; 3316 } 3317 3318 /* 3319 * Stop the adapter and free any mbufs allocated to the 3320 * RX and TX lists. 3321 */ 3322 static void dc_stop(sc) 3323 struct dc_softc *sc; 3324 { 3325 int i; 3326 struct ifnet *ifp; 3327 3328 ifp = &sc->arpcom.ac_if; 3329 ifp->if_timer = 0; 3330 3331 callout_stop(&sc->dc_stat_timer); 3332 3333 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3334 3335 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3336 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3337 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3338 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3339 sc->dc_link = 0; 3340 3341 /* 3342 * Free data in the RX lists. 3343 */ 3344 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3345 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3346 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3347 sc->dc_cdata.dc_rx_chain[i] = NULL; 3348 } 3349 } 3350 bzero((char *)&sc->dc_ldata->dc_rx_list, 3351 sizeof(sc->dc_ldata->dc_rx_list)); 3352 3353 /* 3354 * Free the TX list buffers. 3355 */ 3356 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3357 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3358 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl & 3359 DC_TXCTL_SETUP) || 3360 !(sc->dc_ldata->dc_tx_list[i].dc_ctl & 3361 DC_TXCTL_LASTFRAG)) { 3362 sc->dc_cdata.dc_tx_chain[i] = NULL; 3363 continue; 3364 } 3365 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3366 sc->dc_cdata.dc_tx_chain[i] = NULL; 3367 } 3368 } 3369 3370 bzero((char *)&sc->dc_ldata->dc_tx_list, 3371 sizeof(sc->dc_ldata->dc_tx_list)); 3372 3373 return; 3374 } 3375 3376 /* 3377 * Stop all chip I/O so that the kernel's probe routines don't 3378 * get confused by errant DMAs when rebooting. 3379 */ 3380 static void dc_shutdown(dev) 3381 device_t dev; 3382 { 3383 struct dc_softc *sc; 3384 3385 sc = device_get_softc(dev); 3386 3387 dc_stop(sc); 3388 3389 return; 3390 } 3391 3392 /* 3393 * Device suspend routine. Stop the interface and save some PCI 3394 * settings in case the BIOS doesn't restore them properly on 3395 * resume. 3396 */ 3397 static int dc_suspend(dev) 3398 device_t dev; 3399 { 3400 struct dc_softc *sc = device_get_softc(dev); 3401 int i; 3402 3403 crit_enter(); 3404 3405 dc_stop(sc); 3406 3407 for (i = 0; i < 5; i++) 3408 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3409 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3410 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3411 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3412 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3413 3414 sc->suspended = 1; 3415 3416 crit_exit(); 3417 return (0); 3418 } 3419 3420 /* 3421 * Device resume routine. Restore some PCI settings in case the BIOS 3422 * doesn't, re-enable busmastering, and restart the interface if 3423 * appropriate. 3424 */ 3425 static int dc_resume(dev) 3426 device_t dev; 3427 { 3428 struct dc_softc *sc = device_get_softc(dev); 3429 struct ifnet *ifp = &sc->arpcom.ac_if; 3430 int i; 3431 3432 crit_enter(); 3433 3434 dc_acpi(dev); 3435 3436 /* better way to do this? */ 3437 for (i = 0; i < 5; i++) 3438 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3439 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3440 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3441 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3442 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3443 3444 /* reenable busmastering */ 3445 pci_enable_busmaster(dev); 3446 pci_enable_io(dev, DC_RES); 3447 3448 /* reinitialize interface if necessary */ 3449 if (ifp->if_flags & IFF_UP) 3450 dc_init(sc); 3451 3452 sc->suspended = 0; 3453 3454 crit_exit(); 3455 return (0); 3456 } 3457