1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.39 2005/09/06 13:23:36 sephe Exp $ 34 */ 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 48 * Accton EN1217 (www.accton.com) 49 * Conexant LANfinity (www.conexant.com) 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/sysctl.h> 99 #include <sys/thread2.h> 100 101 #include <net/if.h> 102 #include <net/ifq_var.h> 103 #include <net/if_arp.h> 104 #include <net/ethernet.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/vlan/if_vlan_var.h> 109 110 #include <net/bpf.h> 111 112 #include <vm/vm.h> /* for vtophys */ 113 #include <vm/pmap.h> /* for vtophys */ 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include "../mii_layer/mii.h" 122 #include "../mii_layer/miivar.h" 123 124 #include <bus/pci/pcireg.h> 125 #include <bus/pci/pcivar.h> 126 127 #define DC_USEIOSPACE 128 129 #include "if_dcreg.h" 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 /* 135 * Various supported device vendors/types and their names. 136 */ 137 static struct dc_type dc_devs[] = { 138 { DC_VENDORID_DEC, DC_DEVICEID_21143, 139 "Intel 21143 10/100BaseTX" }, 140 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 141 "Davicom DM9009 10/100BaseTX" }, 142 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 143 "Davicom DM9100 10/100BaseTX" }, 144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 145 "Davicom DM9102 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 147 "Davicom DM9102A 10/100BaseTX" }, 148 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 149 "ADMtek AL981 10/100BaseTX" }, 150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 151 "ADMtek AN985 10/100BaseTX" }, 152 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 153 "ADMtek ADM9511 10/100BaseTX" }, 154 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 155 "ADMtek ADM9513 10/100BaseTX" }, 156 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 157 "ASIX AX88140A 10/100BaseTX" }, 158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 159 "ASIX AX88141 10/100BaseTX" }, 160 { DC_VENDORID_MX, DC_DEVICEID_98713, 161 "Macronix 98713 10/100BaseTX" }, 162 { DC_VENDORID_MX, DC_DEVICEID_98713, 163 "Macronix 98713A 10/100BaseTX" }, 164 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 165 "Compex RL100-TX 10/100BaseTX" }, 166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 167 "Compex RL100-TX 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_987x5, 169 "Macronix 98715/98715A 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_987x5, 171 "Macronix 98715AEC-C 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_987x5, 173 "Macronix 98725 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_98727, 175 "Macronix 98727/98732 10/100BaseTX" }, 176 { DC_VENDORID_LO, DC_DEVICEID_82C115, 177 "LC82C115 PNIC II 10/100BaseTX" }, 178 { DC_VENDORID_LO, DC_DEVICEID_82C168, 179 "82c168 PNIC 10/100BaseTX" }, 180 { DC_VENDORID_LO, DC_DEVICEID_82C168, 181 "82c169 PNIC 10/100BaseTX" }, 182 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 183 "Accton EN1217 10/100BaseTX" }, 184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 185 "Accton EN2242 MiniPCI 10/100BaseTX" }, 186 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 187 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 188 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 189 "3Com OfficeConnect 10/100B" }, 190 { 0, 0, NULL } 191 }; 192 193 static int dc_probe (device_t); 194 static int dc_attach (device_t); 195 static int dc_detach (device_t); 196 static int dc_suspend (device_t); 197 static int dc_resume (device_t); 198 static void dc_acpi (device_t); 199 static struct dc_type *dc_devtype (device_t); 200 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 201 static int dc_encap (struct dc_softc *, struct mbuf *, 202 u_int32_t *); 203 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 204 static int dc_rx_resync (struct dc_softc *); 205 static void dc_rxeof (struct dc_softc *); 206 static void dc_txeof (struct dc_softc *); 207 static void dc_tick (void *); 208 static void dc_tx_underrun (struct dc_softc *); 209 static void dc_intr (void *); 210 static void dc_start (struct ifnet *); 211 static int dc_ioctl (struct ifnet *, u_long, caddr_t, 212 struct ucred *); 213 #ifdef DEVICE_POLLING 214 static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd, 215 int count); 216 #endif 217 static void dc_init (void *); 218 static void dc_stop (struct dc_softc *); 219 static void dc_watchdog (struct ifnet *); 220 static void dc_shutdown (device_t); 221 static int dc_ifmedia_upd (struct ifnet *); 222 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 223 224 static void dc_delay (struct dc_softc *); 225 static void dc_eeprom_idle (struct dc_softc *); 226 static void dc_eeprom_putbyte (struct dc_softc *, int); 227 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 228 static void dc_eeprom_getword_pnic 229 (struct dc_softc *, int, u_int16_t *); 230 static void dc_eeprom_width (struct dc_softc *); 231 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, 232 int, int); 233 234 static void dc_mii_writebit (struct dc_softc *, int); 235 static int dc_mii_readbit (struct dc_softc *); 236 static void dc_mii_sync (struct dc_softc *); 237 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 238 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 239 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 240 static int dc_miibus_readreg (device_t, int, int); 241 static int dc_miibus_writereg (device_t, int, int, int); 242 static void dc_miibus_statchg (device_t); 243 static void dc_miibus_mediainit (device_t); 244 245 static u_int32_t dc_crc_mask (struct dc_softc *); 246 static void dc_setcfg (struct dc_softc *, int); 247 static void dc_setfilt_21143 (struct dc_softc *); 248 static void dc_setfilt_asix (struct dc_softc *); 249 static void dc_setfilt_admtek (struct dc_softc *); 250 251 static void dc_setfilt (struct dc_softc *); 252 253 static void dc_reset (struct dc_softc *); 254 static int dc_list_rx_init (struct dc_softc *); 255 static int dc_list_tx_init (struct dc_softc *); 256 257 static void dc_read_srom (struct dc_softc *, int); 258 static void dc_parse_21143_srom (struct dc_softc *); 259 static void dc_decode_leaf_sia (struct dc_softc *, 260 struct dc_eblock_sia *); 261 static void dc_decode_leaf_mii (struct dc_softc *, 262 struct dc_eblock_mii *); 263 static void dc_decode_leaf_sym (struct dc_softc *, 264 struct dc_eblock_sym *); 265 static void dc_apply_fixup (struct dc_softc *, int); 266 267 #ifdef DC_USEIOSPACE 268 #define DC_RES SYS_RES_IOPORT 269 #define DC_RID DC_PCI_CFBIO 270 #else 271 #define DC_RES SYS_RES_MEMORY 272 #define DC_RID DC_PCI_CFBMA 273 #endif 274 275 static device_method_t dc_methods[] = { 276 /* Device interface */ 277 DEVMETHOD(device_probe, dc_probe), 278 DEVMETHOD(device_attach, dc_attach), 279 DEVMETHOD(device_detach, dc_detach), 280 DEVMETHOD(device_suspend, dc_suspend), 281 DEVMETHOD(device_resume, dc_resume), 282 DEVMETHOD(device_shutdown, dc_shutdown), 283 284 /* bus interface */ 285 DEVMETHOD(bus_print_child, bus_generic_print_child), 286 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 287 288 /* MII interface */ 289 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 290 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 291 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 292 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 293 294 { 0, 0 } 295 }; 296 297 static driver_t dc_driver = { 298 "dc", 299 dc_methods, 300 sizeof(struct dc_softc) 301 }; 302 303 static devclass_t dc_devclass; 304 305 #ifdef __i386__ 306 static int dc_quick=1; 307 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 308 &dc_quick,0,"do not mdevget in dc driver"); 309 #endif 310 311 DECLARE_DUMMY_MODULE(if_dc); 312 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 313 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 314 315 #define DC_SETBIT(sc, reg, x) \ 316 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 317 318 #define DC_CLRBIT(sc, reg, x) \ 319 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 320 321 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 322 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 323 324 static void 325 dc_delay(struct dc_softc *sc) 326 { 327 int idx; 328 329 for (idx = (300 / 33) + 1; idx > 0; idx--) 330 CSR_READ_4(sc, DC_BUSCTL); 331 } 332 333 static void 334 dc_eeprom_width(struct dc_softc *sc) 335 { 336 int i; 337 338 /* Force EEPROM to idle state. */ 339 dc_eeprom_idle(sc); 340 341 /* Enter EEPROM access mode. */ 342 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 343 dc_delay(sc); 344 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 345 dc_delay(sc); 346 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 347 dc_delay(sc); 348 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 349 dc_delay(sc); 350 351 for (i = 3; i--;) { 352 if (6 & (1 << i)) 353 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 354 else 355 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 356 dc_delay(sc); 357 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 358 dc_delay(sc); 359 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 360 dc_delay(sc); 361 } 362 363 for (i = 1; i <= 12; i++) { 364 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 365 dc_delay(sc); 366 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 367 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 368 dc_delay(sc); 369 break; 370 } 371 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 372 dc_delay(sc); 373 } 374 375 /* Turn off EEPROM access mode. */ 376 dc_eeprom_idle(sc); 377 378 if (i < 4 || i > 12) 379 sc->dc_romwidth = 6; 380 else 381 sc->dc_romwidth = i; 382 383 /* Enter EEPROM access mode. */ 384 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 385 dc_delay(sc); 386 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 387 dc_delay(sc); 388 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 389 dc_delay(sc); 390 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 391 dc_delay(sc); 392 393 /* Turn off EEPROM access mode. */ 394 dc_eeprom_idle(sc); 395 } 396 397 static void 398 dc_eeprom_idle(struct dc_softc *sc) 399 { 400 int i; 401 402 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 403 dc_delay(sc); 404 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 405 dc_delay(sc); 406 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 407 dc_delay(sc); 408 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 409 dc_delay(sc); 410 411 for (i = 0; i < 25; i++) { 412 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 413 dc_delay(sc); 414 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 415 dc_delay(sc); 416 } 417 418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 419 dc_delay(sc); 420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 421 dc_delay(sc); 422 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 423 424 return; 425 } 426 427 /* 428 * Send a read command and address to the EEPROM, check for ACK. 429 */ 430 static void 431 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 432 { 433 int d, i; 434 435 d = DC_EECMD_READ >> 6; 436 for (i = 3; i--; ) { 437 if (d & (1 << i)) 438 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 439 else 440 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 441 dc_delay(sc); 442 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 443 dc_delay(sc); 444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 } 447 448 /* 449 * Feed in each bit and strobe the clock. 450 */ 451 for (i = sc->dc_romwidth; i--;) { 452 if (addr & (1 << i)) { 453 SIO_SET(DC_SIO_EE_DATAIN); 454 } else { 455 SIO_CLR(DC_SIO_EE_DATAIN); 456 } 457 dc_delay(sc); 458 SIO_SET(DC_SIO_EE_CLK); 459 dc_delay(sc); 460 SIO_CLR(DC_SIO_EE_CLK); 461 dc_delay(sc); 462 } 463 464 return; 465 } 466 467 /* 468 * Read a word of data stored in the EEPROM at address 'addr.' 469 * The PNIC 82c168/82c169 has its own non-standard way to read 470 * the EEPROM. 471 */ 472 static void 473 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 474 { 475 int i; 476 u_int32_t r; 477 478 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 479 480 for (i = 0; i < DC_TIMEOUT; i++) { 481 DELAY(1); 482 r = CSR_READ_4(sc, DC_SIO); 483 if (!(r & DC_PN_SIOCTL_BUSY)) { 484 *dest = (u_int16_t)(r & 0xFFFF); 485 return; 486 } 487 } 488 489 return; 490 } 491 492 /* 493 * Read a word of data stored in the EEPROM at address 'addr.' 494 */ 495 static void 496 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 497 { 498 int i; 499 u_int16_t word = 0; 500 501 /* Force EEPROM to idle state. */ 502 dc_eeprom_idle(sc); 503 504 /* Enter EEPROM access mode. */ 505 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 506 dc_delay(sc); 507 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 508 dc_delay(sc); 509 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 510 dc_delay(sc); 511 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 512 dc_delay(sc); 513 514 /* 515 * Send address of word we want to read. 516 */ 517 dc_eeprom_putbyte(sc, addr); 518 519 /* 520 * Start reading bits from EEPROM. 521 */ 522 for (i = 0x8000; i; i >>= 1) { 523 SIO_SET(DC_SIO_EE_CLK); 524 dc_delay(sc); 525 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 526 word |= i; 527 dc_delay(sc); 528 SIO_CLR(DC_SIO_EE_CLK); 529 dc_delay(sc); 530 } 531 532 /* Turn off EEPROM access mode. */ 533 dc_eeprom_idle(sc); 534 535 *dest = word; 536 537 return; 538 } 539 540 /* 541 * Read a sequence of words from the EEPROM. 542 */ 543 static void 544 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 545 { 546 int i; 547 u_int16_t word = 0, *ptr; 548 549 for (i = 0; i < cnt; i++) { 550 if (DC_IS_PNIC(sc)) 551 dc_eeprom_getword_pnic(sc, off + i, &word); 552 else 553 dc_eeprom_getword(sc, off + i, &word); 554 ptr = (u_int16_t *)(dest + (i * 2)); 555 if (swap) 556 *ptr = ntohs(word); 557 else 558 *ptr = word; 559 } 560 561 return; 562 } 563 564 /* 565 * The following two routines are taken from the Macronix 98713 566 * Application Notes pp.19-21. 567 */ 568 /* 569 * Write a bit to the MII bus. 570 */ 571 static void 572 dc_mii_writebit(struct dc_softc *sc, int bit) 573 { 574 if (bit) 575 CSR_WRITE_4(sc, DC_SIO, 576 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 577 else 578 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 579 580 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 581 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 582 583 return; 584 } 585 586 /* 587 * Read a bit from the MII bus. 588 */ 589 static int 590 dc_mii_readbit(struct dc_softc *sc) 591 { 592 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 593 CSR_READ_4(sc, DC_SIO); 594 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 595 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 596 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 597 return(1); 598 599 return(0); 600 } 601 602 /* 603 * Sync the PHYs by setting data bit and strobing the clock 32 times. 604 */ 605 static void 606 dc_mii_sync(struct dc_softc *sc) 607 { 608 int i; 609 610 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 611 612 for (i = 0; i < 32; i++) 613 dc_mii_writebit(sc, 1); 614 615 return; 616 } 617 618 /* 619 * Clock a series of bits through the MII. 620 */ 621 static void 622 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 623 { 624 int i; 625 626 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 627 dc_mii_writebit(sc, bits & i); 628 } 629 630 /* 631 * Read an PHY register through the MII. 632 */ 633 static int 634 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 635 { 636 int ack, i; 637 638 crit_enter(); 639 640 /* 641 * Set up frame for RX. 642 */ 643 frame->mii_stdelim = DC_MII_STARTDELIM; 644 frame->mii_opcode = DC_MII_READOP; 645 frame->mii_turnaround = 0; 646 frame->mii_data = 0; 647 648 /* 649 * Sync the PHYs. 650 */ 651 dc_mii_sync(sc); 652 653 /* 654 * Send command/address info. 655 */ 656 dc_mii_send(sc, frame->mii_stdelim, 2); 657 dc_mii_send(sc, frame->mii_opcode, 2); 658 dc_mii_send(sc, frame->mii_phyaddr, 5); 659 dc_mii_send(sc, frame->mii_regaddr, 5); 660 661 #ifdef notdef 662 /* Idle bit */ 663 dc_mii_writebit(sc, 1); 664 dc_mii_writebit(sc, 0); 665 #endif 666 667 /* Check for ack */ 668 ack = dc_mii_readbit(sc); 669 670 /* 671 * Now try reading data bits. If the ack failed, we still 672 * need to clock through 16 cycles to keep the PHY(s) in sync. 673 */ 674 if (ack) { 675 for(i = 0; i < 16; i++) { 676 dc_mii_readbit(sc); 677 } 678 goto fail; 679 } 680 681 for (i = 0x8000; i; i >>= 1) { 682 if (!ack) { 683 if (dc_mii_readbit(sc)) 684 frame->mii_data |= i; 685 } 686 } 687 688 fail: 689 690 dc_mii_writebit(sc, 0); 691 dc_mii_writebit(sc, 0); 692 693 crit_exit(); 694 695 if (ack) 696 return(1); 697 return(0); 698 } 699 700 /* 701 * Write to a PHY register through the MII. 702 */ 703 static int 704 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 705 { 706 crit_enter(); 707 708 /* 709 * Set up frame for TX. 710 */ 711 712 frame->mii_stdelim = DC_MII_STARTDELIM; 713 frame->mii_opcode = DC_MII_WRITEOP; 714 frame->mii_turnaround = DC_MII_TURNAROUND; 715 716 /* 717 * Sync the PHYs. 718 */ 719 dc_mii_sync(sc); 720 721 dc_mii_send(sc, frame->mii_stdelim, 2); 722 dc_mii_send(sc, frame->mii_opcode, 2); 723 dc_mii_send(sc, frame->mii_phyaddr, 5); 724 dc_mii_send(sc, frame->mii_regaddr, 5); 725 dc_mii_send(sc, frame->mii_turnaround, 2); 726 dc_mii_send(sc, frame->mii_data, 16); 727 728 /* Idle bit. */ 729 dc_mii_writebit(sc, 0); 730 dc_mii_writebit(sc, 0); 731 732 crit_exit(); 733 734 return(0); 735 } 736 737 static int 738 dc_miibus_readreg(device_t dev, int phy, int reg) 739 { 740 struct dc_mii_frame frame; 741 struct dc_softc *sc; 742 int i, rval, phy_reg = 0; 743 744 sc = device_get_softc(dev); 745 bzero((char *)&frame, sizeof(frame)); 746 747 /* 748 * Note: both the AL981 and AN985 have internal PHYs, 749 * however the AL981 provides direct access to the PHY 750 * registers while the AN985 uses a serial MII interface. 751 * The AN985's MII interface is also buggy in that you 752 * can read from any MII address (0 to 31), but only address 1 753 * behaves normally. To deal with both cases, we pretend 754 * that the PHY is at MII address 1. 755 */ 756 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 757 return(0); 758 759 /* 760 * Note: the ukphy probes of the RS7112 report a PHY at 761 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 762 * so we only respond to correct one. 763 */ 764 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 765 return(0); 766 767 if (sc->dc_pmode != DC_PMODE_MII) { 768 if (phy == (MII_NPHY - 1)) { 769 switch(reg) { 770 case MII_BMSR: 771 /* 772 * Fake something to make the probe 773 * code think there's a PHY here. 774 */ 775 return(BMSR_MEDIAMASK); 776 break; 777 case MII_PHYIDR1: 778 if (DC_IS_PNIC(sc)) 779 return(DC_VENDORID_LO); 780 return(DC_VENDORID_DEC); 781 break; 782 case MII_PHYIDR2: 783 if (DC_IS_PNIC(sc)) 784 return(DC_DEVICEID_82C168); 785 return(DC_DEVICEID_21143); 786 break; 787 default: 788 return(0); 789 break; 790 } 791 } else 792 return(0); 793 } 794 795 if (DC_IS_PNIC(sc)) { 796 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 797 (phy << 23) | (reg << 18)); 798 for (i = 0; i < DC_TIMEOUT; i++) { 799 DELAY(1); 800 rval = CSR_READ_4(sc, DC_PN_MII); 801 if (!(rval & DC_PN_MII_BUSY)) { 802 rval &= 0xFFFF; 803 return(rval == 0xFFFF ? 0 : rval); 804 } 805 } 806 return(0); 807 } 808 809 if (DC_IS_COMET(sc)) { 810 switch(reg) { 811 case MII_BMCR: 812 phy_reg = DC_AL_BMCR; 813 break; 814 case MII_BMSR: 815 phy_reg = DC_AL_BMSR; 816 break; 817 case MII_PHYIDR1: 818 phy_reg = DC_AL_VENID; 819 break; 820 case MII_PHYIDR2: 821 phy_reg = DC_AL_DEVID; 822 break; 823 case MII_ANAR: 824 phy_reg = DC_AL_ANAR; 825 break; 826 case MII_ANLPAR: 827 phy_reg = DC_AL_LPAR; 828 break; 829 case MII_ANER: 830 phy_reg = DC_AL_ANER; 831 break; 832 default: 833 if_printf(&sc->arpcom.ac_if, 834 "phy_read: bad phy register %x\n", reg); 835 return(0); 836 break; 837 } 838 839 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 840 841 if (rval == 0xFFFF) 842 return(0); 843 return(rval); 844 } 845 846 frame.mii_phyaddr = phy; 847 frame.mii_regaddr = reg; 848 if (sc->dc_type == DC_TYPE_98713) { 849 phy_reg = CSR_READ_4(sc, DC_NETCFG); 850 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 851 } 852 dc_mii_readreg(sc, &frame); 853 if (sc->dc_type == DC_TYPE_98713) 854 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 855 856 return(frame.mii_data); 857 } 858 859 static int 860 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 861 { 862 struct dc_softc *sc; 863 struct dc_mii_frame frame; 864 int i, phy_reg = 0; 865 866 sc = device_get_softc(dev); 867 bzero((char *)&frame, sizeof(frame)); 868 869 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 870 return(0); 871 872 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 873 return(0); 874 875 if (DC_IS_PNIC(sc)) { 876 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 877 (phy << 23) | (reg << 10) | data); 878 for (i = 0; i < DC_TIMEOUT; i++) { 879 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 880 break; 881 } 882 return(0); 883 } 884 885 if (DC_IS_COMET(sc)) { 886 switch(reg) { 887 case MII_BMCR: 888 phy_reg = DC_AL_BMCR; 889 break; 890 case MII_BMSR: 891 phy_reg = DC_AL_BMSR; 892 break; 893 case MII_PHYIDR1: 894 phy_reg = DC_AL_VENID; 895 break; 896 case MII_PHYIDR2: 897 phy_reg = DC_AL_DEVID; 898 break; 899 case MII_ANAR: 900 phy_reg = DC_AL_ANAR; 901 break; 902 case MII_ANLPAR: 903 phy_reg = DC_AL_LPAR; 904 break; 905 case MII_ANER: 906 phy_reg = DC_AL_ANER; 907 break; 908 default: 909 if_printf(&sc->arpcom.ac_if, 910 "phy_write: bad phy register %x\n", reg); 911 return(0); 912 break; 913 } 914 915 CSR_WRITE_4(sc, phy_reg, data); 916 return(0); 917 } 918 919 frame.mii_phyaddr = phy; 920 frame.mii_regaddr = reg; 921 frame.mii_data = data; 922 923 if (sc->dc_type == DC_TYPE_98713) { 924 phy_reg = CSR_READ_4(sc, DC_NETCFG); 925 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 926 } 927 dc_mii_writereg(sc, &frame); 928 if (sc->dc_type == DC_TYPE_98713) 929 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 930 931 return(0); 932 } 933 934 static void 935 dc_miibus_statchg(device_t dev) 936 { 937 struct dc_softc *sc; 938 struct mii_data *mii; 939 struct ifmedia *ifm; 940 941 sc = device_get_softc(dev); 942 if (DC_IS_ADMTEK(sc)) 943 return; 944 945 mii = device_get_softc(sc->dc_miibus); 946 ifm = &mii->mii_media; 947 if (DC_IS_DAVICOM(sc) && 948 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 949 dc_setcfg(sc, ifm->ifm_media); 950 sc->dc_if_media = ifm->ifm_media; 951 } else { 952 dc_setcfg(sc, mii->mii_media_active); 953 sc->dc_if_media = mii->mii_media_active; 954 } 955 956 return; 957 } 958 959 /* 960 * Special support for DM9102A cards with HomePNA PHYs. Note: 961 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 962 * to be impossible to talk to the management interface of the DM9801 963 * PHY (its MDIO pin is not connected to anything). Consequently, 964 * the driver has to just 'know' about the additional mode and deal 965 * with it itself. *sigh* 966 */ 967 static void 968 dc_miibus_mediainit(device_t dev) 969 { 970 struct dc_softc *sc; 971 struct mii_data *mii; 972 struct ifmedia *ifm; 973 int rev; 974 975 rev = pci_get_revid(dev); 976 977 sc = device_get_softc(dev); 978 mii = device_get_softc(sc->dc_miibus); 979 ifm = &mii->mii_media; 980 981 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 982 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 983 984 return; 985 } 986 987 #define DC_BITS_512 9 988 #define DC_BITS_128 7 989 #define DC_BITS_64 6 990 991 static u_int32_t 992 dc_crc_mask(struct dc_softc *sc) 993 { 994 /* 995 * The hash table on the PNIC II and the MX98715AEC-C/D/E 996 * chips is only 128 bits wide. 997 */ 998 if (sc->dc_flags & DC_128BIT_HASH) 999 return ((1 << DC_BITS_128) - 1); 1000 1001 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1002 if (sc->dc_flags & DC_64BIT_HASH) 1003 return ((1 << DC_BITS_64) - 1); 1004 1005 return ((1 << DC_BITS_512) - 1); 1006 } 1007 1008 /* 1009 * 21143-style RX filter setup routine. Filter programming is done by 1010 * downloading a special setup frame into the TX engine. 21143, Macronix, 1011 * PNIC, PNIC II and Davicom chips are programmed this way. 1012 * 1013 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1014 * address (our node address) and a 512-bit hash filter for multicast 1015 * frames. We also sneak the broadcast address into the hash filter since 1016 * we need that too. 1017 */ 1018 void 1019 dc_setfilt_21143(struct dc_softc *sc) 1020 { 1021 struct dc_desc *sframe; 1022 u_int32_t h, crc_mask, *sp; 1023 struct ifmultiaddr *ifma; 1024 struct ifnet *ifp; 1025 int i; 1026 1027 ifp = &sc->arpcom.ac_if; 1028 1029 i = sc->dc_cdata.dc_tx_prod; 1030 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1031 sc->dc_cdata.dc_tx_cnt++; 1032 sframe = &sc->dc_ldata->dc_tx_list[i]; 1033 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1034 bzero((char *)sp, DC_SFRAME_LEN); 1035 1036 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1037 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1038 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1039 1040 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1041 1042 /* If we want promiscuous mode, set the allframes bit. */ 1043 if (ifp->if_flags & IFF_PROMISC) 1044 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1045 else 1046 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1047 1048 if (ifp->if_flags & IFF_ALLMULTI) 1049 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1050 else 1051 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1052 1053 crc_mask = dc_crc_mask(sc); 1054 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1055 if (ifma->ifma_addr->sa_family != AF_LINK) 1056 continue; 1057 h = ether_crc32_le( 1058 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1059 ETHER_ADDR_LEN) & crc_mask; 1060 sp[h >> 4] |= 1 << (h & 0xF); 1061 } 1062 1063 if (ifp->if_flags & IFF_BROADCAST) { 1064 h = ether_crc32_le(ifp->if_broadcastaddr, 1065 ETHER_ADDR_LEN) & crc_mask; 1066 sp[h >> 4] |= 1 << (h & 0xF); 1067 } 1068 1069 /* Set our MAC address */ 1070 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1071 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1072 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1073 1074 sframe->dc_status = DC_TXSTAT_OWN; 1075 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1076 1077 /* 1078 * The PNIC takes an exceedingly long time to process its 1079 * setup frame; wait 10ms after posting the setup frame 1080 * before proceeding, just so it has time to swallow its 1081 * medicine. 1082 */ 1083 DELAY(10000); 1084 1085 ifp->if_timer = 5; 1086 1087 return; 1088 } 1089 1090 void 1091 dc_setfilt_admtek(struct dc_softc *sc) 1092 { 1093 struct ifnet *ifp; 1094 int h = 0; 1095 u_int32_t crc_mask; 1096 u_int32_t hashes[2] = { 0, 0 }; 1097 struct ifmultiaddr *ifma; 1098 1099 ifp = &sc->arpcom.ac_if; 1100 1101 /* Init our MAC address */ 1102 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1103 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1104 1105 /* If we want promiscuous mode, set the allframes bit. */ 1106 if (ifp->if_flags & IFF_PROMISC) 1107 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1108 else 1109 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1110 1111 if (ifp->if_flags & IFF_ALLMULTI) 1112 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1113 else 1114 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1115 1116 /* first, zot all the existing hash bits */ 1117 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1118 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1119 1120 /* 1121 * If we're already in promisc or allmulti mode, we 1122 * don't have to bother programming the multicast filter. 1123 */ 1124 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1125 return; 1126 1127 /* now program new ones */ 1128 if (DC_IS_CENTAUR(sc)) 1129 crc_mask = dc_crc_mask(sc); 1130 else 1131 crc_mask = 0x3f; 1132 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1133 if (ifma->ifma_addr->sa_family != AF_LINK) 1134 continue; 1135 if (DC_IS_CENTAUR(sc)) { 1136 h = ether_crc32_le( 1137 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1138 ETHER_ADDR_LEN) & crc_mask; 1139 } else { 1140 h = ether_crc32_be( 1141 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1142 ETHER_ADDR_LEN); 1143 h = (h >> 26) & crc_mask; 1144 } 1145 if (h < 32) 1146 hashes[0] |= (1 << h); 1147 else 1148 hashes[1] |= (1 << (h - 32)); 1149 } 1150 1151 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1152 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1153 1154 return; 1155 } 1156 1157 void 1158 dc_setfilt_asix(struct dc_softc *sc) 1159 { 1160 struct ifnet *ifp; 1161 int h = 0; 1162 u_int32_t hashes[2] = { 0, 0 }; 1163 struct ifmultiaddr *ifma; 1164 1165 ifp = &sc->arpcom.ac_if; 1166 1167 /* Init our MAC address */ 1168 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1169 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1170 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1171 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1172 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1173 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1174 1175 /* If we want promiscuous mode, set the allframes bit. */ 1176 if (ifp->if_flags & IFF_PROMISC) 1177 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1178 else 1179 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1180 1181 if (ifp->if_flags & IFF_ALLMULTI) 1182 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1183 else 1184 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1185 1186 /* 1187 * The ASIX chip has a special bit to enable reception 1188 * of broadcast frames. 1189 */ 1190 if (ifp->if_flags & IFF_BROADCAST) 1191 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1192 else 1193 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1194 1195 /* first, zot all the existing hash bits */ 1196 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1197 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1198 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1199 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1200 1201 /* 1202 * If we're already in promisc or allmulti mode, we 1203 * don't have to bother programming the multicast filter. 1204 */ 1205 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1206 return; 1207 1208 /* now program new ones */ 1209 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1210 if (ifma->ifma_addr->sa_family != AF_LINK) 1211 continue; 1212 h = ether_crc32_be( 1213 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1214 ETHER_ADDR_LEN); 1215 h = (h >> 26) & 0x3f; 1216 if (h < 32) 1217 hashes[0] |= (1 << h); 1218 else 1219 hashes[1] |= (1 << (h - 32)); 1220 } 1221 1222 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1223 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1226 1227 return; 1228 } 1229 1230 static void 1231 dc_setfilt(struct dc_softc *sc) 1232 { 1233 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1234 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1235 dc_setfilt_21143(sc); 1236 1237 if (DC_IS_ASIX(sc)) 1238 dc_setfilt_asix(sc); 1239 1240 if (DC_IS_ADMTEK(sc)) 1241 dc_setfilt_admtek(sc); 1242 1243 return; 1244 } 1245 1246 /* 1247 * In order to fiddle with the 1248 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1249 * first have to put the transmit and/or receive logic in the idle state. 1250 */ 1251 static void 1252 dc_setcfg(struct dc_softc *sc, int media) 1253 { 1254 int i, restart = 0; 1255 u_int32_t isr; 1256 1257 if (IFM_SUBTYPE(media) == IFM_NONE) 1258 return; 1259 1260 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1261 restart = 1; 1262 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1263 1264 for (i = 0; i < DC_TIMEOUT; i++) { 1265 isr = CSR_READ_4(sc, DC_ISR); 1266 if (isr & DC_ISR_TX_IDLE || 1267 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1268 break; 1269 DELAY(10); 1270 } 1271 1272 if (i == DC_TIMEOUT) { 1273 if_printf(&sc->arpcom.ac_if, 1274 "failed to force tx and rx to idle state\n"); 1275 } 1276 } 1277 1278 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1279 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1280 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1281 if (sc->dc_pmode == DC_PMODE_MII) { 1282 int watchdogreg; 1283 1284 if (DC_IS_INTEL(sc)) { 1285 /* there's a write enable bit here that reads as 1 */ 1286 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1287 watchdogreg &= ~DC_WDOG_CTLWREN; 1288 watchdogreg |= DC_WDOG_JABBERDIS; 1289 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1290 } else { 1291 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1292 } 1293 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1294 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1295 if (sc->dc_type == DC_TYPE_98713) 1296 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1297 DC_NETCFG_SCRAMBLER)); 1298 if (!DC_IS_DAVICOM(sc)) 1299 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1300 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1301 if (DC_IS_INTEL(sc)) 1302 dc_apply_fixup(sc, IFM_AUTO); 1303 } else { 1304 if (DC_IS_PNIC(sc)) { 1305 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1306 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1307 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1308 } 1309 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1310 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1311 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1312 if (DC_IS_INTEL(sc)) 1313 dc_apply_fixup(sc, 1314 (media & IFM_GMASK) == IFM_FDX ? 1315 IFM_100_TX|IFM_FDX : IFM_100_TX); 1316 } 1317 } 1318 1319 if (IFM_SUBTYPE(media) == IFM_10_T) { 1320 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1321 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1322 if (sc->dc_pmode == DC_PMODE_MII) { 1323 int watchdogreg; 1324 1325 /* there's a write enable bit here that reads as 1 */ 1326 if (DC_IS_INTEL(sc)) { 1327 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1328 watchdogreg &= ~DC_WDOG_CTLWREN; 1329 watchdogreg |= DC_WDOG_JABBERDIS; 1330 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1331 } else { 1332 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1333 } 1334 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1335 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1336 if (sc->dc_type == DC_TYPE_98713) 1337 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1338 if (!DC_IS_DAVICOM(sc)) 1339 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1340 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1341 if (DC_IS_INTEL(sc)) 1342 dc_apply_fixup(sc, IFM_AUTO); 1343 } else { 1344 if (DC_IS_PNIC(sc)) { 1345 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1346 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1347 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1348 } 1349 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1350 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1351 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1352 if (DC_IS_INTEL(sc)) { 1353 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1354 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1355 if ((media & IFM_GMASK) == IFM_FDX) 1356 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1357 else 1358 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1359 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1360 DC_CLRBIT(sc, DC_10BTCTRL, 1361 DC_TCTL_AUTONEGENBL); 1362 dc_apply_fixup(sc, 1363 (media & IFM_GMASK) == IFM_FDX ? 1364 IFM_10_T|IFM_FDX : IFM_10_T); 1365 DELAY(20000); 1366 } 1367 } 1368 } 1369 1370 /* 1371 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1372 * PHY and we want HomePNA mode, set the portsel bit to turn 1373 * on the external MII port. 1374 */ 1375 if (DC_IS_DAVICOM(sc)) { 1376 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1377 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1378 sc->dc_link = 1; 1379 } else { 1380 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1381 } 1382 } 1383 1384 if ((media & IFM_GMASK) == IFM_FDX) { 1385 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1386 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1387 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1388 } else { 1389 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1390 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1391 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1392 } 1393 1394 if (restart) 1395 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1396 1397 return; 1398 } 1399 1400 static void 1401 dc_reset(struct dc_softc *sc) 1402 { 1403 int i; 1404 1405 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1406 1407 for (i = 0; i < DC_TIMEOUT; i++) { 1408 DELAY(10); 1409 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1410 break; 1411 } 1412 1413 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) { 1414 DELAY(10000); 1415 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1416 i = 0; 1417 } 1418 1419 if (i == DC_TIMEOUT) 1420 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 1421 1422 /* Wait a little while for the chip to get its brains in order. */ 1423 DELAY(1000); 1424 1425 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1426 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1427 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1428 1429 /* 1430 * Bring the SIA out of reset. In some cases, it looks 1431 * like failing to unreset the SIA soon enough gets it 1432 * into a state where it will never come out of reset 1433 * until we reset the whole chip again. 1434 */ 1435 if (DC_IS_INTEL(sc)) { 1436 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1437 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1438 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1439 } 1440 1441 return; 1442 } 1443 1444 static struct dc_type 1445 *dc_devtype(device_t dev) 1446 { 1447 struct dc_type *t; 1448 u_int32_t rev; 1449 1450 t = dc_devs; 1451 1452 while(t->dc_name != NULL) { 1453 if ((pci_get_vendor(dev) == t->dc_vid) && 1454 (pci_get_device(dev) == t->dc_did)) { 1455 /* Check the PCI revision */ 1456 rev = pci_get_revid(dev); 1457 if (t->dc_did == DC_DEVICEID_98713 && 1458 rev >= DC_REVISION_98713A) 1459 t++; 1460 if (t->dc_did == DC_DEVICEID_98713_CP && 1461 rev >= DC_REVISION_98713A) 1462 t++; 1463 if (t->dc_did == DC_DEVICEID_987x5 && 1464 rev >= DC_REVISION_98715AEC_C) 1465 t++; 1466 if (t->dc_did == DC_DEVICEID_987x5 && 1467 rev >= DC_REVISION_98725) 1468 t++; 1469 if (t->dc_did == DC_DEVICEID_AX88140A && 1470 rev >= DC_REVISION_88141) 1471 t++; 1472 if (t->dc_did == DC_DEVICEID_82C168 && 1473 rev >= DC_REVISION_82C169) 1474 t++; 1475 if (t->dc_did == DC_DEVICEID_DM9102 && 1476 rev >= DC_REVISION_DM9102A) 1477 t++; 1478 return(t); 1479 } 1480 t++; 1481 } 1482 1483 return(NULL); 1484 } 1485 1486 /* 1487 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1488 * IDs against our list and return a device name if we find a match. 1489 * We do a little bit of extra work to identify the exact type of 1490 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1491 * but different revision IDs. The same is true for 98715/98715A 1492 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1493 * cases, the exact chip revision affects driver behavior. 1494 */ 1495 static int 1496 dc_probe(device_t dev) 1497 { 1498 struct dc_type *t; 1499 1500 t = dc_devtype(dev); 1501 1502 if (t != NULL) { 1503 device_set_desc(dev, t->dc_name); 1504 return(0); 1505 } 1506 1507 return(ENXIO); 1508 } 1509 1510 static void 1511 dc_acpi(device_t dev) 1512 { 1513 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1514 uint32_t iobase, membase, irq; 1515 struct dc_softc *sc; 1516 1517 /* Save important PCI config data. */ 1518 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1519 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1520 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1521 1522 sc = device_get_softc(dev); 1523 /* Reset the power state. */ 1524 if_printf(&sc->arpcom.ac_if, 1525 "chip is in D%d power mode " 1526 "-- setting to D0\n", pci_get_powerstate(dev)); 1527 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1528 1529 /* Restore PCI config data. */ 1530 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1531 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1532 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1533 } 1534 } 1535 1536 static void 1537 dc_apply_fixup(struct dc_softc *sc, int media) 1538 { 1539 struct dc_mediainfo *m; 1540 u_int8_t *p; 1541 int i; 1542 u_int32_t reg; 1543 1544 m = sc->dc_mi; 1545 1546 while (m != NULL) { 1547 if (m->dc_media == media) 1548 break; 1549 m = m->dc_next; 1550 } 1551 1552 if (m == NULL) 1553 return; 1554 1555 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1556 reg = (p[0] | (p[1] << 8)) << 16; 1557 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1558 } 1559 1560 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1561 reg = (p[0] | (p[1] << 8)) << 16; 1562 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1563 } 1564 1565 return; 1566 } 1567 1568 static void 1569 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1570 { 1571 struct dc_mediainfo *m; 1572 1573 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1574 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){ 1575 case DC_SIA_CODE_10BT: 1576 m->dc_media = IFM_10_T; 1577 break; 1578 1579 case DC_SIA_CODE_10BT_FDX: 1580 m->dc_media = IFM_10_T|IFM_FDX; 1581 break; 1582 1583 case DC_SIA_CODE_10B2: 1584 m->dc_media = IFM_10_2; 1585 break; 1586 1587 case DC_SIA_CODE_10B5: 1588 m->dc_media = IFM_10_5; 1589 break; 1590 } 1591 if (l->dc_sia_code & DC_SIA_CODE_EXT){ 1592 m->dc_gp_len = 2; 1593 m->dc_gp_ptr = 1594 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1595 } else { 1596 m->dc_gp_len = 2; 1597 m->dc_gp_ptr = 1598 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1599 } 1600 1601 m->dc_next = sc->dc_mi; 1602 sc->dc_mi = m; 1603 1604 sc->dc_pmode = DC_PMODE_SIA; 1605 1606 return; 1607 } 1608 1609 static void 1610 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1611 { 1612 struct dc_mediainfo *m; 1613 1614 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1615 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1616 m->dc_media = IFM_100_TX; 1617 1618 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1619 m->dc_media = IFM_100_TX|IFM_FDX; 1620 1621 m->dc_gp_len = 2; 1622 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1623 1624 m->dc_next = sc->dc_mi; 1625 sc->dc_mi = m; 1626 1627 sc->dc_pmode = DC_PMODE_SYM; 1628 1629 return; 1630 } 1631 1632 static void 1633 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1634 { 1635 u_int8_t *p; 1636 struct dc_mediainfo *m; 1637 1638 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1639 /* We abuse IFM_AUTO to represent MII. */ 1640 m->dc_media = IFM_AUTO; 1641 m->dc_gp_len = l->dc_gpr_len; 1642 1643 p = (u_int8_t *)l; 1644 p += sizeof(struct dc_eblock_mii); 1645 m->dc_gp_ptr = p; 1646 p += 2 * l->dc_gpr_len; 1647 m->dc_reset_len = *p; 1648 p++; 1649 m->dc_reset_ptr = p; 1650 1651 m->dc_next = sc->dc_mi; 1652 sc->dc_mi = m; 1653 1654 return; 1655 } 1656 1657 static void 1658 dc_read_srom(struct dc_softc *sc, int bits) 1659 { 1660 int size; 1661 1662 size = 2 << bits; 1663 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT); 1664 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1665 } 1666 1667 static void 1668 dc_parse_21143_srom(struct dc_softc *sc) 1669 { 1670 struct dc_leaf_hdr *lhdr; 1671 struct dc_eblock_hdr *hdr; 1672 int i, loff; 1673 char *ptr; 1674 int have_mii; 1675 1676 have_mii = 0; 1677 loff = sc->dc_srom[27]; 1678 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1679 1680 ptr = (char *)lhdr; 1681 ptr += sizeof(struct dc_leaf_hdr) - 1; 1682 /* 1683 * Look if we got a MII media block. 1684 */ 1685 for (i = 0; i < lhdr->dc_mcnt; i++) { 1686 hdr = (struct dc_eblock_hdr *)ptr; 1687 if (hdr->dc_type == DC_EBLOCK_MII) 1688 have_mii++; 1689 1690 ptr += (hdr->dc_len & 0x7F); 1691 ptr++; 1692 } 1693 1694 /* 1695 * Do the same thing again. Only use SIA and SYM media 1696 * blocks if no MII media block is available. 1697 */ 1698 ptr = (char *)lhdr; 1699 ptr += sizeof(struct dc_leaf_hdr) - 1; 1700 for (i = 0; i < lhdr->dc_mcnt; i++) { 1701 hdr = (struct dc_eblock_hdr *)ptr; 1702 switch(hdr->dc_type) { 1703 case DC_EBLOCK_MII: 1704 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1705 break; 1706 case DC_EBLOCK_SIA: 1707 if (! have_mii) 1708 dc_decode_leaf_sia(sc, 1709 (struct dc_eblock_sia *)hdr); 1710 break; 1711 case DC_EBLOCK_SYM: 1712 if (! have_mii) 1713 dc_decode_leaf_sym(sc, 1714 (struct dc_eblock_sym *)hdr); 1715 break; 1716 default: 1717 /* Don't care. Yet. */ 1718 break; 1719 } 1720 ptr += (hdr->dc_len & 0x7F); 1721 ptr++; 1722 } 1723 1724 return; 1725 } 1726 1727 /* 1728 * Attach the interface. Allocate softc structures, do ifmedia 1729 * setup and ethernet/BPF attach. 1730 */ 1731 static int 1732 dc_attach(device_t dev) 1733 { 1734 int tmp = 0; 1735 u_char eaddr[ETHER_ADDR_LEN]; 1736 u_int32_t command; 1737 struct dc_softc *sc; 1738 struct ifnet *ifp; 1739 u_int32_t revision; 1740 int error = 0, rid, mac_offset; 1741 1742 sc = device_get_softc(dev); 1743 callout_init(&sc->dc_stat_timer); 1744 1745 ifp = &sc->arpcom.ac_if; 1746 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1747 1748 /* 1749 * Handle power management nonsense. 1750 */ 1751 dc_acpi(dev); 1752 1753 /* 1754 * Map control/status registers. 1755 */ 1756 pci_enable_busmaster(dev); 1757 1758 rid = DC_RID; 1759 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1760 1761 if (sc->dc_res == NULL) { 1762 device_printf(dev, "couldn't map ports/memory\n"); 1763 error = ENXIO; 1764 goto fail; 1765 } 1766 1767 sc->dc_btag = rman_get_bustag(sc->dc_res); 1768 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1769 1770 /* Allocate interrupt */ 1771 rid = 0; 1772 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1773 RF_SHAREABLE | RF_ACTIVE); 1774 1775 if (sc->dc_irq == NULL) { 1776 device_printf(dev, "couldn't map interrupt\n"); 1777 error = ENXIO; 1778 goto fail; 1779 } 1780 1781 /* Need this info to decide on a chip type. */ 1782 sc->dc_info = dc_devtype(dev); 1783 revision = pci_get_revid(dev); 1784 1785 /* Get the eeprom width, but PNIC has diff eeprom */ 1786 if (sc->dc_info->dc_did != DC_DEVICEID_82C168) 1787 dc_eeprom_width(sc); 1788 1789 switch(sc->dc_info->dc_did) { 1790 case DC_DEVICEID_21143: 1791 sc->dc_type = DC_TYPE_21143; 1792 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1793 sc->dc_flags |= DC_REDUCED_MII_POLL; 1794 /* Save EEPROM contents so we can parse them later. */ 1795 dc_read_srom(sc, sc->dc_romwidth); 1796 break; 1797 case DC_DEVICEID_DM9009: 1798 case DC_DEVICEID_DM9100: 1799 case DC_DEVICEID_DM9102: 1800 sc->dc_type = DC_TYPE_DM9102; 1801 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1802 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1803 sc->dc_flags |= DC_TX_ALIGN; 1804 sc->dc_pmode = DC_PMODE_MII; 1805 /* Increase the latency timer value. */ 1806 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1807 command &= 0xFFFF00FF; 1808 command |= 0x00008000; 1809 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1810 break; 1811 case DC_DEVICEID_AL981: 1812 sc->dc_type = DC_TYPE_AL981; 1813 sc->dc_flags |= DC_TX_USE_TX_INTR; 1814 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1815 sc->dc_pmode = DC_PMODE_MII; 1816 dc_read_srom(sc, sc->dc_romwidth); 1817 break; 1818 case DC_DEVICEID_AN985: 1819 case DC_DEVICEID_EN2242: 1820 case DC_DEVICEID_3CSOHOB: 1821 sc->dc_type = DC_TYPE_AN985; 1822 sc->dc_flags |= DC_64BIT_HASH; 1823 sc->dc_flags |= DC_TX_USE_TX_INTR; 1824 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1825 sc->dc_pmode = DC_PMODE_MII; 1826 1827 break; 1828 case DC_DEVICEID_98713: 1829 case DC_DEVICEID_98713_CP: 1830 if (revision < DC_REVISION_98713A) { 1831 sc->dc_type = DC_TYPE_98713; 1832 } 1833 if (revision >= DC_REVISION_98713A) { 1834 sc->dc_type = DC_TYPE_98713A; 1835 sc->dc_flags |= DC_21143_NWAY; 1836 } 1837 sc->dc_flags |= DC_REDUCED_MII_POLL; 1838 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1839 break; 1840 case DC_DEVICEID_987x5: 1841 case DC_DEVICEID_EN1217: 1842 /* 1843 * Macronix MX98715AEC-C/D/E parts have only a 1844 * 128-bit hash table. We need to deal with these 1845 * in the same manner as the PNIC II so that we 1846 * get the right number of bits out of the 1847 * CRC routine. 1848 */ 1849 if (revision >= DC_REVISION_98715AEC_C && 1850 revision < DC_REVISION_98725) 1851 sc->dc_flags |= DC_128BIT_HASH; 1852 sc->dc_type = DC_TYPE_987x5; 1853 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1854 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1855 break; 1856 case DC_DEVICEID_98727: 1857 sc->dc_type = DC_TYPE_987x5; 1858 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1859 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1860 break; 1861 case DC_DEVICEID_82C115: 1862 sc->dc_type = DC_TYPE_PNICII; 1863 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1864 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1865 break; 1866 case DC_DEVICEID_82C168: 1867 sc->dc_type = DC_TYPE_PNIC; 1868 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1869 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1870 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK); 1871 if (revision < DC_REVISION_82C169) 1872 sc->dc_pmode = DC_PMODE_SYM; 1873 break; 1874 case DC_DEVICEID_AX88140A: 1875 sc->dc_type = DC_TYPE_ASIX; 1876 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1877 sc->dc_flags |= DC_REDUCED_MII_POLL; 1878 sc->dc_pmode = DC_PMODE_MII; 1879 break; 1880 case DC_DEVICEID_RS7112: 1881 sc->dc_type = DC_TYPE_CONEXANT; 1882 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1883 sc->dc_flags |= DC_REDUCED_MII_POLL; 1884 sc->dc_pmode = DC_PMODE_MII; 1885 dc_read_srom(sc, sc->dc_romwidth); 1886 break; 1887 default: 1888 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 1889 break; 1890 } 1891 1892 /* Save the cache line size. */ 1893 if (DC_IS_DAVICOM(sc)) 1894 sc->dc_cachesize = 0; 1895 else 1896 sc->dc_cachesize = pci_read_config(dev, 1897 DC_PCI_CFLT, 4) & 0xFF; 1898 1899 /* Reset the adapter. */ 1900 dc_reset(sc); 1901 1902 /* Take 21143 out of snooze mode */ 1903 if (DC_IS_INTEL(sc)) { 1904 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1905 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1906 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1907 } 1908 1909 /* 1910 * Try to learn something about the supported media. 1911 * We know that ASIX and ADMtek and Davicom devices 1912 * will *always* be using MII media, so that's a no-brainer. 1913 * The tricky ones are the Macronix/PNIC II and the 1914 * Intel 21143. 1915 */ 1916 if (DC_IS_INTEL(sc)) 1917 dc_parse_21143_srom(sc); 1918 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1919 if (sc->dc_type == DC_TYPE_98713) 1920 sc->dc_pmode = DC_PMODE_MII; 1921 else 1922 sc->dc_pmode = DC_PMODE_SYM; 1923 } else if (!sc->dc_pmode) 1924 sc->dc_pmode = DC_PMODE_MII; 1925 1926 /* 1927 * Get station address from the EEPROM. 1928 */ 1929 switch(sc->dc_type) { 1930 case DC_TYPE_98713: 1931 case DC_TYPE_98713A: 1932 case DC_TYPE_987x5: 1933 case DC_TYPE_PNICII: 1934 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1935 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1936 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1937 break; 1938 case DC_TYPE_PNIC: 1939 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1940 break; 1941 case DC_TYPE_DM9102: 1942 case DC_TYPE_21143: 1943 case DC_TYPE_ASIX: 1944 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1945 break; 1946 case DC_TYPE_AL981: 1947 case DC_TYPE_AN985: 1948 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0); 1949 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1); 1950 break; 1951 case DC_TYPE_CONEXANT: 1952 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 1953 break; 1954 default: 1955 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1956 break; 1957 } 1958 1959 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1960 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1961 1962 if (sc->dc_ldata == NULL) { 1963 device_printf(dev, "no memory for list buffers!\n"); 1964 error = ENXIO; 1965 goto fail; 1966 } 1967 1968 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1969 1970 ifp->if_softc = sc; 1971 ifp->if_mtu = ETHERMTU; 1972 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1973 ifp->if_ioctl = dc_ioctl; 1974 ifp->if_start = dc_start; 1975 #ifdef DEVICE_POLLING 1976 ifp->if_poll = dc_poll; 1977 #endif 1978 ifp->if_watchdog = dc_watchdog; 1979 ifp->if_init = dc_init; 1980 ifp->if_baudrate = 10000000; 1981 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1); 1982 ifq_set_ready(&ifp->if_snd); 1983 1984 /* 1985 * Do MII setup. If this is a 21143, check for a PHY on the 1986 * MII bus after applying any necessary fixups to twiddle the 1987 * GPIO bits. If we don't end up finding a PHY, restore the 1988 * old selection (SIA only or SIA/SYM) and attach the dcphy 1989 * driver instead. 1990 */ 1991 if (DC_IS_INTEL(sc)) { 1992 dc_apply_fixup(sc, IFM_AUTO); 1993 tmp = sc->dc_pmode; 1994 sc->dc_pmode = DC_PMODE_MII; 1995 } 1996 1997 error = mii_phy_probe(dev, &sc->dc_miibus, 1998 dc_ifmedia_upd, dc_ifmedia_sts); 1999 2000 if (error && DC_IS_INTEL(sc)) { 2001 sc->dc_pmode = tmp; 2002 if (sc->dc_pmode != DC_PMODE_SIA) 2003 sc->dc_pmode = DC_PMODE_SYM; 2004 sc->dc_flags |= DC_21143_NWAY; 2005 mii_phy_probe(dev, &sc->dc_miibus, 2006 dc_ifmedia_upd, dc_ifmedia_sts); 2007 /* 2008 * For non-MII cards, we need to have the 21143 2009 * drive the LEDs. Except there are some systems 2010 * like the NEC VersaPro NoteBook PC which have no 2011 * LEDs, and twiddling these bits has adverse effects 2012 * on them. (I.e. you suddenly can't get a link.) 2013 */ 2014 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2015 sc->dc_flags |= DC_TULIP_LEDS; 2016 error = 0; 2017 } 2018 2019 if (error) { 2020 device_printf(dev, "MII without any PHY!\n"); 2021 error = ENXIO; 2022 goto fail; 2023 } 2024 2025 /* 2026 * Call MI attach routine. 2027 */ 2028 ether_ifattach(ifp, eaddr); 2029 2030 if (DC_IS_ADMTEK(sc)) { 2031 /* 2032 * Set automatic TX underrun recovery for the ADMtek chips 2033 */ 2034 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2035 } 2036 2037 /* 2038 * Tell the upper layer(s) we support long frames. 2039 */ 2040 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2041 2042 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 2043 dc_intr, sc, &sc->dc_intrhand, NULL); 2044 if (error) { 2045 ether_ifdetach(ifp); 2046 device_printf(dev, "couldn't set up irq\n"); 2047 goto fail; 2048 } 2049 2050 return(0); 2051 2052 fail: 2053 dc_detach(dev); 2054 return(error); 2055 } 2056 2057 static int 2058 dc_detach(device_t dev) 2059 { 2060 struct dc_softc *sc = device_get_softc(dev); 2061 struct ifnet *ifp = &sc->arpcom.ac_if; 2062 struct dc_mediainfo *m; 2063 2064 crit_enter(); 2065 2066 if (device_is_attached(dev)) { 2067 dc_stop(sc); 2068 ether_ifdetach(ifp); 2069 } 2070 2071 if (sc->dc_miibus) 2072 device_delete_child(dev, sc->dc_miibus); 2073 bus_generic_detach(dev); 2074 2075 if (sc->dc_intrhand) 2076 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2077 2078 crit_exit(); 2079 2080 if (sc->dc_irq) 2081 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2082 if (sc->dc_res) 2083 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2084 2085 if (sc->dc_ldata) 2086 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2087 if (sc->dc_pnic_rx_buf != NULL) 2088 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2089 2090 while(sc->dc_mi != NULL) { 2091 m = sc->dc_mi->dc_next; 2092 free(sc->dc_mi, M_DEVBUF); 2093 sc->dc_mi = m; 2094 } 2095 2096 if (sc->dc_srom) 2097 free(sc->dc_srom, M_DEVBUF); 2098 2099 return(0); 2100 } 2101 2102 /* 2103 * Initialize the transmit descriptors. 2104 */ 2105 static int 2106 dc_list_tx_init(struct dc_softc *sc) 2107 { 2108 struct dc_chain_data *cd; 2109 struct dc_list_data *ld; 2110 int i; 2111 2112 cd = &sc->dc_cdata; 2113 ld = sc->dc_ldata; 2114 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2115 if (i == (DC_TX_LIST_CNT - 1)) { 2116 ld->dc_tx_list[i].dc_next = 2117 vtophys(&ld->dc_tx_list[0]); 2118 } else { 2119 ld->dc_tx_list[i].dc_next = 2120 vtophys(&ld->dc_tx_list[i + 1]); 2121 } 2122 cd->dc_tx_chain[i] = NULL; 2123 ld->dc_tx_list[i].dc_data = 0; 2124 ld->dc_tx_list[i].dc_ctl = 0; 2125 } 2126 2127 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2128 2129 return(0); 2130 } 2131 2132 2133 /* 2134 * Initialize the RX descriptors and allocate mbufs for them. Note that 2135 * we arrange the descriptors in a closed ring, so that the last descriptor 2136 * points back to the first. 2137 */ 2138 static int 2139 dc_list_rx_init(struct dc_softc *sc) 2140 { 2141 struct dc_chain_data *cd; 2142 struct dc_list_data *ld; 2143 int i; 2144 2145 cd = &sc->dc_cdata; 2146 ld = sc->dc_ldata; 2147 2148 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2149 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2150 return(ENOBUFS); 2151 if (i == (DC_RX_LIST_CNT - 1)) { 2152 ld->dc_rx_list[i].dc_next = 2153 vtophys(&ld->dc_rx_list[0]); 2154 } else { 2155 ld->dc_rx_list[i].dc_next = 2156 vtophys(&ld->dc_rx_list[i + 1]); 2157 } 2158 } 2159 2160 cd->dc_rx_prod = 0; 2161 2162 return(0); 2163 } 2164 2165 /* 2166 * Initialize an RX descriptor and attach an MBUF cluster. 2167 */ 2168 static int 2169 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m) 2170 { 2171 struct mbuf *m_new = NULL; 2172 struct dc_desc *c; 2173 2174 c = &sc->dc_ldata->dc_rx_list[i]; 2175 2176 if (m == NULL) { 2177 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2178 if (m_new == NULL) 2179 return (ENOBUFS); 2180 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2181 } else { 2182 m_new = m; 2183 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2184 m_new->m_data = m_new->m_ext.ext_buf; 2185 } 2186 2187 m_adj(m_new, sizeof(u_int64_t)); 2188 2189 /* 2190 * If this is a PNIC chip, zero the buffer. This is part 2191 * of the workaround for the receive bug in the 82c168 and 2192 * 82c169 chips. 2193 */ 2194 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2195 bzero((char *)mtod(m_new, char *), m_new->m_len); 2196 2197 sc->dc_cdata.dc_rx_chain[i] = m_new; 2198 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2199 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2200 c->dc_status = DC_RXSTAT_OWN; 2201 2202 return(0); 2203 } 2204 2205 /* 2206 * Grrrrr. 2207 * The PNIC chip has a terrible bug in it that manifests itself during 2208 * periods of heavy activity. The exact mode of failure if difficult to 2209 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2210 * will happen on slow machines. The bug is that sometimes instead of 2211 * uploading one complete frame during reception, it uploads what looks 2212 * like the entire contents of its FIFO memory. The frame we want is at 2213 * the end of the whole mess, but we never know exactly how much data has 2214 * been uploaded, so salvaging the frame is hard. 2215 * 2216 * There is only one way to do it reliably, and it's disgusting. 2217 * Here's what we know: 2218 * 2219 * - We know there will always be somewhere between one and three extra 2220 * descriptors uploaded. 2221 * 2222 * - We know the desired received frame will always be at the end of the 2223 * total data upload. 2224 * 2225 * - We know the size of the desired received frame because it will be 2226 * provided in the length field of the status word in the last descriptor. 2227 * 2228 * Here's what we do: 2229 * 2230 * - When we allocate buffers for the receive ring, we bzero() them. 2231 * This means that we know that the buffer contents should be all 2232 * zeros, except for data uploaded by the chip. 2233 * 2234 * - We also force the PNIC chip to upload frames that include the 2235 * ethernet CRC at the end. 2236 * 2237 * - We gather all of the bogus frame data into a single buffer. 2238 * 2239 * - We then position a pointer at the end of this buffer and scan 2240 * backwards until we encounter the first non-zero byte of data. 2241 * This is the end of the received frame. We know we will encounter 2242 * some data at the end of the frame because the CRC will always be 2243 * there, so even if the sender transmits a packet of all zeros, 2244 * we won't be fooled. 2245 * 2246 * - We know the size of the actual received frame, so we subtract 2247 * that value from the current pointer location. This brings us 2248 * to the start of the actual received packet. 2249 * 2250 * - We copy this into an mbuf and pass it on, along with the actual 2251 * frame length. 2252 * 2253 * The performance hit is tremendous, but it beats dropping frames all 2254 * the time. 2255 */ 2256 2257 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2258 static void 2259 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2260 { 2261 struct dc_desc *cur_rx; 2262 struct dc_desc *c = NULL; 2263 struct mbuf *m = NULL; 2264 unsigned char *ptr; 2265 int i, total_len; 2266 u_int32_t rxstat = 0; 2267 2268 i = sc->dc_pnic_rx_bug_save; 2269 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2270 ptr = sc->dc_pnic_rx_buf; 2271 bzero(ptr, DC_RXLEN * 5); 2272 2273 /* Copy all the bytes from the bogus buffers. */ 2274 while (1) { 2275 c = &sc->dc_ldata->dc_rx_list[i]; 2276 rxstat = c->dc_status; 2277 m = sc->dc_cdata.dc_rx_chain[i]; 2278 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2279 ptr += DC_RXLEN; 2280 /* If this is the last buffer, break out. */ 2281 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2282 break; 2283 dc_newbuf(sc, i, m); 2284 DC_INC(i, DC_RX_LIST_CNT); 2285 } 2286 2287 /* Find the length of the actual receive frame. */ 2288 total_len = DC_RXBYTES(rxstat); 2289 2290 /* Scan backwards until we hit a non-zero byte. */ 2291 while(*ptr == 0x00) 2292 ptr--; 2293 2294 /* Round off. */ 2295 if ((uintptr_t)(ptr) & 0x3) 2296 ptr -= 1; 2297 2298 /* Now find the start of the frame. */ 2299 ptr -= total_len; 2300 if (ptr < sc->dc_pnic_rx_buf) 2301 ptr = sc->dc_pnic_rx_buf; 2302 2303 /* 2304 * Now copy the salvaged frame to the last mbuf and fake up 2305 * the status word to make it look like a successful 2306 * frame reception. 2307 */ 2308 dc_newbuf(sc, i, m); 2309 bcopy(ptr, mtod(m, char *), total_len); 2310 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2311 2312 return; 2313 } 2314 2315 /* 2316 * This routine searches the RX ring for dirty descriptors in the 2317 * event that the rxeof routine falls out of sync with the chip's 2318 * current descriptor pointer. This may happen sometimes as a result 2319 * of a "no RX buffer available" condition that happens when the chip 2320 * consumes all of the RX buffers before the driver has a chance to 2321 * process the RX ring. This routine may need to be called more than 2322 * once to bring the driver back in sync with the chip, however we 2323 * should still be getting RX DONE interrupts to drive the search 2324 * for new packets in the RX ring, so we should catch up eventually. 2325 */ 2326 static int 2327 dc_rx_resync(struct dc_softc *sc) 2328 { 2329 int i, pos; 2330 struct dc_desc *cur_rx; 2331 2332 pos = sc->dc_cdata.dc_rx_prod; 2333 2334 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2335 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2336 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2337 break; 2338 DC_INC(pos, DC_RX_LIST_CNT); 2339 } 2340 2341 /* If the ring really is empty, then just return. */ 2342 if (i == DC_RX_LIST_CNT) 2343 return(0); 2344 2345 /* We've fallen behing the chip: catch it. */ 2346 sc->dc_cdata.dc_rx_prod = pos; 2347 2348 return(EAGAIN); 2349 } 2350 2351 /* 2352 * A frame has been uploaded: pass the resulting mbuf chain up to 2353 * the higher level protocols. 2354 */ 2355 static void 2356 dc_rxeof(struct dc_softc *sc) 2357 { 2358 struct mbuf *m; 2359 struct ifnet *ifp; 2360 struct dc_desc *cur_rx; 2361 int i, total_len = 0; 2362 u_int32_t rxstat; 2363 2364 ifp = &sc->arpcom.ac_if; 2365 i = sc->dc_cdata.dc_rx_prod; 2366 2367 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2368 2369 #ifdef DEVICE_POLLING 2370 if (ifp->if_flags & IFF_POLLING) { 2371 if (sc->rxcycles <= 0) 2372 break; 2373 sc->rxcycles--; 2374 } 2375 #endif /* DEVICE_POLLING */ 2376 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2377 rxstat = cur_rx->dc_status; 2378 m = sc->dc_cdata.dc_rx_chain[i]; 2379 total_len = DC_RXBYTES(rxstat); 2380 2381 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2382 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2383 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2384 sc->dc_pnic_rx_bug_save = i; 2385 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2386 DC_INC(i, DC_RX_LIST_CNT); 2387 continue; 2388 } 2389 dc_pnic_rx_bug_war(sc, i); 2390 rxstat = cur_rx->dc_status; 2391 total_len = DC_RXBYTES(rxstat); 2392 } 2393 } 2394 2395 sc->dc_cdata.dc_rx_chain[i] = NULL; 2396 2397 /* 2398 * If an error occurs, update stats, clear the 2399 * status word and leave the mbuf cluster in place: 2400 * it should simply get re-used next time this descriptor 2401 * comes up in the ring. However, don't report long 2402 * frames as errors since they could be vlans 2403 */ 2404 if ((rxstat & DC_RXSTAT_RXERR)){ 2405 if (!(rxstat & DC_RXSTAT_GIANT) || 2406 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2407 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2408 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2409 ifp->if_ierrors++; 2410 if (rxstat & DC_RXSTAT_COLLSEEN) 2411 ifp->if_collisions++; 2412 dc_newbuf(sc, i, m); 2413 if (rxstat & DC_RXSTAT_CRCERR) { 2414 DC_INC(i, DC_RX_LIST_CNT); 2415 continue; 2416 } else { 2417 dc_init(sc); 2418 return; 2419 } 2420 } 2421 } 2422 2423 /* No errors; receive the packet. */ 2424 total_len -= ETHER_CRC_LEN; 2425 2426 #ifdef __i386__ 2427 /* 2428 * On the x86 we do not have alignment problems, so try to 2429 * allocate a new buffer for the receive ring, and pass up 2430 * the one where the packet is already, saving the expensive 2431 * copy done in m_devget(). 2432 * If we are on an architecture with alignment problems, or 2433 * if the allocation fails, then use m_devget and leave the 2434 * existing buffer in the receive ring. 2435 */ 2436 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2437 m->m_pkthdr.rcvif = ifp; 2438 m->m_pkthdr.len = m->m_len = total_len; 2439 DC_INC(i, DC_RX_LIST_CNT); 2440 } else 2441 #endif 2442 { 2443 struct mbuf *m0; 2444 2445 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2446 total_len + ETHER_ALIGN, 0, ifp, NULL); 2447 dc_newbuf(sc, i, m); 2448 DC_INC(i, DC_RX_LIST_CNT); 2449 if (m0 == NULL) { 2450 ifp->if_ierrors++; 2451 continue; 2452 } 2453 m_adj(m0, ETHER_ALIGN); 2454 m = m0; 2455 } 2456 2457 ifp->if_ipackets++; 2458 (*ifp->if_input)(ifp, m); 2459 } 2460 2461 sc->dc_cdata.dc_rx_prod = i; 2462 } 2463 2464 /* 2465 * A frame was downloaded to the chip. It's safe for us to clean up 2466 * the list buffers. 2467 */ 2468 2469 static void 2470 dc_txeof(struct dc_softc *sc) 2471 { 2472 struct dc_desc *cur_tx = NULL; 2473 struct ifnet *ifp; 2474 int idx; 2475 2476 ifp = &sc->arpcom.ac_if; 2477 2478 /* 2479 * Go through our tx list and free mbufs for those 2480 * frames that have been transmitted. 2481 */ 2482 idx = sc->dc_cdata.dc_tx_cons; 2483 while(idx != sc->dc_cdata.dc_tx_prod) { 2484 u_int32_t txstat; 2485 2486 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2487 txstat = cur_tx->dc_status; 2488 2489 if (txstat & DC_TXSTAT_OWN) 2490 break; 2491 2492 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2493 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2494 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2495 /* 2496 * Yes, the PNIC is so brain damaged 2497 * that it will sometimes generate a TX 2498 * underrun error while DMAing the RX 2499 * filter setup frame. If we detect this, 2500 * we have to send the setup frame again, 2501 * or else the filter won't be programmed 2502 * correctly. 2503 */ 2504 if (DC_IS_PNIC(sc)) { 2505 if (txstat & DC_TXSTAT_ERRSUM) 2506 dc_setfilt(sc); 2507 } 2508 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2509 } 2510 sc->dc_cdata.dc_tx_cnt--; 2511 DC_INC(idx, DC_TX_LIST_CNT); 2512 continue; 2513 } 2514 2515 if (DC_IS_CONEXANT(sc)) { 2516 /* 2517 * For some reason Conexant chips like 2518 * setting the CARRLOST flag even when 2519 * the carrier is there. In CURRENT we 2520 * have the same problem for Xircom 2521 * cards ! 2522 */ 2523 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2524 sc->dc_pmode == DC_PMODE_MII && 2525 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2526 DC_TXSTAT_NOCARRIER))) 2527 txstat &= ~DC_TXSTAT_ERRSUM; 2528 } else { 2529 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2530 sc->dc_pmode == DC_PMODE_MII && 2531 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2532 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2533 txstat &= ~DC_TXSTAT_ERRSUM; 2534 } 2535 2536 if (txstat & DC_TXSTAT_ERRSUM) { 2537 ifp->if_oerrors++; 2538 if (txstat & DC_TXSTAT_EXCESSCOLL) 2539 ifp->if_collisions++; 2540 if (txstat & DC_TXSTAT_LATECOLL) 2541 ifp->if_collisions++; 2542 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2543 dc_init(sc); 2544 return; 2545 } 2546 } 2547 2548 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2549 2550 ifp->if_opackets++; 2551 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2552 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2553 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2554 } 2555 2556 sc->dc_cdata.dc_tx_cnt--; 2557 DC_INC(idx, DC_TX_LIST_CNT); 2558 } 2559 2560 if (idx != sc->dc_cdata.dc_tx_cons) { 2561 /* some buffers have been freed */ 2562 sc->dc_cdata.dc_tx_cons = idx; 2563 ifp->if_flags &= ~IFF_OACTIVE; 2564 } 2565 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2566 2567 return; 2568 } 2569 2570 static void 2571 dc_tick(void *xsc) 2572 { 2573 struct dc_softc *sc = xsc; 2574 struct ifnet *ifp = &sc->arpcom.ac_if; 2575 struct mii_data *mii; 2576 u_int32_t r; 2577 2578 crit_enter(); 2579 2580 mii = device_get_softc(sc->dc_miibus); 2581 2582 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2583 if (sc->dc_flags & DC_21143_NWAY) { 2584 r = CSR_READ_4(sc, DC_10BTSTAT); 2585 if (IFM_SUBTYPE(mii->mii_media_active) == 2586 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2587 sc->dc_link = 0; 2588 mii_mediachg(mii); 2589 } 2590 if (IFM_SUBTYPE(mii->mii_media_active) == 2591 IFM_10_T && (r & DC_TSTAT_LS10)) { 2592 sc->dc_link = 0; 2593 mii_mediachg(mii); 2594 } 2595 if (sc->dc_link == 0) 2596 mii_tick(mii); 2597 } else { 2598 r = CSR_READ_4(sc, DC_ISR); 2599 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2600 sc->dc_cdata.dc_tx_cnt == 0) { 2601 mii_tick(mii); 2602 if (!(mii->mii_media_status & IFM_ACTIVE)) 2603 sc->dc_link = 0; 2604 } 2605 } 2606 } else 2607 mii_tick(mii); 2608 2609 /* 2610 * When the init routine completes, we expect to be able to send 2611 * packets right away, and in fact the network code will send a 2612 * gratuitous ARP the moment the init routine marks the interface 2613 * as running. However, even though the MAC may have been initialized, 2614 * there may be a delay of a few seconds before the PHY completes 2615 * autonegotiation and the link is brought up. Any transmissions 2616 * made during that delay will be lost. Dealing with this is tricky: 2617 * we can't just pause in the init routine while waiting for the 2618 * PHY to come ready since that would bring the whole system to 2619 * a screeching halt for several seconds. 2620 * 2621 * What we do here is prevent the TX start routine from sending 2622 * any packets until a link has been established. After the 2623 * interface has been initialized, the tick routine will poll 2624 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2625 * that time, packets will stay in the send queue, and once the 2626 * link comes up, they will be flushed out to the wire. 2627 */ 2628 if (!sc->dc_link) { 2629 mii_pollstat(mii); 2630 if (mii->mii_media_status & IFM_ACTIVE && 2631 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2632 sc->dc_link++; 2633 if (!ifq_is_empty(&ifp->if_snd)) 2634 dc_start(ifp); 2635 } 2636 } 2637 2638 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2639 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc); 2640 else 2641 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 2642 2643 crit_exit(); 2644 } 2645 2646 /* 2647 * A transmit underrun has occurred. Back off the transmit threshold, 2648 * or switch to store and forward mode if we have to. 2649 */ 2650 static void 2651 dc_tx_underrun(struct dc_softc *sc) 2652 { 2653 u_int32_t isr; 2654 int i; 2655 2656 if (DC_IS_DAVICOM(sc)) 2657 dc_init(sc); 2658 2659 if (DC_IS_INTEL(sc)) { 2660 /* 2661 * The real 21143 requires that the transmitter be idle 2662 * in order to change the transmit threshold or store 2663 * and forward state. 2664 */ 2665 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2666 2667 for (i = 0; i < DC_TIMEOUT; i++) { 2668 isr = CSR_READ_4(sc, DC_ISR); 2669 if (isr & DC_ISR_TX_IDLE) 2670 break; 2671 DELAY(10); 2672 } 2673 if (i == DC_TIMEOUT) { 2674 if_printf(&sc->arpcom.ac_if, 2675 "failed to force tx to idle state\n"); 2676 dc_init(sc); 2677 } 2678 } 2679 2680 if_printf(&sc->arpcom.ac_if, "TX underrun -- "); 2681 sc->dc_txthresh += DC_TXTHRESH_INC; 2682 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2683 printf("using store and forward mode\n"); 2684 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2685 } else { 2686 printf("increasing TX threshold\n"); 2687 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2688 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2689 } 2690 2691 if (DC_IS_INTEL(sc)) 2692 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2693 2694 return; 2695 } 2696 2697 #ifdef DEVICE_POLLING 2698 2699 static void 2700 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2701 { 2702 struct dc_softc *sc = ifp->if_softc; 2703 u_int32_t status; 2704 2705 switch(cmd) { 2706 case POLL_REGISTER: 2707 /* Disable interrupts */ 2708 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2709 break; 2710 case POLL_DEREGISTER: 2711 /* Re-enable interrupts. */ 2712 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2713 break; 2714 case POLL_ONLY: 2715 sc->rxcycles = count; 2716 dc_rxeof(sc); 2717 dc_txeof(sc); 2718 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2719 dc_start(ifp); 2720 break; 2721 case POLL_AND_CHECK_STATUS: 2722 sc->rxcycles = count; 2723 dc_rxeof(sc); 2724 dc_txeof(sc); 2725 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2726 dc_start(ifp); 2727 status = CSR_READ_4(sc, DC_ISR); 2728 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2729 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2730 DC_ISR_BUS_ERR); 2731 if (!status) 2732 break; 2733 /* ack what we have */ 2734 CSR_WRITE_4(sc, DC_ISR, status); 2735 2736 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2737 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2738 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2739 2740 if (dc_rx_resync(sc)) 2741 dc_rxeof(sc); 2742 } 2743 /* restart transmit unit if necessary */ 2744 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2745 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2746 2747 if (status & DC_ISR_TX_UNDERRUN) 2748 dc_tx_underrun(sc); 2749 2750 if (status & DC_ISR_BUS_ERR) { 2751 if_printf(ifp, "dc_poll: bus error\n"); 2752 dc_reset(sc); 2753 dc_init(sc); 2754 } 2755 break; 2756 } 2757 } 2758 #endif /* DEVICE_POLLING */ 2759 2760 static void 2761 dc_intr(void *arg) 2762 { 2763 struct dc_softc *sc; 2764 struct ifnet *ifp; 2765 u_int32_t status; 2766 2767 sc = arg; 2768 2769 if (sc->suspended) { 2770 return; 2771 } 2772 2773 ifp = &sc->arpcom.ac_if; 2774 2775 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2776 return ; 2777 2778 /* Suppress unwanted interrupts */ 2779 if (!(ifp->if_flags & IFF_UP)) { 2780 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2781 dc_stop(sc); 2782 return; 2783 } 2784 2785 /* Disable interrupts. */ 2786 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2787 2788 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2789 2790 CSR_WRITE_4(sc, DC_ISR, status); 2791 2792 if (status & DC_ISR_RX_OK) { 2793 int curpkts; 2794 curpkts = ifp->if_ipackets; 2795 dc_rxeof(sc); 2796 if (curpkts == ifp->if_ipackets) { 2797 while(dc_rx_resync(sc)) 2798 dc_rxeof(sc); 2799 } 2800 } 2801 2802 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2803 dc_txeof(sc); 2804 2805 if (status & DC_ISR_TX_IDLE) { 2806 dc_txeof(sc); 2807 if (sc->dc_cdata.dc_tx_cnt) { 2808 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2809 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2810 } 2811 } 2812 2813 if (status & DC_ISR_TX_UNDERRUN) 2814 dc_tx_underrun(sc); 2815 2816 if ((status & DC_ISR_RX_WATDOGTIMEO) 2817 || (status & DC_ISR_RX_NOBUF)) { 2818 int curpkts; 2819 curpkts = ifp->if_ipackets; 2820 dc_rxeof(sc); 2821 if (curpkts == ifp->if_ipackets) { 2822 while(dc_rx_resync(sc)) 2823 dc_rxeof(sc); 2824 } 2825 } 2826 2827 if (status & DC_ISR_BUS_ERR) { 2828 dc_reset(sc); 2829 dc_init(sc); 2830 } 2831 } 2832 2833 /* Re-enable interrupts. */ 2834 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2835 2836 if (!ifq_is_empty(&ifp->if_snd)) 2837 dc_start(ifp); 2838 2839 return; 2840 } 2841 2842 /* 2843 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2844 * pointers to the fragment pointers. 2845 */ 2846 static int 2847 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 2848 { 2849 struct dc_desc *f = NULL; 2850 struct mbuf *m; 2851 int frag, cur, cnt = 0; 2852 2853 /* 2854 * Start packing the mbufs in this chain into 2855 * the fragment pointers. Stop when we run out 2856 * of fragments or hit the end of the mbuf chain. 2857 */ 2858 m = m_head; 2859 cur = frag = *txidx; 2860 2861 for (m = m_head; m != NULL; m = m->m_next) { 2862 if (m->m_len != 0) { 2863 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2864 if (*txidx != sc->dc_cdata.dc_tx_prod && 2865 frag == (DC_TX_LIST_CNT - 1)) 2866 return(ENOBUFS); 2867 } 2868 if ((DC_TX_LIST_CNT - 2869 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2870 return(ENOBUFS); 2871 2872 f = &sc->dc_ldata->dc_tx_list[frag]; 2873 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2874 if (cnt == 0) { 2875 f->dc_status = 0; 2876 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2877 } else 2878 f->dc_status = DC_TXSTAT_OWN; 2879 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2880 cur = frag; 2881 DC_INC(frag, DC_TX_LIST_CNT); 2882 cnt++; 2883 } 2884 } 2885 2886 if (m != NULL) 2887 return(ENOBUFS); 2888 2889 sc->dc_cdata.dc_tx_cnt += cnt; 2890 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2891 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2892 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2893 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2894 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2895 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2896 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2897 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2898 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2899 *txidx = frag; 2900 2901 return(0); 2902 } 2903 2904 /* 2905 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2906 * to the mbuf data regions directly in the transmit lists. We also save a 2907 * copy of the pointers since the transmit list fragment pointers are 2908 * physical addresses. 2909 */ 2910 2911 static void 2912 dc_start(struct ifnet *ifp) 2913 { 2914 struct dc_softc *sc; 2915 struct mbuf *m_head = NULL, *m_new; 2916 int did_defrag, idx; 2917 2918 sc = ifp->if_softc; 2919 2920 if (!sc->dc_link) 2921 return; 2922 2923 if (ifp->if_flags & IFF_OACTIVE) 2924 return; 2925 2926 idx = sc->dc_cdata.dc_tx_prod; 2927 2928 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2929 did_defrag = 0; 2930 m_head = ifq_poll(&ifp->if_snd); 2931 if (m_head == NULL) 2932 break; 2933 2934 if (sc->dc_flags & DC_TX_COALESCE && 2935 (m_head->m_next != NULL || 2936 sc->dc_flags & DC_TX_ALIGN)){ 2937 /* 2938 * Check first if coalescing allows us to queue 2939 * the packet. We don't want to loose it if 2940 * the TX queue is full. 2941 */ 2942 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 2943 idx != sc->dc_cdata.dc_tx_prod && 2944 idx == (DC_TX_LIST_CNT - 1)) { 2945 ifp->if_flags |= IFF_OACTIVE; 2946 break; 2947 } 2948 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) { 2949 ifp->if_flags |= IFF_OACTIVE; 2950 break; 2951 } 2952 2953 /* only coalesce if have >1 mbufs */ 2954 m_new = m_defrag_nofree(m_head, MB_DONTWAIT); 2955 if (m_new == NULL) { 2956 ifp->if_flags |= IFF_OACTIVE; 2957 break; 2958 } 2959 m_freem(m_head); 2960 m_head = m_new; 2961 did_defrag = 1; 2962 } 2963 2964 if (dc_encap(sc, m_head, &idx)) { 2965 if (did_defrag) { 2966 m_freem(m_head); 2967 m_new = ifq_dequeue(&ifp->if_snd); 2968 m_freem(m_new); 2969 } 2970 ifp->if_flags |= IFF_OACTIVE; 2971 break; 2972 } 2973 2974 m_new = ifq_dequeue(&ifp->if_snd); 2975 if (did_defrag) 2976 m_freem(m_new); 2977 2978 /* 2979 * If there's a BPF listener, bounce a copy of this frame 2980 * to him. 2981 */ 2982 BPF_MTAP(ifp, m_head); 2983 2984 if (sc->dc_flags & DC_TX_ONE) { 2985 ifp->if_flags |= IFF_OACTIVE; 2986 break; 2987 } 2988 } 2989 2990 /* Transmit */ 2991 sc->dc_cdata.dc_tx_prod = idx; 2992 if (!(sc->dc_flags & DC_TX_POLL)) 2993 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2994 2995 /* 2996 * Set a timeout in case the chip goes out to lunch. 2997 */ 2998 ifp->if_timer = 5; 2999 3000 return; 3001 } 3002 3003 static void 3004 dc_init(void *xsc) 3005 { 3006 struct dc_softc *sc = xsc; 3007 struct ifnet *ifp = &sc->arpcom.ac_if; 3008 struct mii_data *mii; 3009 3010 crit_enter(); 3011 3012 mii = device_get_softc(sc->dc_miibus); 3013 3014 /* 3015 * Cancel pending I/O and free all RX/TX buffers. 3016 */ 3017 dc_stop(sc); 3018 dc_reset(sc); 3019 3020 /* 3021 * Set cache alignment and burst length. 3022 */ 3023 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3024 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3025 else 3026 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3027 /* 3028 * Evenly share the bus between receive and transmit process. 3029 */ 3030 if (DC_IS_INTEL(sc)) 3031 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3032 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3033 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3034 } else { 3035 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3036 } 3037 if (sc->dc_flags & DC_TX_POLL) 3038 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3039 switch(sc->dc_cachesize) { 3040 case 32: 3041 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3042 break; 3043 case 16: 3044 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3045 break; 3046 case 8: 3047 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3048 break; 3049 case 0: 3050 default: 3051 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3052 break; 3053 } 3054 3055 if (sc->dc_flags & DC_TX_STORENFWD) 3056 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3057 else { 3058 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3059 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3060 } else { 3061 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3062 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3063 } 3064 } 3065 3066 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3067 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3068 3069 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3070 /* 3071 * The app notes for the 98713 and 98715A say that 3072 * in order to have the chips operate properly, a magic 3073 * number must be written to CSR16. Macronix does not 3074 * document the meaning of these bits so there's no way 3075 * to know exactly what they do. The 98713 has a magic 3076 * number all its own; the rest all use a different one. 3077 */ 3078 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3079 if (sc->dc_type == DC_TYPE_98713) 3080 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3081 else 3082 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3083 } 3084 3085 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3086 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3087 3088 /* Init circular RX list. */ 3089 if (dc_list_rx_init(sc) == ENOBUFS) { 3090 if_printf(ifp, "initialization failed: no " 3091 "memory for rx buffers\n"); 3092 dc_stop(sc); 3093 crit_exit(); 3094 return; 3095 } 3096 3097 /* 3098 * Init tx descriptors. 3099 */ 3100 dc_list_tx_init(sc); 3101 3102 /* 3103 * Load the address of the RX list. 3104 */ 3105 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3106 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3107 3108 /* 3109 * Enable interrupts. 3110 */ 3111 #ifdef DEVICE_POLLING 3112 /* 3113 * ... but only if we are not polling, and make sure they are off in 3114 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3115 * after a reset. 3116 */ 3117 if (ifp->if_flags & IFF_POLLING) 3118 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3119 else 3120 #endif 3121 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3122 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3123 3124 /* Enable transmitter. */ 3125 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3126 3127 /* 3128 * If this is an Intel 21143 and we're not using the 3129 * MII port, program the LED control pins so we get 3130 * link and activity indications. 3131 */ 3132 if (sc->dc_flags & DC_TULIP_LEDS) { 3133 CSR_WRITE_4(sc, DC_WATCHDOG, 3134 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3135 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3136 } 3137 3138 /* 3139 * Load the RX/multicast filter. We do this sort of late 3140 * because the filter programming scheme on the 21143 and 3141 * some clones requires DMAing a setup frame via the TX 3142 * engine, and we need the transmitter enabled for that. 3143 */ 3144 dc_setfilt(sc); 3145 3146 /* Enable receiver. */ 3147 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3148 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3149 3150 mii_mediachg(mii); 3151 dc_setcfg(sc, sc->dc_if_media); 3152 3153 ifp->if_flags |= IFF_RUNNING; 3154 ifp->if_flags &= ~IFF_OACTIVE; 3155 3156 crit_exit(); 3157 3158 /* Don't start the ticker if this is a homePNA link. */ 3159 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3160 sc->dc_link = 1; 3161 else { 3162 if (sc->dc_flags & DC_21143_NWAY) 3163 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc); 3164 else 3165 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 3166 } 3167 3168 return; 3169 } 3170 3171 /* 3172 * Set media options. 3173 */ 3174 static int 3175 dc_ifmedia_upd(struct ifnet *ifp) 3176 { 3177 struct dc_softc *sc; 3178 struct mii_data *mii; 3179 struct ifmedia *ifm; 3180 3181 sc = ifp->if_softc; 3182 mii = device_get_softc(sc->dc_miibus); 3183 mii_mediachg(mii); 3184 ifm = &mii->mii_media; 3185 3186 if (DC_IS_DAVICOM(sc) && 3187 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3188 dc_setcfg(sc, ifm->ifm_media); 3189 else 3190 sc->dc_link = 0; 3191 3192 return(0); 3193 } 3194 3195 /* 3196 * Report current media status. 3197 */ 3198 static void 3199 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3200 { 3201 struct dc_softc *sc; 3202 struct mii_data *mii; 3203 struct ifmedia *ifm; 3204 3205 sc = ifp->if_softc; 3206 mii = device_get_softc(sc->dc_miibus); 3207 mii_pollstat(mii); 3208 ifm = &mii->mii_media; 3209 if (DC_IS_DAVICOM(sc)) { 3210 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3211 ifmr->ifm_active = ifm->ifm_media; 3212 ifmr->ifm_status = 0; 3213 return; 3214 } 3215 } 3216 ifmr->ifm_active = mii->mii_media_active; 3217 ifmr->ifm_status = mii->mii_media_status; 3218 3219 return; 3220 } 3221 3222 static int 3223 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3224 { 3225 struct dc_softc *sc = ifp->if_softc; 3226 struct ifreq *ifr = (struct ifreq *) data; 3227 struct mii_data *mii; 3228 int error = 0; 3229 3230 crit_enter(); 3231 3232 switch(command) { 3233 case SIOCSIFFLAGS: 3234 if (ifp->if_flags & IFF_UP) { 3235 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3236 (IFF_PROMISC | IFF_ALLMULTI); 3237 if (ifp->if_flags & IFF_RUNNING) { 3238 if (need_setfilt) 3239 dc_setfilt(sc); 3240 } else { 3241 sc->dc_txthresh = 0; 3242 dc_init(sc); 3243 } 3244 } else { 3245 if (ifp->if_flags & IFF_RUNNING) 3246 dc_stop(sc); 3247 } 3248 sc->dc_if_flags = ifp->if_flags; 3249 error = 0; 3250 break; 3251 case SIOCADDMULTI: 3252 case SIOCDELMULTI: 3253 dc_setfilt(sc); 3254 error = 0; 3255 break; 3256 case SIOCGIFMEDIA: 3257 case SIOCSIFMEDIA: 3258 mii = device_get_softc(sc->dc_miibus); 3259 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3260 break; 3261 default: 3262 error = ether_ioctl(ifp, command, data); 3263 break; 3264 } 3265 3266 crit_exit(); 3267 3268 return(error); 3269 } 3270 3271 static void 3272 dc_watchdog(struct ifnet *ifp) 3273 { 3274 struct dc_softc *sc; 3275 3276 sc = ifp->if_softc; 3277 3278 ifp->if_oerrors++; 3279 if_printf(ifp, "watchdog timeout\n"); 3280 3281 dc_stop(sc); 3282 dc_reset(sc); 3283 dc_init(sc); 3284 3285 if (!ifq_is_empty(&ifp->if_snd)) 3286 dc_start(ifp); 3287 3288 return; 3289 } 3290 3291 /* 3292 * Stop the adapter and free any mbufs allocated to the 3293 * RX and TX lists. 3294 */ 3295 static void 3296 dc_stop(struct dc_softc *sc) 3297 { 3298 int i; 3299 struct ifnet *ifp; 3300 3301 ifp = &sc->arpcom.ac_if; 3302 ifp->if_timer = 0; 3303 3304 callout_stop(&sc->dc_stat_timer); 3305 3306 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3307 3308 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3309 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3310 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3311 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3312 sc->dc_link = 0; 3313 3314 /* 3315 * Free data in the RX lists. 3316 */ 3317 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3318 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3319 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3320 sc->dc_cdata.dc_rx_chain[i] = NULL; 3321 } 3322 } 3323 bzero((char *)&sc->dc_ldata->dc_rx_list, 3324 sizeof(sc->dc_ldata->dc_rx_list)); 3325 3326 /* 3327 * Free the TX list buffers. 3328 */ 3329 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3330 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3331 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl & 3332 DC_TXCTL_SETUP) || 3333 !(sc->dc_ldata->dc_tx_list[i].dc_ctl & 3334 DC_TXCTL_LASTFRAG)) { 3335 sc->dc_cdata.dc_tx_chain[i] = NULL; 3336 continue; 3337 } 3338 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3339 sc->dc_cdata.dc_tx_chain[i] = NULL; 3340 } 3341 } 3342 3343 bzero((char *)&sc->dc_ldata->dc_tx_list, 3344 sizeof(sc->dc_ldata->dc_tx_list)); 3345 3346 return; 3347 } 3348 3349 /* 3350 * Stop all chip I/O so that the kernel's probe routines don't 3351 * get confused by errant DMAs when rebooting. 3352 */ 3353 static void 3354 dc_shutdown(device_t dev) 3355 { 3356 struct dc_softc *sc; 3357 3358 sc = device_get_softc(dev); 3359 3360 dc_stop(sc); 3361 3362 return; 3363 } 3364 3365 /* 3366 * Device suspend routine. Stop the interface and save some PCI 3367 * settings in case the BIOS doesn't restore them properly on 3368 * resume. 3369 */ 3370 static int 3371 dc_suspend(device_t dev) 3372 { 3373 struct dc_softc *sc = device_get_softc(dev); 3374 int i; 3375 3376 crit_enter(); 3377 3378 dc_stop(sc); 3379 3380 for (i = 0; i < 5; i++) 3381 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3382 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3383 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3384 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3385 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3386 3387 sc->suspended = 1; 3388 3389 crit_exit(); 3390 return (0); 3391 } 3392 3393 /* 3394 * Device resume routine. Restore some PCI settings in case the BIOS 3395 * doesn't, re-enable busmastering, and restart the interface if 3396 * appropriate. 3397 */ 3398 static int 3399 dc_resume(device_t dev) 3400 { 3401 struct dc_softc *sc = device_get_softc(dev); 3402 struct ifnet *ifp = &sc->arpcom.ac_if; 3403 int i; 3404 3405 crit_enter(); 3406 3407 dc_acpi(dev); 3408 3409 /* better way to do this? */ 3410 for (i = 0; i < 5; i++) 3411 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3412 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3413 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3414 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3415 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3416 3417 /* reenable busmastering */ 3418 pci_enable_busmaster(dev); 3419 pci_enable_io(dev, DC_RES); 3420 3421 /* reinitialize interface if necessary */ 3422 if (ifp->if_flags & IFF_UP) 3423 dc_init(sc); 3424 3425 sc->suspended = 0; 3426 3427 crit_exit(); 3428 return (0); 3429 } 3430