1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.24 2005/05/05 22:57:44 swildner Exp $ 34 */ 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 48 * Accton EN1217 (www.accton.com) 49 * Conexant LANfinity (www.conexant.com) 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/sysctl.h> 99 100 #include <net/if.h> 101 #include <net/ifq_var.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_types.h> 107 #include <net/vlan/if_vlan_var.h> 108 109 #include <net/bpf.h> 110 111 #include <vm/vm.h> /* for vtophys */ 112 #include <vm/pmap.h> /* for vtophys */ 113 #include <machine/clock.h> /* for DELAY */ 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include "../mii_layer/mii.h" 122 #include "../mii_layer/miivar.h" 123 124 #include <bus/pci/pcireg.h> 125 #include <bus/pci/pcivar.h> 126 127 #define DC_USEIOSPACE 128 129 #include "if_dcreg.h" 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 /* 135 * Various supported device vendors/types and their names. 136 */ 137 static struct dc_type dc_devs[] = { 138 { DC_VENDORID_DEC, DC_DEVICEID_21143, 139 "Intel 21143 10/100BaseTX" }, 140 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 141 "Davicom DM9009 10/100BaseTX" }, 142 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 143 "Davicom DM9100 10/100BaseTX" }, 144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 145 "Davicom DM9102 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 147 "Davicom DM9102A 10/100BaseTX" }, 148 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 149 "ADMtek AL981 10/100BaseTX" }, 150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 151 "ADMtek AN985 10/100BaseTX" }, 152 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 153 "ASIX AX88140A 10/100BaseTX" }, 154 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 155 "ASIX AX88141 10/100BaseTX" }, 156 { DC_VENDORID_MX, DC_DEVICEID_98713, 157 "Macronix 98713 10/100BaseTX" }, 158 { DC_VENDORID_MX, DC_DEVICEID_98713, 159 "Macronix 98713A 10/100BaseTX" }, 160 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 161 "Compex RL100-TX 10/100BaseTX" }, 162 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 163 "Compex RL100-TX 10/100BaseTX" }, 164 { DC_VENDORID_MX, DC_DEVICEID_987x5, 165 "Macronix 98715/98715A 10/100BaseTX" }, 166 { DC_VENDORID_MX, DC_DEVICEID_987x5, 167 "Macronix 98715AEC-C 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_987x5, 169 "Macronix 98725 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_98727, 171 "Macronix 98727/98732 10/100BaseTX" }, 172 { DC_VENDORID_LO, DC_DEVICEID_82C115, 173 "LC82C115 PNIC II 10/100BaseTX" }, 174 { DC_VENDORID_LO, DC_DEVICEID_82C168, 175 "82c168 PNIC 10/100BaseTX" }, 176 { DC_VENDORID_LO, DC_DEVICEID_82C168, 177 "82c169 PNIC 10/100BaseTX" }, 178 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 179 "Accton EN1217 10/100BaseTX" }, 180 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 181 "Accton EN2242 MiniPCI 10/100BaseTX" }, 182 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 183 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 184 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 185 "3Com OfficeConnect 10/100B" }, 186 { 0, 0, NULL } 187 }; 188 189 static int dc_probe (device_t); 190 static int dc_attach (device_t); 191 static int dc_detach (device_t); 192 static int dc_suspend (device_t); 193 static int dc_resume (device_t); 194 static void dc_acpi (device_t); 195 static struct dc_type *dc_devtype (device_t); 196 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 197 static int dc_encap (struct dc_softc *, struct mbuf *, 198 u_int32_t *); 199 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 200 static int dc_rx_resync (struct dc_softc *); 201 static void dc_rxeof (struct dc_softc *); 202 static void dc_txeof (struct dc_softc *); 203 static void dc_tick (void *); 204 static void dc_tx_underrun (struct dc_softc *); 205 static void dc_intr (void *); 206 static void dc_start (struct ifnet *); 207 static int dc_ioctl (struct ifnet *, u_long, caddr_t, 208 struct ucred *); 209 static void dc_init (void *); 210 static void dc_stop (struct dc_softc *); 211 static void dc_watchdog (struct ifnet *); 212 static void dc_shutdown (device_t); 213 static int dc_ifmedia_upd (struct ifnet *); 214 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 215 216 static void dc_delay (struct dc_softc *); 217 static void dc_eeprom_idle (struct dc_softc *); 218 static void dc_eeprom_putbyte (struct dc_softc *, int); 219 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 220 static void dc_eeprom_getword_pnic 221 (struct dc_softc *, int, u_int16_t *); 222 static void dc_eeprom_width (struct dc_softc *); 223 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, 224 int, int); 225 226 static void dc_mii_writebit (struct dc_softc *, int); 227 static int dc_mii_readbit (struct dc_softc *); 228 static void dc_mii_sync (struct dc_softc *); 229 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 230 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 231 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 232 static int dc_miibus_readreg (device_t, int, int); 233 static int dc_miibus_writereg (device_t, int, int, int); 234 static void dc_miibus_statchg (device_t); 235 static void dc_miibus_mediainit (device_t); 236 237 static void dc_setcfg (struct dc_softc *, int); 238 static u_int32_t dc_crc_le (struct dc_softc *, c_caddr_t); 239 static u_int32_t dc_crc_be (caddr_t); 240 static void dc_setfilt_21143 (struct dc_softc *); 241 static void dc_setfilt_asix (struct dc_softc *); 242 static void dc_setfilt_admtek (struct dc_softc *); 243 244 static void dc_setfilt (struct dc_softc *); 245 246 static void dc_reset (struct dc_softc *); 247 static int dc_list_rx_init (struct dc_softc *); 248 static int dc_list_tx_init (struct dc_softc *); 249 250 static void dc_read_srom (struct dc_softc *, int); 251 static void dc_parse_21143_srom (struct dc_softc *); 252 static void dc_decode_leaf_sia (struct dc_softc *, 253 struct dc_eblock_sia *); 254 static void dc_decode_leaf_mii (struct dc_softc *, 255 struct dc_eblock_mii *); 256 static void dc_decode_leaf_sym (struct dc_softc *, 257 struct dc_eblock_sym *); 258 static void dc_apply_fixup (struct dc_softc *, int); 259 260 #ifdef DC_USEIOSPACE 261 #define DC_RES SYS_RES_IOPORT 262 #define DC_RID DC_PCI_CFBIO 263 #else 264 #define DC_RES SYS_RES_MEMORY 265 #define DC_RID DC_PCI_CFBMA 266 #endif 267 268 static device_method_t dc_methods[] = { 269 /* Device interface */ 270 DEVMETHOD(device_probe, dc_probe), 271 DEVMETHOD(device_attach, dc_attach), 272 DEVMETHOD(device_detach, dc_detach), 273 DEVMETHOD(device_suspend, dc_suspend), 274 DEVMETHOD(device_resume, dc_resume), 275 DEVMETHOD(device_shutdown, dc_shutdown), 276 277 /* bus interface */ 278 DEVMETHOD(bus_print_child, bus_generic_print_child), 279 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 280 281 /* MII interface */ 282 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 283 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 284 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 285 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 286 287 { 0, 0 } 288 }; 289 290 static driver_t dc_driver = { 291 "dc", 292 dc_methods, 293 sizeof(struct dc_softc) 294 }; 295 296 static devclass_t dc_devclass; 297 298 #ifdef __i386__ 299 static int dc_quick=1; 300 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 301 &dc_quick,0,"do not mdevget in dc driver"); 302 #endif 303 304 DECLARE_DUMMY_MODULE(if_dc); 305 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 306 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 307 308 #define DC_SETBIT(sc, reg, x) \ 309 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 310 311 #define DC_CLRBIT(sc, reg, x) \ 312 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 313 314 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 315 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 316 317 static void dc_delay(sc) 318 struct dc_softc *sc; 319 { 320 int idx; 321 322 for (idx = (300 / 33) + 1; idx > 0; idx--) 323 CSR_READ_4(sc, DC_BUSCTL); 324 } 325 326 static void dc_eeprom_width(sc) 327 struct dc_softc *sc; 328 { 329 int i; 330 331 /* Force EEPROM to idle state. */ 332 dc_eeprom_idle(sc); 333 334 /* Enter EEPROM access mode. */ 335 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 336 dc_delay(sc); 337 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 338 dc_delay(sc); 339 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 340 dc_delay(sc); 341 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 342 dc_delay(sc); 343 344 for (i = 3; i--;) { 345 if (6 & (1 << i)) 346 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 347 else 348 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 349 dc_delay(sc); 350 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 351 dc_delay(sc); 352 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 353 dc_delay(sc); 354 } 355 356 for (i = 1; i <= 12; i++) { 357 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 358 dc_delay(sc); 359 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 360 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 361 dc_delay(sc); 362 break; 363 } 364 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 365 dc_delay(sc); 366 } 367 368 /* Turn off EEPROM access mode. */ 369 dc_eeprom_idle(sc); 370 371 if (i < 4 || i > 12) 372 sc->dc_romwidth = 6; 373 else 374 sc->dc_romwidth = i; 375 376 /* Enter EEPROM access mode. */ 377 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 378 dc_delay(sc); 379 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 380 dc_delay(sc); 381 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 382 dc_delay(sc); 383 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 384 dc_delay(sc); 385 386 /* Turn off EEPROM access mode. */ 387 dc_eeprom_idle(sc); 388 } 389 390 static void dc_eeprom_idle(sc) 391 struct dc_softc *sc; 392 { 393 int i; 394 395 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 396 dc_delay(sc); 397 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 398 dc_delay(sc); 399 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 400 dc_delay(sc); 401 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 402 dc_delay(sc); 403 404 for (i = 0; i < 25; i++) { 405 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 406 dc_delay(sc); 407 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 408 dc_delay(sc); 409 } 410 411 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 412 dc_delay(sc); 413 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 414 dc_delay(sc); 415 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 416 417 return; 418 } 419 420 /* 421 * Send a read command and address to the EEPROM, check for ACK. 422 */ 423 static void dc_eeprom_putbyte(sc, addr) 424 struct dc_softc *sc; 425 int addr; 426 { 427 int d, i; 428 429 d = DC_EECMD_READ >> 6; 430 for (i = 3; i--; ) { 431 if (d & (1 << i)) 432 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 433 else 434 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 435 dc_delay(sc); 436 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 437 dc_delay(sc); 438 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 439 dc_delay(sc); 440 } 441 442 /* 443 * Feed in each bit and strobe the clock. 444 */ 445 for (i = sc->dc_romwidth; i--;) { 446 if (addr & (1 << i)) { 447 SIO_SET(DC_SIO_EE_DATAIN); 448 } else { 449 SIO_CLR(DC_SIO_EE_DATAIN); 450 } 451 dc_delay(sc); 452 SIO_SET(DC_SIO_EE_CLK); 453 dc_delay(sc); 454 SIO_CLR(DC_SIO_EE_CLK); 455 dc_delay(sc); 456 } 457 458 return; 459 } 460 461 /* 462 * Read a word of data stored in the EEPROM at address 'addr.' 463 * The PNIC 82c168/82c169 has its own non-standard way to read 464 * the EEPROM. 465 */ 466 static void dc_eeprom_getword_pnic(sc, addr, dest) 467 struct dc_softc *sc; 468 int addr; 469 u_int16_t *dest; 470 { 471 int i; 472 u_int32_t r; 473 474 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 475 476 for (i = 0; i < DC_TIMEOUT; i++) { 477 DELAY(1); 478 r = CSR_READ_4(sc, DC_SIO); 479 if (!(r & DC_PN_SIOCTL_BUSY)) { 480 *dest = (u_int16_t)(r & 0xFFFF); 481 return; 482 } 483 } 484 485 return; 486 } 487 488 /* 489 * Read a word of data stored in the EEPROM at address 'addr.' 490 */ 491 static void dc_eeprom_getword(sc, addr, dest) 492 struct dc_softc *sc; 493 int addr; 494 u_int16_t *dest; 495 { 496 int i; 497 u_int16_t word = 0; 498 499 /* Force EEPROM to idle state. */ 500 dc_eeprom_idle(sc); 501 502 /* Enter EEPROM access mode. */ 503 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 504 dc_delay(sc); 505 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 506 dc_delay(sc); 507 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 508 dc_delay(sc); 509 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 510 dc_delay(sc); 511 512 /* 513 * Send address of word we want to read. 514 */ 515 dc_eeprom_putbyte(sc, addr); 516 517 /* 518 * Start reading bits from EEPROM. 519 */ 520 for (i = 0x8000; i; i >>= 1) { 521 SIO_SET(DC_SIO_EE_CLK); 522 dc_delay(sc); 523 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 524 word |= i; 525 dc_delay(sc); 526 SIO_CLR(DC_SIO_EE_CLK); 527 dc_delay(sc); 528 } 529 530 /* Turn off EEPROM access mode. */ 531 dc_eeprom_idle(sc); 532 533 *dest = word; 534 535 return; 536 } 537 538 /* 539 * Read a sequence of words from the EEPROM. 540 */ 541 static void dc_read_eeprom(sc, dest, off, cnt, swap) 542 struct dc_softc *sc; 543 caddr_t dest; 544 int off; 545 int cnt; 546 int swap; 547 { 548 int i; 549 u_int16_t word = 0, *ptr; 550 551 for (i = 0; i < cnt; i++) { 552 if (DC_IS_PNIC(sc)) 553 dc_eeprom_getword_pnic(sc, off + i, &word); 554 else 555 dc_eeprom_getword(sc, off + i, &word); 556 ptr = (u_int16_t *)(dest + (i * 2)); 557 if (swap) 558 *ptr = ntohs(word); 559 else 560 *ptr = word; 561 } 562 563 return; 564 } 565 566 /* 567 * The following two routines are taken from the Macronix 98713 568 * Application Notes pp.19-21. 569 */ 570 /* 571 * Write a bit to the MII bus. 572 */ 573 static void dc_mii_writebit(sc, bit) 574 struct dc_softc *sc; 575 int bit; 576 { 577 if (bit) 578 CSR_WRITE_4(sc, DC_SIO, 579 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 580 else 581 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 582 583 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 584 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 585 586 return; 587 } 588 589 /* 590 * Read a bit from the MII bus. 591 */ 592 static int dc_mii_readbit(sc) 593 struct dc_softc *sc; 594 { 595 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 596 CSR_READ_4(sc, DC_SIO); 597 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 598 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 599 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 600 return(1); 601 602 return(0); 603 } 604 605 /* 606 * Sync the PHYs by setting data bit and strobing the clock 32 times. 607 */ 608 static void dc_mii_sync(sc) 609 struct dc_softc *sc; 610 { 611 int i; 612 613 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 614 615 for (i = 0; i < 32; i++) 616 dc_mii_writebit(sc, 1); 617 618 return; 619 } 620 621 /* 622 * Clock a series of bits through the MII. 623 */ 624 static void dc_mii_send(sc, bits, cnt) 625 struct dc_softc *sc; 626 u_int32_t bits; 627 int cnt; 628 { 629 int i; 630 631 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 632 dc_mii_writebit(sc, bits & i); 633 } 634 635 /* 636 * Read an PHY register through the MII. 637 */ 638 static int dc_mii_readreg(sc, frame) 639 struct dc_softc *sc; 640 struct dc_mii_frame *frame; 641 642 { 643 int i, ack, s; 644 645 s = splimp(); 646 647 /* 648 * Set up frame for RX. 649 */ 650 frame->mii_stdelim = DC_MII_STARTDELIM; 651 frame->mii_opcode = DC_MII_READOP; 652 frame->mii_turnaround = 0; 653 frame->mii_data = 0; 654 655 /* 656 * Sync the PHYs. 657 */ 658 dc_mii_sync(sc); 659 660 /* 661 * Send command/address info. 662 */ 663 dc_mii_send(sc, frame->mii_stdelim, 2); 664 dc_mii_send(sc, frame->mii_opcode, 2); 665 dc_mii_send(sc, frame->mii_phyaddr, 5); 666 dc_mii_send(sc, frame->mii_regaddr, 5); 667 668 #ifdef notdef 669 /* Idle bit */ 670 dc_mii_writebit(sc, 1); 671 dc_mii_writebit(sc, 0); 672 #endif 673 674 /* Check for ack */ 675 ack = dc_mii_readbit(sc); 676 677 /* 678 * Now try reading data bits. If the ack failed, we still 679 * need to clock through 16 cycles to keep the PHY(s) in sync. 680 */ 681 if (ack) { 682 for(i = 0; i < 16; i++) { 683 dc_mii_readbit(sc); 684 } 685 goto fail; 686 } 687 688 for (i = 0x8000; i; i >>= 1) { 689 if (!ack) { 690 if (dc_mii_readbit(sc)) 691 frame->mii_data |= i; 692 } 693 } 694 695 fail: 696 697 dc_mii_writebit(sc, 0); 698 dc_mii_writebit(sc, 0); 699 700 splx(s); 701 702 if (ack) 703 return(1); 704 return(0); 705 } 706 707 /* 708 * Write to a PHY register through the MII. 709 */ 710 static int dc_mii_writereg(sc, frame) 711 struct dc_softc *sc; 712 struct dc_mii_frame *frame; 713 714 { 715 int s; 716 717 s = splimp(); 718 /* 719 * Set up frame for TX. 720 */ 721 722 frame->mii_stdelim = DC_MII_STARTDELIM; 723 frame->mii_opcode = DC_MII_WRITEOP; 724 frame->mii_turnaround = DC_MII_TURNAROUND; 725 726 /* 727 * Sync the PHYs. 728 */ 729 dc_mii_sync(sc); 730 731 dc_mii_send(sc, frame->mii_stdelim, 2); 732 dc_mii_send(sc, frame->mii_opcode, 2); 733 dc_mii_send(sc, frame->mii_phyaddr, 5); 734 dc_mii_send(sc, frame->mii_regaddr, 5); 735 dc_mii_send(sc, frame->mii_turnaround, 2); 736 dc_mii_send(sc, frame->mii_data, 16); 737 738 /* Idle bit. */ 739 dc_mii_writebit(sc, 0); 740 dc_mii_writebit(sc, 0); 741 742 splx(s); 743 744 return(0); 745 } 746 747 static int dc_miibus_readreg(dev, phy, reg) 748 device_t dev; 749 int phy, reg; 750 { 751 struct dc_mii_frame frame; 752 struct dc_softc *sc; 753 int i, rval, phy_reg = 0; 754 755 sc = device_get_softc(dev); 756 bzero((char *)&frame, sizeof(frame)); 757 758 /* 759 * Note: both the AL981 and AN985 have internal PHYs, 760 * however the AL981 provides direct access to the PHY 761 * registers while the AN985 uses a serial MII interface. 762 * The AN985's MII interface is also buggy in that you 763 * can read from any MII address (0 to 31), but only address 1 764 * behaves normally. To deal with both cases, we pretend 765 * that the PHY is at MII address 1. 766 */ 767 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 768 return(0); 769 770 /* 771 * Note: the ukphy probes of the RS7112 report a PHY at 772 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 773 * so we only respond to correct one. 774 */ 775 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 776 return(0); 777 778 if (sc->dc_pmode != DC_PMODE_MII) { 779 if (phy == (MII_NPHY - 1)) { 780 switch(reg) { 781 case MII_BMSR: 782 /* 783 * Fake something to make the probe 784 * code think there's a PHY here. 785 */ 786 return(BMSR_MEDIAMASK); 787 break; 788 case MII_PHYIDR1: 789 if (DC_IS_PNIC(sc)) 790 return(DC_VENDORID_LO); 791 return(DC_VENDORID_DEC); 792 break; 793 case MII_PHYIDR2: 794 if (DC_IS_PNIC(sc)) 795 return(DC_DEVICEID_82C168); 796 return(DC_DEVICEID_21143); 797 break; 798 default: 799 return(0); 800 break; 801 } 802 } else 803 return(0); 804 } 805 806 if (DC_IS_PNIC(sc)) { 807 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 808 (phy << 23) | (reg << 18)); 809 for (i = 0; i < DC_TIMEOUT; i++) { 810 DELAY(1); 811 rval = CSR_READ_4(sc, DC_PN_MII); 812 if (!(rval & DC_PN_MII_BUSY)) { 813 rval &= 0xFFFF; 814 return(rval == 0xFFFF ? 0 : rval); 815 } 816 } 817 return(0); 818 } 819 820 if (DC_IS_COMET(sc)) { 821 switch(reg) { 822 case MII_BMCR: 823 phy_reg = DC_AL_BMCR; 824 break; 825 case MII_BMSR: 826 phy_reg = DC_AL_BMSR; 827 break; 828 case MII_PHYIDR1: 829 phy_reg = DC_AL_VENID; 830 break; 831 case MII_PHYIDR2: 832 phy_reg = DC_AL_DEVID; 833 break; 834 case MII_ANAR: 835 phy_reg = DC_AL_ANAR; 836 break; 837 case MII_ANLPAR: 838 phy_reg = DC_AL_LPAR; 839 break; 840 case MII_ANER: 841 phy_reg = DC_AL_ANER; 842 break; 843 default: 844 printf("dc%d: phy_read: bad phy register %x\n", 845 sc->dc_unit, reg); 846 return(0); 847 break; 848 } 849 850 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 851 852 if (rval == 0xFFFF) 853 return(0); 854 return(rval); 855 } 856 857 frame.mii_phyaddr = phy; 858 frame.mii_regaddr = reg; 859 if (sc->dc_type == DC_TYPE_98713) { 860 phy_reg = CSR_READ_4(sc, DC_NETCFG); 861 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 862 } 863 dc_mii_readreg(sc, &frame); 864 if (sc->dc_type == DC_TYPE_98713) 865 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 866 867 return(frame.mii_data); 868 } 869 870 static int dc_miibus_writereg(dev, phy, reg, data) 871 device_t dev; 872 int phy, reg, data; 873 { 874 struct dc_softc *sc; 875 struct dc_mii_frame frame; 876 int i, phy_reg = 0; 877 878 sc = device_get_softc(dev); 879 bzero((char *)&frame, sizeof(frame)); 880 881 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 882 return(0); 883 884 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 885 return(0); 886 887 if (DC_IS_PNIC(sc)) { 888 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 889 (phy << 23) | (reg << 10) | data); 890 for (i = 0; i < DC_TIMEOUT; i++) { 891 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 892 break; 893 } 894 return(0); 895 } 896 897 if (DC_IS_COMET(sc)) { 898 switch(reg) { 899 case MII_BMCR: 900 phy_reg = DC_AL_BMCR; 901 break; 902 case MII_BMSR: 903 phy_reg = DC_AL_BMSR; 904 break; 905 case MII_PHYIDR1: 906 phy_reg = DC_AL_VENID; 907 break; 908 case MII_PHYIDR2: 909 phy_reg = DC_AL_DEVID; 910 break; 911 case MII_ANAR: 912 phy_reg = DC_AL_ANAR; 913 break; 914 case MII_ANLPAR: 915 phy_reg = DC_AL_LPAR; 916 break; 917 case MII_ANER: 918 phy_reg = DC_AL_ANER; 919 break; 920 default: 921 printf("dc%d: phy_write: bad phy register %x\n", 922 sc->dc_unit, reg); 923 return(0); 924 break; 925 } 926 927 CSR_WRITE_4(sc, phy_reg, data); 928 return(0); 929 } 930 931 frame.mii_phyaddr = phy; 932 frame.mii_regaddr = reg; 933 frame.mii_data = data; 934 935 if (sc->dc_type == DC_TYPE_98713) { 936 phy_reg = CSR_READ_4(sc, DC_NETCFG); 937 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 938 } 939 dc_mii_writereg(sc, &frame); 940 if (sc->dc_type == DC_TYPE_98713) 941 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 942 943 return(0); 944 } 945 946 static void dc_miibus_statchg(dev) 947 device_t dev; 948 { 949 struct dc_softc *sc; 950 struct mii_data *mii; 951 struct ifmedia *ifm; 952 953 sc = device_get_softc(dev); 954 if (DC_IS_ADMTEK(sc)) 955 return; 956 957 mii = device_get_softc(sc->dc_miibus); 958 ifm = &mii->mii_media; 959 if (DC_IS_DAVICOM(sc) && 960 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 961 dc_setcfg(sc, ifm->ifm_media); 962 sc->dc_if_media = ifm->ifm_media; 963 } else { 964 dc_setcfg(sc, mii->mii_media_active); 965 sc->dc_if_media = mii->mii_media_active; 966 } 967 968 return; 969 } 970 971 /* 972 * Special support for DM9102A cards with HomePNA PHYs. Note: 973 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 974 * to be impossible to talk to the management interface of the DM9801 975 * PHY (its MDIO pin is not connected to anything). Consequently, 976 * the driver has to just 'know' about the additional mode and deal 977 * with it itself. *sigh* 978 */ 979 static void dc_miibus_mediainit(dev) 980 device_t dev; 981 { 982 struct dc_softc *sc; 983 struct mii_data *mii; 984 struct ifmedia *ifm; 985 int rev; 986 987 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 988 989 sc = device_get_softc(dev); 990 mii = device_get_softc(sc->dc_miibus); 991 ifm = &mii->mii_media; 992 993 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 994 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 995 996 return; 997 } 998 999 #define DC_POLY 0xEDB88320 1000 #define DC_BITS_512 9 1001 #define DC_BITS_128 7 1002 #define DC_BITS_64 6 1003 1004 static u_int32_t dc_crc_le(sc, addr) 1005 struct dc_softc *sc; 1006 c_caddr_t addr; 1007 { 1008 u_int32_t idx, bit, data, crc; 1009 1010 /* Compute CRC for the address value. */ 1011 crc = 0xFFFFFFFF; /* initial value */ 1012 1013 for (idx = 0; idx < 6; idx++) { 1014 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1015 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1016 } 1017 1018 /* 1019 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1020 * chips is only 128 bits wide. 1021 */ 1022 if (sc->dc_flags & DC_128BIT_HASH) 1023 return (crc & ((1 << DC_BITS_128) - 1)); 1024 1025 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1026 if (sc->dc_flags & DC_64BIT_HASH) 1027 return (crc & ((1 << DC_BITS_64) - 1)); 1028 1029 return (crc & ((1 << DC_BITS_512) - 1)); 1030 } 1031 1032 /* 1033 * Calculate CRC of a multicast group address, return the lower 6 bits. 1034 */ 1035 static u_int32_t dc_crc_be(addr) 1036 caddr_t addr; 1037 { 1038 u_int32_t crc, carry; 1039 int i, j; 1040 u_int8_t c; 1041 1042 /* Compute CRC for the address value. */ 1043 crc = 0xFFFFFFFF; /* initial value */ 1044 1045 for (i = 0; i < 6; i++) { 1046 c = *(addr + i); 1047 for (j = 0; j < 8; j++) { 1048 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1049 crc <<= 1; 1050 c >>= 1; 1051 if (carry) 1052 crc = (crc ^ 0x04c11db6) | carry; 1053 } 1054 } 1055 1056 /* return the filter bit position */ 1057 return((crc >> 26) & 0x0000003F); 1058 } 1059 1060 /* 1061 * 21143-style RX filter setup routine. Filter programming is done by 1062 * downloading a special setup frame into the TX engine. 21143, Macronix, 1063 * PNIC, PNIC II and Davicom chips are programmed this way. 1064 * 1065 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1066 * address (our node address) and a 512-bit hash filter for multicast 1067 * frames. We also sneak the broadcast address into the hash filter since 1068 * we need that too. 1069 */ 1070 void dc_setfilt_21143(sc) 1071 struct dc_softc *sc; 1072 { 1073 struct dc_desc *sframe; 1074 u_int32_t h, *sp; 1075 struct ifmultiaddr *ifma; 1076 struct ifnet *ifp; 1077 int i; 1078 1079 ifp = &sc->arpcom.ac_if; 1080 1081 i = sc->dc_cdata.dc_tx_prod; 1082 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1083 sc->dc_cdata.dc_tx_cnt++; 1084 sframe = &sc->dc_ldata->dc_tx_list[i]; 1085 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1086 bzero((char *)sp, DC_SFRAME_LEN); 1087 1088 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1089 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1090 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1091 1092 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1093 1094 /* If we want promiscuous mode, set the allframes bit. */ 1095 if (ifp->if_flags & IFF_PROMISC) 1096 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1097 else 1098 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1099 1100 if (ifp->if_flags & IFF_ALLMULTI) 1101 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1102 else 1103 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1104 1105 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1106 ifma = ifma->ifma_link.le_next) { 1107 if (ifma->ifma_addr->sa_family != AF_LINK) 1108 continue; 1109 h = dc_crc_le(sc, 1110 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1111 sp[h >> 4] |= 1 << (h & 0xF); 1112 } 1113 1114 if (ifp->if_flags & IFF_BROADCAST) { 1115 h = dc_crc_le(sc, ifp->if_broadcastaddr); 1116 sp[h >> 4] |= 1 << (h & 0xF); 1117 } 1118 1119 /* Set our MAC address */ 1120 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1121 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1122 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1123 1124 sframe->dc_status = DC_TXSTAT_OWN; 1125 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1126 1127 /* 1128 * The PNIC takes an exceedingly long time to process its 1129 * setup frame; wait 10ms after posting the setup frame 1130 * before proceeding, just so it has time to swallow its 1131 * medicine. 1132 */ 1133 DELAY(10000); 1134 1135 ifp->if_timer = 5; 1136 1137 return; 1138 } 1139 1140 void dc_setfilt_admtek(sc) 1141 struct dc_softc *sc; 1142 { 1143 struct ifnet *ifp; 1144 int h = 0; 1145 u_int32_t hashes[2] = { 0, 0 }; 1146 struct ifmultiaddr *ifma; 1147 1148 ifp = &sc->arpcom.ac_if; 1149 1150 /* Init our MAC address */ 1151 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1152 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1153 1154 /* If we want promiscuous mode, set the allframes bit. */ 1155 if (ifp->if_flags & IFF_PROMISC) 1156 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1157 else 1158 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1159 1160 if (ifp->if_flags & IFF_ALLMULTI) 1161 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1162 else 1163 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1164 1165 /* first, zot all the existing hash bits */ 1166 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1167 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1168 1169 /* 1170 * If we're already in promisc or allmulti mode, we 1171 * don't have to bother programming the multicast filter. 1172 */ 1173 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1174 return; 1175 1176 /* now program new ones */ 1177 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1178 ifma = ifma->ifma_link.le_next) { 1179 if (ifma->ifma_addr->sa_family != AF_LINK) 1180 continue; 1181 if (DC_IS_CENTAUR(sc)) 1182 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1183 else 1184 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1185 if (h < 32) 1186 hashes[0] |= (1 << h); 1187 else 1188 hashes[1] |= (1 << (h - 32)); 1189 } 1190 1191 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1192 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1193 1194 return; 1195 } 1196 1197 void dc_setfilt_asix(sc) 1198 struct dc_softc *sc; 1199 { 1200 struct ifnet *ifp; 1201 int h = 0; 1202 u_int32_t hashes[2] = { 0, 0 }; 1203 struct ifmultiaddr *ifma; 1204 1205 ifp = &sc->arpcom.ac_if; 1206 1207 /* Init our MAC address */ 1208 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1209 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1210 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1211 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1212 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1213 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1214 1215 /* If we want promiscuous mode, set the allframes bit. */ 1216 if (ifp->if_flags & IFF_PROMISC) 1217 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1218 else 1219 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1220 1221 if (ifp->if_flags & IFF_ALLMULTI) 1222 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1223 else 1224 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1225 1226 /* 1227 * The ASIX chip has a special bit to enable reception 1228 * of broadcast frames. 1229 */ 1230 if (ifp->if_flags & IFF_BROADCAST) 1231 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1232 else 1233 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1234 1235 /* first, zot all the existing hash bits */ 1236 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1237 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1238 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1239 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1240 1241 /* 1242 * If we're already in promisc or allmulti mode, we 1243 * don't have to bother programming the multicast filter. 1244 */ 1245 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1246 return; 1247 1248 /* now program new ones */ 1249 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1250 ifma = ifma->ifma_link.le_next) { 1251 if (ifma->ifma_addr->sa_family != AF_LINK) 1252 continue; 1253 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1254 if (h < 32) 1255 hashes[0] |= (1 << h); 1256 else 1257 hashes[1] |= (1 << (h - 32)); 1258 } 1259 1260 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1261 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1262 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1263 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1264 1265 return; 1266 } 1267 1268 static void dc_setfilt(sc) 1269 struct dc_softc *sc; 1270 { 1271 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1272 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1273 dc_setfilt_21143(sc); 1274 1275 if (DC_IS_ASIX(sc)) 1276 dc_setfilt_asix(sc); 1277 1278 if (DC_IS_ADMTEK(sc)) 1279 dc_setfilt_admtek(sc); 1280 1281 return; 1282 } 1283 1284 /* 1285 * In order to fiddle with the 1286 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1287 * first have to put the transmit and/or receive logic in the idle state. 1288 */ 1289 static void dc_setcfg(sc, media) 1290 struct dc_softc *sc; 1291 int media; 1292 { 1293 int i, restart = 0; 1294 u_int32_t isr; 1295 1296 if (IFM_SUBTYPE(media) == IFM_NONE) 1297 return; 1298 1299 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1300 restart = 1; 1301 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1302 1303 for (i = 0; i < DC_TIMEOUT; i++) { 1304 isr = CSR_READ_4(sc, DC_ISR); 1305 if (isr & DC_ISR_TX_IDLE || 1306 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1307 break; 1308 DELAY(10); 1309 } 1310 1311 if (i == DC_TIMEOUT) 1312 printf("dc%d: failed to force tx and " 1313 "rx to idle state\n", sc->dc_unit); 1314 } 1315 1316 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1317 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1318 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1319 if (sc->dc_pmode == DC_PMODE_MII) { 1320 int watchdogreg; 1321 1322 if (DC_IS_INTEL(sc)) { 1323 /* there's a write enable bit here that reads as 1 */ 1324 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1325 watchdogreg &= ~DC_WDOG_CTLWREN; 1326 watchdogreg |= DC_WDOG_JABBERDIS; 1327 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1328 } else { 1329 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1330 } 1331 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1332 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1333 if (sc->dc_type == DC_TYPE_98713) 1334 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1335 DC_NETCFG_SCRAMBLER)); 1336 if (!DC_IS_DAVICOM(sc)) 1337 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1338 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1339 if (DC_IS_INTEL(sc)) 1340 dc_apply_fixup(sc, IFM_AUTO); 1341 } else { 1342 if (DC_IS_PNIC(sc)) { 1343 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1344 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1345 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1346 } 1347 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1348 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1349 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1350 if (DC_IS_INTEL(sc)) 1351 dc_apply_fixup(sc, 1352 (media & IFM_GMASK) == IFM_FDX ? 1353 IFM_100_TX|IFM_FDX : IFM_100_TX); 1354 } 1355 } 1356 1357 if (IFM_SUBTYPE(media) == IFM_10_T) { 1358 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1359 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1360 if (sc->dc_pmode == DC_PMODE_MII) { 1361 int watchdogreg; 1362 1363 /* there's a write enable bit here that reads as 1 */ 1364 if (DC_IS_INTEL(sc)) { 1365 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1366 watchdogreg &= ~DC_WDOG_CTLWREN; 1367 watchdogreg |= DC_WDOG_JABBERDIS; 1368 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1369 } else { 1370 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1371 } 1372 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1373 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1374 if (sc->dc_type == DC_TYPE_98713) 1375 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1376 if (!DC_IS_DAVICOM(sc)) 1377 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1378 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1379 if (DC_IS_INTEL(sc)) 1380 dc_apply_fixup(sc, IFM_AUTO); 1381 } else { 1382 if (DC_IS_PNIC(sc)) { 1383 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1384 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1385 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1386 } 1387 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1388 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1389 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1390 if (DC_IS_INTEL(sc)) { 1391 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1392 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1393 if ((media & IFM_GMASK) == IFM_FDX) 1394 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1395 else 1396 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1397 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1398 DC_CLRBIT(sc, DC_10BTCTRL, 1399 DC_TCTL_AUTONEGENBL); 1400 dc_apply_fixup(sc, 1401 (media & IFM_GMASK) == IFM_FDX ? 1402 IFM_10_T|IFM_FDX : IFM_10_T); 1403 DELAY(20000); 1404 } 1405 } 1406 } 1407 1408 /* 1409 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1410 * PHY and we want HomePNA mode, set the portsel bit to turn 1411 * on the external MII port. 1412 */ 1413 if (DC_IS_DAVICOM(sc)) { 1414 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1415 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1416 sc->dc_link = 1; 1417 } else { 1418 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1419 } 1420 } 1421 1422 if ((media & IFM_GMASK) == IFM_FDX) { 1423 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1424 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1425 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1426 } else { 1427 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1428 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1429 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1430 } 1431 1432 if (restart) 1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1434 1435 return; 1436 } 1437 1438 static void dc_reset(sc) 1439 struct dc_softc *sc; 1440 { 1441 int i; 1442 1443 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1444 1445 for (i = 0; i < DC_TIMEOUT; i++) { 1446 DELAY(10); 1447 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1448 break; 1449 } 1450 1451 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) { 1452 DELAY(10000); 1453 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1454 i = 0; 1455 } 1456 1457 if (i == DC_TIMEOUT) 1458 printf("dc%d: reset never completed!\n", sc->dc_unit); 1459 1460 /* Wait a little while for the chip to get its brains in order. */ 1461 DELAY(1000); 1462 1463 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1464 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1465 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1466 1467 /* 1468 * Bring the SIA out of reset. In some cases, it looks 1469 * like failing to unreset the SIA soon enough gets it 1470 * into a state where it will never come out of reset 1471 * until we reset the whole chip again. 1472 */ 1473 if (DC_IS_INTEL(sc)) { 1474 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1475 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1476 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1477 } 1478 1479 return; 1480 } 1481 1482 static struct dc_type *dc_devtype(dev) 1483 device_t dev; 1484 { 1485 struct dc_type *t; 1486 u_int32_t rev; 1487 1488 t = dc_devs; 1489 1490 while(t->dc_name != NULL) { 1491 if ((pci_get_vendor(dev) == t->dc_vid) && 1492 (pci_get_device(dev) == t->dc_did)) { 1493 /* Check the PCI revision */ 1494 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1495 if (t->dc_did == DC_DEVICEID_98713 && 1496 rev >= DC_REVISION_98713A) 1497 t++; 1498 if (t->dc_did == DC_DEVICEID_98713_CP && 1499 rev >= DC_REVISION_98713A) 1500 t++; 1501 if (t->dc_did == DC_DEVICEID_987x5 && 1502 rev >= DC_REVISION_98715AEC_C) 1503 t++; 1504 if (t->dc_did == DC_DEVICEID_987x5 && 1505 rev >= DC_REVISION_98725) 1506 t++; 1507 if (t->dc_did == DC_DEVICEID_AX88140A && 1508 rev >= DC_REVISION_88141) 1509 t++; 1510 if (t->dc_did == DC_DEVICEID_82C168 && 1511 rev >= DC_REVISION_82C169) 1512 t++; 1513 if (t->dc_did == DC_DEVICEID_DM9102 && 1514 rev >= DC_REVISION_DM9102A) 1515 t++; 1516 return(t); 1517 } 1518 t++; 1519 } 1520 1521 return(NULL); 1522 } 1523 1524 /* 1525 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1526 * IDs against our list and return a device name if we find a match. 1527 * We do a little bit of extra work to identify the exact type of 1528 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1529 * but different revision IDs. The same is true for 98715/98715A 1530 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1531 * cases, the exact chip revision affects driver behavior. 1532 */ 1533 static int dc_probe(dev) 1534 device_t dev; 1535 { 1536 struct dc_type *t; 1537 1538 t = dc_devtype(dev); 1539 1540 if (t != NULL) { 1541 device_set_desc(dev, t->dc_name); 1542 return(0); 1543 } 1544 1545 return(ENXIO); 1546 } 1547 1548 static void dc_acpi(dev) 1549 device_t dev; 1550 { 1551 u_int32_t r, cptr; 1552 int unit; 1553 1554 unit = device_get_unit(dev); 1555 1556 /* Find the location of the capabilities block */ 1557 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1558 1559 r = pci_read_config(dev, cptr, 4) & 0xFF; 1560 if (r == 0x01) { 1561 1562 r = pci_read_config(dev, cptr + 4, 4); 1563 if (r & DC_PSTATE_D3) { 1564 u_int32_t iobase, membase, irq; 1565 1566 /* Save important PCI config data. */ 1567 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1568 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1569 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1570 1571 /* Reset the power state. */ 1572 printf("dc%d: chip is in D%d power mode " 1573 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1574 r &= 0xFFFFFFFC; 1575 pci_write_config(dev, cptr + 4, r, 4); 1576 1577 /* Restore PCI config data. */ 1578 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1579 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1580 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1581 } 1582 } 1583 return; 1584 } 1585 1586 static void dc_apply_fixup(sc, media) 1587 struct dc_softc *sc; 1588 int media; 1589 { 1590 struct dc_mediainfo *m; 1591 u_int8_t *p; 1592 int i; 1593 u_int32_t reg; 1594 1595 m = sc->dc_mi; 1596 1597 while (m != NULL) { 1598 if (m->dc_media == media) 1599 break; 1600 m = m->dc_next; 1601 } 1602 1603 if (m == NULL) 1604 return; 1605 1606 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1607 reg = (p[0] | (p[1] << 8)) << 16; 1608 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1609 } 1610 1611 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1612 reg = (p[0] | (p[1] << 8)) << 16; 1613 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1614 } 1615 1616 return; 1617 } 1618 1619 static void dc_decode_leaf_sia(sc, l) 1620 struct dc_softc *sc; 1621 struct dc_eblock_sia *l; 1622 { 1623 struct dc_mediainfo *m; 1624 1625 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1626 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1627 m->dc_media = IFM_10_T; 1628 1629 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1630 m->dc_media = IFM_10_T|IFM_FDX; 1631 1632 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1633 m->dc_media = IFM_10_2; 1634 1635 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1636 m->dc_media = IFM_10_5; 1637 1638 m->dc_gp_len = 2; 1639 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1640 1641 m->dc_next = sc->dc_mi; 1642 sc->dc_mi = m; 1643 1644 sc->dc_pmode = DC_PMODE_SIA; 1645 1646 return; 1647 } 1648 1649 static void dc_decode_leaf_sym(sc, l) 1650 struct dc_softc *sc; 1651 struct dc_eblock_sym *l; 1652 { 1653 struct dc_mediainfo *m; 1654 1655 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1656 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1657 m->dc_media = IFM_100_TX; 1658 1659 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1660 m->dc_media = IFM_100_TX|IFM_FDX; 1661 1662 m->dc_gp_len = 2; 1663 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1664 1665 m->dc_next = sc->dc_mi; 1666 sc->dc_mi = m; 1667 1668 sc->dc_pmode = DC_PMODE_SYM; 1669 1670 return; 1671 } 1672 1673 static void dc_decode_leaf_mii(sc, l) 1674 struct dc_softc *sc; 1675 struct dc_eblock_mii *l; 1676 { 1677 u_int8_t *p; 1678 struct dc_mediainfo *m; 1679 1680 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1681 /* We abuse IFM_AUTO to represent MII. */ 1682 m->dc_media = IFM_AUTO; 1683 m->dc_gp_len = l->dc_gpr_len; 1684 1685 p = (u_int8_t *)l; 1686 p += sizeof(struct dc_eblock_mii); 1687 m->dc_gp_ptr = p; 1688 p += 2 * l->dc_gpr_len; 1689 m->dc_reset_len = *p; 1690 p++; 1691 m->dc_reset_ptr = p; 1692 1693 m->dc_next = sc->dc_mi; 1694 sc->dc_mi = m; 1695 1696 return; 1697 } 1698 1699 static void dc_read_srom(sc, bits) 1700 struct dc_softc *sc; 1701 int bits; 1702 { 1703 int size; 1704 1705 size = 2 << bits; 1706 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT); 1707 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1708 } 1709 1710 static void dc_parse_21143_srom(sc) 1711 struct dc_softc *sc; 1712 { 1713 struct dc_leaf_hdr *lhdr; 1714 struct dc_eblock_hdr *hdr; 1715 int i, loff; 1716 char *ptr; 1717 int have_mii; 1718 1719 have_mii = 0; 1720 loff = sc->dc_srom[27]; 1721 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1722 1723 ptr = (char *)lhdr; 1724 ptr += sizeof(struct dc_leaf_hdr) - 1; 1725 /* 1726 * Look if we got a MII media block. 1727 */ 1728 for (i = 0; i < lhdr->dc_mcnt; i++) { 1729 hdr = (struct dc_eblock_hdr *)ptr; 1730 if (hdr->dc_type == DC_EBLOCK_MII) 1731 have_mii++; 1732 1733 ptr += (hdr->dc_len & 0x7F); 1734 ptr++; 1735 } 1736 1737 /* 1738 * Do the same thing again. Only use SIA and SYM media 1739 * blocks if no MII media block is available. 1740 */ 1741 ptr = (char *)lhdr; 1742 ptr += sizeof(struct dc_leaf_hdr) - 1; 1743 for (i = 0; i < lhdr->dc_mcnt; i++) { 1744 hdr = (struct dc_eblock_hdr *)ptr; 1745 switch(hdr->dc_type) { 1746 case DC_EBLOCK_MII: 1747 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1748 break; 1749 case DC_EBLOCK_SIA: 1750 if (! have_mii) 1751 dc_decode_leaf_sia(sc, 1752 (struct dc_eblock_sia *)hdr); 1753 break; 1754 case DC_EBLOCK_SYM: 1755 if (! have_mii) 1756 dc_decode_leaf_sym(sc, 1757 (struct dc_eblock_sym *)hdr); 1758 break; 1759 default: 1760 /* Don't care. Yet. */ 1761 break; 1762 } 1763 ptr += (hdr->dc_len & 0x7F); 1764 ptr++; 1765 } 1766 1767 return; 1768 } 1769 1770 /* 1771 * Attach the interface. Allocate softc structures, do ifmedia 1772 * setup and ethernet/BPF attach. 1773 */ 1774 static int dc_attach(dev) 1775 device_t dev; 1776 { 1777 int s, tmp = 0; 1778 u_char eaddr[ETHER_ADDR_LEN]; 1779 u_int32_t command; 1780 struct dc_softc *sc; 1781 struct ifnet *ifp; 1782 u_int32_t revision; 1783 int unit, error = 0, rid, mac_offset; 1784 1785 s = splimp(); 1786 1787 sc = device_get_softc(dev); 1788 unit = device_get_unit(dev); 1789 bzero(sc, sizeof(struct dc_softc)); 1790 callout_init(&sc->dc_stat_timer); 1791 1792 /* 1793 * Handle power management nonsense. 1794 */ 1795 dc_acpi(dev); 1796 1797 /* 1798 * Map control/status registers. 1799 */ 1800 command = pci_read_config(dev, PCIR_COMMAND, 4); 1801 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1802 pci_write_config(dev, PCIR_COMMAND, command, 4); 1803 command = pci_read_config(dev, PCIR_COMMAND, 4); 1804 1805 #ifdef DC_USEIOSPACE 1806 if (!(command & PCIM_CMD_PORTEN)) { 1807 printf("dc%d: failed to enable I/O ports!\n", unit); 1808 error = ENXIO; 1809 goto fail; 1810 } 1811 #else 1812 if (!(command & PCIM_CMD_MEMEN)) { 1813 printf("dc%d: failed to enable memory mapping!\n", unit); 1814 error = ENXIO; 1815 goto fail; 1816 } 1817 #endif 1818 1819 rid = DC_RID; 1820 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1821 0, ~0, 1, RF_ACTIVE); 1822 1823 if (sc->dc_res == NULL) { 1824 printf("dc%d: couldn't map ports/memory\n", unit); 1825 error = ENXIO; 1826 goto fail; 1827 } 1828 1829 sc->dc_btag = rman_get_bustag(sc->dc_res); 1830 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1831 1832 /* Allocate interrupt */ 1833 rid = 0; 1834 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1835 RF_SHAREABLE | RF_ACTIVE); 1836 1837 if (sc->dc_irq == NULL) { 1838 printf("dc%d: couldn't map interrupt\n", unit); 1839 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1840 error = ENXIO; 1841 goto fail; 1842 } 1843 1844 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1845 dc_intr, sc, &sc->dc_intrhand); 1846 1847 if (error) { 1848 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1849 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1850 printf("dc%d: couldn't set up irq\n", unit); 1851 goto fail; 1852 } 1853 1854 /* Need this info to decide on a chip type. */ 1855 sc->dc_info = dc_devtype(dev); 1856 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1857 1858 /* Get the eeprom width, but PNIC has diff eeprom */ 1859 if (sc->dc_info->dc_did != DC_DEVICEID_82C168) 1860 dc_eeprom_width(sc); 1861 1862 switch(sc->dc_info->dc_did) { 1863 case DC_DEVICEID_21143: 1864 sc->dc_type = DC_TYPE_21143; 1865 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1866 sc->dc_flags |= DC_REDUCED_MII_POLL; 1867 /* Save EEPROM contents so we can parse them later. */ 1868 dc_read_srom(sc, sc->dc_romwidth); 1869 break; 1870 case DC_DEVICEID_DM9009: 1871 case DC_DEVICEID_DM9100: 1872 case DC_DEVICEID_DM9102: 1873 sc->dc_type = DC_TYPE_DM9102; 1874 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1875 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1876 sc->dc_pmode = DC_PMODE_MII; 1877 /* Increase the latency timer value. */ 1878 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1879 command &= 0xFFFF00FF; 1880 command |= 0x00008000; 1881 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1882 break; 1883 case DC_DEVICEID_AL981: 1884 sc->dc_type = DC_TYPE_AL981; 1885 sc->dc_flags |= DC_TX_USE_TX_INTR; 1886 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1887 sc->dc_pmode = DC_PMODE_MII; 1888 dc_read_srom(sc, sc->dc_romwidth); 1889 break; 1890 case DC_DEVICEID_AN985: 1891 case DC_DEVICEID_EN2242: 1892 case DC_DEVICEID_3CSOHOB: 1893 sc->dc_type = DC_TYPE_AN985; 1894 sc->dc_flags |= DC_64BIT_HASH; 1895 sc->dc_flags |= DC_TX_USE_TX_INTR; 1896 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1897 sc->dc_pmode = DC_PMODE_MII; 1898 dc_read_srom(sc, sc->dc_romwidth); 1899 break; 1900 case DC_DEVICEID_98713: 1901 case DC_DEVICEID_98713_CP: 1902 if (revision < DC_REVISION_98713A) { 1903 sc->dc_type = DC_TYPE_98713; 1904 } 1905 if (revision >= DC_REVISION_98713A) { 1906 sc->dc_type = DC_TYPE_98713A; 1907 sc->dc_flags |= DC_21143_NWAY; 1908 } 1909 sc->dc_flags |= DC_REDUCED_MII_POLL; 1910 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1911 break; 1912 case DC_DEVICEID_987x5: 1913 case DC_DEVICEID_EN1217: 1914 /* 1915 * Macronix MX98715AEC-C/D/E parts have only a 1916 * 128-bit hash table. We need to deal with these 1917 * in the same manner as the PNIC II so that we 1918 * get the right number of bits out of the 1919 * CRC routine. 1920 */ 1921 if (revision >= DC_REVISION_98715AEC_C && 1922 revision < DC_REVISION_98725) 1923 sc->dc_flags |= DC_128BIT_HASH; 1924 sc->dc_type = DC_TYPE_987x5; 1925 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1926 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1927 break; 1928 case DC_DEVICEID_98727: 1929 sc->dc_type = DC_TYPE_987x5; 1930 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1931 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1932 break; 1933 case DC_DEVICEID_82C115: 1934 sc->dc_type = DC_TYPE_PNICII; 1935 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1936 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1937 break; 1938 case DC_DEVICEID_82C168: 1939 sc->dc_type = DC_TYPE_PNIC; 1940 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1941 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1942 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK); 1943 if (revision < DC_REVISION_82C169) 1944 sc->dc_pmode = DC_PMODE_SYM; 1945 break; 1946 case DC_DEVICEID_AX88140A: 1947 sc->dc_type = DC_TYPE_ASIX; 1948 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1949 sc->dc_flags |= DC_REDUCED_MII_POLL; 1950 sc->dc_pmode = DC_PMODE_MII; 1951 break; 1952 case DC_DEVICEID_RS7112: 1953 sc->dc_type = DC_TYPE_CONEXANT; 1954 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1955 sc->dc_flags |= DC_REDUCED_MII_POLL; 1956 sc->dc_pmode = DC_PMODE_MII; 1957 dc_read_srom(sc, sc->dc_romwidth); 1958 break; 1959 default: 1960 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1961 sc->dc_info->dc_did); 1962 break; 1963 } 1964 1965 /* Save the cache line size. */ 1966 if (DC_IS_DAVICOM(sc)) 1967 sc->dc_cachesize = 0; 1968 else 1969 sc->dc_cachesize = pci_read_config(dev, 1970 DC_PCI_CFLT, 4) & 0xFF; 1971 1972 /* Reset the adapter. */ 1973 dc_reset(sc); 1974 1975 /* Take 21143 out of snooze mode */ 1976 if (DC_IS_INTEL(sc)) { 1977 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1978 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1979 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1980 } 1981 1982 /* 1983 * Try to learn something about the supported media. 1984 * We know that ASIX and ADMtek and Davicom devices 1985 * will *always* be using MII media, so that's a no-brainer. 1986 * The tricky ones are the Macronix/PNIC II and the 1987 * Intel 21143. 1988 */ 1989 if (DC_IS_INTEL(sc)) 1990 dc_parse_21143_srom(sc); 1991 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1992 if (sc->dc_type == DC_TYPE_98713) 1993 sc->dc_pmode = DC_PMODE_MII; 1994 else 1995 sc->dc_pmode = DC_PMODE_SYM; 1996 } else if (!sc->dc_pmode) 1997 sc->dc_pmode = DC_PMODE_MII; 1998 1999 /* 2000 * Get station address from the EEPROM. 2001 */ 2002 switch(sc->dc_type) { 2003 case DC_TYPE_98713: 2004 case DC_TYPE_98713A: 2005 case DC_TYPE_987x5: 2006 case DC_TYPE_PNICII: 2007 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2008 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2009 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2010 break; 2011 case DC_TYPE_PNIC: 2012 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2013 break; 2014 case DC_TYPE_DM9102: 2015 case DC_TYPE_21143: 2016 case DC_TYPE_ASIX: 2017 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2018 break; 2019 case DC_TYPE_AL981: 2020 case DC_TYPE_AN985: 2021 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 2022 ETHER_ADDR_LEN); 2023 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2024 break; 2025 case DC_TYPE_CONEXANT: 2026 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2027 break; 2028 default: 2029 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2030 break; 2031 } 2032 2033 sc->dc_unit = unit; 2034 2035 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2036 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2037 2038 if (sc->dc_ldata == NULL) { 2039 printf("dc%d: no memory for list buffers!\n", unit); 2040 if (sc->dc_pnic_rx_buf != NULL) 2041 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2042 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2043 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2044 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2045 error = ENXIO; 2046 goto fail; 2047 } 2048 2049 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2050 2051 ifp = &sc->arpcom.ac_if; 2052 ifp->if_softc = sc; 2053 if_initname(ifp, "dc", unit); 2054 ifp->if_mtu = ETHERMTU; 2055 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2056 ifp->if_ioctl = dc_ioctl; 2057 ifp->if_start = dc_start; 2058 ifp->if_watchdog = dc_watchdog; 2059 ifp->if_init = dc_init; 2060 ifp->if_baudrate = 10000000; 2061 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2062 ifq_set_ready(&ifp->if_snd); 2063 2064 /* 2065 * Do MII setup. If this is a 21143, check for a PHY on the 2066 * MII bus after applying any necessary fixups to twiddle the 2067 * GPIO bits. If we don't end up finding a PHY, restore the 2068 * old selection (SIA only or SIA/SYM) and attach the dcphy 2069 * driver instead. 2070 */ 2071 if (DC_IS_INTEL(sc)) { 2072 dc_apply_fixup(sc, IFM_AUTO); 2073 tmp = sc->dc_pmode; 2074 sc->dc_pmode = DC_PMODE_MII; 2075 } 2076 2077 error = mii_phy_probe(dev, &sc->dc_miibus, 2078 dc_ifmedia_upd, dc_ifmedia_sts); 2079 2080 if (error && DC_IS_INTEL(sc)) { 2081 sc->dc_pmode = tmp; 2082 if (sc->dc_pmode != DC_PMODE_SIA) 2083 sc->dc_pmode = DC_PMODE_SYM; 2084 sc->dc_flags |= DC_21143_NWAY; 2085 mii_phy_probe(dev, &sc->dc_miibus, 2086 dc_ifmedia_upd, dc_ifmedia_sts); 2087 /* 2088 * For non-MII cards, we need to have the 21143 2089 * drive the LEDs. Except there are some systems 2090 * like the NEC VersaPro NoteBook PC which have no 2091 * LEDs, and twiddling these bits has adverse effects 2092 * on them. (I.e. you suddenly can't get a link.) 2093 */ 2094 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2095 sc->dc_flags |= DC_TULIP_LEDS; 2096 error = 0; 2097 } 2098 2099 if (error) { 2100 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2101 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), 2102 M_DEVBUF); 2103 if (sc->dc_pnic_rx_buf != NULL) 2104 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2105 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2106 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2107 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2108 error = ENXIO; 2109 goto fail; 2110 } 2111 2112 /* 2113 * Call MI attach routine. 2114 */ 2115 ether_ifattach(ifp, eaddr); 2116 2117 if (DC_IS_ADMTEK(sc)) { 2118 /* 2119 * Set automatic TX underrun recovery for the ADMtek chips 2120 */ 2121 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2122 } 2123 2124 /* 2125 * Tell the upper layer(s) we support long frames. 2126 */ 2127 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2128 2129 fail: 2130 splx(s); 2131 2132 return(error); 2133 } 2134 2135 static int dc_detach(dev) 2136 device_t dev; 2137 { 2138 struct dc_softc *sc; 2139 struct ifnet *ifp; 2140 int s; 2141 struct dc_mediainfo *m; 2142 2143 s = splimp(); 2144 2145 sc = device_get_softc(dev); 2146 ifp = &sc->arpcom.ac_if; 2147 2148 dc_stop(sc); 2149 ether_ifdetach(ifp); 2150 2151 bus_generic_detach(dev); 2152 device_delete_child(dev, sc->dc_miibus); 2153 2154 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2155 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2156 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2157 2158 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2159 if (sc->dc_pnic_rx_buf != NULL) 2160 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2161 2162 while(sc->dc_mi != NULL) { 2163 m = sc->dc_mi->dc_next; 2164 free(sc->dc_mi, M_DEVBUF); 2165 sc->dc_mi = m; 2166 } 2167 free(sc->dc_srom, M_DEVBUF); 2168 2169 splx(s); 2170 2171 return(0); 2172 } 2173 2174 /* 2175 * Initialize the transmit descriptors. 2176 */ 2177 static int dc_list_tx_init(sc) 2178 struct dc_softc *sc; 2179 { 2180 struct dc_chain_data *cd; 2181 struct dc_list_data *ld; 2182 int i; 2183 2184 cd = &sc->dc_cdata; 2185 ld = sc->dc_ldata; 2186 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2187 if (i == (DC_TX_LIST_CNT - 1)) { 2188 ld->dc_tx_list[i].dc_next = 2189 vtophys(&ld->dc_tx_list[0]); 2190 } else { 2191 ld->dc_tx_list[i].dc_next = 2192 vtophys(&ld->dc_tx_list[i + 1]); 2193 } 2194 cd->dc_tx_chain[i] = NULL; 2195 ld->dc_tx_list[i].dc_data = 0; 2196 ld->dc_tx_list[i].dc_ctl = 0; 2197 } 2198 2199 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2200 2201 return(0); 2202 } 2203 2204 2205 /* 2206 * Initialize the RX descriptors and allocate mbufs for them. Note that 2207 * we arrange the descriptors in a closed ring, so that the last descriptor 2208 * points back to the first. 2209 */ 2210 static int dc_list_rx_init(sc) 2211 struct dc_softc *sc; 2212 { 2213 struct dc_chain_data *cd; 2214 struct dc_list_data *ld; 2215 int i; 2216 2217 cd = &sc->dc_cdata; 2218 ld = sc->dc_ldata; 2219 2220 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2221 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2222 return(ENOBUFS); 2223 if (i == (DC_RX_LIST_CNT - 1)) { 2224 ld->dc_rx_list[i].dc_next = 2225 vtophys(&ld->dc_rx_list[0]); 2226 } else { 2227 ld->dc_rx_list[i].dc_next = 2228 vtophys(&ld->dc_rx_list[i + 1]); 2229 } 2230 } 2231 2232 cd->dc_rx_prod = 0; 2233 2234 return(0); 2235 } 2236 2237 /* 2238 * Initialize an RX descriptor and attach an MBUF cluster. 2239 */ 2240 static int dc_newbuf(sc, i, m) 2241 struct dc_softc *sc; 2242 int i; 2243 struct mbuf *m; 2244 { 2245 struct mbuf *m_new = NULL; 2246 struct dc_desc *c; 2247 2248 c = &sc->dc_ldata->dc_rx_list[i]; 2249 2250 if (m == NULL) { 2251 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 2252 if (m_new == NULL) 2253 return(ENOBUFS); 2254 2255 MCLGET(m_new, MB_DONTWAIT); 2256 if (!(m_new->m_flags & M_EXT)) { 2257 m_freem(m_new); 2258 return(ENOBUFS); 2259 } 2260 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2261 } else { 2262 m_new = m; 2263 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2264 m_new->m_data = m_new->m_ext.ext_buf; 2265 } 2266 2267 m_adj(m_new, sizeof(u_int64_t)); 2268 2269 /* 2270 * If this is a PNIC chip, zero the buffer. This is part 2271 * of the workaround for the receive bug in the 82c168 and 2272 * 82c169 chips. 2273 */ 2274 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2275 bzero((char *)mtod(m_new, char *), m_new->m_len); 2276 2277 sc->dc_cdata.dc_rx_chain[i] = m_new; 2278 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2279 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2280 c->dc_status = DC_RXSTAT_OWN; 2281 2282 return(0); 2283 } 2284 2285 /* 2286 * Grrrrr. 2287 * The PNIC chip has a terrible bug in it that manifests itself during 2288 * periods of heavy activity. The exact mode of failure if difficult to 2289 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2290 * will happen on slow machines. The bug is that sometimes instead of 2291 * uploading one complete frame during reception, it uploads what looks 2292 * like the entire contents of its FIFO memory. The frame we want is at 2293 * the end of the whole mess, but we never know exactly how much data has 2294 * been uploaded, so salvaging the frame is hard. 2295 * 2296 * There is only one way to do it reliably, and it's disgusting. 2297 * Here's what we know: 2298 * 2299 * - We know there will always be somewhere between one and three extra 2300 * descriptors uploaded. 2301 * 2302 * - We know the desired received frame will always be at the end of the 2303 * total data upload. 2304 * 2305 * - We know the size of the desired received frame because it will be 2306 * provided in the length field of the status word in the last descriptor. 2307 * 2308 * Here's what we do: 2309 * 2310 * - When we allocate buffers for the receive ring, we bzero() them. 2311 * This means that we know that the buffer contents should be all 2312 * zeros, except for data uploaded by the chip. 2313 * 2314 * - We also force the PNIC chip to upload frames that include the 2315 * ethernet CRC at the end. 2316 * 2317 * - We gather all of the bogus frame data into a single buffer. 2318 * 2319 * - We then position a pointer at the end of this buffer and scan 2320 * backwards until we encounter the first non-zero byte of data. 2321 * This is the end of the received frame. We know we will encounter 2322 * some data at the end of the frame because the CRC will always be 2323 * there, so even if the sender transmits a packet of all zeros, 2324 * we won't be fooled. 2325 * 2326 * - We know the size of the actual received frame, so we subtract 2327 * that value from the current pointer location. This brings us 2328 * to the start of the actual received packet. 2329 * 2330 * - We copy this into an mbuf and pass it on, along with the actual 2331 * frame length. 2332 * 2333 * The performance hit is tremendous, but it beats dropping frames all 2334 * the time. 2335 */ 2336 2337 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2338 static void dc_pnic_rx_bug_war(sc, idx) 2339 struct dc_softc *sc; 2340 int idx; 2341 { 2342 struct dc_desc *cur_rx; 2343 struct dc_desc *c = NULL; 2344 struct mbuf *m = NULL; 2345 unsigned char *ptr; 2346 int i, total_len; 2347 u_int32_t rxstat = 0; 2348 2349 i = sc->dc_pnic_rx_bug_save; 2350 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2351 ptr = sc->dc_pnic_rx_buf; 2352 bzero(ptr, DC_RXLEN * 5); 2353 2354 /* Copy all the bytes from the bogus buffers. */ 2355 while (1) { 2356 c = &sc->dc_ldata->dc_rx_list[i]; 2357 rxstat = c->dc_status; 2358 m = sc->dc_cdata.dc_rx_chain[i]; 2359 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2360 ptr += DC_RXLEN; 2361 /* If this is the last buffer, break out. */ 2362 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2363 break; 2364 dc_newbuf(sc, i, m); 2365 DC_INC(i, DC_RX_LIST_CNT); 2366 } 2367 2368 /* Find the length of the actual receive frame. */ 2369 total_len = DC_RXBYTES(rxstat); 2370 2371 /* Scan backwards until we hit a non-zero byte. */ 2372 while(*ptr == 0x00) 2373 ptr--; 2374 2375 /* Round off. */ 2376 if ((uintptr_t)(ptr) & 0x3) 2377 ptr -= 1; 2378 2379 /* Now find the start of the frame. */ 2380 ptr -= total_len; 2381 if (ptr < sc->dc_pnic_rx_buf) 2382 ptr = sc->dc_pnic_rx_buf; 2383 2384 /* 2385 * Now copy the salvaged frame to the last mbuf and fake up 2386 * the status word to make it look like a successful 2387 * frame reception. 2388 */ 2389 dc_newbuf(sc, i, m); 2390 bcopy(ptr, mtod(m, char *), total_len); 2391 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2392 2393 return; 2394 } 2395 2396 /* 2397 * This routine searches the RX ring for dirty descriptors in the 2398 * event that the rxeof routine falls out of sync with the chip's 2399 * current descriptor pointer. This may happen sometimes as a result 2400 * of a "no RX buffer available" condition that happens when the chip 2401 * consumes all of the RX buffers before the driver has a chance to 2402 * process the RX ring. This routine may need to be called more than 2403 * once to bring the driver back in sync with the chip, however we 2404 * should still be getting RX DONE interrupts to drive the search 2405 * for new packets in the RX ring, so we should catch up eventually. 2406 */ 2407 static int dc_rx_resync(sc) 2408 struct dc_softc *sc; 2409 { 2410 int i, pos; 2411 struct dc_desc *cur_rx; 2412 2413 pos = sc->dc_cdata.dc_rx_prod; 2414 2415 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2416 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2417 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2418 break; 2419 DC_INC(pos, DC_RX_LIST_CNT); 2420 } 2421 2422 /* If the ring really is empty, then just return. */ 2423 if (i == DC_RX_LIST_CNT) 2424 return(0); 2425 2426 /* We've fallen behing the chip: catch it. */ 2427 sc->dc_cdata.dc_rx_prod = pos; 2428 2429 return(EAGAIN); 2430 } 2431 2432 /* 2433 * A frame has been uploaded: pass the resulting mbuf chain up to 2434 * the higher level protocols. 2435 */ 2436 static void dc_rxeof(sc) 2437 struct dc_softc *sc; 2438 { 2439 struct mbuf *m; 2440 struct ifnet *ifp; 2441 struct dc_desc *cur_rx; 2442 int i, total_len = 0; 2443 u_int32_t rxstat; 2444 2445 ifp = &sc->arpcom.ac_if; 2446 i = sc->dc_cdata.dc_rx_prod; 2447 2448 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2449 2450 #ifdef DEVICE_POLLING 2451 if (ifp->if_flags & IFF_POLLING) { 2452 if (sc->rxcycles <= 0) 2453 break; 2454 sc->rxcycles--; 2455 } 2456 #endif /* DEVICE_POLLING */ 2457 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2458 rxstat = cur_rx->dc_status; 2459 m = sc->dc_cdata.dc_rx_chain[i]; 2460 total_len = DC_RXBYTES(rxstat); 2461 2462 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2463 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2464 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2465 sc->dc_pnic_rx_bug_save = i; 2466 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2467 DC_INC(i, DC_RX_LIST_CNT); 2468 continue; 2469 } 2470 dc_pnic_rx_bug_war(sc, i); 2471 rxstat = cur_rx->dc_status; 2472 total_len = DC_RXBYTES(rxstat); 2473 } 2474 } 2475 2476 sc->dc_cdata.dc_rx_chain[i] = NULL; 2477 2478 /* 2479 * If an error occurs, update stats, clear the 2480 * status word and leave the mbuf cluster in place: 2481 * it should simply get re-used next time this descriptor 2482 * comes up in the ring. However, don't report long 2483 * frames as errors since they could be vlans 2484 */ 2485 if ((rxstat & DC_RXSTAT_RXERR)){ 2486 if (!(rxstat & DC_RXSTAT_GIANT) || 2487 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2488 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2489 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2490 ifp->if_ierrors++; 2491 if (rxstat & DC_RXSTAT_COLLSEEN) 2492 ifp->if_collisions++; 2493 dc_newbuf(sc, i, m); 2494 if (rxstat & DC_RXSTAT_CRCERR) { 2495 DC_INC(i, DC_RX_LIST_CNT); 2496 continue; 2497 } else { 2498 dc_init(sc); 2499 return; 2500 } 2501 } 2502 } 2503 2504 /* No errors; receive the packet. */ 2505 total_len -= ETHER_CRC_LEN; 2506 2507 #ifdef __i386__ 2508 /* 2509 * On the x86 we do not have alignment problems, so try to 2510 * allocate a new buffer for the receive ring, and pass up 2511 * the one where the packet is already, saving the expensive 2512 * copy done in m_devget(). 2513 * If we are on an architecture with alignment problems, or 2514 * if the allocation fails, then use m_devget and leave the 2515 * existing buffer in the receive ring. 2516 */ 2517 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2518 m->m_pkthdr.rcvif = ifp; 2519 m->m_pkthdr.len = m->m_len = total_len; 2520 DC_INC(i, DC_RX_LIST_CNT); 2521 } else 2522 #endif 2523 { 2524 struct mbuf *m0; 2525 2526 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2527 total_len + ETHER_ALIGN, 0, ifp, NULL); 2528 dc_newbuf(sc, i, m); 2529 DC_INC(i, DC_RX_LIST_CNT); 2530 if (m0 == NULL) { 2531 ifp->if_ierrors++; 2532 continue; 2533 } 2534 m_adj(m0, ETHER_ALIGN); 2535 m = m0; 2536 } 2537 2538 ifp->if_ipackets++; 2539 (*ifp->if_input)(ifp, m); 2540 } 2541 2542 sc->dc_cdata.dc_rx_prod = i; 2543 } 2544 2545 /* 2546 * A frame was downloaded to the chip. It's safe for us to clean up 2547 * the list buffers. 2548 */ 2549 2550 static void 2551 dc_txeof(sc) 2552 struct dc_softc *sc; 2553 { 2554 struct dc_desc *cur_tx = NULL; 2555 struct ifnet *ifp; 2556 int idx; 2557 2558 ifp = &sc->arpcom.ac_if; 2559 2560 /* 2561 * Go through our tx list and free mbufs for those 2562 * frames that have been transmitted. 2563 */ 2564 idx = sc->dc_cdata.dc_tx_cons; 2565 while(idx != sc->dc_cdata.dc_tx_prod) { 2566 u_int32_t txstat; 2567 2568 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2569 txstat = cur_tx->dc_status; 2570 2571 if (txstat & DC_TXSTAT_OWN) 2572 break; 2573 2574 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2575 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2576 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2577 /* 2578 * Yes, the PNIC is so brain damaged 2579 * that it will sometimes generate a TX 2580 * underrun error while DMAing the RX 2581 * filter setup frame. If we detect this, 2582 * we have to send the setup frame again, 2583 * or else the filter won't be programmed 2584 * correctly. 2585 */ 2586 if (DC_IS_PNIC(sc)) { 2587 if (txstat & DC_TXSTAT_ERRSUM) 2588 dc_setfilt(sc); 2589 } 2590 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2591 } 2592 sc->dc_cdata.dc_tx_cnt--; 2593 DC_INC(idx, DC_TX_LIST_CNT); 2594 continue; 2595 } 2596 2597 if (DC_IS_CONEXANT(sc)) { 2598 /* 2599 * For some reason Conexant chips like 2600 * setting the CARRLOST flag even when 2601 * the carrier is there. In CURRENT we 2602 * have the same problem for Xircom 2603 * cards ! 2604 */ 2605 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2606 sc->dc_pmode == DC_PMODE_MII && 2607 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2608 DC_TXSTAT_NOCARRIER))) 2609 txstat &= ~DC_TXSTAT_ERRSUM; 2610 } else { 2611 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2612 sc->dc_pmode == DC_PMODE_MII && 2613 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2614 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2615 txstat &= ~DC_TXSTAT_ERRSUM; 2616 } 2617 2618 if (txstat & DC_TXSTAT_ERRSUM) { 2619 ifp->if_oerrors++; 2620 if (txstat & DC_TXSTAT_EXCESSCOLL) 2621 ifp->if_collisions++; 2622 if (txstat & DC_TXSTAT_LATECOLL) 2623 ifp->if_collisions++; 2624 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2625 dc_init(sc); 2626 return; 2627 } 2628 } 2629 2630 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2631 2632 ifp->if_opackets++; 2633 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2634 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2635 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2636 } 2637 2638 sc->dc_cdata.dc_tx_cnt--; 2639 DC_INC(idx, DC_TX_LIST_CNT); 2640 } 2641 2642 if (idx != sc->dc_cdata.dc_tx_cons) { 2643 /* some buffers have been freed */ 2644 sc->dc_cdata.dc_tx_cons = idx; 2645 ifp->if_flags &= ~IFF_OACTIVE; 2646 } 2647 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2648 2649 return; 2650 } 2651 2652 static void dc_tick(xsc) 2653 void *xsc; 2654 { 2655 struct dc_softc *sc; 2656 struct mii_data *mii; 2657 struct ifnet *ifp; 2658 int s; 2659 u_int32_t r; 2660 2661 s = splimp(); 2662 2663 sc = xsc; 2664 ifp = &sc->arpcom.ac_if; 2665 mii = device_get_softc(sc->dc_miibus); 2666 2667 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2668 if (sc->dc_flags & DC_21143_NWAY) { 2669 r = CSR_READ_4(sc, DC_10BTSTAT); 2670 if (IFM_SUBTYPE(mii->mii_media_active) == 2671 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2672 sc->dc_link = 0; 2673 mii_mediachg(mii); 2674 } 2675 if (IFM_SUBTYPE(mii->mii_media_active) == 2676 IFM_10_T && (r & DC_TSTAT_LS10)) { 2677 sc->dc_link = 0; 2678 mii_mediachg(mii); 2679 } 2680 if (sc->dc_link == 0) 2681 mii_tick(mii); 2682 } else { 2683 r = CSR_READ_4(sc, DC_ISR); 2684 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2685 sc->dc_cdata.dc_tx_cnt == 0) 2686 mii_tick(mii); 2687 if (!(mii->mii_media_status & IFM_ACTIVE)) 2688 sc->dc_link = 0; 2689 } 2690 } else 2691 mii_tick(mii); 2692 2693 /* 2694 * When the init routine completes, we expect to be able to send 2695 * packets right away, and in fact the network code will send a 2696 * gratuitous ARP the moment the init routine marks the interface 2697 * as running. However, even though the MAC may have been initialized, 2698 * there may be a delay of a few seconds before the PHY completes 2699 * autonegotiation and the link is brought up. Any transmissions 2700 * made during that delay will be lost. Dealing with this is tricky: 2701 * we can't just pause in the init routine while waiting for the 2702 * PHY to come ready since that would bring the whole system to 2703 * a screeching halt for several seconds. 2704 * 2705 * What we do here is prevent the TX start routine from sending 2706 * any packets until a link has been established. After the 2707 * interface has been initialized, the tick routine will poll 2708 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2709 * that time, packets will stay in the send queue, and once the 2710 * link comes up, they will be flushed out to the wire. 2711 */ 2712 if (!sc->dc_link) { 2713 mii_pollstat(mii); 2714 if (mii->mii_media_status & IFM_ACTIVE && 2715 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2716 sc->dc_link++; 2717 if (!ifq_is_empty(&ifp->if_snd)) 2718 dc_start(ifp); 2719 } 2720 } 2721 2722 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2723 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc); 2724 else 2725 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 2726 2727 splx(s); 2728 2729 return; 2730 } 2731 2732 /* 2733 * A transmit underrun has occurred. Back off the transmit threshold, 2734 * or switch to store and forward mode if we have to. 2735 */ 2736 static void dc_tx_underrun(sc) 2737 struct dc_softc *sc; 2738 { 2739 u_int32_t isr; 2740 int i; 2741 2742 if (DC_IS_DAVICOM(sc)) 2743 dc_init(sc); 2744 2745 if (DC_IS_INTEL(sc)) { 2746 /* 2747 * The real 21143 requires that the transmitter be idle 2748 * in order to change the transmit threshold or store 2749 * and forward state. 2750 */ 2751 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2752 2753 for (i = 0; i < DC_TIMEOUT; i++) { 2754 isr = CSR_READ_4(sc, DC_ISR); 2755 if (isr & DC_ISR_TX_IDLE) 2756 break; 2757 DELAY(10); 2758 } 2759 if (i == DC_TIMEOUT) { 2760 printf("dc%d: failed to force tx to idle state\n", 2761 sc->dc_unit); 2762 dc_init(sc); 2763 } 2764 } 2765 2766 printf("dc%d: TX underrun -- ", sc->dc_unit); 2767 sc->dc_txthresh += DC_TXTHRESH_INC; 2768 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2769 printf("using store and forward mode\n"); 2770 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2771 } else { 2772 printf("increasing TX threshold\n"); 2773 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2774 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2775 } 2776 2777 if (DC_IS_INTEL(sc)) 2778 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2779 2780 return; 2781 } 2782 2783 #ifdef DEVICE_POLLING 2784 static poll_handler_t dc_poll; 2785 2786 static void 2787 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2788 { 2789 struct dc_softc *sc = ifp->if_softc; 2790 2791 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2792 /* Re-enable interrupts. */ 2793 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2794 return; 2795 } 2796 sc->rxcycles = count; 2797 dc_rxeof(sc); 2798 dc_txeof(sc); 2799 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd)) 2800 dc_start(ifp); 2801 2802 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2803 u_int32_t status; 2804 2805 status = CSR_READ_4(sc, DC_ISR); 2806 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2807 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2808 DC_ISR_BUS_ERR); 2809 if (!status) 2810 return ; 2811 /* ack what we have */ 2812 CSR_WRITE_4(sc, DC_ISR, status); 2813 2814 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2815 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2816 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2817 2818 if (dc_rx_resync(sc)) 2819 dc_rxeof(sc); 2820 } 2821 /* restart transmit unit if necessary */ 2822 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2823 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2824 2825 if (status & DC_ISR_TX_UNDERRUN) 2826 dc_tx_underrun(sc); 2827 2828 if (status & DC_ISR_BUS_ERR) { 2829 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2830 dc_reset(sc); 2831 dc_init(sc); 2832 } 2833 } 2834 } 2835 #endif /* DEVICE_POLLING */ 2836 2837 static void dc_intr(arg) 2838 void *arg; 2839 { 2840 struct dc_softc *sc; 2841 struct ifnet *ifp; 2842 u_int32_t status; 2843 2844 sc = arg; 2845 2846 if (sc->suspended) { 2847 return; 2848 } 2849 2850 ifp = &sc->arpcom.ac_if; 2851 2852 #ifdef DEVICE_POLLING 2853 if (ifp->if_flags & IFF_POLLING) 2854 return; 2855 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2856 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2857 return; 2858 } 2859 #endif /* DEVICE_POLLING */ 2860 2861 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2862 return ; 2863 2864 /* Suppress unwanted interrupts */ 2865 if (!(ifp->if_flags & IFF_UP)) { 2866 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2867 dc_stop(sc); 2868 return; 2869 } 2870 2871 /* Disable interrupts. */ 2872 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2873 2874 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2875 2876 CSR_WRITE_4(sc, DC_ISR, status); 2877 2878 if (status & DC_ISR_RX_OK) { 2879 int curpkts; 2880 curpkts = ifp->if_ipackets; 2881 dc_rxeof(sc); 2882 if (curpkts == ifp->if_ipackets) { 2883 while(dc_rx_resync(sc)) 2884 dc_rxeof(sc); 2885 } 2886 } 2887 2888 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2889 dc_txeof(sc); 2890 2891 if (status & DC_ISR_TX_IDLE) { 2892 dc_txeof(sc); 2893 if (sc->dc_cdata.dc_tx_cnt) { 2894 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2895 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2896 } 2897 } 2898 2899 if (status & DC_ISR_TX_UNDERRUN) 2900 dc_tx_underrun(sc); 2901 2902 if ((status & DC_ISR_RX_WATDOGTIMEO) 2903 || (status & DC_ISR_RX_NOBUF)) { 2904 int curpkts; 2905 curpkts = ifp->if_ipackets; 2906 dc_rxeof(sc); 2907 if (curpkts == ifp->if_ipackets) { 2908 while(dc_rx_resync(sc)) 2909 dc_rxeof(sc); 2910 } 2911 } 2912 2913 if (status & DC_ISR_BUS_ERR) { 2914 dc_reset(sc); 2915 dc_init(sc); 2916 } 2917 } 2918 2919 /* Re-enable interrupts. */ 2920 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2921 2922 if (!ifq_is_empty(&ifp->if_snd)) 2923 dc_start(ifp); 2924 2925 return; 2926 } 2927 2928 /* 2929 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2930 * pointers to the fragment pointers. 2931 */ 2932 static int dc_encap(sc, m_head, txidx) 2933 struct dc_softc *sc; 2934 struct mbuf *m_head; 2935 u_int32_t *txidx; 2936 { 2937 struct dc_desc *f = NULL; 2938 struct mbuf *m; 2939 int frag, cur, cnt = 0; 2940 2941 /* 2942 * Start packing the mbufs in this chain into 2943 * the fragment pointers. Stop when we run out 2944 * of fragments or hit the end of the mbuf chain. 2945 */ 2946 m = m_head; 2947 cur = frag = *txidx; 2948 2949 for (m = m_head; m != NULL; m = m->m_next) { 2950 if (m->m_len != 0) { 2951 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2952 if (*txidx != sc->dc_cdata.dc_tx_prod && 2953 frag == (DC_TX_LIST_CNT - 1)) 2954 return(ENOBUFS); 2955 } 2956 if ((DC_TX_LIST_CNT - 2957 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2958 return(ENOBUFS); 2959 2960 f = &sc->dc_ldata->dc_tx_list[frag]; 2961 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2962 if (cnt == 0) { 2963 f->dc_status = 0; 2964 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2965 } else 2966 f->dc_status = DC_TXSTAT_OWN; 2967 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2968 cur = frag; 2969 DC_INC(frag, DC_TX_LIST_CNT); 2970 cnt++; 2971 } 2972 } 2973 2974 if (m != NULL) 2975 return(ENOBUFS); 2976 2977 sc->dc_cdata.dc_tx_cnt += cnt; 2978 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2979 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2980 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2981 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2982 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2983 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2984 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2985 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2986 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2987 *txidx = frag; 2988 2989 return(0); 2990 } 2991 2992 /* 2993 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2994 * to the mbuf data regions directly in the transmit lists. We also save a 2995 * copy of the pointers since the transmit list fragment pointers are 2996 * physical addresses. 2997 */ 2998 2999 static void dc_start(ifp) 3000 struct ifnet *ifp; 3001 { 3002 struct dc_softc *sc; 3003 struct mbuf *m_head = NULL, *m_new; 3004 int did_defrag, idx; 3005 3006 sc = ifp->if_softc; 3007 3008 if (!sc->dc_link) 3009 return; 3010 3011 if (ifp->if_flags & IFF_OACTIVE) 3012 return; 3013 3014 idx = sc->dc_cdata.dc_tx_prod; 3015 3016 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3017 did_defrag = 0; 3018 m_head = ifq_poll(&ifp->if_snd); 3019 if (m_head == NULL) 3020 break; 3021 3022 if (sc->dc_flags & DC_TX_COALESCE && 3023 m_head->m_next != NULL) { 3024 /* 3025 * Check first if coalescing allows us to queue 3026 * the packet. We don't want to loose it if 3027 * the TX queue is full. 3028 */ 3029 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3030 idx != sc->dc_cdata.dc_tx_prod && 3031 idx == (DC_TX_LIST_CNT - 1)) { 3032 ifp->if_flags |= IFF_OACTIVE; 3033 break; 3034 } 3035 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) { 3036 ifp->if_flags |= IFF_OACTIVE; 3037 break; 3038 } 3039 3040 /* only coalesce if have >1 mbufs */ 3041 m_new = m_defrag_nofree(m_head, MB_DONTWAIT); 3042 if (m_new == NULL) { 3043 ifp->if_flags |= IFF_OACTIVE; 3044 break; 3045 } 3046 m_freem(m_head); 3047 m_head = m_new; 3048 did_defrag = 1; 3049 } 3050 3051 if (dc_encap(sc, m_head, &idx)) { 3052 if (did_defrag) { 3053 m_freem(m_head); 3054 m_new = ifq_dequeue(&ifp->if_snd); 3055 m_freem(m_new); 3056 } 3057 ifp->if_flags |= IFF_OACTIVE; 3058 break; 3059 } 3060 3061 m_new = ifq_dequeue(&ifp->if_snd); 3062 if (did_defrag) 3063 m_freem(m_new); 3064 3065 /* 3066 * If there's a BPF listener, bounce a copy of this frame 3067 * to him. 3068 */ 3069 BPF_MTAP(ifp, m_head); 3070 3071 if (sc->dc_flags & DC_TX_ONE) { 3072 ifp->if_flags |= IFF_OACTIVE; 3073 break; 3074 } 3075 } 3076 3077 /* Transmit */ 3078 sc->dc_cdata.dc_tx_prod = idx; 3079 if (!(sc->dc_flags & DC_TX_POLL)) 3080 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3081 3082 /* 3083 * Set a timeout in case the chip goes out to lunch. 3084 */ 3085 ifp->if_timer = 5; 3086 3087 return; 3088 } 3089 3090 static void dc_init(xsc) 3091 void *xsc; 3092 { 3093 struct dc_softc *sc = xsc; 3094 struct ifnet *ifp = &sc->arpcom.ac_if; 3095 struct mii_data *mii; 3096 int s; 3097 3098 s = splimp(); 3099 3100 mii = device_get_softc(sc->dc_miibus); 3101 3102 /* 3103 * Cancel pending I/O and free all RX/TX buffers. 3104 */ 3105 dc_stop(sc); 3106 dc_reset(sc); 3107 3108 /* 3109 * Set cache alignment and burst length. 3110 */ 3111 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3112 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3113 else 3114 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3115 /* 3116 * Evenly share the bus between receive and transmit process. 3117 */ 3118 if (DC_IS_INTEL(sc)) 3119 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3120 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3121 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3122 } else { 3123 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3124 } 3125 if (sc->dc_flags & DC_TX_POLL) 3126 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3127 switch(sc->dc_cachesize) { 3128 case 32: 3129 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3130 break; 3131 case 16: 3132 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3133 break; 3134 case 8: 3135 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3136 break; 3137 case 0: 3138 default: 3139 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3140 break; 3141 } 3142 3143 if (sc->dc_flags & DC_TX_STORENFWD) 3144 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3145 else { 3146 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3147 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3148 } else { 3149 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3150 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3151 } 3152 } 3153 3154 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3155 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3156 3157 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3158 /* 3159 * The app notes for the 98713 and 98715A say that 3160 * in order to have the chips operate properly, a magic 3161 * number must be written to CSR16. Macronix does not 3162 * document the meaning of these bits so there's no way 3163 * to know exactly what they do. The 98713 has a magic 3164 * number all its own; the rest all use a different one. 3165 */ 3166 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3167 if (sc->dc_type == DC_TYPE_98713) 3168 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3169 else 3170 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3171 } 3172 3173 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3174 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3175 3176 /* Init circular RX list. */ 3177 if (dc_list_rx_init(sc) == ENOBUFS) { 3178 printf("dc%d: initialization failed: no " 3179 "memory for rx buffers\n", sc->dc_unit); 3180 dc_stop(sc); 3181 (void)splx(s); 3182 return; 3183 } 3184 3185 /* 3186 * Init tx descriptors. 3187 */ 3188 dc_list_tx_init(sc); 3189 3190 /* 3191 * Load the address of the RX list. 3192 */ 3193 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3194 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3195 3196 /* 3197 * Enable interrupts. 3198 */ 3199 #ifdef DEVICE_POLLING 3200 /* 3201 * ... but only if we are not polling, and make sure they are off in 3202 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3203 * after a reset. 3204 */ 3205 if (ifp->if_flags & IFF_POLLING) 3206 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3207 else 3208 #endif 3209 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3210 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3211 3212 /* Enable transmitter. */ 3213 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3214 3215 /* 3216 * If this is an Intel 21143 and we're not using the 3217 * MII port, program the LED control pins so we get 3218 * link and activity indications. 3219 */ 3220 if (sc->dc_flags & DC_TULIP_LEDS) { 3221 CSR_WRITE_4(sc, DC_WATCHDOG, 3222 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3223 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3224 } 3225 3226 /* 3227 * Load the RX/multicast filter. We do this sort of late 3228 * because the filter programming scheme on the 21143 and 3229 * some clones requires DMAing a setup frame via the TX 3230 * engine, and we need the transmitter enabled for that. 3231 */ 3232 dc_setfilt(sc); 3233 3234 /* Enable receiver. */ 3235 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3236 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3237 3238 mii_mediachg(mii); 3239 dc_setcfg(sc, sc->dc_if_media); 3240 3241 ifp->if_flags |= IFF_RUNNING; 3242 ifp->if_flags &= ~IFF_OACTIVE; 3243 3244 (void)splx(s); 3245 3246 /* Don't start the ticker if this is a homePNA link. */ 3247 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3248 sc->dc_link = 1; 3249 else { 3250 if (sc->dc_flags & DC_21143_NWAY) 3251 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc); 3252 else 3253 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 3254 } 3255 3256 return; 3257 } 3258 3259 /* 3260 * Set media options. 3261 */ 3262 static int dc_ifmedia_upd(ifp) 3263 struct ifnet *ifp; 3264 { 3265 struct dc_softc *sc; 3266 struct mii_data *mii; 3267 struct ifmedia *ifm; 3268 3269 sc = ifp->if_softc; 3270 mii = device_get_softc(sc->dc_miibus); 3271 mii_mediachg(mii); 3272 ifm = &mii->mii_media; 3273 3274 if (DC_IS_DAVICOM(sc) && 3275 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3276 dc_setcfg(sc, ifm->ifm_media); 3277 else 3278 sc->dc_link = 0; 3279 3280 return(0); 3281 } 3282 3283 /* 3284 * Report current media status. 3285 */ 3286 static void dc_ifmedia_sts(ifp, ifmr) 3287 struct ifnet *ifp; 3288 struct ifmediareq *ifmr; 3289 { 3290 struct dc_softc *sc; 3291 struct mii_data *mii; 3292 struct ifmedia *ifm; 3293 3294 sc = ifp->if_softc; 3295 mii = device_get_softc(sc->dc_miibus); 3296 mii_pollstat(mii); 3297 ifm = &mii->mii_media; 3298 if (DC_IS_DAVICOM(sc)) { 3299 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3300 ifmr->ifm_active = ifm->ifm_media; 3301 ifmr->ifm_status = 0; 3302 return; 3303 } 3304 } 3305 ifmr->ifm_active = mii->mii_media_active; 3306 ifmr->ifm_status = mii->mii_media_status; 3307 3308 return; 3309 } 3310 3311 static int dc_ioctl(ifp, command, data, cr) 3312 struct ifnet *ifp; 3313 u_long command; 3314 caddr_t data; 3315 struct ucred *cr; 3316 { 3317 struct dc_softc *sc = ifp->if_softc; 3318 struct ifreq *ifr = (struct ifreq *) data; 3319 struct mii_data *mii; 3320 int s, error = 0; 3321 3322 s = splimp(); 3323 3324 switch(command) { 3325 case SIOCSIFADDR: 3326 case SIOCGIFADDR: 3327 case SIOCSIFMTU: 3328 error = ether_ioctl(ifp, command, data); 3329 break; 3330 case SIOCSIFFLAGS: 3331 if (ifp->if_flags & IFF_UP) { 3332 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3333 (IFF_PROMISC | IFF_ALLMULTI); 3334 if (ifp->if_flags & IFF_RUNNING) { 3335 if (need_setfilt) 3336 dc_setfilt(sc); 3337 } else { 3338 sc->dc_txthresh = 0; 3339 dc_init(sc); 3340 } 3341 } else { 3342 if (ifp->if_flags & IFF_RUNNING) 3343 dc_stop(sc); 3344 } 3345 sc->dc_if_flags = ifp->if_flags; 3346 error = 0; 3347 break; 3348 case SIOCADDMULTI: 3349 case SIOCDELMULTI: 3350 dc_setfilt(sc); 3351 error = 0; 3352 break; 3353 case SIOCGIFMEDIA: 3354 case SIOCSIFMEDIA: 3355 mii = device_get_softc(sc->dc_miibus); 3356 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3357 break; 3358 default: 3359 error = EINVAL; 3360 break; 3361 } 3362 3363 (void)splx(s); 3364 3365 return(error); 3366 } 3367 3368 static void dc_watchdog(ifp) 3369 struct ifnet *ifp; 3370 { 3371 struct dc_softc *sc; 3372 3373 sc = ifp->if_softc; 3374 3375 ifp->if_oerrors++; 3376 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3377 3378 dc_stop(sc); 3379 dc_reset(sc); 3380 dc_init(sc); 3381 3382 if (!ifq_is_empty(&ifp->if_snd)) 3383 dc_start(ifp); 3384 3385 return; 3386 } 3387 3388 /* 3389 * Stop the adapter and free any mbufs allocated to the 3390 * RX and TX lists. 3391 */ 3392 static void dc_stop(sc) 3393 struct dc_softc *sc; 3394 { 3395 int i; 3396 struct ifnet *ifp; 3397 3398 ifp = &sc->arpcom.ac_if; 3399 ifp->if_timer = 0; 3400 3401 callout_stop(&sc->dc_stat_timer); 3402 3403 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3404 #ifdef DEVICE_POLLING 3405 ether_poll_deregister(ifp); 3406 #endif 3407 3408 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3409 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3410 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3411 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3412 sc->dc_link = 0; 3413 3414 /* 3415 * Free data in the RX lists. 3416 */ 3417 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3418 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3419 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3420 sc->dc_cdata.dc_rx_chain[i] = NULL; 3421 } 3422 } 3423 bzero((char *)&sc->dc_ldata->dc_rx_list, 3424 sizeof(sc->dc_ldata->dc_rx_list)); 3425 3426 /* 3427 * Free the TX list buffers. 3428 */ 3429 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3430 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3431 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl & 3432 DC_TXCTL_SETUP) || 3433 !(sc->dc_ldata->dc_tx_list[i].dc_ctl & 3434 DC_TXCTL_LASTFRAG)) { 3435 sc->dc_cdata.dc_tx_chain[i] = NULL; 3436 continue; 3437 } 3438 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3439 sc->dc_cdata.dc_tx_chain[i] = NULL; 3440 } 3441 } 3442 3443 bzero((char *)&sc->dc_ldata->dc_tx_list, 3444 sizeof(sc->dc_ldata->dc_tx_list)); 3445 3446 return; 3447 } 3448 3449 /* 3450 * Stop all chip I/O so that the kernel's probe routines don't 3451 * get confused by errant DMAs when rebooting. 3452 */ 3453 static void dc_shutdown(dev) 3454 device_t dev; 3455 { 3456 struct dc_softc *sc; 3457 3458 sc = device_get_softc(dev); 3459 3460 dc_stop(sc); 3461 3462 return; 3463 } 3464 3465 /* 3466 * Device suspend routine. Stop the interface and save some PCI 3467 * settings in case the BIOS doesn't restore them properly on 3468 * resume. 3469 */ 3470 static int dc_suspend(dev) 3471 device_t dev; 3472 { 3473 int i; 3474 int s; 3475 struct dc_softc *sc; 3476 3477 s = splimp(); 3478 3479 sc = device_get_softc(dev); 3480 3481 dc_stop(sc); 3482 3483 for (i = 0; i < 5; i++) 3484 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3485 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3486 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3487 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3488 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3489 3490 sc->suspended = 1; 3491 3492 splx(s); 3493 return (0); 3494 } 3495 3496 /* 3497 * Device resume routine. Restore some PCI settings in case the BIOS 3498 * doesn't, re-enable busmastering, and restart the interface if 3499 * appropriate. 3500 */ 3501 static int dc_resume(dev) 3502 device_t dev; 3503 { 3504 int i; 3505 int s; 3506 struct dc_softc *sc; 3507 struct ifnet *ifp; 3508 3509 s = splimp(); 3510 3511 sc = device_get_softc(dev); 3512 ifp = &sc->arpcom.ac_if; 3513 3514 dc_acpi(dev); 3515 3516 /* better way to do this? */ 3517 for (i = 0; i < 5; i++) 3518 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3519 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3520 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3521 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3522 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3523 3524 /* reenable busmastering */ 3525 pci_enable_busmaster(dev); 3526 pci_enable_io(dev, DC_RES); 3527 3528 /* reinitialize interface if necessary */ 3529 if (ifp->if_flags & IFF_UP) 3530 dc_init(sc); 3531 3532 sc->suspended = 0; 3533 3534 splx(s); 3535 return (0); 3536 } 3537