1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $ 34 */ 35 36 /* 37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Engineer, Wind River Systems 41 */ 42 43 /* 44 * The Broadcom BCM5700 is based on technology originally developed by 45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 49 * frames, highly configurable RX filtering, and 16 RX and TX queues 50 * (which, along with RX filter rules, can be used for QOS applications). 51 * Other features, such as TCP segmentation, may be available as part 52 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 53 * firmware images can be stored in hardware and need not be compiled 54 * into the driver. 55 * 56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 58 * 59 * The BCM5701 is a single-chip solution incorporating both the BCM5700 60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 61 * does not support external SSRAM. 62 * 63 * Broadcom also produces a variation of the BCM5700 under the "Altima" 64 * brand name, which is functionally similar but lacks PCI-X support. 65 * 66 * Without external SSRAM, you can only have at most 4 TX rings, 67 * and the use of the mini RX ring is disabled. This seems to imply 68 * that these features are simply not available on the BCM5701. As a 69 * result, this driver does not implement any support for the mini RX 70 * ring. 71 */ 72 73 #include "opt_ifpoll.h" 74 75 #include <sys/param.h> 76 #include <sys/bus.h> 77 #include <sys/endian.h> 78 #include <sys/kernel.h> 79 #include <sys/ktr.h> 80 #include <sys/interrupt.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/queue.h> 84 #include <sys/rman.h> 85 #include <sys/serialize.h> 86 #include <sys/socket.h> 87 #include <sys/sockio.h> 88 #include <sys/sysctl.h> 89 90 #include <netinet/ip.h> 91 #include <netinet/tcp.h> 92 93 #include <net/bpf.h> 94 #include <net/ethernet.h> 95 #include <net/if.h> 96 #include <net/if_arp.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 #include <net/if_poll.h> 100 #include <net/if_types.h> 101 #include <net/ifq_var.h> 102 #include <net/vlan/if_vlan_var.h> 103 #include <net/vlan/if_vlan_ether.h> 104 105 #include <dev/netif/mii_layer/mii.h> 106 #include <dev/netif/mii_layer/miivar.h> 107 #include <dev/netif/mii_layer/brgphyreg.h> 108 109 #include "pcidevs.h" 110 #include <bus/pci/pcireg.h> 111 #include <bus/pci/pcivar.h> 112 113 #include <dev/netif/bge/if_bgereg.h> 114 #include <dev/netif/bge/if_bgevar.h> 115 116 /* "device miibus" required. See GENERIC if you get errors here. */ 117 #include "miibus_if.h" 118 119 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 120 121 #define BGE_RESET_SHUTDOWN 0 122 #define BGE_RESET_START 1 123 #define BGE_RESET_SUSPEND 2 124 125 static const struct bge_type { 126 uint16_t bge_vid; 127 uint16_t bge_did; 128 char *bge_name; 129 } bge_devs[] = { 130 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996, 131 "3COM 3C996 Gigabit Ethernet" }, 132 133 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700, 134 "Alteon BCM5700 Gigabit Ethernet" }, 135 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701, 136 "Alteon BCM5701 Gigabit Ethernet" }, 137 138 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000, 139 "Altima AC1000 Gigabit Ethernet" }, 140 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001, 141 "Altima AC1002 Gigabit Ethernet" }, 142 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100, 143 "Altima AC9100 Gigabit Ethernet" }, 144 145 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701, 146 "Apple BCM5701 Gigabit Ethernet" }, 147 148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700, 149 "Broadcom BCM5700 Gigabit Ethernet" }, 150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701, 151 "Broadcom BCM5701 Gigabit Ethernet" }, 152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702, 153 "Broadcom BCM5702 Gigabit Ethernet" }, 154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X, 155 "Broadcom BCM5702X Gigabit Ethernet" }, 156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT, 157 "Broadcom BCM5702 Gigabit Ethernet" }, 158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703, 159 "Broadcom BCM5703 Gigabit Ethernet" }, 160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X, 161 "Broadcom BCM5703X Gigabit Ethernet" }, 162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3, 163 "Broadcom BCM5703 Gigabit Ethernet" }, 164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C, 165 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S, 167 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT, 169 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705, 171 "Broadcom BCM5705 Gigabit Ethernet" }, 172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F, 173 "Broadcom BCM5705F Gigabit Ethernet" }, 174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K, 175 "Broadcom BCM5705K Gigabit Ethernet" }, 176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M, 177 "Broadcom BCM5705M Gigabit Ethernet" }, 178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 179 "Broadcom BCM5705M Gigabit Ethernet" }, 180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714, 181 "Broadcom BCM5714C Gigabit Ethernet" }, 182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S, 183 "Broadcom BCM5714S Gigabit Ethernet" }, 184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715, 185 "Broadcom BCM5715 Gigabit Ethernet" }, 186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S, 187 "Broadcom BCM5715S Gigabit Ethernet" }, 188 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720, 189 "Broadcom BCM5720 Gigabit Ethernet" }, 190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721, 191 "Broadcom BCM5721 Gigabit Ethernet" }, 192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722, 193 "Broadcom BCM5722 Gigabit Ethernet" }, 194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723, 195 "Broadcom BCM5723 Gigabit Ethernet" }, 196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750, 197 "Broadcom BCM5750 Gigabit Ethernet" }, 198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M, 199 "Broadcom BCM5750M Gigabit Ethernet" }, 200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751, 201 "Broadcom BCM5751 Gigabit Ethernet" }, 202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F, 203 "Broadcom BCM5751F Gigabit Ethernet" }, 204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M, 205 "Broadcom BCM5751M Gigabit Ethernet" }, 206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752, 207 "Broadcom BCM5752 Gigabit Ethernet" }, 208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M, 209 "Broadcom BCM5752M Gigabit Ethernet" }, 210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753, 211 "Broadcom BCM5753 Gigabit Ethernet" }, 212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F, 213 "Broadcom BCM5753F Gigabit Ethernet" }, 214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M, 215 "Broadcom BCM5753M Gigabit Ethernet" }, 216 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754, 217 "Broadcom BCM5754 Gigabit Ethernet" }, 218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M, 219 "Broadcom BCM5754M Gigabit Ethernet" }, 220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755, 221 "Broadcom BCM5755 Gigabit Ethernet" }, 222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M, 223 "Broadcom BCM5755M Gigabit Ethernet" }, 224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756, 225 "Broadcom BCM5756 Gigabit Ethernet" }, 226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761, 227 "Broadcom BCM5761 Gigabit Ethernet" }, 228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E, 229 "Broadcom BCM5761E Gigabit Ethernet" }, 230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S, 231 "Broadcom BCM5761S Gigabit Ethernet" }, 232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE, 233 "Broadcom BCM5761SE Gigabit Ethernet" }, 234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764, 235 "Broadcom BCM5764 Gigabit Ethernet" }, 236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780, 237 "Broadcom BCM5780 Gigabit Ethernet" }, 238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S, 239 "Broadcom BCM5780S Gigabit Ethernet" }, 240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781, 241 "Broadcom BCM5781 Gigabit Ethernet" }, 242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782, 243 "Broadcom BCM5782 Gigabit Ethernet" }, 244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784, 245 "Broadcom BCM5784 Gigabit Ethernet" }, 246 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F, 247 "Broadcom BCM5785F Gigabit Ethernet" }, 248 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G, 249 "Broadcom BCM5785G Gigabit Ethernet" }, 250 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786, 251 "Broadcom BCM5786 Gigabit Ethernet" }, 252 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787, 253 "Broadcom BCM5787 Gigabit Ethernet" }, 254 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F, 255 "Broadcom BCM5787F Gigabit Ethernet" }, 256 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M, 257 "Broadcom BCM5787M Gigabit Ethernet" }, 258 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788, 259 "Broadcom BCM5788 Gigabit Ethernet" }, 260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789, 261 "Broadcom BCM5789 Gigabit Ethernet" }, 262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901, 263 "Broadcom BCM5901 Fast Ethernet" }, 264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2, 265 "Broadcom BCM5901A2 Fast Ethernet" }, 266 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M, 267 "Broadcom BCM5903M Fast Ethernet" }, 268 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906, 269 "Broadcom BCM5906 Fast Ethernet"}, 270 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M, 271 "Broadcom BCM5906M Fast Ethernet"}, 272 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760, 273 "Broadcom BCM57760 Gigabit Ethernet"}, 274 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780, 275 "Broadcom BCM57780 Gigabit Ethernet"}, 276 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788, 277 "Broadcom BCM57788 Gigabit Ethernet"}, 278 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790, 279 "Broadcom BCM57790 Gigabit Ethernet"}, 280 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 281 "SysKonnect Gigabit Ethernet" }, 282 283 { 0, 0, NULL } 284 }; 285 286 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 287 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 288 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 289 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 290 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 291 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 292 #define BGE_IS_5788(sc) ((sc)->bge_flags & BGE_FLAG_5788) 293 294 #define BGE_IS_CRIPPLED(sc) \ 295 (BGE_IS_5788((sc)) || (sc)->bge_asicrev == BGE_ASICREV_BCM5700) 296 297 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 298 299 static int bge_probe(device_t); 300 static int bge_attach(device_t); 301 static int bge_detach(device_t); 302 static void bge_txeof(struct bge_softc *, uint16_t); 303 static void bge_rxeof(struct bge_softc *, uint16_t, int); 304 305 static void bge_tick(void *); 306 static void bge_stats_update(struct bge_softc *); 307 static void bge_stats_update_regs(struct bge_softc *); 308 static struct mbuf * 309 bge_defrag_shortdma(struct mbuf *); 310 static int bge_encap(struct bge_softc *, struct mbuf **, 311 uint32_t *, int *); 312 static void bge_xmit(struct bge_softc *, uint32_t); 313 static int bge_setup_tso(struct bge_softc *, struct mbuf **, 314 uint16_t *, uint16_t *); 315 316 #ifdef IFPOLL_ENABLE 317 static void bge_npoll(struct ifnet *, struct ifpoll_info *); 318 static void bge_npoll_compat(struct ifnet *, void *, int ); 319 #endif 320 static void bge_intr_crippled(void *); 321 static void bge_intr_legacy(void *); 322 static void bge_msi(void *); 323 static void bge_msi_oneshot(void *); 324 static void bge_intr(struct bge_softc *); 325 static void bge_enable_intr(struct bge_softc *); 326 static void bge_disable_intr(struct bge_softc *); 327 static void bge_start(struct ifnet *, struct ifaltq_subque *); 328 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 329 static void bge_init(void *); 330 static void bge_stop(struct bge_softc *); 331 static void bge_watchdog(struct ifnet *); 332 static void bge_shutdown(device_t); 333 static int bge_suspend(device_t); 334 static int bge_resume(device_t); 335 static int bge_ifmedia_upd(struct ifnet *); 336 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 337 338 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 339 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 340 341 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *); 342 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t); 343 344 static void bge_setmulti(struct bge_softc *); 345 static void bge_setpromisc(struct bge_softc *); 346 static void bge_enable_msi(struct bge_softc *sc); 347 348 static int bge_alloc_jumbo_mem(struct bge_softc *); 349 static void bge_free_jumbo_mem(struct bge_softc *); 350 static struct bge_jslot 351 *bge_jalloc(struct bge_softc *); 352 static void bge_jfree(void *); 353 static void bge_jref(void *); 354 static int bge_newbuf_std(struct bge_softc *, int, int); 355 static int bge_newbuf_jumbo(struct bge_softc *, int, int); 356 static void bge_setup_rxdesc_std(struct bge_softc *, int); 357 static void bge_setup_rxdesc_jumbo(struct bge_softc *, int); 358 static int bge_init_rx_ring_std(struct bge_softc *); 359 static void bge_free_rx_ring_std(struct bge_softc *); 360 static int bge_init_rx_ring_jumbo(struct bge_softc *); 361 static void bge_free_rx_ring_jumbo(struct bge_softc *); 362 static void bge_free_tx_ring(struct bge_softc *); 363 static int bge_init_tx_ring(struct bge_softc *); 364 365 static int bge_chipinit(struct bge_softc *); 366 static int bge_blockinit(struct bge_softc *); 367 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 368 369 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t); 370 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t); 371 #ifdef notdef 372 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t); 373 #endif 374 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t); 375 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t); 376 static void bge_writembx(struct bge_softc *, int, int); 377 378 static int bge_miibus_readreg(device_t, int, int); 379 static int bge_miibus_writereg(device_t, int, int, int); 380 static void bge_miibus_statchg(device_t); 381 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t); 382 static void bge_tbi_link_upd(struct bge_softc *, uint32_t); 383 static void bge_copper_link_upd(struct bge_softc *, uint32_t); 384 static void bge_autopoll_link_upd(struct bge_softc *, uint32_t); 385 static void bge_link_poll(struct bge_softc *); 386 387 static void bge_reset(struct bge_softc *); 388 389 static int bge_dma_alloc(struct bge_softc *); 390 static void bge_dma_free(struct bge_softc *); 391 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t, 392 bus_dma_tag_t *, bus_dmamap_t *, 393 void **, bus_addr_t *); 394 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *); 395 396 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 397 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 398 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 399 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 400 401 static void bge_coal_change(struct bge_softc *); 402 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS); 403 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS); 404 static int bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS); 405 static int bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS); 406 static int bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS); 407 static int bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS); 408 static int bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS); 409 static int bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS); 410 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, 411 int, int, uint32_t); 412 413 static void bge_sig_post_reset(struct bge_softc *, int); 414 static void bge_sig_legacy(struct bge_softc *, int); 415 static void bge_sig_pre_reset(struct bge_softc *, int); 416 static void bge_stop_fw(struct bge_softc *); 417 static void bge_asf_driver_up(struct bge_softc *); 418 419 /* 420 * Set following tunable to 1 for some IBM blade servers with the DNLK 421 * switch module. Auto negotiation is broken for those configurations. 422 */ 423 static int bge_fake_autoneg = 0; 424 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg); 425 426 static int bge_msi_enable = 1; 427 TUNABLE_INT("hw.bge.msi.enable", &bge_msi_enable); 428 429 static int bge_allow_asf = 1; 430 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 431 432 #if !defined(KTR_IF_BGE) 433 #define KTR_IF_BGE KTR_ALL 434 #endif 435 KTR_INFO_MASTER(if_bge); 436 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr"); 437 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt"); 438 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt"); 439 #define logif(name) KTR_LOG(if_bge_ ## name) 440 441 static device_method_t bge_methods[] = { 442 /* Device interface */ 443 DEVMETHOD(device_probe, bge_probe), 444 DEVMETHOD(device_attach, bge_attach), 445 DEVMETHOD(device_detach, bge_detach), 446 DEVMETHOD(device_shutdown, bge_shutdown), 447 DEVMETHOD(device_suspend, bge_suspend), 448 DEVMETHOD(device_resume, bge_resume), 449 450 /* bus interface */ 451 DEVMETHOD(bus_print_child, bus_generic_print_child), 452 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 453 454 /* MII interface */ 455 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 456 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 457 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 458 459 DEVMETHOD_END 460 }; 461 462 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc)); 463 static devclass_t bge_devclass; 464 465 DECLARE_DUMMY_MODULE(if_bge); 466 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL); 467 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL); 468 469 static uint32_t 470 bge_readmem_ind(struct bge_softc *sc, uint32_t off) 471 { 472 device_t dev = sc->bge_dev; 473 uint32_t val; 474 475 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 476 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 477 return 0; 478 479 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 480 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 481 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 482 return (val); 483 } 484 485 static void 486 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val) 487 { 488 device_t dev = sc->bge_dev; 489 490 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 491 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 492 return; 493 494 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 495 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 496 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 497 } 498 499 #ifdef notdef 500 static uint32_t 501 bge_readreg_ind(struct bge_softc *sc, uin32_t off) 502 { 503 device_t dev = sc->bge_dev; 504 505 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 506 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 507 } 508 #endif 509 510 static void 511 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val) 512 { 513 device_t dev = sc->bge_dev; 514 515 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 516 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 517 } 518 519 static void 520 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val) 521 { 522 CSR_WRITE_4(sc, off, val); 523 } 524 525 static void 526 bge_writembx(struct bge_softc *sc, int off, int val) 527 { 528 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 529 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 530 531 CSR_WRITE_4(sc, off, val); 532 if (sc->bge_mbox_reorder) 533 CSR_READ_4(sc, off); 534 } 535 536 static uint8_t 537 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 538 { 539 uint32_t access, byte = 0; 540 int i; 541 542 /* Lock. */ 543 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 544 for (i = 0; i < 8000; i++) { 545 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 546 break; 547 DELAY(20); 548 } 549 if (i == 8000) 550 return (1); 551 552 /* Enable access. */ 553 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 554 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 555 556 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 557 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 558 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 559 DELAY(10); 560 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 561 DELAY(10); 562 break; 563 } 564 } 565 566 if (i == BGE_TIMEOUT * 10) { 567 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n"); 568 return (1); 569 } 570 571 /* Get result. */ 572 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 573 574 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 575 576 /* Disable access. */ 577 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 578 579 /* Unlock. */ 580 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 581 CSR_READ_4(sc, BGE_NVRAM_SWARB); 582 583 return (0); 584 } 585 586 /* 587 * Read a sequence of bytes from NVRAM. 588 */ 589 static int 590 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 591 { 592 int err = 0, i; 593 uint8_t byte = 0; 594 595 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 596 return (1); 597 598 for (i = 0; i < cnt; i++) { 599 err = bge_nvram_getbyte(sc, off + i, &byte); 600 if (err) 601 break; 602 *(dest + i) = byte; 603 } 604 605 return (err ? 1 : 0); 606 } 607 608 /* 609 * Read a byte of data stored in the EEPROM at address 'addr.' The 610 * BCM570x supports both the traditional bitbang interface and an 611 * auto access interface for reading the EEPROM. We use the auto 612 * access method. 613 */ 614 static uint8_t 615 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest) 616 { 617 int i; 618 uint32_t byte = 0; 619 620 /* 621 * Enable use of auto EEPROM access so we can avoid 622 * having to use the bitbang method. 623 */ 624 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 625 626 /* Reset the EEPROM, load the clock period. */ 627 CSR_WRITE_4(sc, BGE_EE_ADDR, 628 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 629 DELAY(20); 630 631 /* Issue the read EEPROM command. */ 632 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 633 634 /* Wait for completion */ 635 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 636 DELAY(10); 637 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 638 break; 639 } 640 641 if (i == BGE_TIMEOUT) { 642 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n"); 643 return(1); 644 } 645 646 /* Get result. */ 647 byte = CSR_READ_4(sc, BGE_EE_DATA); 648 649 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 650 651 return(0); 652 } 653 654 /* 655 * Read a sequence of bytes from the EEPROM. 656 */ 657 static int 658 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len) 659 { 660 size_t i; 661 int err; 662 uint8_t byte; 663 664 for (byte = 0, err = 0, i = 0; i < len; i++) { 665 err = bge_eeprom_getbyte(sc, off + i, &byte); 666 if (err) 667 break; 668 *(dest + i) = byte; 669 } 670 671 return(err ? 1 : 0); 672 } 673 674 static int 675 bge_miibus_readreg(device_t dev, int phy, int reg) 676 { 677 struct bge_softc *sc = device_get_softc(dev); 678 uint32_t val; 679 int i; 680 681 KASSERT(phy == sc->bge_phyno, 682 ("invalid phyno %d, should be %d", phy, sc->bge_phyno)); 683 684 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 685 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 686 CSR_WRITE_4(sc, BGE_MI_MODE, 687 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 688 DELAY(80); 689 } 690 691 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 692 BGE_MIPHY(phy) | BGE_MIREG(reg)); 693 694 /* Poll for the PHY register access to complete. */ 695 for (i = 0; i < BGE_TIMEOUT; i++) { 696 DELAY(10); 697 val = CSR_READ_4(sc, BGE_MI_COMM); 698 if ((val & BGE_MICOMM_BUSY) == 0) { 699 DELAY(5); 700 val = CSR_READ_4(sc, BGE_MI_COMM); 701 break; 702 } 703 } 704 if (i == BGE_TIMEOUT) { 705 if_printf(&sc->arpcom.ac_if, "PHY read timed out " 706 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val); 707 val = 0; 708 } 709 710 /* Restore the autopoll bit if necessary. */ 711 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 712 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 713 DELAY(80); 714 } 715 716 if (val & BGE_MICOMM_READFAIL) 717 return 0; 718 719 return (val & 0xFFFF); 720 } 721 722 static int 723 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 724 { 725 struct bge_softc *sc = device_get_softc(dev); 726 int i; 727 728 KASSERT(phy == sc->bge_phyno, 729 ("invalid phyno %d, should be %d", phy, sc->bge_phyno)); 730 731 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 732 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 733 return 0; 734 735 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 736 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 737 CSR_WRITE_4(sc, BGE_MI_MODE, 738 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 739 DELAY(80); 740 } 741 742 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 743 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 744 745 for (i = 0; i < BGE_TIMEOUT; i++) { 746 DELAY(10); 747 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 748 DELAY(5); 749 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 750 break; 751 } 752 } 753 if (i == BGE_TIMEOUT) { 754 if_printf(&sc->arpcom.ac_if, "PHY write timed out " 755 "(phy %d, reg %d, val %d)\n", phy, reg, val); 756 } 757 758 /* Restore the autopoll bit if necessary. */ 759 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 760 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 761 DELAY(80); 762 } 763 764 return 0; 765 } 766 767 static void 768 bge_miibus_statchg(device_t dev) 769 { 770 struct bge_softc *sc; 771 struct mii_data *mii; 772 773 sc = device_get_softc(dev); 774 if ((sc->arpcom.ac_if.if_flags & IFF_RUNNING) == 0) 775 return; 776 777 mii = device_get_softc(sc->bge_miibus); 778 779 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 780 (IFM_ACTIVE | IFM_AVALID)) { 781 switch (IFM_SUBTYPE(mii->mii_media_active)) { 782 case IFM_10_T: 783 case IFM_100_TX: 784 sc->bge_link = 1; 785 break; 786 case IFM_1000_T: 787 case IFM_1000_SX: 788 case IFM_2500_SX: 789 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 790 sc->bge_link = 1; 791 else 792 sc->bge_link = 0; 793 break; 794 default: 795 sc->bge_link = 0; 796 break; 797 } 798 } else { 799 sc->bge_link = 0; 800 } 801 if (sc->bge_link == 0) 802 return; 803 804 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 805 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 806 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 807 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 808 } else { 809 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 810 } 811 812 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 813 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 814 } else { 815 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 816 } 817 } 818 819 /* 820 * Memory management for jumbo frames. 821 */ 822 static int 823 bge_alloc_jumbo_mem(struct bge_softc *sc) 824 { 825 struct ifnet *ifp = &sc->arpcom.ac_if; 826 struct bge_jslot *entry; 827 uint8_t *ptr; 828 bus_addr_t paddr; 829 int i, error; 830 831 /* 832 * Create tag for jumbo mbufs. 833 * This is really a bit of a kludge. We allocate a special 834 * jumbo buffer pool which (thanks to the way our DMA 835 * memory allocation works) will consist of contiguous 836 * pages. This means that even though a jumbo buffer might 837 * be larger than a page size, we don't really need to 838 * map it into more than one DMA segment. However, the 839 * default mbuf tag will result in multi-segment mappings, 840 * so we have to create a special jumbo mbuf tag that 841 * lets us get away with mapping the jumbo buffers as 842 * a single segment. I think eventually the driver should 843 * be changed so that it uses ordinary mbufs and cluster 844 * buffers, i.e. jumbo frames can span multiple DMA 845 * descriptors. But that's a project for another day. 846 */ 847 848 /* 849 * Create DMA stuffs for jumbo RX ring. 850 */ 851 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ, 852 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 853 &sc->bge_cdata.bge_rx_jumbo_ring_map, 854 (void *)&sc->bge_ldata.bge_rx_jumbo_ring, 855 &sc->bge_ldata.bge_rx_jumbo_ring_paddr); 856 if (error) { 857 if_printf(ifp, "could not create jumbo RX ring\n"); 858 return error; 859 } 860 861 /* 862 * Create DMA stuffs for jumbo buffer block. 863 */ 864 error = bge_dma_block_alloc(sc, BGE_JMEM, 865 &sc->bge_cdata.bge_jumbo_tag, 866 &sc->bge_cdata.bge_jumbo_map, 867 (void **)&sc->bge_ldata.bge_jumbo_buf, 868 &paddr); 869 if (error) { 870 if_printf(ifp, "could not create jumbo buffer\n"); 871 return error; 872 } 873 874 SLIST_INIT(&sc->bge_jfree_listhead); 875 876 /* 877 * Now divide it up into 9K pieces and save the addresses 878 * in an array. Note that we play an evil trick here by using 879 * the first few bytes in the buffer to hold the the address 880 * of the softc structure for this interface. This is because 881 * bge_jfree() needs it, but it is called by the mbuf management 882 * code which will not pass it to us explicitly. 883 */ 884 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) { 885 entry = &sc->bge_cdata.bge_jslots[i]; 886 entry->bge_sc = sc; 887 entry->bge_buf = ptr; 888 entry->bge_paddr = paddr; 889 entry->bge_inuse = 0; 890 entry->bge_slot = i; 891 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link); 892 893 ptr += BGE_JLEN; 894 paddr += BGE_JLEN; 895 } 896 return 0; 897 } 898 899 static void 900 bge_free_jumbo_mem(struct bge_softc *sc) 901 { 902 /* Destroy jumbo RX ring. */ 903 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 904 sc->bge_cdata.bge_rx_jumbo_ring_map, 905 sc->bge_ldata.bge_rx_jumbo_ring); 906 907 /* Destroy jumbo buffer block. */ 908 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag, 909 sc->bge_cdata.bge_jumbo_map, 910 sc->bge_ldata.bge_jumbo_buf); 911 } 912 913 /* 914 * Allocate a jumbo buffer. 915 */ 916 static struct bge_jslot * 917 bge_jalloc(struct bge_softc *sc) 918 { 919 struct bge_jslot *entry; 920 921 lwkt_serialize_enter(&sc->bge_jslot_serializer); 922 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 923 if (entry) { 924 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link); 925 entry->bge_inuse = 1; 926 } else { 927 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n"); 928 } 929 lwkt_serialize_exit(&sc->bge_jslot_serializer); 930 return(entry); 931 } 932 933 /* 934 * Adjust usage count on a jumbo buffer. 935 */ 936 static void 937 bge_jref(void *arg) 938 { 939 struct bge_jslot *entry = (struct bge_jslot *)arg; 940 struct bge_softc *sc = entry->bge_sc; 941 942 if (sc == NULL) 943 panic("bge_jref: can't find softc pointer!"); 944 945 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) { 946 panic("bge_jref: asked to reference buffer " 947 "that we don't manage!"); 948 } else if (entry->bge_inuse == 0) { 949 panic("bge_jref: buffer already free!"); 950 } else { 951 atomic_add_int(&entry->bge_inuse, 1); 952 } 953 } 954 955 /* 956 * Release a jumbo buffer. 957 */ 958 static void 959 bge_jfree(void *arg) 960 { 961 struct bge_jslot *entry = (struct bge_jslot *)arg; 962 struct bge_softc *sc = entry->bge_sc; 963 964 if (sc == NULL) 965 panic("bge_jfree: can't find softc pointer!"); 966 967 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) { 968 panic("bge_jfree: asked to free buffer that we don't manage!"); 969 } else if (entry->bge_inuse == 0) { 970 panic("bge_jfree: buffer already free!"); 971 } else { 972 /* 973 * Possible MP race to 0, use the serializer. The atomic insn 974 * is still needed for races against bge_jref(). 975 */ 976 lwkt_serialize_enter(&sc->bge_jslot_serializer); 977 atomic_subtract_int(&entry->bge_inuse, 1); 978 if (entry->bge_inuse == 0) { 979 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 980 entry, jslot_link); 981 } 982 lwkt_serialize_exit(&sc->bge_jslot_serializer); 983 } 984 } 985 986 987 /* 988 * Intialize a standard receive ring descriptor. 989 */ 990 static int 991 bge_newbuf_std(struct bge_softc *sc, int i, int init) 992 { 993 struct mbuf *m_new = NULL; 994 bus_dma_segment_t seg; 995 bus_dmamap_t map; 996 int error, nsegs; 997 998 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 999 if (m_new == NULL) 1000 return ENOBUFS; 1001 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1002 1003 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1004 m_adj(m_new, ETHER_ALIGN); 1005 1006 error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag, 1007 sc->bge_cdata.bge_rx_tmpmap, m_new, 1008 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1009 if (error) { 1010 m_freem(m_new); 1011 return error; 1012 } 1013 1014 if (!init) { 1015 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1016 sc->bge_cdata.bge_rx_std_dmamap[i], 1017 BUS_DMASYNC_POSTREAD); 1018 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1019 sc->bge_cdata.bge_rx_std_dmamap[i]); 1020 } 1021 1022 map = sc->bge_cdata.bge_rx_tmpmap; 1023 sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i]; 1024 sc->bge_cdata.bge_rx_std_dmamap[i] = map; 1025 1026 sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new; 1027 sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr; 1028 1029 bge_setup_rxdesc_std(sc, i); 1030 return 0; 1031 } 1032 1033 static void 1034 bge_setup_rxdesc_std(struct bge_softc *sc, int i) 1035 { 1036 struct bge_rxchain *rc; 1037 struct bge_rx_bd *r; 1038 1039 rc = &sc->bge_cdata.bge_rx_std_chain[i]; 1040 r = &sc->bge_ldata.bge_rx_std_ring[i]; 1041 1042 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr); 1043 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr); 1044 r->bge_len = rc->bge_mbuf->m_len; 1045 r->bge_idx = i; 1046 r->bge_flags = BGE_RXBDFLAG_END; 1047 } 1048 1049 /* 1050 * Initialize a jumbo receive ring descriptor. This allocates 1051 * a jumbo buffer from the pool managed internally by the driver. 1052 */ 1053 static int 1054 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init) 1055 { 1056 struct mbuf *m_new = NULL; 1057 struct bge_jslot *buf; 1058 bus_addr_t paddr; 1059 1060 /* Allocate the mbuf. */ 1061 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 1062 if (m_new == NULL) 1063 return ENOBUFS; 1064 1065 /* Allocate the jumbo buffer */ 1066 buf = bge_jalloc(sc); 1067 if (buf == NULL) { 1068 m_freem(m_new); 1069 return ENOBUFS; 1070 } 1071 1072 /* Attach the buffer to the mbuf. */ 1073 m_new->m_ext.ext_arg = buf; 1074 m_new->m_ext.ext_buf = buf->bge_buf; 1075 m_new->m_ext.ext_free = bge_jfree; 1076 m_new->m_ext.ext_ref = bge_jref; 1077 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1078 1079 m_new->m_flags |= M_EXT; 1080 1081 m_new->m_data = m_new->m_ext.ext_buf; 1082 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 1083 1084 paddr = buf->bge_paddr; 1085 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) { 1086 m_adj(m_new, ETHER_ALIGN); 1087 paddr += ETHER_ALIGN; 1088 } 1089 1090 /* Save necessary information */ 1091 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new; 1092 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr; 1093 1094 /* Set up the descriptor. */ 1095 bge_setup_rxdesc_jumbo(sc, i); 1096 return 0; 1097 } 1098 1099 static void 1100 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i) 1101 { 1102 struct bge_rx_bd *r; 1103 struct bge_rxchain *rc; 1104 1105 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 1106 rc = &sc->bge_cdata.bge_rx_jumbo_chain[i]; 1107 1108 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr); 1109 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr); 1110 r->bge_len = rc->bge_mbuf->m_len; 1111 r->bge_idx = i; 1112 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1113 } 1114 1115 static int 1116 bge_init_rx_ring_std(struct bge_softc *sc) 1117 { 1118 int i, error; 1119 1120 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1121 error = bge_newbuf_std(sc, i, 1); 1122 if (error) 1123 return error; 1124 } 1125 1126 sc->bge_std = BGE_STD_RX_RING_CNT - 1; 1127 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1128 1129 return(0); 1130 } 1131 1132 static void 1133 bge_free_rx_ring_std(struct bge_softc *sc) 1134 { 1135 int i; 1136 1137 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1138 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i]; 1139 1140 if (rc->bge_mbuf != NULL) { 1141 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1142 sc->bge_cdata.bge_rx_std_dmamap[i]); 1143 m_freem(rc->bge_mbuf); 1144 rc->bge_mbuf = NULL; 1145 } 1146 bzero(&sc->bge_ldata.bge_rx_std_ring[i], 1147 sizeof(struct bge_rx_bd)); 1148 } 1149 } 1150 1151 static int 1152 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1153 { 1154 struct bge_rcb *rcb; 1155 int i, error; 1156 1157 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1158 error = bge_newbuf_jumbo(sc, i, 1); 1159 if (error) 1160 return error; 1161 } 1162 1163 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1; 1164 1165 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1166 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 1167 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1168 1169 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1170 1171 return(0); 1172 } 1173 1174 static void 1175 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1176 { 1177 int i; 1178 1179 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1180 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i]; 1181 1182 if (rc->bge_mbuf != NULL) { 1183 m_freem(rc->bge_mbuf); 1184 rc->bge_mbuf = NULL; 1185 } 1186 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i], 1187 sizeof(struct bge_rx_bd)); 1188 } 1189 } 1190 1191 static void 1192 bge_free_tx_ring(struct bge_softc *sc) 1193 { 1194 int i; 1195 1196 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1197 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1198 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1199 sc->bge_cdata.bge_tx_dmamap[i]); 1200 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1201 sc->bge_cdata.bge_tx_chain[i] = NULL; 1202 } 1203 bzero(&sc->bge_ldata.bge_tx_ring[i], 1204 sizeof(struct bge_tx_bd)); 1205 } 1206 } 1207 1208 static int 1209 bge_init_tx_ring(struct bge_softc *sc) 1210 { 1211 sc->bge_txcnt = 0; 1212 sc->bge_tx_saved_considx = 0; 1213 sc->bge_tx_prodidx = 0; 1214 1215 /* Initialize transmit producer index for host-memory send ring. */ 1216 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1217 1218 /* 5700 b2 errata */ 1219 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1220 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1221 1222 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1223 /* 5700 b2 errata */ 1224 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1225 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1226 1227 return(0); 1228 } 1229 1230 static void 1231 bge_setmulti(struct bge_softc *sc) 1232 { 1233 struct ifnet *ifp; 1234 struct ifmultiaddr *ifma; 1235 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1236 int h, i; 1237 1238 ifp = &sc->arpcom.ac_if; 1239 1240 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1241 for (i = 0; i < 4; i++) 1242 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1243 return; 1244 } 1245 1246 /* First, zot all the existing filters. */ 1247 for (i = 0; i < 4; i++) 1248 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1249 1250 /* Now program new ones. */ 1251 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1252 if (ifma->ifma_addr->sa_family != AF_LINK) 1253 continue; 1254 h = ether_crc32_le( 1255 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1256 ETHER_ADDR_LEN) & 0x7f; 1257 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1258 } 1259 1260 for (i = 0; i < 4; i++) 1261 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1262 } 1263 1264 /* 1265 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1266 * self-test results. 1267 */ 1268 static int 1269 bge_chipinit(struct bge_softc *sc) 1270 { 1271 int i; 1272 uint32_t dma_rw_ctl, mode_ctl; 1273 uint16_t val; 1274 1275 /* Set endian type before we access any non-PCI registers. */ 1276 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1277 BGE_INIT | sc->bge_pci_miscctl, 4); 1278 1279 /* Clear the MAC control register */ 1280 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1281 1282 /* 1283 * Clear the MAC statistics block in the NIC's 1284 * internal memory. 1285 */ 1286 for (i = BGE_STATS_BLOCK; 1287 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1288 BGE_MEMWIN_WRITE(sc, i, 0); 1289 1290 for (i = BGE_STATUS_BLOCK; 1291 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1292 BGE_MEMWIN_WRITE(sc, i, 0); 1293 1294 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1295 /* 1296 * Fix data corruption caused by non-qword write with WB. 1297 * Fix master abort in PCI mode. 1298 * Fix PCI latency timer. 1299 */ 1300 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1301 val |= (1 << 10) | (1 << 12) | (1 << 13); 1302 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1303 } 1304 1305 /* Set up the PCI DMA control register. */ 1306 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1307 if (sc->bge_flags & BGE_FLAG_PCIE) { 1308 /* PCI-E bus */ 1309 /* DMA read watermark not used on PCI-E */ 1310 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1311 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1312 /* PCI-X bus */ 1313 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) { 1314 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1315 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1316 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1317 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5714) { 1318 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1319 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1320 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1321 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1322 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1323 uint32_t rd_wat = 0x7; 1324 uint32_t clkctl; 1325 1326 clkctl = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1327 if ((sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) && 1328 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1329 dma_rw_ctl |= 1330 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1331 } else if (clkctl == 0x6 || clkctl == 0x7) { 1332 dma_rw_ctl |= 1333 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1334 } 1335 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) 1336 rd_wat = 0x4; 1337 1338 dma_rw_ctl |= (rd_wat << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1339 (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1340 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1341 } else { 1342 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1343 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1344 dma_rw_ctl |= 0xf; 1345 } 1346 } else { 1347 /* Conventional PCI bus */ 1348 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1349 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1350 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1351 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1352 dma_rw_ctl |= 0xf; 1353 } 1354 1355 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1356 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1357 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1358 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1359 sc->bge_asicrev == BGE_ASICREV_BCM5701) { 1360 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1361 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1362 } 1363 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1364 1365 /* 1366 * Set up general mode register. 1367 */ 1368 mode_ctl = BGE_DMA_SWAP_OPTIONS| 1369 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1370 BGE_MODECTL_TX_NO_PHDR_CSUM; 1371 1372 /* 1373 * BCM5701 B5 have a bug causing data corruption when using 1374 * 64-bit DMA reads, which can be terminated early and then 1375 * completed later as 32-bit accesses, in combination with 1376 * certain bridges. 1377 */ 1378 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1379 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1380 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1381 1382 /* 1383 * Tell the firmware the driver is running 1384 */ 1385 if (sc->bge_asf_mode & ASF_STACKUP) 1386 mode_ctl |= BGE_MODECTL_STACKUP; 1387 1388 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1389 1390 /* 1391 * Disable memory write invalidate. Apparently it is not supported 1392 * properly by these devices. Also ensure that INTx isn't disabled, 1393 * as these chips need it even when using MSI. 1394 */ 1395 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1396 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4); 1397 1398 /* Set the timer prescaler (always 66Mhz) */ 1399 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1400 1401 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1402 DELAY(40); /* XXX */ 1403 1404 /* Put PHY into ready state */ 1405 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1406 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1407 DELAY(40); 1408 } 1409 1410 return(0); 1411 } 1412 1413 static int 1414 bge_blockinit(struct bge_softc *sc) 1415 { 1416 struct bge_rcb *rcb; 1417 bus_size_t vrcb; 1418 bge_hostaddr taddr; 1419 uint32_t val; 1420 int i, limit; 1421 1422 /* 1423 * Initialize the memory window pointer register so that 1424 * we can access the first 32K of internal NIC RAM. This will 1425 * allow us to set up the TX send ring RCBs and the RX return 1426 * ring RCBs, plus other things which live in NIC memory. 1427 */ 1428 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1429 1430 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1431 1432 if (!BGE_IS_5705_PLUS(sc)) { 1433 /* Configure mbuf memory pool */ 1434 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1435 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1436 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1437 else 1438 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1439 1440 /* Configure DMA resource pool */ 1441 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1442 BGE_DMA_DESCRIPTORS); 1443 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1444 } 1445 1446 /* Configure mbuf pool watermarks */ 1447 if (!BGE_IS_5705_PLUS(sc)) { 1448 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1449 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1450 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1451 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1452 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1453 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1454 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1455 } else { 1456 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1457 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1458 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1459 } 1460 1461 /* Configure DMA resource watermarks */ 1462 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1463 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1464 1465 /* Enable buffer manager */ 1466 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1467 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1468 1469 /* Poll for buffer manager start indication */ 1470 for (i = 0; i < BGE_TIMEOUT; i++) { 1471 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1472 break; 1473 DELAY(10); 1474 } 1475 1476 if (i == BGE_TIMEOUT) { 1477 if_printf(&sc->arpcom.ac_if, 1478 "buffer manager failed to start\n"); 1479 return(ENXIO); 1480 } 1481 1482 /* Enable flow-through queues */ 1483 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1484 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1485 1486 /* Wait until queue initialization is complete */ 1487 for (i = 0; i < BGE_TIMEOUT; i++) { 1488 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1489 break; 1490 DELAY(10); 1491 } 1492 1493 if (i == BGE_TIMEOUT) { 1494 if_printf(&sc->arpcom.ac_if, 1495 "flow-through queue init failed\n"); 1496 return(ENXIO); 1497 } 1498 1499 /* 1500 * Summary of rings supported by the controller: 1501 * 1502 * Standard Receive Producer Ring 1503 * - This ring is used to feed receive buffers for "standard" 1504 * sized frames (typically 1536 bytes) to the controller. 1505 * 1506 * Jumbo Receive Producer Ring 1507 * - This ring is used to feed receive buffers for jumbo sized 1508 * frames (i.e. anything bigger than the "standard" frames) 1509 * to the controller. 1510 * 1511 * Mini Receive Producer Ring 1512 * - This ring is used to feed receive buffers for "mini" 1513 * sized frames to the controller. 1514 * - This feature required external memory for the controller 1515 * but was never used in a production system. Should always 1516 * be disabled. 1517 * 1518 * Receive Return Ring 1519 * - After the controller has placed an incoming frame into a 1520 * receive buffer that buffer is moved into a receive return 1521 * ring. The driver is then responsible to passing the 1522 * buffer up to the stack. Many versions of the controller 1523 * support multiple RR rings. 1524 * 1525 * Send Ring 1526 * - This ring is used for outgoing frames. Many versions of 1527 * the controller support multiple send rings. 1528 */ 1529 1530 /* Initialize the standard receive producer ring control block. */ 1531 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1532 rcb->bge_hostaddr.bge_addr_lo = 1533 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1534 rcb->bge_hostaddr.bge_addr_hi = 1535 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1536 if (BGE_IS_5705_PLUS(sc)) { 1537 /* 1538 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 1539 * Bits 15-2 : Reserved (should be 0) 1540 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1541 * Bit 0 : Reserved 1542 */ 1543 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1544 } else { 1545 /* 1546 * Ring size is always XXX entries 1547 * Bits 31-16: Maximum RX frame size 1548 * Bits 15-2 : Reserved (should be 0) 1549 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1550 * Bit 0 : Reserved 1551 */ 1552 rcb->bge_maxlen_flags = 1553 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1554 } 1555 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1556 /* Write the standard receive producer ring control block. */ 1557 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1558 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1559 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1560 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1561 /* Reset the standard receive producer ring producer index. */ 1562 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1563 1564 /* 1565 * Initialize the jumbo RX producer ring control 1566 * block. We set the 'ring disabled' bit in the 1567 * flags field until we're actually ready to start 1568 * using this ring (i.e. once we set the MTU 1569 * high enough to require it). 1570 */ 1571 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1572 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1573 /* Get the jumbo receive producer ring RCB parameters. */ 1574 rcb->bge_hostaddr.bge_addr_lo = 1575 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1576 rcb->bge_hostaddr.bge_addr_hi = 1577 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1578 rcb->bge_maxlen_flags = 1579 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1580 BGE_RCB_FLAG_RING_DISABLED); 1581 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1582 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1583 rcb->bge_hostaddr.bge_addr_hi); 1584 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1585 rcb->bge_hostaddr.bge_addr_lo); 1586 /* Program the jumbo receive producer ring RCB parameters. */ 1587 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1588 rcb->bge_maxlen_flags); 1589 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1590 /* Reset the jumbo receive producer ring producer index. */ 1591 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1592 } 1593 1594 /* Disable the mini receive producer ring RCB. */ 1595 if (BGE_IS_5700_FAMILY(sc)) { 1596 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1597 rcb->bge_maxlen_flags = 1598 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1599 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1600 rcb->bge_maxlen_flags); 1601 /* Reset the mini receive producer ring producer index. */ 1602 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1603 } 1604 1605 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 1606 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1607 (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 1608 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 1609 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) { 1610 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 1611 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 1612 } 1613 1614 /* 1615 * The BD ring replenish thresholds control how often the 1616 * hardware fetches new BD's from the producer rings in host 1617 * memory. Setting the value too low on a busy system can 1618 * starve the hardware and recue the throughpout. 1619 * 1620 * Set the BD ring replentish thresholds. The recommended 1621 * values are 1/8th the number of descriptors allocated to 1622 * each ring. 1623 */ 1624 if (BGE_IS_5705_PLUS(sc)) 1625 val = 8; 1626 else 1627 val = BGE_STD_RX_RING_CNT / 8; 1628 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1629 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1630 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1631 BGE_JUMBO_RX_RING_CNT/8); 1632 } 1633 1634 /* 1635 * Disable all send rings by setting the 'ring disabled' bit 1636 * in the flags field of all the TX send ring control blocks, 1637 * located in NIC memory. 1638 */ 1639 if (!BGE_IS_5705_PLUS(sc)) { 1640 /* 5700 to 5704 had 16 send rings. */ 1641 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 1642 } else { 1643 limit = 1; 1644 } 1645 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1646 for (i = 0; i < limit; i++) { 1647 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1648 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1649 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1650 vrcb += sizeof(struct bge_rcb); 1651 } 1652 1653 /* Configure send ring RCB 0 (we use only the first ring) */ 1654 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1655 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1656 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1657 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1658 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1659 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1660 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1661 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1662 1663 /* 1664 * Disable all receive return rings by setting the 1665 * 'ring diabled' bit in the flags field of all the receive 1666 * return ring control blocks, located in NIC memory. 1667 */ 1668 if (!BGE_IS_5705_PLUS(sc)) 1669 limit = BGE_RX_RINGS_MAX; 1670 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755) 1671 limit = 4; 1672 else 1673 limit = 1; 1674 /* Disable all receive return rings. */ 1675 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1676 for (i = 0; i < limit; i++) { 1677 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1678 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1679 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1680 BGE_RCB_FLAG_RING_DISABLED); 1681 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1682 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1683 (i * (sizeof(uint64_t))), 0); 1684 vrcb += sizeof(struct bge_rcb); 1685 } 1686 1687 /* 1688 * Set up receive return ring 0. Note that the NIC address 1689 * for RX return rings is 0x0. The return rings live entirely 1690 * within the host, so the nicaddr field in the RCB isn't used. 1691 */ 1692 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1693 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1694 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1695 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1696 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1697 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1698 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1699 1700 /* Set random backoff seed for TX */ 1701 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1702 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1703 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1704 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1705 BGE_TX_BACKOFF_SEED_MASK); 1706 1707 /* Set inter-packet gap */ 1708 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1709 1710 /* 1711 * Specify which ring to use for packets that don't match 1712 * any RX rules. 1713 */ 1714 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1715 1716 /* 1717 * Configure number of RX lists. One interrupt distribution 1718 * list, sixteen active lists, one bad frames class. 1719 */ 1720 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1721 1722 /* Inialize RX list placement stats mask. */ 1723 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1724 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1725 1726 /* Disable host coalescing until we get it set up */ 1727 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1728 1729 /* Poll to make sure it's shut down. */ 1730 for (i = 0; i < BGE_TIMEOUT; i++) { 1731 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1732 break; 1733 DELAY(10); 1734 } 1735 1736 if (i == BGE_TIMEOUT) { 1737 if_printf(&sc->arpcom.ac_if, 1738 "host coalescing engine failed to idle\n"); 1739 return(ENXIO); 1740 } 1741 1742 /* Set up host coalescing defaults */ 1743 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1744 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1745 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds); 1746 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds); 1747 if (!BGE_IS_5705_PLUS(sc)) { 1748 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 1749 sc->bge_rx_coal_ticks_int); 1750 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 1751 sc->bge_tx_coal_ticks_int); 1752 } 1753 /* 1754 * NOTE: 1755 * The datasheet (57XX-PG105-R) says BCM5705+ do not 1756 * have following two registers; obviously it is wrong. 1757 */ 1758 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int); 1759 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int); 1760 1761 /* Set up address of statistics block */ 1762 if (!BGE_IS_5705_PLUS(sc)) { 1763 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1764 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1765 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1766 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1767 1768 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1769 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1770 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1771 } 1772 1773 /* Set up address of status block */ 1774 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 1775 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1776 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1777 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1778 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1779 1780 /* 1781 * Set up status block partail update size. 1782 * 1783 * Because only single TX ring, RX produce ring and Rx return ring 1784 * are used, ask device to update only minimum part of status block 1785 * except for BCM5700 AX/BX, whose status block partial update size 1786 * can't be configured. 1787 */ 1788 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1789 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 1790 /* XXX Actually reserved on BCM5700 AX/BX */ 1791 val = BGE_STATBLKSZ_FULL; 1792 } else { 1793 val = BGE_STATBLKSZ_32BYTE; 1794 } 1795 #if 0 1796 /* 1797 * Does not seem to have visible effect in both 1798 * bulk data (1472B UDP datagram) and tiny data 1799 * (18B UDP datagram) TX tests. 1800 */ 1801 if (!BGE_IS_CRIPPLED(sc)) 1802 val |= BGE_HCCMODE_CLRTICK_TX; 1803 #endif 1804 1805 /* Turn on host coalescing state machine */ 1806 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 1807 1808 /* Turn on RX BD completion state machine and enable attentions */ 1809 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1810 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1811 1812 /* Turn on RX list placement state machine */ 1813 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1814 1815 /* Turn on RX list selector state machine. */ 1816 if (!BGE_IS_5705_PLUS(sc)) 1817 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1818 1819 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 1820 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 1821 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 1822 BGE_MACMODE_FRMHDR_DMA_ENB; 1823 1824 if (sc->bge_flags & BGE_FLAG_TBI) 1825 val |= BGE_PORTMODE_TBI; 1826 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 1827 val |= BGE_PORTMODE_GMII; 1828 else 1829 val |= BGE_PORTMODE_MII; 1830 1831 /* Turn on DMA, clear stats */ 1832 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 1833 1834 /* Set misc. local control, enable interrupts on attentions */ 1835 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1836 1837 #ifdef notdef 1838 /* Assert GPIO pins for PHY reset */ 1839 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1840 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1841 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1842 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1843 #endif 1844 1845 /* Turn on DMA completion state machine */ 1846 if (!BGE_IS_5705_PLUS(sc)) 1847 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1848 1849 /* Turn on write DMA state machine */ 1850 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 1851 if (BGE_IS_5755_PLUS(sc)) { 1852 /* Enable host coalescing bug fix. */ 1853 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1854 } 1855 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) { 1856 /* Request larger DMA burst size to get better performance. */ 1857 val |= BGE_WDMAMODE_BURST_ALL_DATA; 1858 } 1859 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1860 DELAY(40); 1861 1862 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 1863 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1864 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1865 sc->bge_asicrev == BGE_ASICREV_BCM57780) { 1866 /* 1867 * Enable fix for read DMA FIFO overruns. 1868 * The fix is to limit the number of RX BDs 1869 * the hardware would fetch at a fime. 1870 */ 1871 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 1872 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, 1873 val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 1874 } 1875 1876 /* Turn on read DMA state machine */ 1877 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1878 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1879 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1880 sc->bge_asicrev == BGE_ASICREV_BCM57780) 1881 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1882 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1883 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 1884 if (sc->bge_flags & BGE_FLAG_PCIE) 1885 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1886 if (sc->bge_flags & BGE_FLAG_TSO) 1887 val |= BGE_RDMAMODE_TSO4_ENABLE; 1888 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1889 DELAY(40); 1890 1891 /* Turn on RX data completion state machine */ 1892 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1893 1894 /* Turn on RX BD initiator state machine */ 1895 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1896 1897 /* Turn on RX data and RX BD initiator state machine */ 1898 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1899 1900 /* Turn on Mbuf cluster free state machine */ 1901 if (!BGE_IS_5705_PLUS(sc)) 1902 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1903 1904 /* Turn on send BD completion state machine */ 1905 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1906 1907 /* Turn on send data completion state machine */ 1908 val = BGE_SDCMODE_ENABLE; 1909 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 1910 val |= BGE_SDCMODE_CDELAY; 1911 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 1912 1913 /* Turn on send data initiator state machine */ 1914 if (sc->bge_flags & BGE_FLAG_TSO) 1915 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 1916 BGE_SDIMODE_HW_LSO_PRE_DMA); 1917 else 1918 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1919 1920 /* Turn on send BD initiator state machine */ 1921 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1922 1923 /* Turn on send BD selector state machine */ 1924 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1925 1926 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1927 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1928 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1929 1930 /* ack/clear link change events */ 1931 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1932 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1933 BGE_MACSTAT_LINK_CHANGED); 1934 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1935 1936 /* 1937 * Enable attention when the link has changed state for 1938 * devices that use auto polling. 1939 */ 1940 if (sc->bge_flags & BGE_FLAG_TBI) { 1941 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1942 } else { 1943 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 1944 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1945 DELAY(80); 1946 } 1947 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1948 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 1949 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1950 BGE_EVTENB_MI_INTERRUPT); 1951 } 1952 } 1953 1954 /* 1955 * Clear any pending link state attention. 1956 * Otherwise some link state change events may be lost until attention 1957 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence. 1958 * It's not necessary on newer BCM chips - perhaps enabling link 1959 * state change attentions implies clearing pending attention. 1960 */ 1961 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1962 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1963 BGE_MACSTAT_LINK_CHANGED); 1964 1965 /* Enable link state change attentions. */ 1966 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1967 1968 return(0); 1969 } 1970 1971 /* 1972 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1973 * against our list and return its name if we find a match. Note 1974 * that since the Broadcom controller contains VPD support, we 1975 * can get the device name string from the controller itself instead 1976 * of the compiled-in string. This is a little slow, but it guarantees 1977 * we'll always announce the right product name. 1978 */ 1979 static int 1980 bge_probe(device_t dev) 1981 { 1982 const struct bge_type *t; 1983 uint16_t product, vendor; 1984 1985 product = pci_get_device(dev); 1986 vendor = pci_get_vendor(dev); 1987 1988 for (t = bge_devs; t->bge_name != NULL; t++) { 1989 if (vendor == t->bge_vid && product == t->bge_did) 1990 break; 1991 } 1992 if (t->bge_name == NULL) 1993 return(ENXIO); 1994 1995 device_set_desc(dev, t->bge_name); 1996 return(0); 1997 } 1998 1999 static int 2000 bge_attach(device_t dev) 2001 { 2002 struct ifnet *ifp; 2003 struct bge_softc *sc; 2004 uint32_t hwcfg = 0, misccfg; 2005 int error = 0, rid, capmask; 2006 uint8_t ether_addr[ETHER_ADDR_LEN]; 2007 uint16_t product, vendor; 2008 driver_intr_t *intr_func; 2009 uintptr_t mii_priv = 0; 2010 u_int intr_flags; 2011 int msi_enable; 2012 2013 sc = device_get_softc(dev); 2014 sc->bge_dev = dev; 2015 callout_init_mp(&sc->bge_stat_timer); 2016 lwkt_serialize_init(&sc->bge_jslot_serializer); 2017 2018 product = pci_get_device(dev); 2019 vendor = pci_get_vendor(dev); 2020 2021 #ifndef BURN_BRIDGES 2022 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2023 uint32_t irq, mem; 2024 2025 irq = pci_read_config(dev, PCIR_INTLINE, 4); 2026 mem = pci_read_config(dev, BGE_PCI_BAR0, 4); 2027 2028 device_printf(dev, "chip is in D%d power mode " 2029 "-- setting to D0\n", pci_get_powerstate(dev)); 2030 2031 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2032 2033 pci_write_config(dev, PCIR_INTLINE, irq, 4); 2034 pci_write_config(dev, BGE_PCI_BAR0, mem, 4); 2035 } 2036 #endif /* !BURN_BRIDGE */ 2037 2038 /* 2039 * Map control/status registers. 2040 */ 2041 pci_enable_busmaster(dev); 2042 2043 rid = BGE_PCI_BAR0; 2044 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2045 RF_ACTIVE); 2046 2047 if (sc->bge_res == NULL) { 2048 device_printf(dev, "couldn't map memory\n"); 2049 return ENXIO; 2050 } 2051 2052 sc->bge_btag = rman_get_bustag(sc->bge_res); 2053 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2054 2055 /* Save various chip information */ 2056 sc->bge_chipid = 2057 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2058 BGE_PCIMISCCTL_ASICREV_SHIFT; 2059 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2060 /* All chips, which use BGE_PCI_PRODID_ASICREV, have CPMU */ 2061 sc->bge_flags |= BGE_FLAG_CPMU; 2062 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2063 } 2064 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2065 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2066 2067 /* Save chipset family. */ 2068 switch (sc->bge_asicrev) { 2069 case BGE_ASICREV_BCM5755: 2070 case BGE_ASICREV_BCM5761: 2071 case BGE_ASICREV_BCM5784: 2072 case BGE_ASICREV_BCM5785: 2073 case BGE_ASICREV_BCM5787: 2074 case BGE_ASICREV_BCM57780: 2075 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2076 BGE_FLAG_5705_PLUS; 2077 break; 2078 2079 case BGE_ASICREV_BCM5700: 2080 case BGE_ASICREV_BCM5701: 2081 case BGE_ASICREV_BCM5703: 2082 case BGE_ASICREV_BCM5704: 2083 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2084 break; 2085 2086 case BGE_ASICREV_BCM5714_A0: 2087 case BGE_ASICREV_BCM5780: 2088 case BGE_ASICREV_BCM5714: 2089 sc->bge_flags |= BGE_FLAG_5714_FAMILY; 2090 /* Fall through */ 2091 2092 case BGE_ASICREV_BCM5750: 2093 case BGE_ASICREV_BCM5752: 2094 case BGE_ASICREV_BCM5906: 2095 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2096 /* Fall through */ 2097 2098 case BGE_ASICREV_BCM5705: 2099 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2100 break; 2101 } 2102 2103 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 2104 sc->bge_flags |= BGE_FLAG_NO_EEPROM; 2105 2106 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2107 sc->bge_flags |= BGE_FLAG_APE; 2108 2109 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 2110 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2111 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2112 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2113 sc->bge_flags |= BGE_FLAG_5788; 2114 2115 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 2116 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 2117 sc->bge_flags |= BGE_FLAG_SHORTDMA; 2118 2119 /* 2120 * Increase STD RX ring prod index by at most 8 for BCM5750, 2121 * BCM5752 and BCM5755 to workaround hardware errata. 2122 */ 2123 if (sc->bge_asicrev == BGE_ASICREV_BCM5750 || 2124 sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2125 sc->bge_asicrev == BGE_ASICREV_BCM5755) 2126 sc->bge_rx_wreg = 8; 2127 2128 /* 2129 * Check if this is a PCI-X or PCI Express device. 2130 */ 2131 if (BGE_IS_5705_PLUS(sc)) { 2132 if (pci_is_pcie(dev)) { 2133 sc->bge_flags |= BGE_FLAG_PCIE; 2134 sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev); 2135 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096); 2136 } 2137 } else { 2138 /* 2139 * Check if the device is in PCI-X Mode. 2140 * (This bit is not valid on PCI Express controllers.) 2141 */ 2142 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 2143 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2144 sc->bge_flags |= BGE_FLAG_PCIX; 2145 sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev); 2146 sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev, 2147 "mbox_reorder", 0); 2148 } 2149 } 2150 device_printf(dev, "CHIP ID 0x%08x; " 2151 "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 2152 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 2153 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" 2154 : ((sc->bge_flags & BGE_FLAG_PCIE) ? 2155 "PCI-E" : "PCI")); 2156 2157 /* 2158 * The 40bit DMA bug applies to the 5714/5715 controllers and is 2159 * not actually a MAC controller bug but an issue with the embedded 2160 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 2161 */ 2162 if ((sc->bge_flags & BGE_FLAG_PCIX) && 2163 (BGE_IS_5714_FAMILY(sc) || device_getenv_int(dev, "dma40b", 0))) 2164 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT; 2165 2166 /* 2167 * When using the BCM5701 in PCI-X mode, data corruption has 2168 * been observed in the first few bytes of some received packets. 2169 * Aligning the packet buffer in memory eliminates the corruption. 2170 * Unfortunately, this misaligns the packet payloads. On platforms 2171 * which do not support unaligned accesses, we will realign the 2172 * payloads by copying the received packets. 2173 */ 2174 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2175 (sc->bge_flags & BGE_FLAG_PCIX)) 2176 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2177 2178 if (!BGE_IS_CRIPPLED(sc)) { 2179 if (device_getenv_int(dev, "status_tag", 1)) { 2180 sc->bge_flags |= BGE_FLAG_STATUS_TAG; 2181 sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS; 2182 if (bootverbose) 2183 device_printf(dev, "enable status tag\n"); 2184 } 2185 } 2186 2187 if (BGE_IS_5755_PLUS(sc)) { 2188 /* 2189 * BCM5754 and BCM5787 shares the same ASIC id so 2190 * explicit device id check is required. 2191 * Due to unknown reason TSO does not work on BCM5755M. 2192 */ 2193 if (product != PCI_PRODUCT_BROADCOM_BCM5754 && 2194 product != PCI_PRODUCT_BROADCOM_BCM5754M && 2195 product != PCI_PRODUCT_BROADCOM_BCM5755M) 2196 sc->bge_flags |= BGE_FLAG_TSO; 2197 } 2198 2199 /* 2200 * Set various PHY quirk flags. 2201 */ 2202 2203 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 || 2204 sc->bge_asicrev == BGE_ASICREV_BCM5701) && 2205 pci_get_subvendor(dev) == PCI_VENDOR_DELL) 2206 mii_priv |= BRGPHY_FLAG_NO_3LED; 2207 2208 capmask = MII_CAPMASK_DEFAULT; 2209 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 2210 (misccfg == 0x4000 || misccfg == 0x8000)) || 2211 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2212 vendor == PCI_VENDOR_BROADCOM && 2213 (product == PCI_PRODUCT_BROADCOM_BCM5901 || 2214 product == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2215 product == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2216 (vendor == PCI_VENDOR_BROADCOM && 2217 (product == PCI_PRODUCT_BROADCOM_BCM5751F || 2218 product == PCI_PRODUCT_BROADCOM_BCM5753F || 2219 product == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2220 product == PCI_PRODUCT_BROADCOM_BCM57790 || 2221 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2222 /* 10/100 only */ 2223 capmask &= ~BMSR_EXTSTAT; 2224 } 2225 2226 mii_priv |= BRGPHY_FLAG_WIRESPEED; 2227 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 2228 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2229 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2230 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2231 sc->bge_asicrev == BGE_ASICREV_BCM5906) 2232 mii_priv &= ~BRGPHY_FLAG_WIRESPEED; 2233 2234 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2235 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2236 mii_priv |= BRGPHY_FLAG_CRC_BUG; 2237 2238 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2239 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2240 mii_priv |= BRGPHY_FLAG_ADC_BUG; 2241 2242 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2243 mii_priv |= BRGPHY_FLAG_5704_A0; 2244 2245 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 2246 mii_priv |= BRGPHY_FLAG_5906; 2247 2248 if (BGE_IS_5705_PLUS(sc) && 2249 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2250 /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */ 2251 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 2252 /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */ 2253 sc->bge_asicrev != BGE_ASICREV_BCM57780) { 2254 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2255 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2256 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2257 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2258 if (product != PCI_PRODUCT_BROADCOM_BCM5722 && 2259 product != PCI_PRODUCT_BROADCOM_BCM5756) 2260 mii_priv |= BRGPHY_FLAG_JITTER_BUG; 2261 if (product == PCI_PRODUCT_BROADCOM_BCM5755M) 2262 mii_priv |= BRGPHY_FLAG_ADJUST_TRIM; 2263 } else { 2264 mii_priv |= BRGPHY_FLAG_BER_BUG; 2265 } 2266 } 2267 2268 /* 2269 * Allocate interrupt 2270 */ 2271 msi_enable = bge_msi_enable; 2272 if ((sc->bge_flags & BGE_FLAG_STATUS_TAG) == 0) { 2273 /* If "tagged status" is disabled, don't enable MSI */ 2274 msi_enable = 0; 2275 } else if (msi_enable) { 2276 msi_enable = 0; /* Disable by default */ 2277 if (BGE_IS_575X_PLUS(sc)) { 2278 msi_enable = 1; 2279 /* XXX we filter all 5714 chips */ 2280 if (sc->bge_asicrev == BGE_ASICREV_BCM5714 || 2281 (sc->bge_asicrev == BGE_ASICREV_BCM5750 && 2282 (sc->bge_chiprev == BGE_CHIPREV_5750_AX || 2283 sc->bge_chiprev == BGE_CHIPREV_5750_BX))) 2284 msi_enable = 0; 2285 else if (BGE_IS_5755_PLUS(sc) || 2286 sc->bge_asicrev == BGE_ASICREV_BCM5906) 2287 sc->bge_flags |= BGE_FLAG_ONESHOT_MSI; 2288 } 2289 } 2290 if (msi_enable) { 2291 if (pci_find_extcap(dev, PCIY_MSI, &sc->bge_msicap)) { 2292 device_printf(dev, "no MSI capability\n"); 2293 msi_enable = 0; 2294 } 2295 } 2296 2297 sc->bge_irq_type = pci_alloc_1intr(dev, msi_enable, &sc->bge_irq_rid, 2298 &intr_flags); 2299 2300 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bge_irq_rid, 2301 intr_flags); 2302 if (sc->bge_irq == NULL) { 2303 device_printf(dev, "couldn't map interrupt\n"); 2304 error = ENXIO; 2305 goto fail; 2306 } 2307 2308 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) 2309 bge_enable_msi(sc); 2310 else 2311 sc->bge_flags &= ~BGE_FLAG_ONESHOT_MSI; 2312 2313 /* Initialize if_name earlier, so if_printf could be used */ 2314 ifp = &sc->arpcom.ac_if; 2315 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2316 2317 sc->bge_asf_mode = 0; 2318 /* No ASF if APE present. */ 2319 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 2320 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 2321 BGE_SRAM_DATA_SIG_MAGIC)) { 2322 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 2323 BGE_HWCFG_ASF) { 2324 sc->bge_asf_mode |= ASF_ENABLE; 2325 sc->bge_asf_mode |= ASF_STACKUP; 2326 if (BGE_IS_575X_PLUS(sc)) 2327 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2328 } 2329 } 2330 } 2331 2332 /* 2333 * Try to reset the chip. 2334 */ 2335 bge_stop_fw(sc); 2336 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 2337 bge_reset(sc); 2338 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 2339 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 2340 2341 if (bge_chipinit(sc)) { 2342 device_printf(dev, "chip initialization failed\n"); 2343 error = ENXIO; 2344 goto fail; 2345 } 2346 2347 /* 2348 * Get station address 2349 */ 2350 error = bge_get_eaddr(sc, ether_addr); 2351 if (error) { 2352 device_printf(dev, "failed to read station address\n"); 2353 goto fail; 2354 } 2355 2356 /* 5705/5750 limits RX return ring to 512 entries. */ 2357 if (BGE_IS_5705_PLUS(sc)) 2358 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2359 else 2360 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2361 2362 error = bge_dma_alloc(sc); 2363 if (error) 2364 goto fail; 2365 2366 /* Set default tuneable values. */ 2367 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2368 sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF; 2369 sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF; 2370 sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF; 2371 sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF; 2372 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 2373 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF; 2374 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF; 2375 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF; 2376 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF; 2377 } else { 2378 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN; 2379 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN; 2380 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN; 2381 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN; 2382 } 2383 sc->bge_tx_wreg = BGE_TX_WREG_NSEGS; 2384 2385 /* Set up TX spare and reserved descriptor count */ 2386 if (sc->bge_flags & BGE_FLAG_TSO) { 2387 sc->bge_txspare = BGE_NSEG_SPARE_TSO; 2388 sc->bge_txrsvd = BGE_NSEG_RSVD_TSO; 2389 } else { 2390 sc->bge_txspare = BGE_NSEG_SPARE; 2391 sc->bge_txrsvd = BGE_NSEG_RSVD; 2392 } 2393 2394 /* Set up ifnet structure */ 2395 ifp->if_softc = sc; 2396 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2397 ifp->if_ioctl = bge_ioctl; 2398 ifp->if_start = bge_start; 2399 #ifdef IFPOLL_ENABLE 2400 ifp->if_npoll = bge_npoll; 2401 #endif 2402 ifp->if_watchdog = bge_watchdog; 2403 ifp->if_init = bge_init; 2404 ifp->if_mtu = ETHERMTU; 2405 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2406 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1); 2407 ifq_set_ready(&ifp->if_snd); 2408 2409 /* 2410 * 5700 B0 chips do not support checksumming correctly due 2411 * to hardware bugs. 2412 */ 2413 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) { 2414 ifp->if_capabilities |= IFCAP_HWCSUM; 2415 ifp->if_hwassist |= BGE_CSUM_FEATURES; 2416 } 2417 if (sc->bge_flags & BGE_FLAG_TSO) { 2418 ifp->if_capabilities |= IFCAP_TSO; 2419 ifp->if_hwassist |= CSUM_TSO; 2420 } 2421 ifp->if_capenable = ifp->if_capabilities; 2422 2423 /* 2424 * Figure out what sort of media we have by checking the 2425 * hardware config word in the first 32k of NIC internal memory, 2426 * or fall back to examining the EEPROM if necessary. 2427 * Note: on some BCM5700 cards, this value appears to be unset. 2428 * If that's the case, we have to rely on identifying the NIC 2429 * by its PCI subsystem ID, as we do below for the SysKonnect 2430 * SK-9D41. 2431 */ 2432 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2433 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2434 } else { 2435 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2436 sizeof(hwcfg))) { 2437 device_printf(dev, "failed to read EEPROM\n"); 2438 error = ENXIO; 2439 goto fail; 2440 } 2441 hwcfg = ntohl(hwcfg); 2442 } 2443 2444 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2445 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 || 2446 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2447 if (BGE_IS_5714_FAMILY(sc)) 2448 sc->bge_flags |= BGE_FLAG_MII_SERDES; 2449 else 2450 sc->bge_flags |= BGE_FLAG_TBI; 2451 } 2452 2453 /* Setup MI MODE */ 2454 if (sc->bge_flags & BGE_FLAG_CPMU) 2455 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 2456 else 2457 sc->bge_mi_mode = BGE_MIMODE_BASE; 2458 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) { 2459 /* Enable auto polling for BCM570[0-5]. */ 2460 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 2461 } 2462 2463 /* Setup link status update stuffs */ 2464 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2465 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 2466 sc->bge_link_upd = bge_bcm5700_link_upd; 2467 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT; 2468 } else if (sc->bge_flags & BGE_FLAG_TBI) { 2469 sc->bge_link_upd = bge_tbi_link_upd; 2470 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED; 2471 } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2472 sc->bge_link_upd = bge_autopoll_link_upd; 2473 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED; 2474 } else { 2475 sc->bge_link_upd = bge_copper_link_upd; 2476 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED; 2477 } 2478 2479 /* 2480 * Broadcom's own driver always assumes the internal 2481 * PHY is at GMII address 1. On some chips, the PHY responds 2482 * to accesses at all addresses, which could cause us to 2483 * bogusly attach the PHY 32 times at probe type. Always 2484 * restricting the lookup to address 1 is simpler than 2485 * trying to figure out which chips revisions should be 2486 * special-cased. 2487 */ 2488 sc->bge_phyno = 1; 2489 2490 if (sc->bge_flags & BGE_FLAG_TBI) { 2491 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 2492 bge_ifmedia_upd, bge_ifmedia_sts); 2493 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2494 ifmedia_add(&sc->bge_ifmedia, 2495 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2496 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2497 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2498 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2499 } else { 2500 struct mii_probe_args mii_args; 2501 int tries; 2502 2503 /* 2504 * Do transceiver setup and tell the firmware the 2505 * driver is down so we can try to get access the 2506 * probe if ASF is running. Retry a couple of times 2507 * if we get a conflict with the ASF firmware accessing 2508 * the PHY. 2509 */ 2510 tries = 0; 2511 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2512 again: 2513 bge_asf_driver_up(sc); 2514 2515 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts); 2516 mii_args.mii_probemask = 1 << sc->bge_phyno; 2517 mii_args.mii_capmask = capmask; 2518 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY; 2519 mii_args.mii_priv = mii_priv; 2520 2521 error = mii_probe(dev, &sc->bge_miibus, &mii_args); 2522 if (error) { 2523 if (tries++ < 4) { 2524 device_printf(sc->bge_dev, "Probe MII again\n"); 2525 bge_miibus_writereg(sc->bge_dev, 2526 sc->bge_phyno, MII_BMCR, BMCR_RESET); 2527 goto again; 2528 } 2529 device_printf(dev, "MII without any PHY!\n"); 2530 goto fail; 2531 } 2532 2533 /* 2534 * Now tell the firmware we are going up after probing the PHY 2535 */ 2536 if (sc->bge_asf_mode & ASF_STACKUP) 2537 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2538 } 2539 2540 /* 2541 * Create sysctl nodes. 2542 */ 2543 sysctl_ctx_init(&sc->bge_sysctl_ctx); 2544 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx, 2545 SYSCTL_STATIC_CHILDREN(_hw), 2546 OID_AUTO, 2547 device_get_nameunit(dev), 2548 CTLFLAG_RD, 0, ""); 2549 if (sc->bge_sysctl_tree == NULL) { 2550 device_printf(dev, "can't add sysctl node\n"); 2551 error = ENXIO; 2552 goto fail; 2553 } 2554 2555 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2556 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2557 OID_AUTO, "rx_coal_ticks", 2558 CTLTYPE_INT | CTLFLAG_RW, 2559 sc, 0, bge_sysctl_rx_coal_ticks, "I", 2560 "Receive coalescing ticks (usec)."); 2561 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2562 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2563 OID_AUTO, "tx_coal_ticks", 2564 CTLTYPE_INT | CTLFLAG_RW, 2565 sc, 0, bge_sysctl_tx_coal_ticks, "I", 2566 "Transmit coalescing ticks (usec)."); 2567 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2568 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2569 OID_AUTO, "rx_coal_bds", 2570 CTLTYPE_INT | CTLFLAG_RW, 2571 sc, 0, bge_sysctl_rx_coal_bds, "I", 2572 "Receive max coalesced BD count."); 2573 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2574 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2575 OID_AUTO, "tx_coal_bds", 2576 CTLTYPE_INT | CTLFLAG_RW, 2577 sc, 0, bge_sysctl_tx_coal_bds, "I", 2578 "Transmit max coalesced BD count."); 2579 2580 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx, 2581 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2582 OID_AUTO, "tx_wreg", CTLFLAG_RW, 2583 &sc->bge_tx_wreg, 0, 2584 "# of segments before writing to hardware register"); 2585 2586 if (sc->bge_flags & BGE_FLAG_PCIE) { 2587 /* 2588 * A common design characteristic for many Broadcom 2589 * client controllers is that they only support a 2590 * single outstanding DMA read operation on the PCIe 2591 * bus. This means that it will take twice as long to 2592 * fetch a TX frame that is split into header and 2593 * payload buffers as it does to fetch a single, 2594 * contiguous TX frame (2 reads vs. 1 read). For these 2595 * controllers, coalescing buffers to reduce the number 2596 * of memory reads is effective way to get maximum 2597 * performance(about 940Mbps). Without collapsing TX 2598 * buffers the maximum TCP bulk transfer performance 2599 * is about 850Mbps. However forcing coalescing mbufs 2600 * consumes a lot of CPU cycles, so leave it off by 2601 * default. 2602 */ 2603 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx, 2604 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2605 OID_AUTO, "force_defrag", CTLFLAG_RW, 2606 &sc->bge_force_defrag, 0, 2607 "Force defragment on TX path"); 2608 } 2609 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 2610 if (!BGE_IS_5705_PLUS(sc)) { 2611 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2612 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO, 2613 "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW, 2614 sc, 0, bge_sysctl_rx_coal_ticks_int, "I", 2615 "Receive coalescing ticks " 2616 "during interrupt (usec)."); 2617 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2618 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO, 2619 "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW, 2620 sc, 0, bge_sysctl_tx_coal_ticks_int, "I", 2621 "Transmit coalescing ticks " 2622 "during interrupt (usec)."); 2623 } 2624 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2625 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO, 2626 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW, 2627 sc, 0, bge_sysctl_rx_coal_bds_int, "I", 2628 "Receive max coalesced BD count during interrupt."); 2629 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2630 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO, 2631 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW, 2632 sc, 0, bge_sysctl_tx_coal_bds_int, "I", 2633 "Transmit max coalesced BD count during interrupt."); 2634 } 2635 2636 /* 2637 * Call MI attach routine. 2638 */ 2639 ether_ifattach(ifp, ether_addr, NULL); 2640 2641 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq)); 2642 2643 #ifdef IFPOLL_ENABLE 2644 /* Polling setup */ 2645 ifpoll_compat_setup(&sc->bge_npoll, 2646 &sc->bge_sysctl_ctx, sc->bge_sysctl_tree, device_get_unit(dev), 2647 ifp->if_serializer); 2648 #endif 2649 2650 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) { 2651 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 2652 intr_func = bge_msi_oneshot; 2653 if (bootverbose) 2654 device_printf(dev, "oneshot MSI\n"); 2655 } else { 2656 intr_func = bge_msi; 2657 } 2658 } else if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 2659 intr_func = bge_intr_legacy; 2660 } else { 2661 intr_func = bge_intr_crippled; 2662 } 2663 error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc, 2664 &sc->bge_intrhand, ifp->if_serializer); 2665 if (error) { 2666 ether_ifdetach(ifp); 2667 device_printf(dev, "couldn't set up irq\n"); 2668 goto fail; 2669 } 2670 2671 return(0); 2672 fail: 2673 bge_detach(dev); 2674 return(error); 2675 } 2676 2677 static int 2678 bge_detach(device_t dev) 2679 { 2680 struct bge_softc *sc = device_get_softc(dev); 2681 2682 if (device_is_attached(dev)) { 2683 struct ifnet *ifp = &sc->arpcom.ac_if; 2684 2685 lwkt_serialize_enter(ifp->if_serializer); 2686 bge_stop(sc); 2687 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2688 lwkt_serialize_exit(ifp->if_serializer); 2689 2690 ether_ifdetach(ifp); 2691 } 2692 2693 if (sc->bge_flags & BGE_FLAG_TBI) 2694 ifmedia_removeall(&sc->bge_ifmedia); 2695 if (sc->bge_miibus) 2696 device_delete_child(dev, sc->bge_miibus); 2697 bus_generic_detach(dev); 2698 2699 if (sc->bge_irq != NULL) { 2700 bus_release_resource(dev, SYS_RES_IRQ, sc->bge_irq_rid, 2701 sc->bge_irq); 2702 } 2703 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) 2704 pci_release_msi(dev); 2705 2706 if (sc->bge_res != NULL) { 2707 bus_release_resource(dev, SYS_RES_MEMORY, 2708 BGE_PCI_BAR0, sc->bge_res); 2709 } 2710 2711 if (sc->bge_sysctl_tree != NULL) 2712 sysctl_ctx_free(&sc->bge_sysctl_ctx); 2713 2714 bge_dma_free(sc); 2715 2716 return 0; 2717 } 2718 2719 static void 2720 bge_reset(struct bge_softc *sc) 2721 { 2722 device_t dev; 2723 uint32_t cachesize, command, pcistate, reset; 2724 void (*write_op)(struct bge_softc *, uint32_t, uint32_t); 2725 int i, val = 0; 2726 2727 dev = sc->bge_dev; 2728 2729 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 2730 sc->bge_asicrev != BGE_ASICREV_BCM5906) { 2731 if (sc->bge_flags & BGE_FLAG_PCIE) 2732 write_op = bge_writemem_direct; 2733 else 2734 write_op = bge_writemem_ind; 2735 } else { 2736 write_op = bge_writereg_ind; 2737 } 2738 2739 /* Save some important PCI state. */ 2740 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2741 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2742 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2743 2744 pci_write_config(dev, BGE_PCI_MISC_CTL, 2745 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2746 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW| 2747 sc->bge_pci_miscctl, 4); 2748 2749 /* Disable fastboot on controllers that support it. */ 2750 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2751 BGE_IS_5755_PLUS(sc)) { 2752 if (bootverbose) 2753 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n"); 2754 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2755 } 2756 2757 /* 2758 * Write the magic number to SRAM at offset 0xB50. 2759 * When firmware finishes its initialization it will 2760 * write ~BGE_MAGIC_NUMBER to the same location. 2761 */ 2762 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2763 2764 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1); 2765 2766 /* XXX: Broadcom Linux driver. */ 2767 if (sc->bge_flags & BGE_FLAG_PCIE) { 2768 /* Force PCI-E 1.0a mode */ 2769 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 2770 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) == 2771 (BGE_PCIE_PHY_TSTCTL_PSCRAM | 2772 BGE_PCIE_PHY_TSTCTL_PCIE10)) { 2773 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL, 2774 BGE_PCIE_PHY_TSTCTL_PSCRAM); 2775 } 2776 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2777 /* Prevent PCIE link training during global reset */ 2778 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); 2779 reset |= (1<<29); 2780 } 2781 } 2782 2783 /* 2784 * Set GPHY Power Down Override to leave GPHY 2785 * powered up in D0 uninitialized. 2786 */ 2787 if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0) 2788 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 2789 2790 /* Issue global reset */ 2791 write_op(sc, BGE_MISC_CFG, reset); 2792 2793 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2794 uint32_t status, ctrl; 2795 2796 status = CSR_READ_4(sc, BGE_VCPU_STATUS); 2797 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2798 status | BGE_VCPU_STATUS_DRV_RESET); 2799 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2800 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2801 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2802 } 2803 2804 DELAY(1000); 2805 2806 /* XXX: Broadcom Linux driver. */ 2807 if (sc->bge_flags & BGE_FLAG_PCIE) { 2808 uint16_t devctl; 2809 2810 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2811 uint32_t v; 2812 2813 DELAY(500000); /* wait for link training to complete */ 2814 v = pci_read_config(dev, 0xc4, 4); 2815 pci_write_config(dev, 0xc4, v | (1<<15), 4); 2816 } 2817 2818 devctl = pci_read_config(dev, 2819 sc->bge_pciecap + PCIER_DEVCTRL, 2); 2820 2821 /* Disable no snoop and disable relaxed ordering. */ 2822 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP); 2823 2824 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */ 2825 if ((sc->bge_flags & BGE_FLAG_CPMU) == 0) { 2826 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK; 2827 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128; 2828 } 2829 2830 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL, 2831 devctl, 2); 2832 2833 /* Clear error status. */ 2834 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS, 2835 PCIEM_DEVSTS_CORR_ERR | 2836 PCIEM_DEVSTS_NFATAL_ERR | 2837 PCIEM_DEVSTS_FATAL_ERR | 2838 PCIEM_DEVSTS_UNSUPP_REQ, 2); 2839 } 2840 2841 /* Reset some of the PCI state that got zapped by reset */ 2842 pci_write_config(dev, BGE_PCI_MISC_CTL, 2843 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2844 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW| 2845 sc->bge_pci_miscctl, 4); 2846 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2847 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2848 write_op(sc, BGE_MISC_CFG, (65 << 1)); 2849 2850 /* 2851 * Disable PCI-X relaxed ordering to ensure status block update 2852 * comes first then packet buffer DMA. Otherwise driver may 2853 * read stale status block. 2854 */ 2855 if (sc->bge_flags & BGE_FLAG_PCIX) { 2856 uint16_t devctl; 2857 2858 devctl = pci_read_config(dev, 2859 sc->bge_pcixcap + PCIXR_COMMAND, 2); 2860 devctl &= ~PCIXM_COMMAND_ERO; 2861 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 2862 devctl &= ~PCIXM_COMMAND_MAX_READ; 2863 devctl |= PCIXM_COMMAND_MAX_READ_2048; 2864 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 2865 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 2866 PCIXM_COMMAND_MAX_READ); 2867 devctl |= PCIXM_COMMAND_MAX_READ_2048; 2868 } 2869 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 2870 devctl, 2); 2871 } 2872 2873 /* 2874 * Enable memory arbiter and re-enable MSI if necessary. 2875 */ 2876 if (BGE_IS_5714_FAMILY(sc)) { 2877 uint32_t val; 2878 2879 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) { 2880 /* 2881 * Resetting BCM5714 family will clear MSI 2882 * enable bit; restore it after resetting. 2883 */ 2884 PCI_SETBIT(sc->bge_dev, sc->bge_msicap + PCIR_MSI_CTRL, 2885 PCIM_MSICTRL_MSI_ENABLE, 2); 2886 BGE_SETBIT(sc, BGE_MSI_MODE, BGE_MSIMODE_ENABLE); 2887 } 2888 val = CSR_READ_4(sc, BGE_MARB_MODE); 2889 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 2890 } else { 2891 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2892 } 2893 2894 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2895 for (i = 0; i < BGE_TIMEOUT; i++) { 2896 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2897 if (val & BGE_VCPU_STATUS_INIT_DONE) 2898 break; 2899 DELAY(100); 2900 } 2901 if (i == BGE_TIMEOUT) { 2902 if_printf(&sc->arpcom.ac_if, "reset timed out\n"); 2903 return; 2904 } 2905 } else { 2906 /* 2907 * Poll until we see the 1's complement of the magic number. 2908 * This indicates that the firmware initialization 2909 * is complete. 2910 */ 2911 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) { 2912 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2913 if (val == ~BGE_MAGIC_NUMBER) 2914 break; 2915 DELAY(10); 2916 } 2917 if (i == BGE_FIRMWARE_TIMEOUT) { 2918 if_printf(&sc->arpcom.ac_if, "firmware handshake " 2919 "timed out, found 0x%08x\n", val); 2920 } 2921 } 2922 2923 /* 2924 * XXX Wait for the value of the PCISTATE register to 2925 * return to its original pre-reset state. This is a 2926 * fairly good indicator of reset completion. If we don't 2927 * wait for the reset to fully complete, trying to read 2928 * from the device's non-PCI registers may yield garbage 2929 * results. 2930 */ 2931 for (i = 0; i < BGE_TIMEOUT; i++) { 2932 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2933 break; 2934 DELAY(10); 2935 } 2936 2937 /* Fix up byte swapping */ 2938 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 2939 BGE_MODECTL_BYTESWAP_DATA); 2940 2941 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2942 2943 /* 2944 * The 5704 in TBI mode apparently needs some special 2945 * adjustment to insure the SERDES drive level is set 2946 * to 1.2V. 2947 */ 2948 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 2949 (sc->bge_flags & BGE_FLAG_TBI)) { 2950 uint32_t serdescfg; 2951 2952 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2953 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2954 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2955 } 2956 2957 /* XXX: Broadcom Linux driver. */ 2958 if ((sc->bge_flags & BGE_FLAG_PCIE) && 2959 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 2960 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 2961 uint32_t v; 2962 2963 /* Enable Data FIFO protection. */ 2964 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT); 2965 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25)); 2966 } 2967 2968 DELAY(10000); 2969 } 2970 2971 /* 2972 * Frame reception handling. This is called if there's a frame 2973 * on the receive return list. 2974 * 2975 * Note: we have to be able to handle two possibilities here: 2976 * 1) the frame is from the jumbo recieve ring 2977 * 2) the frame is from the standard receive ring 2978 */ 2979 2980 static void 2981 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int count) 2982 { 2983 struct ifnet *ifp; 2984 int stdcnt = 0, jumbocnt = 0; 2985 2986 ifp = &sc->arpcom.ac_if; 2987 2988 while (sc->bge_rx_saved_considx != rx_prod && count != 0) { 2989 struct bge_rx_bd *cur_rx; 2990 uint32_t rxidx; 2991 struct mbuf *m = NULL; 2992 uint16_t vlan_tag = 0; 2993 int have_tag = 0; 2994 2995 --count; 2996 2997 cur_rx = 2998 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 2999 3000 rxidx = cur_rx->bge_idx; 3001 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 3002 logif(rx_pkt); 3003 3004 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3005 have_tag = 1; 3006 vlan_tag = cur_rx->bge_vlan_tag; 3007 } 3008 3009 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3010 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3011 jumbocnt++; 3012 3013 if (rxidx != sc->bge_jumbo) { 3014 IFNET_STAT_INC(ifp, ierrors, 1); 3015 if_printf(ifp, "sw jumbo index(%d) " 3016 "and hw jumbo index(%d) mismatch, drop!\n", 3017 sc->bge_jumbo, rxidx); 3018 bge_setup_rxdesc_jumbo(sc, rxidx); 3019 continue; 3020 } 3021 3022 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf; 3023 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3024 IFNET_STAT_INC(ifp, ierrors, 1); 3025 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo); 3026 continue; 3027 } 3028 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) { 3029 IFNET_STAT_INC(ifp, ierrors, 1); 3030 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo); 3031 continue; 3032 } 3033 } else { 3034 int discard = 0; 3035 3036 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3037 stdcnt++; 3038 3039 if (rxidx != sc->bge_std) { 3040 IFNET_STAT_INC(ifp, ierrors, 1); 3041 if_printf(ifp, "sw std index(%d) " 3042 "and hw std index(%d) mismatch, drop!\n", 3043 sc->bge_std, rxidx); 3044 bge_setup_rxdesc_std(sc, rxidx); 3045 discard = 1; 3046 goto refresh_rx; 3047 } 3048 3049 m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf; 3050 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3051 IFNET_STAT_INC(ifp, ierrors, 1); 3052 bge_setup_rxdesc_std(sc, sc->bge_std); 3053 discard = 1; 3054 goto refresh_rx; 3055 } 3056 if (bge_newbuf_std(sc, sc->bge_std, 0)) { 3057 IFNET_STAT_INC(ifp, ierrors, 1); 3058 bge_setup_rxdesc_std(sc, sc->bge_std); 3059 discard = 1; 3060 } 3061 refresh_rx: 3062 if (sc->bge_rx_wreg > 0 && stdcnt >= sc->bge_rx_wreg) { 3063 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 3064 sc->bge_std); 3065 stdcnt = 0; 3066 } 3067 if (discard) 3068 continue; 3069 } 3070 3071 IFNET_STAT_INC(ifp, ipackets, 1); 3072 #if !defined(__i386__) && !defined(__x86_64__) 3073 /* 3074 * The x86 allows unaligned accesses, but for other 3075 * platforms we must make sure the payload is aligned. 3076 */ 3077 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3078 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3079 cur_rx->bge_len); 3080 m->m_data += ETHER_ALIGN; 3081 } 3082 #endif 3083 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3084 m->m_pkthdr.rcvif = ifp; 3085 3086 if (ifp->if_capenable & IFCAP_RXCSUM) { 3087 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3088 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3089 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 3090 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3091 } 3092 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) && 3093 m->m_pkthdr.len >= BGE_MIN_FRAMELEN) { 3094 m->m_pkthdr.csum_data = 3095 cur_rx->bge_tcp_udp_csum; 3096 m->m_pkthdr.csum_flags |= 3097 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 3098 } 3099 } 3100 3101 /* 3102 * If we received a packet with a vlan tag, pass it 3103 * to vlan_input() instead of ether_input(). 3104 */ 3105 if (have_tag) { 3106 m->m_flags |= M_VLANTAG; 3107 m->m_pkthdr.ether_vlantag = vlan_tag; 3108 } 3109 ifp->if_input(ifp, m); 3110 } 3111 3112 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3113 if (stdcnt) 3114 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3115 if (jumbocnt) 3116 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3117 } 3118 3119 static void 3120 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 3121 { 3122 struct ifnet *ifp; 3123 3124 ifp = &sc->arpcom.ac_if; 3125 3126 /* 3127 * Go through our tx ring and free mbufs for those 3128 * frames that have been sent. 3129 */ 3130 while (sc->bge_tx_saved_considx != tx_cons) { 3131 uint32_t idx = 0; 3132 3133 idx = sc->bge_tx_saved_considx; 3134 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3135 IFNET_STAT_INC(ifp, opackets, 1); 3136 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 3137 sc->bge_cdata.bge_tx_dmamap[idx]); 3138 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3139 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3140 } 3141 sc->bge_txcnt--; 3142 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3143 logif(tx_pkt); 3144 } 3145 3146 if ((BGE_TX_RING_CNT - sc->bge_txcnt) >= 3147 (sc->bge_txrsvd + sc->bge_txspare)) 3148 ifq_clr_oactive(&ifp->if_snd); 3149 3150 if (sc->bge_txcnt == 0) 3151 ifp->if_timer = 0; 3152 3153 if (!ifq_is_empty(&ifp->if_snd)) 3154 if_devstart(ifp); 3155 } 3156 3157 #ifdef IFPOLL_ENABLE 3158 3159 static void 3160 bge_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycles) 3161 { 3162 struct bge_softc *sc = ifp->if_softc; 3163 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3164 uint16_t rx_prod, tx_cons; 3165 3166 ASSERT_SERIALIZED(ifp->if_serializer); 3167 3168 if (sc->bge_npoll.ifpc_stcount-- == 0) { 3169 sc->bge_npoll.ifpc_stcount = sc->bge_npoll.ifpc_stfrac; 3170 /* 3171 * Process link state changes. 3172 */ 3173 bge_link_poll(sc); 3174 } 3175 3176 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 3177 sc->bge_status_tag = sblk->bge_status_tag; 3178 /* 3179 * Use a load fence to ensure that status_tag 3180 * is saved before rx_prod and tx_cons. 3181 */ 3182 cpu_lfence(); 3183 } 3184 3185 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3186 if (sc->bge_rx_saved_considx != rx_prod) 3187 bge_rxeof(sc, rx_prod, cycles); 3188 3189 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3190 if (sc->bge_tx_saved_considx != tx_cons) 3191 bge_txeof(sc, tx_cons); 3192 3193 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) 3194 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 3195 3196 if (sc->bge_coal_chg) 3197 bge_coal_change(sc); 3198 } 3199 3200 static void 3201 bge_npoll(struct ifnet *ifp, struct ifpoll_info *info) 3202 { 3203 struct bge_softc *sc = ifp->if_softc; 3204 3205 ASSERT_SERIALIZED(ifp->if_serializer); 3206 3207 if (info != NULL) { 3208 int cpuid = sc->bge_npoll.ifpc_cpuid; 3209 3210 info->ifpi_rx[cpuid].poll_func = bge_npoll_compat; 3211 info->ifpi_rx[cpuid].arg = NULL; 3212 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 3213 3214 if (ifp->if_flags & IFF_RUNNING) 3215 bge_disable_intr(sc); 3216 ifq_set_cpuid(&ifp->if_snd, cpuid); 3217 } else { 3218 if (ifp->if_flags & IFF_RUNNING) 3219 bge_enable_intr(sc); 3220 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq)); 3221 } 3222 } 3223 3224 #endif /* IFPOLL_ENABLE */ 3225 3226 static void 3227 bge_intr_crippled(void *xsc) 3228 { 3229 struct bge_softc *sc = xsc; 3230 struct ifnet *ifp = &sc->arpcom.ac_if; 3231 3232 logif(intr); 3233 3234 /* 3235 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3236 * disable interrupts by writing nonzero like we used to, since with 3237 * our current organization this just gives complications and 3238 * pessimizations for re-enabling interrupts. We used to have races 3239 * instead of the necessary complications. Disabling interrupts 3240 * would just reduce the chance of a status update while we are 3241 * running (by switching to the interrupt-mode coalescence 3242 * parameters), but this chance is already very low so it is more 3243 * efficient to get another interrupt than prevent it. 3244 * 3245 * We do the ack first to ensure another interrupt if there is a 3246 * status update after the ack. We don't check for the status 3247 * changing later because it is more efficient to get another 3248 * interrupt than prevent it, not quite as above (not checking is 3249 * a smaller optimization than not toggling the interrupt enable, 3250 * since checking doesn't involve PCI accesses and toggling require 3251 * the status check). So toggling would probably be a pessimization 3252 * even with MSI. It would only be needed for using a task queue. 3253 */ 3254 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3255 3256 /* 3257 * Process link state changes. 3258 */ 3259 bge_link_poll(sc); 3260 3261 if (ifp->if_flags & IFF_RUNNING) { 3262 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3263 uint16_t rx_prod, tx_cons; 3264 3265 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3266 if (sc->bge_rx_saved_considx != rx_prod) 3267 bge_rxeof(sc, rx_prod, -1); 3268 3269 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3270 if (sc->bge_tx_saved_considx != tx_cons) 3271 bge_txeof(sc, tx_cons); 3272 } 3273 3274 if (sc->bge_coal_chg) 3275 bge_coal_change(sc); 3276 } 3277 3278 static void 3279 bge_intr_legacy(void *xsc) 3280 { 3281 struct bge_softc *sc = xsc; 3282 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3283 3284 if (sc->bge_status_tag == sblk->bge_status_tag) { 3285 uint32_t val; 3286 3287 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3288 if (val & BGE_PCISTAT_INTR_NOTACT) 3289 return; 3290 } 3291 3292 /* 3293 * NOTE: 3294 * Interrupt will have to be disabled if tagged status 3295 * is used, else interrupt will always be asserted on 3296 * certain chips (at least on BCM5750 AX/BX). 3297 */ 3298 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3299 3300 bge_intr(sc); 3301 } 3302 3303 static void 3304 bge_msi(void *xsc) 3305 { 3306 struct bge_softc *sc = xsc; 3307 3308 /* Disable interrupt first */ 3309 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3310 bge_intr(sc); 3311 } 3312 3313 static void 3314 bge_msi_oneshot(void *xsc) 3315 { 3316 bge_intr(xsc); 3317 } 3318 3319 static void 3320 bge_intr(struct bge_softc *sc) 3321 { 3322 struct ifnet *ifp = &sc->arpcom.ac_if; 3323 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3324 uint16_t rx_prod, tx_cons; 3325 uint32_t status; 3326 3327 sc->bge_status_tag = sblk->bge_status_tag; 3328 /* 3329 * Use a load fence to ensure that status_tag is saved 3330 * before rx_prod, tx_cons and status. 3331 */ 3332 cpu_lfence(); 3333 3334 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3335 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3336 status = sblk->bge_status; 3337 3338 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt) 3339 bge_link_poll(sc); 3340 3341 if (ifp->if_flags & IFF_RUNNING) { 3342 if (sc->bge_rx_saved_considx != rx_prod) 3343 bge_rxeof(sc, rx_prod, -1); 3344 3345 if (sc->bge_tx_saved_considx != tx_cons) 3346 bge_txeof(sc, tx_cons); 3347 } 3348 3349 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 3350 3351 if (sc->bge_coal_chg) 3352 bge_coal_change(sc); 3353 } 3354 3355 static void 3356 bge_tick(void *xsc) 3357 { 3358 struct bge_softc *sc = xsc; 3359 struct ifnet *ifp = &sc->arpcom.ac_if; 3360 3361 lwkt_serialize_enter(ifp->if_serializer); 3362 3363 if (BGE_IS_5705_PLUS(sc)) 3364 bge_stats_update_regs(sc); 3365 else 3366 bge_stats_update(sc); 3367 3368 if (sc->bge_flags & BGE_FLAG_TBI) { 3369 /* 3370 * Since in TBI mode auto-polling can't be used we should poll 3371 * link status manually. Here we register pending link event 3372 * and trigger interrupt. 3373 */ 3374 sc->bge_link_evt++; 3375 if (BGE_IS_CRIPPLED(sc)) 3376 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3377 else 3378 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3379 } else if (!sc->bge_link) { 3380 mii_tick(device_get_softc(sc->bge_miibus)); 3381 } 3382 3383 bge_asf_driver_up(sc); 3384 3385 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 3386 3387 lwkt_serialize_exit(ifp->if_serializer); 3388 } 3389 3390 static void 3391 bge_stats_update_regs(struct bge_softc *sc) 3392 { 3393 struct ifnet *ifp = &sc->arpcom.ac_if; 3394 struct bge_mac_stats_regs stats; 3395 uint32_t *s; 3396 int i; 3397 3398 s = (uint32_t *)&stats; 3399 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 3400 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 3401 s++; 3402 } 3403 3404 IFNET_STAT_SET(ifp, collisions, 3405 (stats.dot3StatsSingleCollisionFrames + 3406 stats.dot3StatsMultipleCollisionFrames + 3407 stats.dot3StatsExcessiveCollisions + 3408 stats.dot3StatsLateCollisions)); 3409 } 3410 3411 static void 3412 bge_stats_update(struct bge_softc *sc) 3413 { 3414 struct ifnet *ifp = &sc->arpcom.ac_if; 3415 bus_size_t stats; 3416 3417 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3418 3419 #define READ_STAT(sc, stats, stat) \ 3420 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3421 3422 IFNET_STAT_SET(ifp, collisions, 3423 (READ_STAT(sc, stats, 3424 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) + 3425 READ_STAT(sc, stats, 3426 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3427 READ_STAT(sc, stats, 3428 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) + 3429 READ_STAT(sc, stats, 3430 txstats.dot3StatsLateCollisions.bge_addr_lo))); 3431 3432 #undef READ_STAT 3433 3434 #ifdef notdef 3435 IFNET_STAT_SET(ifp, collisions, 3436 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3437 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3438 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3439 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions)); 3440 #endif 3441 } 3442 3443 /* 3444 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3445 * pointers to descriptors. 3446 */ 3447 static int 3448 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx, 3449 int *segs_used) 3450 { 3451 struct bge_tx_bd *d = NULL, *last_d; 3452 uint16_t csum_flags = 0, mss = 0; 3453 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3454 bus_dmamap_t map; 3455 int error, maxsegs, nsegs, idx, i; 3456 struct mbuf *m_head = *m_head0, *m_new; 3457 3458 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3459 error = bge_setup_tso(sc, m_head0, &mss, &csum_flags); 3460 if (error) 3461 return ENOBUFS; 3462 m_head = *m_head0; 3463 } else if (m_head->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) { 3464 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3465 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3466 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3467 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3468 if (m_head->m_flags & M_LASTFRAG) 3469 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3470 else if (m_head->m_flags & M_FRAG) 3471 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3472 } 3473 3474 idx = *txidx; 3475 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3476 3477 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - sc->bge_txrsvd; 3478 KASSERT(maxsegs >= sc->bge_txspare, 3479 ("not enough segments %d", maxsegs)); 3480 3481 if (maxsegs > BGE_NSEG_NEW) 3482 maxsegs = BGE_NSEG_NEW; 3483 3484 /* 3485 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason. 3486 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN, 3487 * but when such padded frames employ the bge IP/TCP checksum 3488 * offload, the hardware checksum assist gives incorrect results 3489 * (possibly from incorporating its own padding into the UDP/TCP 3490 * checksum; who knows). If we pad such runts with zeros, the 3491 * onboard checksum comes out correct. 3492 */ 3493 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) && 3494 m_head->m_pkthdr.len < BGE_MIN_FRAMELEN) { 3495 error = m_devpad(m_head, BGE_MIN_FRAMELEN); 3496 if (error) 3497 goto back; 3498 } 3499 3500 if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) { 3501 m_new = bge_defrag_shortdma(m_head); 3502 if (m_new == NULL) { 3503 error = ENOBUFS; 3504 goto back; 3505 } 3506 *m_head0 = m_head = m_new; 3507 } 3508 if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 && 3509 sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) && 3510 m_head->m_next != NULL) { 3511 /* 3512 * Forcefully defragment mbuf chain to overcome hardware 3513 * limitation which only support a single outstanding 3514 * DMA read operation. If it fails, keep moving on using 3515 * the original mbuf chain. 3516 */ 3517 m_new = m_defrag(m_head, MB_DONTWAIT); 3518 if (m_new != NULL) 3519 *m_head0 = m_head = m_new; 3520 } 3521 3522 error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map, 3523 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 3524 if (error) 3525 goto back; 3526 *segs_used += nsegs; 3527 3528 m_head = *m_head0; 3529 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 3530 3531 for (i = 0; ; i++) { 3532 d = &sc->bge_ldata.bge_tx_ring[idx]; 3533 3534 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3535 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3536 d->bge_len = segs[i].ds_len; 3537 d->bge_flags = csum_flags; 3538 d->bge_mss = mss; 3539 3540 if (i == nsegs - 1) 3541 break; 3542 BGE_INC(idx, BGE_TX_RING_CNT); 3543 } 3544 last_d = d; 3545 3546 /* Set vlan tag to the first segment of the packet. */ 3547 d = &sc->bge_ldata.bge_tx_ring[*txidx]; 3548 if (m_head->m_flags & M_VLANTAG) { 3549 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3550 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag; 3551 } else { 3552 d->bge_vlan_tag = 0; 3553 } 3554 3555 /* Mark the last segment as end of packet... */ 3556 last_d->bge_flags |= BGE_TXBDFLAG_END; 3557 3558 /* 3559 * Insure that the map for this transmission is placed at 3560 * the array index of the last descriptor in this chain. 3561 */ 3562 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3563 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3564 sc->bge_cdata.bge_tx_chain[idx] = m_head; 3565 sc->bge_txcnt += nsegs; 3566 3567 BGE_INC(idx, BGE_TX_RING_CNT); 3568 *txidx = idx; 3569 back: 3570 if (error) { 3571 m_freem(*m_head0); 3572 *m_head0 = NULL; 3573 } 3574 return error; 3575 } 3576 3577 static void 3578 bge_xmit(struct bge_softc *sc, uint32_t prodidx) 3579 { 3580 /* Transmit */ 3581 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3582 /* 5700 b2 errata */ 3583 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3584 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3585 } 3586 3587 /* 3588 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3589 * to the mbuf data regions directly in the transmit descriptors. 3590 */ 3591 static void 3592 bge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 3593 { 3594 struct bge_softc *sc = ifp->if_softc; 3595 struct mbuf *m_head = NULL; 3596 uint32_t prodidx; 3597 int nsegs = 0; 3598 3599 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 3600 3601 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 3602 return; 3603 3604 prodidx = sc->bge_tx_prodidx; 3605 3606 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3607 m_head = ifq_dequeue(&ifp->if_snd); 3608 if (m_head == NULL) 3609 break; 3610 3611 /* 3612 * XXX 3613 * The code inside the if() block is never reached since we 3614 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3615 * requests to checksum TCP/UDP in a fragmented packet. 3616 * 3617 * XXX 3618 * safety overkill. If this is a fragmented packet chain 3619 * with delayed TCP/UDP checksums, then only encapsulate 3620 * it if we have enough descriptors to handle the entire 3621 * chain at once. 3622 * (paranoia -- may not actually be needed) 3623 */ 3624 if ((m_head->m_flags & M_FIRSTFRAG) && 3625 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) { 3626 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3627 m_head->m_pkthdr.csum_data + sc->bge_txrsvd) { 3628 ifq_set_oactive(&ifp->if_snd); 3629 ifq_prepend(&ifp->if_snd, m_head); 3630 break; 3631 } 3632 } 3633 3634 /* 3635 * Sanity check: avoid coming within bge_txrsvd 3636 * descriptors of the end of the ring. Also make 3637 * sure there are bge_txspare descriptors for 3638 * jumbo buffers' defragmentation. 3639 */ 3640 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3641 (sc->bge_txrsvd + sc->bge_txspare)) { 3642 ifq_set_oactive(&ifp->if_snd); 3643 ifq_prepend(&ifp->if_snd, m_head); 3644 break; 3645 } 3646 3647 /* 3648 * Pack the data into the transmit ring. If we 3649 * don't have room, set the OACTIVE flag and wait 3650 * for the NIC to drain the ring. 3651 */ 3652 if (bge_encap(sc, &m_head, &prodidx, &nsegs)) { 3653 ifq_set_oactive(&ifp->if_snd); 3654 IFNET_STAT_INC(ifp, oerrors, 1); 3655 break; 3656 } 3657 3658 if (nsegs >= sc->bge_tx_wreg) { 3659 bge_xmit(sc, prodidx); 3660 nsegs = 0; 3661 } 3662 3663 ETHER_BPF_MTAP(ifp, m_head); 3664 3665 /* 3666 * Set a timeout in case the chip goes out to lunch. 3667 */ 3668 ifp->if_timer = 5; 3669 } 3670 3671 if (nsegs > 0) 3672 bge_xmit(sc, prodidx); 3673 sc->bge_tx_prodidx = prodidx; 3674 } 3675 3676 static void 3677 bge_init(void *xsc) 3678 { 3679 struct bge_softc *sc = xsc; 3680 struct ifnet *ifp = &sc->arpcom.ac_if; 3681 uint16_t *m; 3682 uint32_t mode; 3683 3684 ASSERT_SERIALIZED(ifp->if_serializer); 3685 3686 /* Cancel pending I/O and flush buffers. */ 3687 bge_stop(sc); 3688 3689 bge_stop_fw(sc); 3690 bge_sig_pre_reset(sc, BGE_RESET_START); 3691 bge_reset(sc); 3692 bge_sig_legacy(sc, BGE_RESET_START); 3693 bge_sig_post_reset(sc, BGE_RESET_START); 3694 3695 bge_chipinit(sc); 3696 3697 /* 3698 * Init the various state machines, ring 3699 * control blocks and firmware. 3700 */ 3701 if (bge_blockinit(sc)) { 3702 if_printf(ifp, "initialization failure\n"); 3703 bge_stop(sc); 3704 return; 3705 } 3706 3707 /* Specify MTU. */ 3708 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3709 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN); 3710 3711 /* Load our MAC address. */ 3712 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 3713 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3714 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3715 3716 /* Enable or disable promiscuous mode as needed. */ 3717 bge_setpromisc(sc); 3718 3719 /* Program multicast filter. */ 3720 bge_setmulti(sc); 3721 3722 /* Init RX ring. */ 3723 if (bge_init_rx_ring_std(sc)) { 3724 if_printf(ifp, "RX ring initialization failed\n"); 3725 bge_stop(sc); 3726 return; 3727 } 3728 3729 /* 3730 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3731 * memory to insure that the chip has in fact read the first 3732 * entry of the ring. 3733 */ 3734 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3735 uint32_t v, i; 3736 for (i = 0; i < 10; i++) { 3737 DELAY(20); 3738 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3739 if (v == (MCLBYTES - ETHER_ALIGN)) 3740 break; 3741 } 3742 if (i == 10) 3743 if_printf(ifp, "5705 A0 chip failed to load RX ring\n"); 3744 } 3745 3746 /* Init jumbo RX ring. */ 3747 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) { 3748 if (bge_init_rx_ring_jumbo(sc)) { 3749 if_printf(ifp, "Jumbo RX ring initialization failed\n"); 3750 bge_stop(sc); 3751 return; 3752 } 3753 } 3754 3755 /* Init our RX return ring index */ 3756 sc->bge_rx_saved_considx = 0; 3757 3758 /* Init TX ring. */ 3759 bge_init_tx_ring(sc); 3760 3761 /* Enable TX MAC state machine lockup fix. */ 3762 mode = CSR_READ_4(sc, BGE_TX_MODE); 3763 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3764 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 3765 /* Turn on transmitter */ 3766 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 3767 3768 /* Turn on receiver */ 3769 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3770 3771 /* 3772 * Set the number of good frames to receive after RX MBUF 3773 * Low Watermark has been reached. After the RX MAC receives 3774 * this number of frames, it will drop subsequent incoming 3775 * frames until the MBUF High Watermark is reached. 3776 */ 3777 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3778 3779 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) { 3780 if (bootverbose) { 3781 if_printf(ifp, "MSI_MODE: %#x\n", 3782 CSR_READ_4(sc, BGE_MSI_MODE)); 3783 } 3784 3785 /* 3786 * XXX 3787 * Linux driver turns it on for all chips supporting MSI?! 3788 */ 3789 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 3790 /* 3791 * XXX 3792 * According to 5722-PG101-R, 3793 * BGE_PCIE_TRANSACT_ONESHOT_MSI applies only to 3794 * BCM5906. 3795 */ 3796 BGE_SETBIT(sc, BGE_PCIE_TRANSACT, 3797 BGE_PCIE_TRANSACT_ONESHOT_MSI); 3798 } 3799 } 3800 3801 /* Tell firmware we're alive. */ 3802 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3803 3804 /* Enable host interrupts if polling(4) is not enabled. */ 3805 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4); 3806 #ifdef IFPOLL_ENABLE 3807 if (ifp->if_flags & IFF_NPOLLING) 3808 bge_disable_intr(sc); 3809 else 3810 #endif 3811 bge_enable_intr(sc); 3812 3813 ifp->if_flags |= IFF_RUNNING; 3814 ifq_clr_oactive(&ifp->if_snd); 3815 3816 bge_ifmedia_upd(ifp); 3817 3818 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 3819 } 3820 3821 /* 3822 * Set media options. 3823 */ 3824 static int 3825 bge_ifmedia_upd(struct ifnet *ifp) 3826 { 3827 struct bge_softc *sc = ifp->if_softc; 3828 3829 /* If this is a 1000baseX NIC, enable the TBI port. */ 3830 if (sc->bge_flags & BGE_FLAG_TBI) { 3831 struct ifmedia *ifm = &sc->bge_ifmedia; 3832 3833 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3834 return(EINVAL); 3835 3836 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3837 case IFM_AUTO: 3838 /* 3839 * The BCM5704 ASIC appears to have a special 3840 * mechanism for programming the autoneg 3841 * advertisement registers in TBI mode. 3842 */ 3843 if (!bge_fake_autoneg && 3844 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3845 uint32_t sgdig; 3846 3847 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3848 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3849 sgdig |= BGE_SGDIGCFG_AUTO | 3850 BGE_SGDIGCFG_PAUSE_CAP | 3851 BGE_SGDIGCFG_ASYM_PAUSE; 3852 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3853 sgdig | BGE_SGDIGCFG_SEND); 3854 DELAY(5); 3855 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3856 } 3857 break; 3858 case IFM_1000_SX: 3859 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3860 BGE_CLRBIT(sc, BGE_MAC_MODE, 3861 BGE_MACMODE_HALF_DUPLEX); 3862 } else { 3863 BGE_SETBIT(sc, BGE_MAC_MODE, 3864 BGE_MACMODE_HALF_DUPLEX); 3865 } 3866 break; 3867 default: 3868 return(EINVAL); 3869 } 3870 } else { 3871 struct mii_data *mii = device_get_softc(sc->bge_miibus); 3872 3873 sc->bge_link_evt++; 3874 sc->bge_link = 0; 3875 if (mii->mii_instance) { 3876 struct mii_softc *miisc; 3877 3878 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3879 mii_phy_reset(miisc); 3880 } 3881 mii_mediachg(mii); 3882 3883 /* 3884 * Force an interrupt so that we will call bge_link_upd 3885 * if needed and clear any pending link state attention. 3886 * Without this we are not getting any further interrupts 3887 * for link state changes and thus will not UP the link and 3888 * not be able to send in bge_start. The only way to get 3889 * things working was to receive a packet and get an RX 3890 * intr. 3891 * 3892 * bge_tick should help for fiber cards and we might not 3893 * need to do this here if BGE_FLAG_TBI is set but as 3894 * we poll for fiber anyway it should not harm. 3895 */ 3896 if (BGE_IS_CRIPPLED(sc)) 3897 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3898 else 3899 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3900 } 3901 return(0); 3902 } 3903 3904 /* 3905 * Report current media status. 3906 */ 3907 static void 3908 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3909 { 3910 struct bge_softc *sc = ifp->if_softc; 3911 3912 if ((ifp->if_flags & IFF_RUNNING) == 0) 3913 return; 3914 3915 if (sc->bge_flags & BGE_FLAG_TBI) { 3916 ifmr->ifm_status = IFM_AVALID; 3917 ifmr->ifm_active = IFM_ETHER; 3918 if (CSR_READ_4(sc, BGE_MAC_STS) & 3919 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3920 ifmr->ifm_status |= IFM_ACTIVE; 3921 } else { 3922 ifmr->ifm_active |= IFM_NONE; 3923 return; 3924 } 3925 3926 ifmr->ifm_active |= IFM_1000_SX; 3927 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3928 ifmr->ifm_active |= IFM_HDX; 3929 else 3930 ifmr->ifm_active |= IFM_FDX; 3931 } else { 3932 struct mii_data *mii = device_get_softc(sc->bge_miibus); 3933 3934 mii_pollstat(mii); 3935 ifmr->ifm_active = mii->mii_media_active; 3936 ifmr->ifm_status = mii->mii_media_status; 3937 } 3938 } 3939 3940 static int 3941 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3942 { 3943 struct bge_softc *sc = ifp->if_softc; 3944 struct ifreq *ifr = (struct ifreq *)data; 3945 int mask, error = 0; 3946 3947 ASSERT_SERIALIZED(ifp->if_serializer); 3948 3949 switch (command) { 3950 case SIOCSIFMTU: 3951 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) || 3952 (BGE_IS_JUMBO_CAPABLE(sc) && 3953 ifr->ifr_mtu > BGE_JUMBO_MTU)) { 3954 error = EINVAL; 3955 } else if (ifp->if_mtu != ifr->ifr_mtu) { 3956 ifp->if_mtu = ifr->ifr_mtu; 3957 if (ifp->if_flags & IFF_RUNNING) 3958 bge_init(sc); 3959 } 3960 break; 3961 case SIOCSIFFLAGS: 3962 if (ifp->if_flags & IFF_UP) { 3963 if (ifp->if_flags & IFF_RUNNING) { 3964 mask = ifp->if_flags ^ sc->bge_if_flags; 3965 3966 /* 3967 * If only the state of the PROMISC flag 3968 * changed, then just use the 'set promisc 3969 * mode' command instead of reinitializing 3970 * the entire NIC. Doing a full re-init 3971 * means reloading the firmware and waiting 3972 * for it to start up, which may take a 3973 * second or two. Similarly for ALLMULTI. 3974 */ 3975 if (mask & IFF_PROMISC) 3976 bge_setpromisc(sc); 3977 if (mask & IFF_ALLMULTI) 3978 bge_setmulti(sc); 3979 } else { 3980 bge_init(sc); 3981 } 3982 } else if (ifp->if_flags & IFF_RUNNING) { 3983 bge_stop(sc); 3984 } 3985 sc->bge_if_flags = ifp->if_flags; 3986 break; 3987 case SIOCADDMULTI: 3988 case SIOCDELMULTI: 3989 if (ifp->if_flags & IFF_RUNNING) 3990 bge_setmulti(sc); 3991 break; 3992 case SIOCSIFMEDIA: 3993 case SIOCGIFMEDIA: 3994 if (sc->bge_flags & BGE_FLAG_TBI) { 3995 error = ifmedia_ioctl(ifp, ifr, 3996 &sc->bge_ifmedia, command); 3997 } else { 3998 struct mii_data *mii; 3999 4000 mii = device_get_softc(sc->bge_miibus); 4001 error = ifmedia_ioctl(ifp, ifr, 4002 &mii->mii_media, command); 4003 } 4004 break; 4005 case SIOCSIFCAP: 4006 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4007 if (mask & IFCAP_HWCSUM) { 4008 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 4009 if (ifp->if_capenable & IFCAP_TXCSUM) 4010 ifp->if_hwassist |= BGE_CSUM_FEATURES; 4011 else 4012 ifp->if_hwassist &= ~BGE_CSUM_FEATURES; 4013 } 4014 if (mask & IFCAP_TSO) { 4015 ifp->if_capenable ^= IFCAP_TSO; 4016 if (ifp->if_capenable & IFCAP_TSO) 4017 ifp->if_hwassist |= CSUM_TSO; 4018 else 4019 ifp->if_hwassist &= ~CSUM_TSO; 4020 } 4021 break; 4022 default: 4023 error = ether_ioctl(ifp, command, data); 4024 break; 4025 } 4026 return error; 4027 } 4028 4029 static void 4030 bge_watchdog(struct ifnet *ifp) 4031 { 4032 struct bge_softc *sc = ifp->if_softc; 4033 4034 if_printf(ifp, "watchdog timeout -- resetting\n"); 4035 4036 bge_init(sc); 4037 4038 IFNET_STAT_INC(ifp, oerrors, 1); 4039 4040 if (!ifq_is_empty(&ifp->if_snd)) 4041 if_devstart(ifp); 4042 } 4043 4044 /* 4045 * Stop the adapter and free any mbufs allocated to the 4046 * RX and TX lists. 4047 */ 4048 static void 4049 bge_stop(struct bge_softc *sc) 4050 { 4051 struct ifnet *ifp = &sc->arpcom.ac_if; 4052 4053 ASSERT_SERIALIZED(ifp->if_serializer); 4054 4055 callout_stop(&sc->bge_stat_timer); 4056 4057 /* Disable host interrupts. */ 4058 bge_disable_intr(sc); 4059 4060 /* 4061 * Tell firmware we're shutting down. 4062 */ 4063 bge_stop_fw(sc); 4064 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 4065 4066 /* 4067 * Disable all of the receiver blocks 4068 */ 4069 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4070 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4071 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4072 if (BGE_IS_5700_FAMILY(sc)) 4073 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4074 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4075 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4076 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4077 4078 /* 4079 * Disable all of the transmit blocks 4080 */ 4081 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4082 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4083 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4084 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4085 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4086 if (BGE_IS_5700_FAMILY(sc)) 4087 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4088 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4089 4090 /* 4091 * Shut down all of the memory managers and related 4092 * state machines. 4093 */ 4094 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4095 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4096 if (BGE_IS_5700_FAMILY(sc)) 4097 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4098 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4099 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4100 if (!BGE_IS_5705_PLUS(sc)) { 4101 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4102 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4103 } 4104 4105 bge_reset(sc); 4106 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 4107 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 4108 4109 /* 4110 * Keep the ASF firmware running if up. 4111 */ 4112 if (sc->bge_asf_mode & ASF_STACKUP) 4113 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4114 else 4115 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4116 4117 /* Free the RX lists. */ 4118 bge_free_rx_ring_std(sc); 4119 4120 /* Free jumbo RX list. */ 4121 if (BGE_IS_JUMBO_CAPABLE(sc)) 4122 bge_free_rx_ring_jumbo(sc); 4123 4124 /* Free TX buffers. */ 4125 bge_free_tx_ring(sc); 4126 4127 sc->bge_status_tag = 0; 4128 sc->bge_link = 0; 4129 sc->bge_coal_chg = 0; 4130 4131 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4132 4133 ifp->if_flags &= ~IFF_RUNNING; 4134 ifq_clr_oactive(&ifp->if_snd); 4135 ifp->if_timer = 0; 4136 } 4137 4138 /* 4139 * Stop all chip I/O so that the kernel's probe routines don't 4140 * get confused by errant DMAs when rebooting. 4141 */ 4142 static void 4143 bge_shutdown(device_t dev) 4144 { 4145 struct bge_softc *sc = device_get_softc(dev); 4146 struct ifnet *ifp = &sc->arpcom.ac_if; 4147 4148 lwkt_serialize_enter(ifp->if_serializer); 4149 bge_stop(sc); 4150 lwkt_serialize_exit(ifp->if_serializer); 4151 } 4152 4153 static int 4154 bge_suspend(device_t dev) 4155 { 4156 struct bge_softc *sc = device_get_softc(dev); 4157 struct ifnet *ifp = &sc->arpcom.ac_if; 4158 4159 lwkt_serialize_enter(ifp->if_serializer); 4160 bge_stop(sc); 4161 lwkt_serialize_exit(ifp->if_serializer); 4162 4163 return 0; 4164 } 4165 4166 static int 4167 bge_resume(device_t dev) 4168 { 4169 struct bge_softc *sc = device_get_softc(dev); 4170 struct ifnet *ifp = &sc->arpcom.ac_if; 4171 4172 lwkt_serialize_enter(ifp->if_serializer); 4173 4174 if (ifp->if_flags & IFF_UP) { 4175 bge_init(sc); 4176 4177 if (!ifq_is_empty(&ifp->if_snd)) 4178 if_devstart(ifp); 4179 } 4180 4181 lwkt_serialize_exit(ifp->if_serializer); 4182 4183 return 0; 4184 } 4185 4186 static void 4187 bge_setpromisc(struct bge_softc *sc) 4188 { 4189 struct ifnet *ifp = &sc->arpcom.ac_if; 4190 4191 if (ifp->if_flags & IFF_PROMISC) 4192 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4193 else 4194 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4195 } 4196 4197 static void 4198 bge_dma_free(struct bge_softc *sc) 4199 { 4200 int i; 4201 4202 /* Destroy RX mbuf DMA stuffs. */ 4203 if (sc->bge_cdata.bge_rx_mtag != NULL) { 4204 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 4205 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 4206 sc->bge_cdata.bge_rx_std_dmamap[i]); 4207 } 4208 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 4209 sc->bge_cdata.bge_rx_tmpmap); 4210 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 4211 } 4212 4213 /* Destroy TX mbuf DMA stuffs. */ 4214 if (sc->bge_cdata.bge_tx_mtag != NULL) { 4215 for (i = 0; i < BGE_TX_RING_CNT; i++) { 4216 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 4217 sc->bge_cdata.bge_tx_dmamap[i]); 4218 } 4219 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 4220 } 4221 4222 /* Destroy standard RX ring */ 4223 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag, 4224 sc->bge_cdata.bge_rx_std_ring_map, 4225 sc->bge_ldata.bge_rx_std_ring); 4226 4227 if (BGE_IS_JUMBO_CAPABLE(sc)) 4228 bge_free_jumbo_mem(sc); 4229 4230 /* Destroy RX return ring */ 4231 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag, 4232 sc->bge_cdata.bge_rx_return_ring_map, 4233 sc->bge_ldata.bge_rx_return_ring); 4234 4235 /* Destroy TX ring */ 4236 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag, 4237 sc->bge_cdata.bge_tx_ring_map, 4238 sc->bge_ldata.bge_tx_ring); 4239 4240 /* Destroy status block */ 4241 bge_dma_block_free(sc->bge_cdata.bge_status_tag, 4242 sc->bge_cdata.bge_status_map, 4243 sc->bge_ldata.bge_status_block); 4244 4245 /* Destroy statistics block */ 4246 bge_dma_block_free(sc->bge_cdata.bge_stats_tag, 4247 sc->bge_cdata.bge_stats_map, 4248 sc->bge_ldata.bge_stats); 4249 4250 /* Destroy the parent tag */ 4251 if (sc->bge_cdata.bge_parent_tag != NULL) 4252 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 4253 } 4254 4255 static int 4256 bge_dma_alloc(struct bge_softc *sc) 4257 { 4258 struct ifnet *ifp = &sc->arpcom.ac_if; 4259 int i, error; 4260 bus_addr_t lowaddr; 4261 bus_size_t txmaxsz; 4262 4263 lowaddr = BUS_SPACE_MAXADDR; 4264 if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) 4265 lowaddr = BGE_DMA_MAXADDR_40BIT; 4266 4267 /* 4268 * Allocate the parent bus DMA tag appropriate for PCI. 4269 * 4270 * All of the NetExtreme/NetLink controllers have 4GB boundary 4271 * DMA bug. 4272 * Whenever an address crosses a multiple of the 4GB boundary 4273 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 4274 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 4275 * state machine will lockup and cause the device to hang. 4276 */ 4277 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G, 4278 lowaddr, BUS_SPACE_MAXADDR, 4279 NULL, NULL, 4280 BUS_SPACE_MAXSIZE_32BIT, 0, 4281 BUS_SPACE_MAXSIZE_32BIT, 4282 0, &sc->bge_cdata.bge_parent_tag); 4283 if (error) { 4284 if_printf(ifp, "could not allocate parent dma tag\n"); 4285 return error; 4286 } 4287 4288 /* 4289 * Create DMA tag and maps for RX mbufs. 4290 */ 4291 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0, 4292 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4293 NULL, NULL, MCLBYTES, 1, MCLBYTES, 4294 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 4295 &sc->bge_cdata.bge_rx_mtag); 4296 if (error) { 4297 if_printf(ifp, "could not allocate RX mbuf dma tag\n"); 4298 return error; 4299 } 4300 4301 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 4302 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap); 4303 if (error) { 4304 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 4305 sc->bge_cdata.bge_rx_mtag = NULL; 4306 return error; 4307 } 4308 4309 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 4310 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 4311 BUS_DMA_WAITOK, 4312 &sc->bge_cdata.bge_rx_std_dmamap[i]); 4313 if (error) { 4314 int j; 4315 4316 for (j = 0; j < i; ++j) { 4317 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 4318 sc->bge_cdata.bge_rx_std_dmamap[j]); 4319 } 4320 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 4321 sc->bge_cdata.bge_rx_mtag = NULL; 4322 4323 if_printf(ifp, "could not create DMA map for RX\n"); 4324 return error; 4325 } 4326 } 4327 4328 /* 4329 * Create DMA tag and maps for TX mbufs. 4330 */ 4331 if (sc->bge_flags & BGE_FLAG_TSO) 4332 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header); 4333 else 4334 txmaxsz = BGE_JUMBO_FRAMELEN; 4335 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0, 4336 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4337 NULL, NULL, 4338 txmaxsz, BGE_NSEG_NEW, PAGE_SIZE, 4339 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 4340 BUS_DMA_ONEBPAGE, 4341 &sc->bge_cdata.bge_tx_mtag); 4342 if (error) { 4343 if_printf(ifp, "could not allocate TX mbuf dma tag\n"); 4344 return error; 4345 } 4346 4347 for (i = 0; i < BGE_TX_RING_CNT; i++) { 4348 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 4349 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 4350 &sc->bge_cdata.bge_tx_dmamap[i]); 4351 if (error) { 4352 int j; 4353 4354 for (j = 0; j < i; ++j) { 4355 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 4356 sc->bge_cdata.bge_tx_dmamap[j]); 4357 } 4358 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 4359 sc->bge_cdata.bge_tx_mtag = NULL; 4360 4361 if_printf(ifp, "could not create DMA map for TX\n"); 4362 return error; 4363 } 4364 } 4365 4366 /* 4367 * Create DMA stuffs for standard RX ring. 4368 */ 4369 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ, 4370 &sc->bge_cdata.bge_rx_std_ring_tag, 4371 &sc->bge_cdata.bge_rx_std_ring_map, 4372 (void *)&sc->bge_ldata.bge_rx_std_ring, 4373 &sc->bge_ldata.bge_rx_std_ring_paddr); 4374 if (error) { 4375 if_printf(ifp, "could not create std RX ring\n"); 4376 return error; 4377 } 4378 4379 /* 4380 * Create jumbo buffer pool. 4381 */ 4382 if (BGE_IS_JUMBO_CAPABLE(sc)) { 4383 error = bge_alloc_jumbo_mem(sc); 4384 if (error) { 4385 if_printf(ifp, "could not create jumbo buffer pool\n"); 4386 return error; 4387 } 4388 } 4389 4390 /* 4391 * Create DMA stuffs for RX return ring. 4392 */ 4393 error = bge_dma_block_alloc(sc, 4394 BGE_RX_RTN_RING_SZ(sc->bge_return_ring_cnt), 4395 &sc->bge_cdata.bge_rx_return_ring_tag, 4396 &sc->bge_cdata.bge_rx_return_ring_map, 4397 (void *)&sc->bge_ldata.bge_rx_return_ring, 4398 &sc->bge_ldata.bge_rx_return_ring_paddr); 4399 if (error) { 4400 if_printf(ifp, "could not create RX ret ring\n"); 4401 return error; 4402 } 4403 4404 /* 4405 * Create DMA stuffs for TX ring. 4406 */ 4407 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ, 4408 &sc->bge_cdata.bge_tx_ring_tag, 4409 &sc->bge_cdata.bge_tx_ring_map, 4410 (void *)&sc->bge_ldata.bge_tx_ring, 4411 &sc->bge_ldata.bge_tx_ring_paddr); 4412 if (error) { 4413 if_printf(ifp, "could not create TX ring\n"); 4414 return error; 4415 } 4416 4417 /* 4418 * Create DMA stuffs for status block. 4419 */ 4420 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ, 4421 &sc->bge_cdata.bge_status_tag, 4422 &sc->bge_cdata.bge_status_map, 4423 (void *)&sc->bge_ldata.bge_status_block, 4424 &sc->bge_ldata.bge_status_block_paddr); 4425 if (error) { 4426 if_printf(ifp, "could not create status block\n"); 4427 return error; 4428 } 4429 4430 /* 4431 * Create DMA stuffs for statistics block. 4432 */ 4433 error = bge_dma_block_alloc(sc, BGE_STATS_SZ, 4434 &sc->bge_cdata.bge_stats_tag, 4435 &sc->bge_cdata.bge_stats_map, 4436 (void *)&sc->bge_ldata.bge_stats, 4437 &sc->bge_ldata.bge_stats_paddr); 4438 if (error) { 4439 if_printf(ifp, "could not create stats block\n"); 4440 return error; 4441 } 4442 return 0; 4443 } 4444 4445 static int 4446 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag, 4447 bus_dmamap_t *map, void **addr, bus_addr_t *paddr) 4448 { 4449 bus_dmamem_t dmem; 4450 int error; 4451 4452 error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0, 4453 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4454 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 4455 if (error) 4456 return error; 4457 4458 *tag = dmem.dmem_tag; 4459 *map = dmem.dmem_map; 4460 *addr = dmem.dmem_addr; 4461 *paddr = dmem.dmem_busaddr; 4462 4463 return 0; 4464 } 4465 4466 static void 4467 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr) 4468 { 4469 if (tag != NULL) { 4470 bus_dmamap_unload(tag, map); 4471 bus_dmamem_free(tag, addr, map); 4472 bus_dma_tag_destroy(tag); 4473 } 4474 } 4475 4476 /* 4477 * Grrr. The link status word in the status block does 4478 * not work correctly on the BCM5700 rev AX and BX chips, 4479 * according to all available information. Hence, we have 4480 * to enable MII interrupts in order to properly obtain 4481 * async link changes. Unfortunately, this also means that 4482 * we have to read the MAC status register to detect link 4483 * changes, thereby adding an additional register access to 4484 * the interrupt handler. 4485 * 4486 * XXX: perhaps link state detection procedure used for 4487 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4488 */ 4489 static void 4490 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused) 4491 { 4492 struct ifnet *ifp = &sc->arpcom.ac_if; 4493 struct mii_data *mii = device_get_softc(sc->bge_miibus); 4494 4495 mii_pollstat(mii); 4496 4497 if (!sc->bge_link && 4498 (mii->mii_media_status & IFM_ACTIVE) && 4499 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4500 sc->bge_link++; 4501 if (bootverbose) 4502 if_printf(ifp, "link UP\n"); 4503 } else if (sc->bge_link && 4504 (!(mii->mii_media_status & IFM_ACTIVE) || 4505 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4506 sc->bge_link = 0; 4507 if (bootverbose) 4508 if_printf(ifp, "link DOWN\n"); 4509 } 4510 4511 /* Clear the interrupt. */ 4512 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT); 4513 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4514 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS); 4515 } 4516 4517 static void 4518 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status) 4519 { 4520 struct ifnet *ifp = &sc->arpcom.ac_if; 4521 4522 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE) 4523 4524 /* 4525 * Sometimes PCS encoding errors are detected in 4526 * TBI mode (on fiber NICs), and for some reason 4527 * the chip will signal them as link changes. 4528 * If we get a link change event, but the 'PCS 4529 * encoding error' bit in the MAC status register 4530 * is set, don't bother doing a link check. 4531 * This avoids spurious "gigabit link up" messages 4532 * that sometimes appear on fiber NICs during 4533 * periods of heavy traffic. 4534 */ 4535 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4536 if (!sc->bge_link) { 4537 sc->bge_link++; 4538 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4539 BGE_CLRBIT(sc, BGE_MAC_MODE, 4540 BGE_MACMODE_TBI_SEND_CFGS); 4541 } 4542 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4543 4544 if (bootverbose) 4545 if_printf(ifp, "link UP\n"); 4546 4547 ifp->if_link_state = LINK_STATE_UP; 4548 if_link_state_change(ifp); 4549 } 4550 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) { 4551 if (sc->bge_link) { 4552 sc->bge_link = 0; 4553 4554 if (bootverbose) 4555 if_printf(ifp, "link DOWN\n"); 4556 4557 ifp->if_link_state = LINK_STATE_DOWN; 4558 if_link_state_change(ifp); 4559 } 4560 } 4561 4562 #undef PCS_ENCODE_ERR 4563 4564 /* Clear the attention. */ 4565 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4566 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4567 BGE_MACSTAT_LINK_CHANGED); 4568 } 4569 4570 static void 4571 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused) 4572 { 4573 struct ifnet *ifp = &sc->arpcom.ac_if; 4574 struct mii_data *mii = device_get_softc(sc->bge_miibus); 4575 4576 mii_pollstat(mii); 4577 bge_miibus_statchg(sc->bge_dev); 4578 4579 if (bootverbose) { 4580 if (sc->bge_link) 4581 if_printf(ifp, "link UP\n"); 4582 else 4583 if_printf(ifp, "link DOWN\n"); 4584 } 4585 4586 /* Clear the attention. */ 4587 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4588 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4589 BGE_MACSTAT_LINK_CHANGED); 4590 } 4591 4592 static void 4593 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused) 4594 { 4595 struct ifnet *ifp = &sc->arpcom.ac_if; 4596 struct mii_data *mii = device_get_softc(sc->bge_miibus); 4597 4598 mii_pollstat(mii); 4599 4600 if (!sc->bge_link && 4601 (mii->mii_media_status & IFM_ACTIVE) && 4602 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4603 sc->bge_link++; 4604 if (bootverbose) 4605 if_printf(ifp, "link UP\n"); 4606 } else if (sc->bge_link && 4607 (!(mii->mii_media_status & IFM_ACTIVE) || 4608 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4609 sc->bge_link = 0; 4610 if (bootverbose) 4611 if_printf(ifp, "link DOWN\n"); 4612 } 4613 4614 /* Clear the attention. */ 4615 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4616 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4617 BGE_MACSTAT_LINK_CHANGED); 4618 } 4619 4620 static int 4621 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS) 4622 { 4623 struct bge_softc *sc = arg1; 4624 4625 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4626 &sc->bge_rx_coal_ticks, 4627 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX, 4628 BGE_RX_COAL_TICKS_CHG); 4629 } 4630 4631 static int 4632 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS) 4633 { 4634 struct bge_softc *sc = arg1; 4635 4636 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4637 &sc->bge_tx_coal_ticks, 4638 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX, 4639 BGE_TX_COAL_TICKS_CHG); 4640 } 4641 4642 static int 4643 bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS) 4644 { 4645 struct bge_softc *sc = arg1; 4646 4647 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4648 &sc->bge_rx_coal_bds, 4649 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX, 4650 BGE_RX_COAL_BDS_CHG); 4651 } 4652 4653 static int 4654 bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS) 4655 { 4656 struct bge_softc *sc = arg1; 4657 4658 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4659 &sc->bge_tx_coal_bds, 4660 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX, 4661 BGE_TX_COAL_BDS_CHG); 4662 } 4663 4664 static int 4665 bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS) 4666 { 4667 struct bge_softc *sc = arg1; 4668 4669 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4670 &sc->bge_rx_coal_ticks_int, 4671 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX, 4672 BGE_RX_COAL_TICKS_INT_CHG); 4673 } 4674 4675 static int 4676 bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS) 4677 { 4678 struct bge_softc *sc = arg1; 4679 4680 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4681 &sc->bge_tx_coal_ticks_int, 4682 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX, 4683 BGE_TX_COAL_TICKS_INT_CHG); 4684 } 4685 4686 static int 4687 bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS) 4688 { 4689 struct bge_softc *sc = arg1; 4690 4691 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4692 &sc->bge_rx_coal_bds_int, 4693 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX, 4694 BGE_RX_COAL_BDS_INT_CHG); 4695 } 4696 4697 static int 4698 bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS) 4699 { 4700 struct bge_softc *sc = arg1; 4701 4702 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4703 &sc->bge_tx_coal_bds_int, 4704 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX, 4705 BGE_TX_COAL_BDS_INT_CHG); 4706 } 4707 4708 static int 4709 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal, 4710 int coal_min, int coal_max, uint32_t coal_chg_mask) 4711 { 4712 struct bge_softc *sc = arg1; 4713 struct ifnet *ifp = &sc->arpcom.ac_if; 4714 int error = 0, v; 4715 4716 lwkt_serialize_enter(ifp->if_serializer); 4717 4718 v = *coal; 4719 error = sysctl_handle_int(oidp, &v, 0, req); 4720 if (!error && req->newptr != NULL) { 4721 if (v < coal_min || v > coal_max) { 4722 error = EINVAL; 4723 } else { 4724 *coal = v; 4725 sc->bge_coal_chg |= coal_chg_mask; 4726 } 4727 } 4728 4729 lwkt_serialize_exit(ifp->if_serializer); 4730 return error; 4731 } 4732 4733 static void 4734 bge_coal_change(struct bge_softc *sc) 4735 { 4736 struct ifnet *ifp = &sc->arpcom.ac_if; 4737 4738 ASSERT_SERIALIZED(ifp->if_serializer); 4739 4740 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) { 4741 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, 4742 sc->bge_rx_coal_ticks); 4743 DELAY(10); 4744 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4745 4746 if (bootverbose) { 4747 if_printf(ifp, "rx_coal_ticks -> %u\n", 4748 sc->bge_rx_coal_ticks); 4749 } 4750 } 4751 4752 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) { 4753 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, 4754 sc->bge_tx_coal_ticks); 4755 DELAY(10); 4756 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS); 4757 4758 if (bootverbose) { 4759 if_printf(ifp, "tx_coal_ticks -> %u\n", 4760 sc->bge_tx_coal_ticks); 4761 } 4762 } 4763 4764 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_CHG) { 4765 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, 4766 sc->bge_rx_coal_bds); 4767 DELAY(10); 4768 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4769 4770 if (bootverbose) { 4771 if_printf(ifp, "rx_coal_bds -> %u\n", 4772 sc->bge_rx_coal_bds); 4773 } 4774 } 4775 4776 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_CHG) { 4777 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, 4778 sc->bge_tx_coal_bds); 4779 DELAY(10); 4780 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS); 4781 4782 if (bootverbose) { 4783 if_printf(ifp, "tx_max_coal_bds -> %u\n", 4784 sc->bge_tx_coal_bds); 4785 } 4786 } 4787 4788 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_INT_CHG) { 4789 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 4790 sc->bge_rx_coal_ticks_int); 4791 DELAY(10); 4792 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS_INT); 4793 4794 if (bootverbose) { 4795 if_printf(ifp, "rx_coal_ticks_int -> %u\n", 4796 sc->bge_rx_coal_ticks_int); 4797 } 4798 } 4799 4800 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_INT_CHG) { 4801 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 4802 sc->bge_tx_coal_ticks_int); 4803 DELAY(10); 4804 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS_INT); 4805 4806 if (bootverbose) { 4807 if_printf(ifp, "tx_coal_ticks_int -> %u\n", 4808 sc->bge_tx_coal_ticks_int); 4809 } 4810 } 4811 4812 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_INT_CHG) { 4813 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 4814 sc->bge_rx_coal_bds_int); 4815 DELAY(10); 4816 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT); 4817 4818 if (bootverbose) { 4819 if_printf(ifp, "rx_coal_bds_int -> %u\n", 4820 sc->bge_rx_coal_bds_int); 4821 } 4822 } 4823 4824 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_INT_CHG) { 4825 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 4826 sc->bge_tx_coal_bds_int); 4827 DELAY(10); 4828 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT); 4829 4830 if (bootverbose) { 4831 if_printf(ifp, "tx_coal_bds_int -> %u\n", 4832 sc->bge_tx_coal_bds_int); 4833 } 4834 } 4835 4836 sc->bge_coal_chg = 0; 4837 } 4838 4839 static void 4840 bge_enable_intr(struct bge_softc *sc) 4841 { 4842 struct ifnet *ifp = &sc->arpcom.ac_if; 4843 4844 lwkt_serialize_handler_enable(ifp->if_serializer); 4845 4846 /* 4847 * Enable interrupt. 4848 */ 4849 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 4850 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 4851 /* XXX Linux driver */ 4852 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 4853 } 4854 4855 /* 4856 * Unmask the interrupt when we stop polling. 4857 */ 4858 PCI_CLRBIT(sc->bge_dev, BGE_PCI_MISC_CTL, 4859 BGE_PCIMISCCTL_MASK_PCI_INTR, 4); 4860 4861 /* 4862 * Trigger another interrupt, since above writing 4863 * to interrupt mailbox0 may acknowledge pending 4864 * interrupt. 4865 */ 4866 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4867 } 4868 4869 static void 4870 bge_disable_intr(struct bge_softc *sc) 4871 { 4872 struct ifnet *ifp = &sc->arpcom.ac_if; 4873 4874 /* 4875 * Mask the interrupt when we start polling. 4876 */ 4877 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, 4878 BGE_PCIMISCCTL_MASK_PCI_INTR, 4); 4879 4880 /* 4881 * Acknowledge possible asserted interrupt. 4882 */ 4883 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4884 4885 sc->bge_npoll.ifpc_stcount = 0; 4886 4887 lwkt_serialize_handler_disable(ifp->if_serializer); 4888 } 4889 4890 static int 4891 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4892 { 4893 uint32_t mac_addr; 4894 int ret = 1; 4895 4896 mac_addr = bge_readmem_ind(sc, 0x0c14); 4897 if ((mac_addr >> 16) == 0x484b) { 4898 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4899 ether_addr[1] = (uint8_t)mac_addr; 4900 mac_addr = bge_readmem_ind(sc, 0x0c18); 4901 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4902 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4903 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4904 ether_addr[5] = (uint8_t)mac_addr; 4905 ret = 0; 4906 } 4907 return ret; 4908 } 4909 4910 static int 4911 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4912 { 4913 int mac_offset = BGE_EE_MAC_OFFSET; 4914 4915 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4916 mac_offset = BGE_EE_MAC_OFFSET_5906; 4917 4918 return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN); 4919 } 4920 4921 static int 4922 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4923 { 4924 if (sc->bge_flags & BGE_FLAG_NO_EEPROM) 4925 return 1; 4926 4927 return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4928 ETHER_ADDR_LEN); 4929 } 4930 4931 static int 4932 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4933 { 4934 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4935 /* NOTE: Order is critical */ 4936 bge_get_eaddr_mem, 4937 bge_get_eaddr_nvram, 4938 bge_get_eaddr_eeprom, 4939 NULL 4940 }; 4941 const bge_eaddr_fcn_t *func; 4942 4943 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4944 if ((*func)(sc, eaddr) == 0) 4945 break; 4946 } 4947 return (*func == NULL ? ENXIO : 0); 4948 } 4949 4950 /* 4951 * NOTE: 'm' is not freed upon failure 4952 */ 4953 struct mbuf * 4954 bge_defrag_shortdma(struct mbuf *m) 4955 { 4956 struct mbuf *n; 4957 int found; 4958 4959 /* 4960 * If device receive two back-to-back send BDs with less than 4961 * or equal to 8 total bytes then the device may hang. The two 4962 * back-to-back send BDs must in the same frame for this failure 4963 * to occur. Scan mbuf chains and see whether two back-to-back 4964 * send BDs are there. If this is the case, allocate new mbuf 4965 * and copy the frame to workaround the silicon bug. 4966 */ 4967 for (n = m, found = 0; n != NULL; n = n->m_next) { 4968 if (n->m_len < 8) { 4969 found++; 4970 if (found > 1) 4971 break; 4972 continue; 4973 } 4974 found = 0; 4975 } 4976 4977 if (found > 1) 4978 n = m_defrag(m, MB_DONTWAIT); 4979 else 4980 n = m; 4981 return n; 4982 } 4983 4984 static void 4985 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 4986 { 4987 int i; 4988 4989 BGE_CLRBIT(sc, reg, bit); 4990 for (i = 0; i < BGE_TIMEOUT; i++) { 4991 if ((CSR_READ_4(sc, reg) & bit) == 0) 4992 return; 4993 DELAY(100); 4994 } 4995 } 4996 4997 static void 4998 bge_link_poll(struct bge_softc *sc) 4999 { 5000 uint32_t status; 5001 5002 status = CSR_READ_4(sc, BGE_MAC_STS); 5003 if ((status & sc->bge_link_chg) || sc->bge_link_evt) { 5004 sc->bge_link_evt = 0; 5005 sc->bge_link_upd(sc, status); 5006 } 5007 } 5008 5009 static void 5010 bge_enable_msi(struct bge_softc *sc) 5011 { 5012 uint32_t msi_mode; 5013 5014 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE); 5015 msi_mode |= BGE_MSIMODE_ENABLE; 5016 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 5017 /* 5018 * According to all of the datasheets that are publicly 5019 * available, bit 5 of the MSI_MODE is defined to be 5020 * "MSI FIFO Underrun Attn" for BCM5755+ and BCM5906, on 5021 * which "oneshot MSI" is enabled. However, it is always 5022 * safe to clear it here. 5023 */ 5024 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE; 5025 } 5026 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode); 5027 } 5028 5029 static int 5030 bge_setup_tso(struct bge_softc *sc, struct mbuf **mp, 5031 uint16_t *mss0, uint16_t *flags0) 5032 { 5033 struct mbuf *m; 5034 struct ip *ip; 5035 struct tcphdr *th; 5036 int thoff, iphlen, hoff, hlen; 5037 uint16_t flags, mss; 5038 5039 m = *mp; 5040 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 5041 5042 hoff = m->m_pkthdr.csum_lhlen; 5043 iphlen = m->m_pkthdr.csum_iphlen; 5044 thoff = m->m_pkthdr.csum_thlen; 5045 5046 KASSERT(hoff > 0, ("invalid ether header len")); 5047 KASSERT(iphlen > 0, ("invalid ip header len")); 5048 KASSERT(thoff > 0, ("invalid tcp header len")); 5049 5050 if (__predict_false(m->m_len < hoff + iphlen + thoff)) { 5051 m = m_pullup(m, hoff + iphlen + thoff); 5052 if (m == NULL) { 5053 *mp = NULL; 5054 return ENOBUFS; 5055 } 5056 *mp = m; 5057 } 5058 ip = mtodoff(m, struct ip *, hoff); 5059 th = mtodoff(m, struct tcphdr *, hoff + iphlen); 5060 5061 mss = m->m_pkthdr.tso_segsz; 5062 flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA; 5063 5064 ip->ip_len = htons(mss + iphlen + thoff); 5065 th->th_sum = 0; 5066 5067 hlen = (iphlen + thoff) >> 2; 5068 mss |= (hlen << 11); 5069 5070 *mss0 = mss; 5071 *flags0 = flags; 5072 5073 return 0; 5074 } 5075 5076 static void 5077 bge_stop_fw(struct bge_softc *sc) 5078 { 5079 int i; 5080 5081 if (sc->bge_asf_mode) { 5082 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 5083 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 5084 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 5085 5086 for (i = 0; i < 100; i++ ) { 5087 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 5088 BGE_RX_CPU_DRV_EVENT)) 5089 break; 5090 DELAY(10); 5091 } 5092 } 5093 } 5094 5095 static void 5096 bge_sig_pre_reset(struct bge_softc *sc, int type) 5097 { 5098 /* 5099 * Some chips don't like this so only do this if ASF is enabled 5100 */ 5101 if (sc->bge_asf_mode) 5102 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 5103 5104 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 5105 switch (type) { 5106 case BGE_RESET_START: 5107 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5108 BGE_FW_DRV_STATE_START); 5109 break; 5110 case BGE_RESET_SHUTDOWN: 5111 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5112 BGE_FW_DRV_STATE_UNLOAD); 5113 break; 5114 case BGE_RESET_SUSPEND: 5115 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5116 BGE_FW_DRV_STATE_SUSPEND); 5117 break; 5118 } 5119 } 5120 5121 #ifdef notyet 5122 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 5123 bge_ape_driver_state_change(sc, type); 5124 #endif 5125 } 5126 5127 static void 5128 bge_sig_legacy(struct bge_softc *sc, int type) 5129 { 5130 if (sc->bge_asf_mode) { 5131 switch (type) { 5132 case BGE_RESET_START: 5133 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5134 BGE_FW_DRV_STATE_START); 5135 break; 5136 case BGE_RESET_SHUTDOWN: 5137 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5138 BGE_FW_DRV_STATE_UNLOAD); 5139 break; 5140 } 5141 } 5142 } 5143 5144 static void 5145 bge_sig_post_reset(struct bge_softc *sc, int type) 5146 { 5147 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 5148 switch (type) { 5149 case BGE_RESET_START: 5150 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5151 BGE_FW_DRV_STATE_START_DONE); 5152 /* START DONE */ 5153 break; 5154 case BGE_RESET_SHUTDOWN: 5155 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 5156 BGE_FW_DRV_STATE_UNLOAD_DONE); 5157 break; 5158 } 5159 } 5160 #ifdef notyet 5161 if (type == BGE_RESET_SHUTDOWN) 5162 bge_ape_driver_state_change(sc, type); 5163 #endif 5164 } 5165 5166 static void 5167 bge_asf_driver_up(struct bge_softc *sc) 5168 { 5169 if (sc->bge_asf_mode & ASF_STACKUP) { 5170 /* Send ASF heartbeat aprox. every 2s */ 5171 if (sc->bge_asf_count) 5172 sc->bge_asf_count --; 5173 else { 5174 sc->bge_asf_count = 2; 5175 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 5176 BGE_FW_CMD_DRV_ALIVE); 5177 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 5178 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 5179 BGE_FW_HB_TIMEOUT_SEC); 5180 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 5181 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 5182 BGE_RX_CPU_DRV_EVENT); 5183 } 5184 } 5185 } 5186