1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $ 34 */ 35 36 /* 37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Engineer, Wind River Systems 41 */ 42 43 /* 44 * The Broadcom BCM5700 is based on technology originally developed by 45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 49 * frames, highly configurable RX filtering, and 16 RX and TX queues 50 * (which, along with RX filter rules, can be used for QOS applications). 51 * Other features, such as TCP segmentation, may be available as part 52 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 53 * firmware images can be stored in hardware and need not be compiled 54 * into the driver. 55 * 56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 58 * 59 * The BCM5701 is a single-chip solution incorporating both the BCM5700 60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 61 * does not support external SSRAM. 62 * 63 * Broadcom also produces a variation of the BCM5700 under the "Altima" 64 * brand name, which is functionally similar but lacks PCI-X support. 65 * 66 * Without external SSRAM, you can only have at most 4 TX rings, 67 * and the use of the mini RX ring is disabled. This seems to imply 68 * that these features are simply not available on the BCM5701. As a 69 * result, this driver does not implement any support for the mini RX 70 * ring. 71 */ 72 73 #include "opt_polling.h" 74 75 #include <sys/param.h> 76 #include <sys/bus.h> 77 #include <sys/endian.h> 78 #include <sys/kernel.h> 79 #include <sys/ktr.h> 80 #include <sys/interrupt.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/queue.h> 84 #include <sys/rman.h> 85 #include <sys/serialize.h> 86 #include <sys/socket.h> 87 #include <sys/sockio.h> 88 #include <sys/sysctl.h> 89 90 #include <netinet/ip.h> 91 #include <netinet/tcp.h> 92 93 #include <net/bpf.h> 94 #include <net/ethernet.h> 95 #include <net/if.h> 96 #include <net/if_arp.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 #include <net/if_types.h> 100 #include <net/ifq_var.h> 101 #include <net/vlan/if_vlan_var.h> 102 #include <net/vlan/if_vlan_ether.h> 103 104 #include <dev/netif/mii_layer/mii.h> 105 #include <dev/netif/mii_layer/miivar.h> 106 #include <dev/netif/mii_layer/brgphyreg.h> 107 108 #include <bus/pci/pcidevs.h> 109 #include <bus/pci/pcireg.h> 110 #include <bus/pci/pcivar.h> 111 112 #include <dev/netif/bge/if_bgereg.h> 113 #include <dev/netif/bge/if_bgevar.h> 114 115 /* "device miibus" required. See GENERIC if you get errors here. */ 116 #include "miibus_if.h" 117 118 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 119 120 static const struct bge_type { 121 uint16_t bge_vid; 122 uint16_t bge_did; 123 char *bge_name; 124 } bge_devs[] = { 125 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996, 126 "3COM 3C996 Gigabit Ethernet" }, 127 128 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700, 129 "Alteon BCM5700 Gigabit Ethernet" }, 130 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701, 131 "Alteon BCM5701 Gigabit Ethernet" }, 132 133 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000, 134 "Altima AC1000 Gigabit Ethernet" }, 135 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001, 136 "Altima AC1002 Gigabit Ethernet" }, 137 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100, 138 "Altima AC9100 Gigabit Ethernet" }, 139 140 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701, 141 "Apple BCM5701 Gigabit Ethernet" }, 142 143 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700, 144 "Broadcom BCM5700 Gigabit Ethernet" }, 145 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701, 146 "Broadcom BCM5701 Gigabit Ethernet" }, 147 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702, 148 "Broadcom BCM5702 Gigabit Ethernet" }, 149 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X, 150 "Broadcom BCM5702X Gigabit Ethernet" }, 151 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT, 152 "Broadcom BCM5702 Gigabit Ethernet" }, 153 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703, 154 "Broadcom BCM5703 Gigabit Ethernet" }, 155 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X, 156 "Broadcom BCM5703X Gigabit Ethernet" }, 157 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3, 158 "Broadcom BCM5703 Gigabit Ethernet" }, 159 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C, 160 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 161 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S, 162 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 163 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT, 164 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 165 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705, 166 "Broadcom BCM5705 Gigabit Ethernet" }, 167 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F, 168 "Broadcom BCM5705F Gigabit Ethernet" }, 169 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K, 170 "Broadcom BCM5705K Gigabit Ethernet" }, 171 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M, 172 "Broadcom BCM5705M Gigabit Ethernet" }, 173 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 174 "Broadcom BCM5705M Gigabit Ethernet" }, 175 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714, 176 "Broadcom BCM5714C Gigabit Ethernet" }, 177 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S, 178 "Broadcom BCM5714S Gigabit Ethernet" }, 179 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715, 180 "Broadcom BCM5715 Gigabit Ethernet" }, 181 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S, 182 "Broadcom BCM5715S Gigabit Ethernet" }, 183 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720, 184 "Broadcom BCM5720 Gigabit Ethernet" }, 185 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721, 186 "Broadcom BCM5721 Gigabit Ethernet" }, 187 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722, 188 "Broadcom BCM5722 Gigabit Ethernet" }, 189 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723, 190 "Broadcom BCM5723 Gigabit Ethernet" }, 191 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750, 192 "Broadcom BCM5750 Gigabit Ethernet" }, 193 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M, 194 "Broadcom BCM5750M Gigabit Ethernet" }, 195 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751, 196 "Broadcom BCM5751 Gigabit Ethernet" }, 197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F, 198 "Broadcom BCM5751F Gigabit Ethernet" }, 199 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M, 200 "Broadcom BCM5751M Gigabit Ethernet" }, 201 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752, 202 "Broadcom BCM5752 Gigabit Ethernet" }, 203 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M, 204 "Broadcom BCM5752M Gigabit Ethernet" }, 205 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753, 206 "Broadcom BCM5753 Gigabit Ethernet" }, 207 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F, 208 "Broadcom BCM5753F Gigabit Ethernet" }, 209 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M, 210 "Broadcom BCM5753M Gigabit Ethernet" }, 211 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754, 212 "Broadcom BCM5754 Gigabit Ethernet" }, 213 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M, 214 "Broadcom BCM5754M Gigabit Ethernet" }, 215 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755, 216 "Broadcom BCM5755 Gigabit Ethernet" }, 217 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M, 218 "Broadcom BCM5755M Gigabit Ethernet" }, 219 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756, 220 "Broadcom BCM5756 Gigabit Ethernet" }, 221 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761, 222 "Broadcom BCM5761 Gigabit Ethernet" }, 223 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E, 224 "Broadcom BCM5761E Gigabit Ethernet" }, 225 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S, 226 "Broadcom BCM5761S Gigabit Ethernet" }, 227 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE, 228 "Broadcom BCM5761SE Gigabit Ethernet" }, 229 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764, 230 "Broadcom BCM5764 Gigabit Ethernet" }, 231 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780, 232 "Broadcom BCM5780 Gigabit Ethernet" }, 233 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S, 234 "Broadcom BCM5780S Gigabit Ethernet" }, 235 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781, 236 "Broadcom BCM5781 Gigabit Ethernet" }, 237 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782, 238 "Broadcom BCM5782 Gigabit Ethernet" }, 239 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784, 240 "Broadcom BCM5784 Gigabit Ethernet" }, 241 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F, 242 "Broadcom BCM5785F Gigabit Ethernet" }, 243 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G, 244 "Broadcom BCM5785G Gigabit Ethernet" }, 245 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786, 246 "Broadcom BCM5786 Gigabit Ethernet" }, 247 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787, 248 "Broadcom BCM5787 Gigabit Ethernet" }, 249 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F, 250 "Broadcom BCM5787F Gigabit Ethernet" }, 251 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M, 252 "Broadcom BCM5787M Gigabit Ethernet" }, 253 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788, 254 "Broadcom BCM5788 Gigabit Ethernet" }, 255 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789, 256 "Broadcom BCM5789 Gigabit Ethernet" }, 257 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901, 258 "Broadcom BCM5901 Fast Ethernet" }, 259 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2, 260 "Broadcom BCM5901A2 Fast Ethernet" }, 261 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M, 262 "Broadcom BCM5903M Fast Ethernet" }, 263 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906, 264 "Broadcom BCM5906 Fast Ethernet"}, 265 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M, 266 "Broadcom BCM5906M Fast Ethernet"}, 267 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760, 268 "Broadcom BCM57760 Gigabit Ethernet"}, 269 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780, 270 "Broadcom BCM57780 Gigabit Ethernet"}, 271 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788, 272 "Broadcom BCM57788 Gigabit Ethernet"}, 273 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790, 274 "Broadcom BCM57790 Gigabit Ethernet"}, 275 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 276 "SysKonnect Gigabit Ethernet" }, 277 278 { 0, 0, NULL } 279 }; 280 281 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 282 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 283 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 284 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 285 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 286 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 287 #define BGE_IS_5788(sc) ((sc)->bge_flags & BGE_FLAG_5788) 288 289 #define BGE_IS_CRIPPLED(sc) \ 290 (BGE_IS_5788((sc)) || (sc)->bge_asicrev == BGE_ASICREV_BCM5700) 291 292 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 293 294 static int bge_probe(device_t); 295 static int bge_attach(device_t); 296 static int bge_detach(device_t); 297 static void bge_txeof(struct bge_softc *, uint16_t); 298 static void bge_rxeof(struct bge_softc *, uint16_t); 299 300 static void bge_tick(void *); 301 static void bge_stats_update(struct bge_softc *); 302 static void bge_stats_update_regs(struct bge_softc *); 303 static struct mbuf * 304 bge_defrag_shortdma(struct mbuf *); 305 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 306 static int bge_setup_tso(struct bge_softc *, struct mbuf **, 307 uint16_t *, uint16_t *); 308 309 #ifdef DEVICE_POLLING 310 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 311 #endif 312 static void bge_intr_crippled(void *); 313 static void bge_intr_legacy(void *); 314 static void bge_msi(void *); 315 static void bge_msi_oneshot(void *); 316 static void bge_intr(struct bge_softc *); 317 static void bge_enable_intr(struct bge_softc *); 318 static void bge_disable_intr(struct bge_softc *); 319 static void bge_start(struct ifnet *); 320 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 321 static void bge_init(void *); 322 static void bge_stop(struct bge_softc *); 323 static void bge_watchdog(struct ifnet *); 324 static void bge_shutdown(device_t); 325 static int bge_suspend(device_t); 326 static int bge_resume(device_t); 327 static int bge_ifmedia_upd(struct ifnet *); 328 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 329 330 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 331 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 332 333 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *); 334 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t); 335 336 static void bge_setmulti(struct bge_softc *); 337 static void bge_setpromisc(struct bge_softc *); 338 static void bge_enable_msi(struct bge_softc *sc); 339 340 static int bge_alloc_jumbo_mem(struct bge_softc *); 341 static void bge_free_jumbo_mem(struct bge_softc *); 342 static struct bge_jslot 343 *bge_jalloc(struct bge_softc *); 344 static void bge_jfree(void *); 345 static void bge_jref(void *); 346 static int bge_newbuf_std(struct bge_softc *, int, int); 347 static int bge_newbuf_jumbo(struct bge_softc *, int, int); 348 static void bge_setup_rxdesc_std(struct bge_softc *, int); 349 static void bge_setup_rxdesc_jumbo(struct bge_softc *, int); 350 static int bge_init_rx_ring_std(struct bge_softc *); 351 static void bge_free_rx_ring_std(struct bge_softc *); 352 static int bge_init_rx_ring_jumbo(struct bge_softc *); 353 static void bge_free_rx_ring_jumbo(struct bge_softc *); 354 static void bge_free_tx_ring(struct bge_softc *); 355 static int bge_init_tx_ring(struct bge_softc *); 356 357 static int bge_chipinit(struct bge_softc *); 358 static int bge_blockinit(struct bge_softc *); 359 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 360 361 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t); 362 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t); 363 #ifdef notdef 364 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t); 365 #endif 366 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t); 367 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t); 368 static void bge_writembx(struct bge_softc *, int, int); 369 370 static int bge_miibus_readreg(device_t, int, int); 371 static int bge_miibus_writereg(device_t, int, int, int); 372 static void bge_miibus_statchg(device_t); 373 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t); 374 static void bge_tbi_link_upd(struct bge_softc *, uint32_t); 375 static void bge_copper_link_upd(struct bge_softc *, uint32_t); 376 static void bge_autopoll_link_upd(struct bge_softc *, uint32_t); 377 static void bge_link_poll(struct bge_softc *); 378 379 static void bge_reset(struct bge_softc *); 380 381 static int bge_dma_alloc(struct bge_softc *); 382 static void bge_dma_free(struct bge_softc *); 383 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t, 384 bus_dma_tag_t *, bus_dmamap_t *, 385 void **, bus_addr_t *); 386 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *); 387 388 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 389 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 390 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 391 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 392 393 static void bge_coal_change(struct bge_softc *); 394 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS); 395 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS); 396 static int bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS); 397 static int bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS); 398 static int bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS); 399 static int bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS); 400 static int bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS); 401 static int bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS); 402 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, 403 int, int, uint32_t); 404 405 /* 406 * Set following tunable to 1 for some IBM blade servers with the DNLK 407 * switch module. Auto negotiation is broken for those configurations. 408 */ 409 static int bge_fake_autoneg = 0; 410 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg); 411 412 static int bge_msi_enable = 1; 413 TUNABLE_INT("hw.bge.msi.enable", &bge_msi_enable); 414 415 #if !defined(KTR_IF_BGE) 416 #define KTR_IF_BGE KTR_ALL 417 #endif 418 KTR_INFO_MASTER(if_bge); 419 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr"); 420 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt"); 421 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt"); 422 #define logif(name) KTR_LOG(if_bge_ ## name) 423 424 static device_method_t bge_methods[] = { 425 /* Device interface */ 426 DEVMETHOD(device_probe, bge_probe), 427 DEVMETHOD(device_attach, bge_attach), 428 DEVMETHOD(device_detach, bge_detach), 429 DEVMETHOD(device_shutdown, bge_shutdown), 430 DEVMETHOD(device_suspend, bge_suspend), 431 DEVMETHOD(device_resume, bge_resume), 432 433 /* bus interface */ 434 DEVMETHOD(bus_print_child, bus_generic_print_child), 435 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 436 437 /* MII interface */ 438 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 439 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 440 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 441 442 { 0, 0 } 443 }; 444 445 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc)); 446 static devclass_t bge_devclass; 447 448 DECLARE_DUMMY_MODULE(if_bge); 449 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL); 450 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL); 451 452 static uint32_t 453 bge_readmem_ind(struct bge_softc *sc, uint32_t off) 454 { 455 device_t dev = sc->bge_dev; 456 uint32_t val; 457 458 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 459 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 460 return 0; 461 462 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 463 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 464 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 465 return (val); 466 } 467 468 static void 469 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val) 470 { 471 device_t dev = sc->bge_dev; 472 473 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 474 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 475 return; 476 477 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 478 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 479 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 480 } 481 482 #ifdef notdef 483 static uint32_t 484 bge_readreg_ind(struct bge_softc *sc, uin32_t off) 485 { 486 device_t dev = sc->bge_dev; 487 488 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 489 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 490 } 491 #endif 492 493 static void 494 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val) 495 { 496 device_t dev = sc->bge_dev; 497 498 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 499 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 500 } 501 502 static void 503 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val) 504 { 505 CSR_WRITE_4(sc, off, val); 506 } 507 508 static void 509 bge_writembx(struct bge_softc *sc, int off, int val) 510 { 511 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 512 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 513 514 CSR_WRITE_4(sc, off, val); 515 if (sc->bge_mbox_reorder) 516 CSR_READ_4(sc, off); 517 } 518 519 static uint8_t 520 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 521 { 522 uint32_t access, byte = 0; 523 int i; 524 525 /* Lock. */ 526 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 527 for (i = 0; i < 8000; i++) { 528 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 529 break; 530 DELAY(20); 531 } 532 if (i == 8000) 533 return (1); 534 535 /* Enable access. */ 536 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 537 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 538 539 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 540 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 541 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 542 DELAY(10); 543 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 544 DELAY(10); 545 break; 546 } 547 } 548 549 if (i == BGE_TIMEOUT * 10) { 550 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n"); 551 return (1); 552 } 553 554 /* Get result. */ 555 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 556 557 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 558 559 /* Disable access. */ 560 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 561 562 /* Unlock. */ 563 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 564 CSR_READ_4(sc, BGE_NVRAM_SWARB); 565 566 return (0); 567 } 568 569 /* 570 * Read a sequence of bytes from NVRAM. 571 */ 572 static int 573 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 574 { 575 int err = 0, i; 576 uint8_t byte = 0; 577 578 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 579 return (1); 580 581 for (i = 0; i < cnt; i++) { 582 err = bge_nvram_getbyte(sc, off + i, &byte); 583 if (err) 584 break; 585 *(dest + i) = byte; 586 } 587 588 return (err ? 1 : 0); 589 } 590 591 /* 592 * Read a byte of data stored in the EEPROM at address 'addr.' The 593 * BCM570x supports both the traditional bitbang interface and an 594 * auto access interface for reading the EEPROM. We use the auto 595 * access method. 596 */ 597 static uint8_t 598 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest) 599 { 600 int i; 601 uint32_t byte = 0; 602 603 /* 604 * Enable use of auto EEPROM access so we can avoid 605 * having to use the bitbang method. 606 */ 607 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 608 609 /* Reset the EEPROM, load the clock period. */ 610 CSR_WRITE_4(sc, BGE_EE_ADDR, 611 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 612 DELAY(20); 613 614 /* Issue the read EEPROM command. */ 615 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 616 617 /* Wait for completion */ 618 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 619 DELAY(10); 620 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 621 break; 622 } 623 624 if (i == BGE_TIMEOUT) { 625 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n"); 626 return(1); 627 } 628 629 /* Get result. */ 630 byte = CSR_READ_4(sc, BGE_EE_DATA); 631 632 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 633 634 return(0); 635 } 636 637 /* 638 * Read a sequence of bytes from the EEPROM. 639 */ 640 static int 641 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len) 642 { 643 size_t i; 644 int err; 645 uint8_t byte; 646 647 for (byte = 0, err = 0, i = 0; i < len; i++) { 648 err = bge_eeprom_getbyte(sc, off + i, &byte); 649 if (err) 650 break; 651 *(dest + i) = byte; 652 } 653 654 return(err ? 1 : 0); 655 } 656 657 static int 658 bge_miibus_readreg(device_t dev, int phy, int reg) 659 { 660 struct bge_softc *sc = device_get_softc(dev); 661 uint32_t val; 662 int i; 663 664 KASSERT(phy == sc->bge_phyno, 665 ("invalid phyno %d, should be %d", phy, sc->bge_phyno)); 666 667 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 668 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 669 CSR_WRITE_4(sc, BGE_MI_MODE, 670 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 671 DELAY(80); 672 } 673 674 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 675 BGE_MIPHY(phy) | BGE_MIREG(reg)); 676 677 /* Poll for the PHY register access to complete. */ 678 for (i = 0; i < BGE_TIMEOUT; i++) { 679 DELAY(10); 680 val = CSR_READ_4(sc, BGE_MI_COMM); 681 if ((val & BGE_MICOMM_BUSY) == 0) { 682 DELAY(5); 683 val = CSR_READ_4(sc, BGE_MI_COMM); 684 break; 685 } 686 } 687 if (i == BGE_TIMEOUT) { 688 if_printf(&sc->arpcom.ac_if, "PHY read timed out " 689 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val); 690 val = 0; 691 } 692 693 /* Restore the autopoll bit if necessary. */ 694 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 695 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 696 DELAY(80); 697 } 698 699 if (val & BGE_MICOMM_READFAIL) 700 return 0; 701 702 return (val & 0xFFFF); 703 } 704 705 static int 706 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 707 { 708 struct bge_softc *sc = device_get_softc(dev); 709 int i; 710 711 KASSERT(phy == sc->bge_phyno, 712 ("invalid phyno %d, should be %d", phy, sc->bge_phyno)); 713 714 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 715 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 716 return 0; 717 718 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 719 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 720 CSR_WRITE_4(sc, BGE_MI_MODE, 721 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 722 DELAY(80); 723 } 724 725 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 726 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 727 728 for (i = 0; i < BGE_TIMEOUT; i++) { 729 DELAY(10); 730 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 731 DELAY(5); 732 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 733 break; 734 } 735 } 736 if (i == BGE_TIMEOUT) { 737 if_printf(&sc->arpcom.ac_if, "PHY write timed out " 738 "(phy %d, reg %d, val %d)\n", phy, reg, val); 739 } 740 741 /* Restore the autopoll bit if necessary. */ 742 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 743 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 744 DELAY(80); 745 } 746 747 return 0; 748 } 749 750 static void 751 bge_miibus_statchg(device_t dev) 752 { 753 struct bge_softc *sc; 754 struct mii_data *mii; 755 756 sc = device_get_softc(dev); 757 mii = device_get_softc(sc->bge_miibus); 758 759 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 760 (IFM_ACTIVE | IFM_AVALID)) { 761 switch (IFM_SUBTYPE(mii->mii_media_active)) { 762 case IFM_10_T: 763 case IFM_100_TX: 764 sc->bge_link = 1; 765 break; 766 case IFM_1000_T: 767 case IFM_1000_SX: 768 case IFM_2500_SX: 769 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 770 sc->bge_link = 1; 771 else 772 sc->bge_link = 0; 773 break; 774 default: 775 sc->bge_link = 0; 776 break; 777 } 778 } else { 779 sc->bge_link = 0; 780 } 781 if (sc->bge_link == 0) 782 return; 783 784 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 785 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 786 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 787 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 788 } else { 789 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 790 } 791 792 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 793 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 794 } else { 795 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 796 } 797 } 798 799 /* 800 * Memory management for jumbo frames. 801 */ 802 static int 803 bge_alloc_jumbo_mem(struct bge_softc *sc) 804 { 805 struct ifnet *ifp = &sc->arpcom.ac_if; 806 struct bge_jslot *entry; 807 uint8_t *ptr; 808 bus_addr_t paddr; 809 int i, error; 810 811 /* 812 * Create tag for jumbo mbufs. 813 * This is really a bit of a kludge. We allocate a special 814 * jumbo buffer pool which (thanks to the way our DMA 815 * memory allocation works) will consist of contiguous 816 * pages. This means that even though a jumbo buffer might 817 * be larger than a page size, we don't really need to 818 * map it into more than one DMA segment. However, the 819 * default mbuf tag will result in multi-segment mappings, 820 * so we have to create a special jumbo mbuf tag that 821 * lets us get away with mapping the jumbo buffers as 822 * a single segment. I think eventually the driver should 823 * be changed so that it uses ordinary mbufs and cluster 824 * buffers, i.e. jumbo frames can span multiple DMA 825 * descriptors. But that's a project for another day. 826 */ 827 828 /* 829 * Create DMA stuffs for jumbo RX ring. 830 */ 831 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ, 832 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 833 &sc->bge_cdata.bge_rx_jumbo_ring_map, 834 (void *)&sc->bge_ldata.bge_rx_jumbo_ring, 835 &sc->bge_ldata.bge_rx_jumbo_ring_paddr); 836 if (error) { 837 if_printf(ifp, "could not create jumbo RX ring\n"); 838 return error; 839 } 840 841 /* 842 * Create DMA stuffs for jumbo buffer block. 843 */ 844 error = bge_dma_block_alloc(sc, BGE_JMEM, 845 &sc->bge_cdata.bge_jumbo_tag, 846 &sc->bge_cdata.bge_jumbo_map, 847 (void **)&sc->bge_ldata.bge_jumbo_buf, 848 &paddr); 849 if (error) { 850 if_printf(ifp, "could not create jumbo buffer\n"); 851 return error; 852 } 853 854 SLIST_INIT(&sc->bge_jfree_listhead); 855 856 /* 857 * Now divide it up into 9K pieces and save the addresses 858 * in an array. Note that we play an evil trick here by using 859 * the first few bytes in the buffer to hold the the address 860 * of the softc structure for this interface. This is because 861 * bge_jfree() needs it, but it is called by the mbuf management 862 * code which will not pass it to us explicitly. 863 */ 864 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) { 865 entry = &sc->bge_cdata.bge_jslots[i]; 866 entry->bge_sc = sc; 867 entry->bge_buf = ptr; 868 entry->bge_paddr = paddr; 869 entry->bge_inuse = 0; 870 entry->bge_slot = i; 871 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link); 872 873 ptr += BGE_JLEN; 874 paddr += BGE_JLEN; 875 } 876 return 0; 877 } 878 879 static void 880 bge_free_jumbo_mem(struct bge_softc *sc) 881 { 882 /* Destroy jumbo RX ring. */ 883 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 884 sc->bge_cdata.bge_rx_jumbo_ring_map, 885 sc->bge_ldata.bge_rx_jumbo_ring); 886 887 /* Destroy jumbo buffer block. */ 888 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag, 889 sc->bge_cdata.bge_jumbo_map, 890 sc->bge_ldata.bge_jumbo_buf); 891 } 892 893 /* 894 * Allocate a jumbo buffer. 895 */ 896 static struct bge_jslot * 897 bge_jalloc(struct bge_softc *sc) 898 { 899 struct bge_jslot *entry; 900 901 lwkt_serialize_enter(&sc->bge_jslot_serializer); 902 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 903 if (entry) { 904 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link); 905 entry->bge_inuse = 1; 906 } else { 907 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n"); 908 } 909 lwkt_serialize_exit(&sc->bge_jslot_serializer); 910 return(entry); 911 } 912 913 /* 914 * Adjust usage count on a jumbo buffer. 915 */ 916 static void 917 bge_jref(void *arg) 918 { 919 struct bge_jslot *entry = (struct bge_jslot *)arg; 920 struct bge_softc *sc = entry->bge_sc; 921 922 if (sc == NULL) 923 panic("bge_jref: can't find softc pointer!"); 924 925 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) { 926 panic("bge_jref: asked to reference buffer " 927 "that we don't manage!"); 928 } else if (entry->bge_inuse == 0) { 929 panic("bge_jref: buffer already free!"); 930 } else { 931 atomic_add_int(&entry->bge_inuse, 1); 932 } 933 } 934 935 /* 936 * Release a jumbo buffer. 937 */ 938 static void 939 bge_jfree(void *arg) 940 { 941 struct bge_jslot *entry = (struct bge_jslot *)arg; 942 struct bge_softc *sc = entry->bge_sc; 943 944 if (sc == NULL) 945 panic("bge_jfree: can't find softc pointer!"); 946 947 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) { 948 panic("bge_jfree: asked to free buffer that we don't manage!"); 949 } else if (entry->bge_inuse == 0) { 950 panic("bge_jfree: buffer already free!"); 951 } else { 952 /* 953 * Possible MP race to 0, use the serializer. The atomic insn 954 * is still needed for races against bge_jref(). 955 */ 956 lwkt_serialize_enter(&sc->bge_jslot_serializer); 957 atomic_subtract_int(&entry->bge_inuse, 1); 958 if (entry->bge_inuse == 0) { 959 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 960 entry, jslot_link); 961 } 962 lwkt_serialize_exit(&sc->bge_jslot_serializer); 963 } 964 } 965 966 967 /* 968 * Intialize a standard receive ring descriptor. 969 */ 970 static int 971 bge_newbuf_std(struct bge_softc *sc, int i, int init) 972 { 973 struct mbuf *m_new = NULL; 974 bus_dma_segment_t seg; 975 bus_dmamap_t map; 976 int error, nsegs; 977 978 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 979 if (m_new == NULL) 980 return ENOBUFS; 981 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 982 983 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 984 m_adj(m_new, ETHER_ALIGN); 985 986 error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag, 987 sc->bge_cdata.bge_rx_tmpmap, m_new, 988 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 989 if (error) { 990 m_freem(m_new); 991 return error; 992 } 993 994 if (!init) { 995 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 996 sc->bge_cdata.bge_rx_std_dmamap[i], 997 BUS_DMASYNC_POSTREAD); 998 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 999 sc->bge_cdata.bge_rx_std_dmamap[i]); 1000 } 1001 1002 map = sc->bge_cdata.bge_rx_tmpmap; 1003 sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i]; 1004 sc->bge_cdata.bge_rx_std_dmamap[i] = map; 1005 1006 sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new; 1007 sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr; 1008 1009 bge_setup_rxdesc_std(sc, i); 1010 return 0; 1011 } 1012 1013 static void 1014 bge_setup_rxdesc_std(struct bge_softc *sc, int i) 1015 { 1016 struct bge_rxchain *rc; 1017 struct bge_rx_bd *r; 1018 1019 rc = &sc->bge_cdata.bge_rx_std_chain[i]; 1020 r = &sc->bge_ldata.bge_rx_std_ring[i]; 1021 1022 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr); 1023 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr); 1024 r->bge_len = rc->bge_mbuf->m_len; 1025 r->bge_idx = i; 1026 r->bge_flags = BGE_RXBDFLAG_END; 1027 } 1028 1029 /* 1030 * Initialize a jumbo receive ring descriptor. This allocates 1031 * a jumbo buffer from the pool managed internally by the driver. 1032 */ 1033 static int 1034 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init) 1035 { 1036 struct mbuf *m_new = NULL; 1037 struct bge_jslot *buf; 1038 bus_addr_t paddr; 1039 1040 /* Allocate the mbuf. */ 1041 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 1042 if (m_new == NULL) 1043 return ENOBUFS; 1044 1045 /* Allocate the jumbo buffer */ 1046 buf = bge_jalloc(sc); 1047 if (buf == NULL) { 1048 m_freem(m_new); 1049 return ENOBUFS; 1050 } 1051 1052 /* Attach the buffer to the mbuf. */ 1053 m_new->m_ext.ext_arg = buf; 1054 m_new->m_ext.ext_buf = buf->bge_buf; 1055 m_new->m_ext.ext_free = bge_jfree; 1056 m_new->m_ext.ext_ref = bge_jref; 1057 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1058 1059 m_new->m_flags |= M_EXT; 1060 1061 m_new->m_data = m_new->m_ext.ext_buf; 1062 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 1063 1064 paddr = buf->bge_paddr; 1065 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) { 1066 m_adj(m_new, ETHER_ALIGN); 1067 paddr += ETHER_ALIGN; 1068 } 1069 1070 /* Save necessary information */ 1071 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new; 1072 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr; 1073 1074 /* Set up the descriptor. */ 1075 bge_setup_rxdesc_jumbo(sc, i); 1076 return 0; 1077 } 1078 1079 static void 1080 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i) 1081 { 1082 struct bge_rx_bd *r; 1083 struct bge_rxchain *rc; 1084 1085 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 1086 rc = &sc->bge_cdata.bge_rx_jumbo_chain[i]; 1087 1088 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr); 1089 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr); 1090 r->bge_len = rc->bge_mbuf->m_len; 1091 r->bge_idx = i; 1092 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1093 } 1094 1095 static int 1096 bge_init_rx_ring_std(struct bge_softc *sc) 1097 { 1098 int i, error; 1099 1100 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1101 error = bge_newbuf_std(sc, i, 1); 1102 if (error) 1103 return error; 1104 }; 1105 1106 sc->bge_std = BGE_STD_RX_RING_CNT - 1; 1107 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1108 1109 return(0); 1110 } 1111 1112 static void 1113 bge_free_rx_ring_std(struct bge_softc *sc) 1114 { 1115 int i; 1116 1117 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1118 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i]; 1119 1120 if (rc->bge_mbuf != NULL) { 1121 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1122 sc->bge_cdata.bge_rx_std_dmamap[i]); 1123 m_freem(rc->bge_mbuf); 1124 rc->bge_mbuf = NULL; 1125 } 1126 bzero(&sc->bge_ldata.bge_rx_std_ring[i], 1127 sizeof(struct bge_rx_bd)); 1128 } 1129 } 1130 1131 static int 1132 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1133 { 1134 struct bge_rcb *rcb; 1135 int i, error; 1136 1137 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1138 error = bge_newbuf_jumbo(sc, i, 1); 1139 if (error) 1140 return error; 1141 }; 1142 1143 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1; 1144 1145 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1146 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 1147 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1148 1149 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1150 1151 return(0); 1152 } 1153 1154 static void 1155 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1156 { 1157 int i; 1158 1159 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1160 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i]; 1161 1162 if (rc->bge_mbuf != NULL) { 1163 m_freem(rc->bge_mbuf); 1164 rc->bge_mbuf = NULL; 1165 } 1166 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i], 1167 sizeof(struct bge_rx_bd)); 1168 } 1169 } 1170 1171 static void 1172 bge_free_tx_ring(struct bge_softc *sc) 1173 { 1174 int i; 1175 1176 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1177 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1178 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1179 sc->bge_cdata.bge_tx_dmamap[i]); 1180 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1181 sc->bge_cdata.bge_tx_chain[i] = NULL; 1182 } 1183 bzero(&sc->bge_ldata.bge_tx_ring[i], 1184 sizeof(struct bge_tx_bd)); 1185 } 1186 } 1187 1188 static int 1189 bge_init_tx_ring(struct bge_softc *sc) 1190 { 1191 sc->bge_txcnt = 0; 1192 sc->bge_tx_saved_considx = 0; 1193 sc->bge_tx_prodidx = 0; 1194 1195 /* Initialize transmit producer index for host-memory send ring. */ 1196 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1197 1198 /* 5700 b2 errata */ 1199 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1200 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1201 1202 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1203 /* 5700 b2 errata */ 1204 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1205 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1206 1207 return(0); 1208 } 1209 1210 static void 1211 bge_setmulti(struct bge_softc *sc) 1212 { 1213 struct ifnet *ifp; 1214 struct ifmultiaddr *ifma; 1215 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1216 int h, i; 1217 1218 ifp = &sc->arpcom.ac_if; 1219 1220 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1221 for (i = 0; i < 4; i++) 1222 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1223 return; 1224 } 1225 1226 /* First, zot all the existing filters. */ 1227 for (i = 0; i < 4; i++) 1228 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1229 1230 /* Now program new ones. */ 1231 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1232 if (ifma->ifma_addr->sa_family != AF_LINK) 1233 continue; 1234 h = ether_crc32_le( 1235 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1236 ETHER_ADDR_LEN) & 0x7f; 1237 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1238 } 1239 1240 for (i = 0; i < 4; i++) 1241 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1242 } 1243 1244 /* 1245 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1246 * self-test results. 1247 */ 1248 static int 1249 bge_chipinit(struct bge_softc *sc) 1250 { 1251 int i; 1252 uint32_t dma_rw_ctl; 1253 uint16_t val; 1254 1255 /* Set endian type before we access any non-PCI registers. */ 1256 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1257 BGE_INIT | sc->bge_pci_miscctl, 4); 1258 1259 /* Clear the MAC control register */ 1260 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1261 1262 /* 1263 * Clear the MAC statistics block in the NIC's 1264 * internal memory. 1265 */ 1266 for (i = BGE_STATS_BLOCK; 1267 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1268 BGE_MEMWIN_WRITE(sc, i, 0); 1269 1270 for (i = BGE_STATUS_BLOCK; 1271 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1272 BGE_MEMWIN_WRITE(sc, i, 0); 1273 1274 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1275 /* 1276 * Fix data corruption caused by non-qword write with WB. 1277 * Fix master abort in PCI mode. 1278 * Fix PCI latency timer. 1279 */ 1280 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1281 val |= (1 << 10) | (1 << 12) | (1 << 13); 1282 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1283 } 1284 1285 /* Set up the PCI DMA control register. */ 1286 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1287 if (sc->bge_flags & BGE_FLAG_PCIE) { 1288 /* PCI-E bus */ 1289 /* DMA read watermark not used on PCI-E */ 1290 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1291 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1292 /* PCI-X bus */ 1293 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) { 1294 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1295 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1296 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1297 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5714) { 1298 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1299 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1300 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1301 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1302 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1303 uint32_t rd_wat = 0x7; 1304 uint32_t clkctl; 1305 1306 clkctl = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1307 if ((sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) && 1308 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1309 dma_rw_ctl |= 1310 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1311 } else if (clkctl == 0x6 || clkctl == 0x7) { 1312 dma_rw_ctl |= 1313 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1314 } 1315 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) 1316 rd_wat = 0x4; 1317 1318 dma_rw_ctl |= (rd_wat << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1319 (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1320 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1321 } else { 1322 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1323 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1324 dma_rw_ctl |= 0xf; 1325 } 1326 } else { 1327 /* Conventional PCI bus */ 1328 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1329 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1330 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1331 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1332 dma_rw_ctl |= 0xf; 1333 } 1334 1335 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1336 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1337 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1338 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1339 sc->bge_asicrev == BGE_ASICREV_BCM5701) { 1340 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1341 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1342 } 1343 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1344 1345 /* 1346 * Set up general mode register. 1347 */ 1348 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1349 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1350 BGE_MODECTL_TX_NO_PHDR_CSUM); 1351 1352 /* 1353 * BCM5701 B5 have a bug causing data corruption when using 1354 * 64-bit DMA reads, which can be terminated early and then 1355 * completed later as 32-bit accesses, in combination with 1356 * certain bridges. 1357 */ 1358 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1359 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1360 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1361 1362 /* 1363 * Disable memory write invalidate. Apparently it is not supported 1364 * properly by these devices. Also ensure that INTx isn't disabled, 1365 * as these chips need it even when using MSI. 1366 */ 1367 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1368 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4); 1369 1370 /* Set the timer prescaler (always 66Mhz) */ 1371 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1372 1373 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1374 DELAY(40); /* XXX */ 1375 1376 /* Put PHY into ready state */ 1377 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1378 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1379 DELAY(40); 1380 } 1381 1382 return(0); 1383 } 1384 1385 static int 1386 bge_blockinit(struct bge_softc *sc) 1387 { 1388 struct bge_rcb *rcb; 1389 bus_size_t vrcb; 1390 bge_hostaddr taddr; 1391 uint32_t val; 1392 int i, limit; 1393 1394 /* 1395 * Initialize the memory window pointer register so that 1396 * we can access the first 32K of internal NIC RAM. This will 1397 * allow us to set up the TX send ring RCBs and the RX return 1398 * ring RCBs, plus other things which live in NIC memory. 1399 */ 1400 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1401 1402 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1403 1404 if (!BGE_IS_5705_PLUS(sc)) { 1405 /* Configure mbuf memory pool */ 1406 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1407 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1408 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1409 else 1410 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1411 1412 /* Configure DMA resource pool */ 1413 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1414 BGE_DMA_DESCRIPTORS); 1415 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1416 } 1417 1418 /* Configure mbuf pool watermarks */ 1419 if (!BGE_IS_5705_PLUS(sc)) { 1420 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1421 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1422 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1423 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1424 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1425 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1426 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1427 } else { 1428 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1429 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1430 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1431 } 1432 1433 /* Configure DMA resource watermarks */ 1434 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1435 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1436 1437 /* Enable buffer manager */ 1438 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1439 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1440 1441 /* Poll for buffer manager start indication */ 1442 for (i = 0; i < BGE_TIMEOUT; i++) { 1443 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1444 break; 1445 DELAY(10); 1446 } 1447 1448 if (i == BGE_TIMEOUT) { 1449 if_printf(&sc->arpcom.ac_if, 1450 "buffer manager failed to start\n"); 1451 return(ENXIO); 1452 } 1453 1454 /* Enable flow-through queues */ 1455 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1456 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1457 1458 /* Wait until queue initialization is complete */ 1459 for (i = 0; i < BGE_TIMEOUT; i++) { 1460 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1461 break; 1462 DELAY(10); 1463 } 1464 1465 if (i == BGE_TIMEOUT) { 1466 if_printf(&sc->arpcom.ac_if, 1467 "flow-through queue init failed\n"); 1468 return(ENXIO); 1469 } 1470 1471 /* 1472 * Summary of rings supported by the controller: 1473 * 1474 * Standard Receive Producer Ring 1475 * - This ring is used to feed receive buffers for "standard" 1476 * sized frames (typically 1536 bytes) to the controller. 1477 * 1478 * Jumbo Receive Producer Ring 1479 * - This ring is used to feed receive buffers for jumbo sized 1480 * frames (i.e. anything bigger than the "standard" frames) 1481 * to the controller. 1482 * 1483 * Mini Receive Producer Ring 1484 * - This ring is used to feed receive buffers for "mini" 1485 * sized frames to the controller. 1486 * - This feature required external memory for the controller 1487 * but was never used in a production system. Should always 1488 * be disabled. 1489 * 1490 * Receive Return Ring 1491 * - After the controller has placed an incoming frame into a 1492 * receive buffer that buffer is moved into a receive return 1493 * ring. The driver is then responsible to passing the 1494 * buffer up to the stack. Many versions of the controller 1495 * support multiple RR rings. 1496 * 1497 * Send Ring 1498 * - This ring is used for outgoing frames. Many versions of 1499 * the controller support multiple send rings. 1500 */ 1501 1502 /* Initialize the standard receive producer ring control block. */ 1503 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1504 rcb->bge_hostaddr.bge_addr_lo = 1505 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1506 rcb->bge_hostaddr.bge_addr_hi = 1507 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1508 if (BGE_IS_5705_PLUS(sc)) { 1509 /* 1510 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 1511 * Bits 15-2 : Reserved (should be 0) 1512 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1513 * Bit 0 : Reserved 1514 */ 1515 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1516 } else { 1517 /* 1518 * Ring size is always XXX entries 1519 * Bits 31-16: Maximum RX frame size 1520 * Bits 15-2 : Reserved (should be 0) 1521 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1522 * Bit 0 : Reserved 1523 */ 1524 rcb->bge_maxlen_flags = 1525 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1526 } 1527 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1528 /* Write the standard receive producer ring control block. */ 1529 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1530 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1531 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1532 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1533 /* Reset the standard receive producer ring producer index. */ 1534 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1535 1536 /* 1537 * Initialize the jumbo RX producer ring control 1538 * block. We set the 'ring disabled' bit in the 1539 * flags field until we're actually ready to start 1540 * using this ring (i.e. once we set the MTU 1541 * high enough to require it). 1542 */ 1543 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1544 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1545 /* Get the jumbo receive producer ring RCB parameters. */ 1546 rcb->bge_hostaddr.bge_addr_lo = 1547 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1548 rcb->bge_hostaddr.bge_addr_hi = 1549 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1550 rcb->bge_maxlen_flags = 1551 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1552 BGE_RCB_FLAG_RING_DISABLED); 1553 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1554 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1555 rcb->bge_hostaddr.bge_addr_hi); 1556 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1557 rcb->bge_hostaddr.bge_addr_lo); 1558 /* Program the jumbo receive producer ring RCB parameters. */ 1559 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1560 rcb->bge_maxlen_flags); 1561 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1562 /* Reset the jumbo receive producer ring producer index. */ 1563 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1564 } 1565 1566 /* Disable the mini receive producer ring RCB. */ 1567 if (BGE_IS_5700_FAMILY(sc)) { 1568 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1569 rcb->bge_maxlen_flags = 1570 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1571 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1572 rcb->bge_maxlen_flags); 1573 /* Reset the mini receive producer ring producer index. */ 1574 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1575 } 1576 1577 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 1578 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1579 (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 1580 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 1581 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) { 1582 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 1583 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 1584 } 1585 1586 /* 1587 * The BD ring replenish thresholds control how often the 1588 * hardware fetches new BD's from the producer rings in host 1589 * memory. Setting the value too low on a busy system can 1590 * starve the hardware and recue the throughpout. 1591 * 1592 * Set the BD ring replentish thresholds. The recommended 1593 * values are 1/8th the number of descriptors allocated to 1594 * each ring. 1595 */ 1596 if (BGE_IS_5705_PLUS(sc)) 1597 val = 8; 1598 else 1599 val = BGE_STD_RX_RING_CNT / 8; 1600 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1601 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1602 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1603 BGE_JUMBO_RX_RING_CNT/8); 1604 } 1605 1606 /* 1607 * Disable all send rings by setting the 'ring disabled' bit 1608 * in the flags field of all the TX send ring control blocks, 1609 * located in NIC memory. 1610 */ 1611 if (!BGE_IS_5705_PLUS(sc)) { 1612 /* 5700 to 5704 had 16 send rings. */ 1613 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 1614 } else { 1615 limit = 1; 1616 } 1617 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1618 for (i = 0; i < limit; i++) { 1619 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1620 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1621 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1622 vrcb += sizeof(struct bge_rcb); 1623 } 1624 1625 /* Configure send ring RCB 0 (we use only the first ring) */ 1626 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1627 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1628 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1629 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1630 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1631 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1632 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1633 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1634 1635 /* 1636 * Disable all receive return rings by setting the 1637 * 'ring diabled' bit in the flags field of all the receive 1638 * return ring control blocks, located in NIC memory. 1639 */ 1640 if (!BGE_IS_5705_PLUS(sc)) 1641 limit = BGE_RX_RINGS_MAX; 1642 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755) 1643 limit = 4; 1644 else 1645 limit = 1; 1646 /* Disable all receive return rings. */ 1647 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1648 for (i = 0; i < limit; i++) { 1649 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1650 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1651 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1652 BGE_RCB_FLAG_RING_DISABLED); 1653 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1654 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1655 (i * (sizeof(uint64_t))), 0); 1656 vrcb += sizeof(struct bge_rcb); 1657 } 1658 1659 /* 1660 * Set up receive return ring 0. Note that the NIC address 1661 * for RX return rings is 0x0. The return rings live entirely 1662 * within the host, so the nicaddr field in the RCB isn't used. 1663 */ 1664 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1665 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1666 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1667 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1668 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1669 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1670 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1671 1672 /* Set random backoff seed for TX */ 1673 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1674 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1675 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1676 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1677 BGE_TX_BACKOFF_SEED_MASK); 1678 1679 /* Set inter-packet gap */ 1680 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1681 1682 /* 1683 * Specify which ring to use for packets that don't match 1684 * any RX rules. 1685 */ 1686 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1687 1688 /* 1689 * Configure number of RX lists. One interrupt distribution 1690 * list, sixteen active lists, one bad frames class. 1691 */ 1692 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1693 1694 /* Inialize RX list placement stats mask. */ 1695 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1696 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1697 1698 /* Disable host coalescing until we get it set up */ 1699 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1700 1701 /* Poll to make sure it's shut down. */ 1702 for (i = 0; i < BGE_TIMEOUT; i++) { 1703 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1704 break; 1705 DELAY(10); 1706 } 1707 1708 if (i == BGE_TIMEOUT) { 1709 if_printf(&sc->arpcom.ac_if, 1710 "host coalescing engine failed to idle\n"); 1711 return(ENXIO); 1712 } 1713 1714 /* Set up host coalescing defaults */ 1715 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1716 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1717 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds); 1718 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds); 1719 if (!BGE_IS_5705_PLUS(sc)) { 1720 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 1721 sc->bge_rx_coal_ticks_int); 1722 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 1723 sc->bge_tx_coal_ticks_int); 1724 } 1725 /* 1726 * NOTE: 1727 * The datasheet (57XX-PG105-R) says BCM5705+ do not 1728 * have following two registers; obviously it is wrong. 1729 */ 1730 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int); 1731 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int); 1732 1733 /* Set up address of statistics block */ 1734 if (!BGE_IS_5705_PLUS(sc)) { 1735 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1736 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1737 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1738 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1739 1740 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1741 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1742 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1743 } 1744 1745 /* Set up address of status block */ 1746 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 1747 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1748 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1749 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1750 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1751 1752 /* 1753 * Set up status block partail update size. 1754 * 1755 * Because only single TX ring, RX produce ring and Rx return ring 1756 * are used, ask device to update only minimum part of status block 1757 * except for BCM5700 AX/BX, whose status block partial update size 1758 * can't be configured. 1759 */ 1760 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1761 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 1762 /* XXX Actually reserved on BCM5700 AX/BX */ 1763 val = BGE_STATBLKSZ_FULL; 1764 } else { 1765 val = BGE_STATBLKSZ_32BYTE; 1766 } 1767 #if 0 1768 /* 1769 * Does not seem to have visible effect in both 1770 * bulk data (1472B UDP datagram) and tiny data 1771 * (18B UDP datagram) TX tests. 1772 */ 1773 if (!BGE_IS_CRIPPLED(sc)) 1774 val |= BGE_HCCMODE_CLRTICK_TX; 1775 #endif 1776 1777 /* Turn on host coalescing state machine */ 1778 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 1779 1780 /* Turn on RX BD completion state machine and enable attentions */ 1781 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1782 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1783 1784 /* Turn on RX list placement state machine */ 1785 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1786 1787 /* Turn on RX list selector state machine. */ 1788 if (!BGE_IS_5705_PLUS(sc)) 1789 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1790 1791 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 1792 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 1793 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 1794 BGE_MACMODE_FRMHDR_DMA_ENB; 1795 1796 if (sc->bge_flags & BGE_FLAG_TBI) 1797 val |= BGE_PORTMODE_TBI; 1798 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 1799 val |= BGE_PORTMODE_GMII; 1800 else 1801 val |= BGE_PORTMODE_MII; 1802 1803 /* Turn on DMA, clear stats */ 1804 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 1805 1806 /* Set misc. local control, enable interrupts on attentions */ 1807 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1808 1809 #ifdef notdef 1810 /* Assert GPIO pins for PHY reset */ 1811 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1812 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1813 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1814 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1815 #endif 1816 1817 /* Turn on DMA completion state machine */ 1818 if (!BGE_IS_5705_PLUS(sc)) 1819 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1820 1821 /* Turn on write DMA state machine */ 1822 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 1823 if (BGE_IS_5755_PLUS(sc)) { 1824 /* Enable host coalescing bug fix. */ 1825 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1826 } 1827 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) { 1828 /* Request larger DMA burst size to get better performance. */ 1829 val |= BGE_WDMAMODE_BURST_ALL_DATA; 1830 } 1831 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1832 DELAY(40); 1833 1834 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 1835 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1836 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1837 sc->bge_asicrev == BGE_ASICREV_BCM57780) { 1838 /* 1839 * Enable fix for read DMA FIFO overruns. 1840 * The fix is to limit the number of RX BDs 1841 * the hardware would fetch at a fime. 1842 */ 1843 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 1844 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, 1845 val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 1846 } 1847 1848 /* Turn on read DMA state machine */ 1849 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1850 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1851 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1852 sc->bge_asicrev == BGE_ASICREV_BCM57780) 1853 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1854 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1855 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 1856 if (sc->bge_flags & BGE_FLAG_PCIE) 1857 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1858 if (sc->bge_flags & BGE_FLAG_TSO) 1859 val |= BGE_RDMAMODE_TSO4_ENABLE; 1860 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1861 DELAY(40); 1862 1863 /* Turn on RX data completion state machine */ 1864 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1865 1866 /* Turn on RX BD initiator state machine */ 1867 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1868 1869 /* Turn on RX data and RX BD initiator state machine */ 1870 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1871 1872 /* Turn on Mbuf cluster free state machine */ 1873 if (!BGE_IS_5705_PLUS(sc)) 1874 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1875 1876 /* Turn on send BD completion state machine */ 1877 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1878 1879 /* Turn on send data completion state machine */ 1880 val = BGE_SDCMODE_ENABLE; 1881 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 1882 val |= BGE_SDCMODE_CDELAY; 1883 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 1884 1885 /* Turn on send data initiator state machine */ 1886 if (sc->bge_flags & BGE_FLAG_TSO) 1887 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 1888 BGE_SDIMODE_HW_LSO_PRE_DMA); 1889 else 1890 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1891 1892 /* Turn on send BD initiator state machine */ 1893 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1894 1895 /* Turn on send BD selector state machine */ 1896 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1897 1898 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1899 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1900 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1901 1902 /* ack/clear link change events */ 1903 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1904 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1905 BGE_MACSTAT_LINK_CHANGED); 1906 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1907 1908 /* 1909 * Enable attention when the link has changed state for 1910 * devices that use auto polling. 1911 */ 1912 if (sc->bge_flags & BGE_FLAG_TBI) { 1913 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1914 } else { 1915 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 1916 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1917 DELAY(80); 1918 } 1919 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1920 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 1921 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1922 BGE_EVTENB_MI_INTERRUPT); 1923 } 1924 } 1925 1926 /* 1927 * Clear any pending link state attention. 1928 * Otherwise some link state change events may be lost until attention 1929 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence. 1930 * It's not necessary on newer BCM chips - perhaps enabling link 1931 * state change attentions implies clearing pending attention. 1932 */ 1933 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1934 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1935 BGE_MACSTAT_LINK_CHANGED); 1936 1937 /* Enable link state change attentions. */ 1938 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1939 1940 return(0); 1941 } 1942 1943 /* 1944 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1945 * against our list and return its name if we find a match. Note 1946 * that since the Broadcom controller contains VPD support, we 1947 * can get the device name string from the controller itself instead 1948 * of the compiled-in string. This is a little slow, but it guarantees 1949 * we'll always announce the right product name. 1950 */ 1951 static int 1952 bge_probe(device_t dev) 1953 { 1954 const struct bge_type *t; 1955 uint16_t product, vendor; 1956 1957 product = pci_get_device(dev); 1958 vendor = pci_get_vendor(dev); 1959 1960 for (t = bge_devs; t->bge_name != NULL; t++) { 1961 if (vendor == t->bge_vid && product == t->bge_did) 1962 break; 1963 } 1964 if (t->bge_name == NULL) 1965 return(ENXIO); 1966 1967 device_set_desc(dev, t->bge_name); 1968 return(0); 1969 } 1970 1971 static int 1972 bge_attach(device_t dev) 1973 { 1974 struct ifnet *ifp; 1975 struct bge_softc *sc; 1976 uint32_t hwcfg = 0, misccfg; 1977 int error = 0, rid, capmask; 1978 uint8_t ether_addr[ETHER_ADDR_LEN]; 1979 uint16_t product, vendor; 1980 driver_intr_t *intr_func; 1981 uintptr_t mii_priv = 0; 1982 u_int intr_flags; 1983 int msi_enable; 1984 1985 sc = device_get_softc(dev); 1986 sc->bge_dev = dev; 1987 callout_init_mp(&sc->bge_stat_timer); 1988 lwkt_serialize_init(&sc->bge_jslot_serializer); 1989 1990 product = pci_get_device(dev); 1991 vendor = pci_get_vendor(dev); 1992 1993 #ifndef BURN_BRIDGES 1994 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1995 uint32_t irq, mem; 1996 1997 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1998 mem = pci_read_config(dev, BGE_PCI_BAR0, 4); 1999 2000 device_printf(dev, "chip is in D%d power mode " 2001 "-- setting to D0\n", pci_get_powerstate(dev)); 2002 2003 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2004 2005 pci_write_config(dev, PCIR_INTLINE, irq, 4); 2006 pci_write_config(dev, BGE_PCI_BAR0, mem, 4); 2007 } 2008 #endif /* !BURN_BRIDGE */ 2009 2010 /* 2011 * Map control/status registers. 2012 */ 2013 pci_enable_busmaster(dev); 2014 2015 rid = BGE_PCI_BAR0; 2016 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2017 RF_ACTIVE); 2018 2019 if (sc->bge_res == NULL) { 2020 device_printf(dev, "couldn't map memory\n"); 2021 return ENXIO; 2022 } 2023 2024 sc->bge_btag = rman_get_bustag(sc->bge_res); 2025 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2026 2027 /* Save various chip information */ 2028 sc->bge_chipid = 2029 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2030 BGE_PCIMISCCTL_ASICREV_SHIFT; 2031 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2032 /* All chips, which use BGE_PCI_PRODID_ASICREV, have CPMU */ 2033 sc->bge_flags |= BGE_FLAG_CPMU; 2034 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2035 } 2036 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2037 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2038 2039 /* Save chipset family. */ 2040 switch (sc->bge_asicrev) { 2041 case BGE_ASICREV_BCM5755: 2042 case BGE_ASICREV_BCM5761: 2043 case BGE_ASICREV_BCM5784: 2044 case BGE_ASICREV_BCM5785: 2045 case BGE_ASICREV_BCM5787: 2046 case BGE_ASICREV_BCM57780: 2047 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2048 BGE_FLAG_5705_PLUS; 2049 break; 2050 2051 case BGE_ASICREV_BCM5700: 2052 case BGE_ASICREV_BCM5701: 2053 case BGE_ASICREV_BCM5703: 2054 case BGE_ASICREV_BCM5704: 2055 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2056 break; 2057 2058 case BGE_ASICREV_BCM5714_A0: 2059 case BGE_ASICREV_BCM5780: 2060 case BGE_ASICREV_BCM5714: 2061 sc->bge_flags |= BGE_FLAG_5714_FAMILY; 2062 /* Fall through */ 2063 2064 case BGE_ASICREV_BCM5750: 2065 case BGE_ASICREV_BCM5752: 2066 case BGE_ASICREV_BCM5906: 2067 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2068 /* Fall through */ 2069 2070 case BGE_ASICREV_BCM5705: 2071 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2072 break; 2073 } 2074 2075 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 2076 sc->bge_flags |= BGE_FLAG_NO_EEPROM; 2077 2078 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 2079 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2080 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2081 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2082 sc->bge_flags |= BGE_FLAG_5788; 2083 2084 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 2085 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 2086 sc->bge_flags |= BGE_FLAG_SHORTDMA; 2087 2088 /* 2089 * Check if this is a PCI-X or PCI Express device. 2090 */ 2091 if (BGE_IS_5705_PLUS(sc)) { 2092 if (pci_is_pcie(dev)) { 2093 sc->bge_flags |= BGE_FLAG_PCIE; 2094 sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev); 2095 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096); 2096 } 2097 } else { 2098 /* 2099 * Check if the device is in PCI-X Mode. 2100 * (This bit is not valid on PCI Express controllers.) 2101 */ 2102 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 2103 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2104 sc->bge_flags |= BGE_FLAG_PCIX; 2105 sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev); 2106 sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev, 2107 "mbox_reorder", 0); 2108 } 2109 } 2110 device_printf(dev, "CHIP ID 0x%08x; " 2111 "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 2112 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 2113 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" 2114 : ((sc->bge_flags & BGE_FLAG_PCIE) ? 2115 "PCI-E" : "PCI")); 2116 2117 /* 2118 * The 40bit DMA bug applies to the 5714/5715 controllers and is 2119 * not actually a MAC controller bug but an issue with the embedded 2120 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 2121 */ 2122 if ((sc->bge_flags & BGE_FLAG_PCIX) && 2123 (BGE_IS_5714_FAMILY(sc) || device_getenv_int(dev, "dma40b", 0))) 2124 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT; 2125 2126 /* 2127 * When using the BCM5701 in PCI-X mode, data corruption has 2128 * been observed in the first few bytes of some received packets. 2129 * Aligning the packet buffer in memory eliminates the corruption. 2130 * Unfortunately, this misaligns the packet payloads. On platforms 2131 * which do not support unaligned accesses, we will realign the 2132 * payloads by copying the received packets. 2133 */ 2134 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2135 (sc->bge_flags & BGE_FLAG_PCIX)) 2136 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2137 2138 if (!BGE_IS_CRIPPLED(sc)) { 2139 if (device_getenv_int(dev, "status_tag", 1)) { 2140 sc->bge_flags |= BGE_FLAG_STATUS_TAG; 2141 sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS; 2142 if (bootverbose) 2143 device_printf(dev, "enable status tag\n"); 2144 } 2145 } 2146 2147 if (BGE_IS_5755_PLUS(sc)) { 2148 /* 2149 * BCM5754 and BCM5787 shares the same ASIC id so 2150 * explicit device id check is required. 2151 * Due to unknown reason TSO does not work on BCM5755M. 2152 */ 2153 if (product != PCI_PRODUCT_BROADCOM_BCM5754 && 2154 product != PCI_PRODUCT_BROADCOM_BCM5754M && 2155 product != PCI_PRODUCT_BROADCOM_BCM5755M) 2156 sc->bge_flags |= BGE_FLAG_TSO; 2157 } 2158 2159 /* 2160 * Set various PHY quirk flags. 2161 */ 2162 2163 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 || 2164 sc->bge_asicrev == BGE_ASICREV_BCM5701) && 2165 pci_get_subvendor(dev) == PCI_VENDOR_DELL) 2166 mii_priv |= BRGPHY_FLAG_NO_3LED; 2167 2168 capmask = MII_CAPMASK_DEFAULT; 2169 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 2170 (misccfg == 0x4000 || misccfg == 0x8000)) || 2171 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2172 vendor == PCI_VENDOR_BROADCOM && 2173 (product == PCI_PRODUCT_BROADCOM_BCM5901 || 2174 product == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2175 product == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2176 (vendor == PCI_VENDOR_BROADCOM && 2177 (product == PCI_PRODUCT_BROADCOM_BCM5751F || 2178 product == PCI_PRODUCT_BROADCOM_BCM5753F || 2179 product == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2180 product == PCI_PRODUCT_BROADCOM_BCM57790 || 2181 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2182 /* 10/100 only */ 2183 capmask &= ~BMSR_EXTSTAT; 2184 } 2185 2186 mii_priv |= BRGPHY_FLAG_WIRESPEED; 2187 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 2188 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2189 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2190 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2191 sc->bge_asicrev == BGE_ASICREV_BCM5906) 2192 mii_priv &= ~BRGPHY_FLAG_WIRESPEED; 2193 2194 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2195 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2196 mii_priv |= BRGPHY_FLAG_CRC_BUG; 2197 2198 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2199 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2200 mii_priv |= BRGPHY_FLAG_ADC_BUG; 2201 2202 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2203 mii_priv |= BRGPHY_FLAG_5704_A0; 2204 2205 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 2206 mii_priv |= BRGPHY_FLAG_5906; 2207 2208 if (BGE_IS_5705_PLUS(sc) && 2209 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2210 /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */ 2211 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 2212 /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */ 2213 sc->bge_asicrev != BGE_ASICREV_BCM57780) { 2214 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2215 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2216 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2217 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2218 if (product != PCI_PRODUCT_BROADCOM_BCM5722 && 2219 product != PCI_PRODUCT_BROADCOM_BCM5756) 2220 mii_priv |= BRGPHY_FLAG_JITTER_BUG; 2221 if (product == PCI_PRODUCT_BROADCOM_BCM5755M) 2222 mii_priv |= BRGPHY_FLAG_ADJUST_TRIM; 2223 } else { 2224 mii_priv |= BRGPHY_FLAG_BER_BUG; 2225 } 2226 } 2227 2228 /* 2229 * Allocate interrupt 2230 */ 2231 msi_enable = bge_msi_enable; 2232 if ((sc->bge_flags & BGE_FLAG_STATUS_TAG) == 0) { 2233 /* If "tagged status" is disabled, don't enable MSI */ 2234 msi_enable = 0; 2235 } else if (msi_enable) { 2236 msi_enable = 0; /* Disable by default */ 2237 if (BGE_IS_575X_PLUS(sc)) { 2238 msi_enable = 1; 2239 /* XXX we filter all 5714 chips */ 2240 if (sc->bge_asicrev == BGE_ASICREV_BCM5714 || 2241 (sc->bge_asicrev == BGE_ASICREV_BCM5750 && 2242 (sc->bge_chiprev == BGE_CHIPREV_5750_AX || 2243 sc->bge_chiprev == BGE_CHIPREV_5750_BX))) 2244 msi_enable = 0; 2245 else if (BGE_IS_5755_PLUS(sc) || 2246 sc->bge_asicrev == BGE_ASICREV_BCM5906) 2247 sc->bge_flags |= BGE_FLAG_ONESHOT_MSI; 2248 } 2249 } 2250 if (msi_enable) { 2251 if (pci_find_extcap(dev, PCIY_MSI, &sc->bge_msicap)) { 2252 device_printf(dev, "no MSI capability\n"); 2253 msi_enable = 0; 2254 } 2255 } 2256 2257 sc->bge_irq_type = pci_alloc_1intr(dev, msi_enable, &sc->bge_irq_rid, 2258 &intr_flags); 2259 2260 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bge_irq_rid, 2261 intr_flags); 2262 if (sc->bge_irq == NULL) { 2263 device_printf(dev, "couldn't map interrupt\n"); 2264 error = ENXIO; 2265 goto fail; 2266 } 2267 2268 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) 2269 bge_enable_msi(sc); 2270 else 2271 sc->bge_flags &= ~BGE_FLAG_ONESHOT_MSI; 2272 2273 /* Initialize if_name earlier, so if_printf could be used */ 2274 ifp = &sc->arpcom.ac_if; 2275 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2276 2277 /* Try to reset the chip. */ 2278 bge_reset(sc); 2279 2280 if (bge_chipinit(sc)) { 2281 device_printf(dev, "chip initialization failed\n"); 2282 error = ENXIO; 2283 goto fail; 2284 } 2285 2286 /* 2287 * Get station address 2288 */ 2289 error = bge_get_eaddr(sc, ether_addr); 2290 if (error) { 2291 device_printf(dev, "failed to read station address\n"); 2292 goto fail; 2293 } 2294 2295 /* 5705/5750 limits RX return ring to 512 entries. */ 2296 if (BGE_IS_5705_PLUS(sc)) 2297 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2298 else 2299 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2300 2301 error = bge_dma_alloc(sc); 2302 if (error) 2303 goto fail; 2304 2305 /* Set default tuneable values. */ 2306 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2307 sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF; 2308 sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF; 2309 sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF; 2310 sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF; 2311 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 2312 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF; 2313 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF; 2314 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF; 2315 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF; 2316 } else { 2317 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN; 2318 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN; 2319 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN; 2320 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN; 2321 } 2322 2323 /* Set up TX spare and reserved descriptor count */ 2324 if (sc->bge_flags & BGE_FLAG_TSO) { 2325 sc->bge_txspare = BGE_NSEG_SPARE_TSO; 2326 sc->bge_txrsvd = BGE_NSEG_RSVD_TSO; 2327 } else { 2328 sc->bge_txspare = BGE_NSEG_SPARE; 2329 sc->bge_txrsvd = BGE_NSEG_RSVD; 2330 } 2331 2332 /* Set up ifnet structure */ 2333 ifp->if_softc = sc; 2334 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2335 ifp->if_ioctl = bge_ioctl; 2336 ifp->if_start = bge_start; 2337 #ifdef DEVICE_POLLING 2338 ifp->if_poll = bge_poll; 2339 #endif 2340 ifp->if_watchdog = bge_watchdog; 2341 ifp->if_init = bge_init; 2342 ifp->if_mtu = ETHERMTU; 2343 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2344 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1); 2345 ifq_set_ready(&ifp->if_snd); 2346 2347 /* 2348 * 5700 B0 chips do not support checksumming correctly due 2349 * to hardware bugs. 2350 */ 2351 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) { 2352 ifp->if_capabilities |= IFCAP_HWCSUM; 2353 ifp->if_hwassist |= BGE_CSUM_FEATURES; 2354 } 2355 if (sc->bge_flags & BGE_FLAG_TSO) { 2356 ifp->if_capabilities |= IFCAP_TSO; 2357 ifp->if_hwassist |= CSUM_TSO; 2358 } 2359 ifp->if_capenable = ifp->if_capabilities; 2360 2361 /* 2362 * Figure out what sort of media we have by checking the 2363 * hardware config word in the first 32k of NIC internal memory, 2364 * or fall back to examining the EEPROM if necessary. 2365 * Note: on some BCM5700 cards, this value appears to be unset. 2366 * If that's the case, we have to rely on identifying the NIC 2367 * by its PCI subsystem ID, as we do below for the SysKonnect 2368 * SK-9D41. 2369 */ 2370 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2371 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2372 } else { 2373 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2374 sizeof(hwcfg))) { 2375 device_printf(dev, "failed to read EEPROM\n"); 2376 error = ENXIO; 2377 goto fail; 2378 } 2379 hwcfg = ntohl(hwcfg); 2380 } 2381 2382 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2383 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 || 2384 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2385 if (BGE_IS_5714_FAMILY(sc)) 2386 sc->bge_flags |= BGE_FLAG_MII_SERDES; 2387 else 2388 sc->bge_flags |= BGE_FLAG_TBI; 2389 } 2390 2391 /* Setup MI MODE */ 2392 if (sc->bge_flags & BGE_FLAG_CPMU) 2393 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 2394 else 2395 sc->bge_mi_mode = BGE_MIMODE_BASE; 2396 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) { 2397 /* Enable auto polling for BCM570[0-5]. */ 2398 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 2399 } 2400 2401 /* Setup link status update stuffs */ 2402 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2403 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 2404 sc->bge_link_upd = bge_bcm5700_link_upd; 2405 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT; 2406 } else if (sc->bge_flags & BGE_FLAG_TBI) { 2407 sc->bge_link_upd = bge_tbi_link_upd; 2408 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED; 2409 } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2410 sc->bge_link_upd = bge_autopoll_link_upd; 2411 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED; 2412 } else { 2413 sc->bge_link_upd = bge_copper_link_upd; 2414 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED; 2415 } 2416 2417 /* 2418 * Broadcom's own driver always assumes the internal 2419 * PHY is at GMII address 1. On some chips, the PHY responds 2420 * to accesses at all addresses, which could cause us to 2421 * bogusly attach the PHY 32 times at probe type. Always 2422 * restricting the lookup to address 1 is simpler than 2423 * trying to figure out which chips revisions should be 2424 * special-cased. 2425 */ 2426 sc->bge_phyno = 1; 2427 2428 if (sc->bge_flags & BGE_FLAG_TBI) { 2429 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 2430 bge_ifmedia_upd, bge_ifmedia_sts); 2431 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2432 ifmedia_add(&sc->bge_ifmedia, 2433 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2434 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2435 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2436 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2437 } else { 2438 struct mii_probe_args mii_args; 2439 2440 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts); 2441 mii_args.mii_probemask = 1 << sc->bge_phyno; 2442 mii_args.mii_capmask = capmask; 2443 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY; 2444 mii_args.mii_priv = mii_priv; 2445 2446 error = mii_probe(dev, &sc->bge_miibus, &mii_args); 2447 if (error) { 2448 device_printf(dev, "MII without any PHY!\n"); 2449 goto fail; 2450 } 2451 } 2452 2453 /* 2454 * Create sysctl nodes. 2455 */ 2456 sysctl_ctx_init(&sc->bge_sysctl_ctx); 2457 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx, 2458 SYSCTL_STATIC_CHILDREN(_hw), 2459 OID_AUTO, 2460 device_get_nameunit(dev), 2461 CTLFLAG_RD, 0, ""); 2462 if (sc->bge_sysctl_tree == NULL) { 2463 device_printf(dev, "can't add sysctl node\n"); 2464 error = ENXIO; 2465 goto fail; 2466 } 2467 2468 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2469 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2470 OID_AUTO, "rx_coal_ticks", 2471 CTLTYPE_INT | CTLFLAG_RW, 2472 sc, 0, bge_sysctl_rx_coal_ticks, "I", 2473 "Receive coalescing ticks (usec)."); 2474 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2475 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2476 OID_AUTO, "tx_coal_ticks", 2477 CTLTYPE_INT | CTLFLAG_RW, 2478 sc, 0, bge_sysctl_tx_coal_ticks, "I", 2479 "Transmit coalescing ticks (usec)."); 2480 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2481 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2482 OID_AUTO, "rx_coal_bds", 2483 CTLTYPE_INT | CTLFLAG_RW, 2484 sc, 0, bge_sysctl_rx_coal_bds, "I", 2485 "Receive max coalesced BD count."); 2486 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2487 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2488 OID_AUTO, "tx_coal_bds", 2489 CTLTYPE_INT | CTLFLAG_RW, 2490 sc, 0, bge_sysctl_tx_coal_bds, "I", 2491 "Transmit max coalesced BD count."); 2492 if (sc->bge_flags & BGE_FLAG_PCIE) { 2493 /* 2494 * A common design characteristic for many Broadcom 2495 * client controllers is that they only support a 2496 * single outstanding DMA read operation on the PCIe 2497 * bus. This means that it will take twice as long to 2498 * fetch a TX frame that is split into header and 2499 * payload buffers as it does to fetch a single, 2500 * contiguous TX frame (2 reads vs. 1 read). For these 2501 * controllers, coalescing buffers to reduce the number 2502 * of memory reads is effective way to get maximum 2503 * performance(about 940Mbps). Without collapsing TX 2504 * buffers the maximum TCP bulk transfer performance 2505 * is about 850Mbps. However forcing coalescing mbufs 2506 * consumes a lot of CPU cycles, so leave it off by 2507 * default. 2508 */ 2509 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx, 2510 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2511 OID_AUTO, "force_defrag", CTLFLAG_RW, 2512 &sc->bge_force_defrag, 0, 2513 "Force defragment on TX path"); 2514 } 2515 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 2516 if (!BGE_IS_5705_PLUS(sc)) { 2517 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2518 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO, 2519 "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW, 2520 sc, 0, bge_sysctl_rx_coal_ticks_int, "I", 2521 "Receive coalescing ticks " 2522 "during interrupt (usec)."); 2523 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2524 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO, 2525 "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW, 2526 sc, 0, bge_sysctl_tx_coal_ticks_int, "I", 2527 "Transmit coalescing ticks " 2528 "during interrupt (usec)."); 2529 } 2530 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2531 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO, 2532 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW, 2533 sc, 0, bge_sysctl_rx_coal_bds_int, "I", 2534 "Receive max coalesced BD count during interrupt."); 2535 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2536 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO, 2537 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW, 2538 sc, 0, bge_sysctl_tx_coal_bds_int, "I", 2539 "Transmit max coalesced BD count during interrupt."); 2540 } 2541 2542 /* 2543 * Call MI attach routine. 2544 */ 2545 ether_ifattach(ifp, ether_addr, NULL); 2546 2547 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) { 2548 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 2549 intr_func = bge_msi_oneshot; 2550 if (bootverbose) 2551 device_printf(dev, "oneshot MSI\n"); 2552 } else { 2553 intr_func = bge_msi; 2554 } 2555 } else if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 2556 intr_func = bge_intr_legacy; 2557 } else { 2558 intr_func = bge_intr_crippled; 2559 } 2560 error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc, 2561 &sc->bge_intrhand, ifp->if_serializer); 2562 if (error) { 2563 ether_ifdetach(ifp); 2564 device_printf(dev, "couldn't set up irq\n"); 2565 goto fail; 2566 } 2567 2568 ifp->if_cpuid = rman_get_cpuid(sc->bge_irq); 2569 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 2570 2571 return(0); 2572 fail: 2573 bge_detach(dev); 2574 return(error); 2575 } 2576 2577 static int 2578 bge_detach(device_t dev) 2579 { 2580 struct bge_softc *sc = device_get_softc(dev); 2581 2582 if (device_is_attached(dev)) { 2583 struct ifnet *ifp = &sc->arpcom.ac_if; 2584 2585 lwkt_serialize_enter(ifp->if_serializer); 2586 bge_stop(sc); 2587 bge_reset(sc); 2588 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2589 lwkt_serialize_exit(ifp->if_serializer); 2590 2591 ether_ifdetach(ifp); 2592 } 2593 2594 if (sc->bge_flags & BGE_FLAG_TBI) 2595 ifmedia_removeall(&sc->bge_ifmedia); 2596 if (sc->bge_miibus) 2597 device_delete_child(dev, sc->bge_miibus); 2598 bus_generic_detach(dev); 2599 2600 if (sc->bge_irq != NULL) { 2601 bus_release_resource(dev, SYS_RES_IRQ, sc->bge_irq_rid, 2602 sc->bge_irq); 2603 } 2604 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) 2605 pci_release_msi(dev); 2606 2607 if (sc->bge_res != NULL) { 2608 bus_release_resource(dev, SYS_RES_MEMORY, 2609 BGE_PCI_BAR0, sc->bge_res); 2610 } 2611 2612 if (sc->bge_sysctl_tree != NULL) 2613 sysctl_ctx_free(&sc->bge_sysctl_ctx); 2614 2615 bge_dma_free(sc); 2616 2617 return 0; 2618 } 2619 2620 static void 2621 bge_reset(struct bge_softc *sc) 2622 { 2623 device_t dev; 2624 uint32_t cachesize, command, pcistate, reset; 2625 void (*write_op)(struct bge_softc *, uint32_t, uint32_t); 2626 int i, val = 0; 2627 2628 dev = sc->bge_dev; 2629 2630 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 2631 sc->bge_asicrev != BGE_ASICREV_BCM5906) { 2632 if (sc->bge_flags & BGE_FLAG_PCIE) 2633 write_op = bge_writemem_direct; 2634 else 2635 write_op = bge_writemem_ind; 2636 } else { 2637 write_op = bge_writereg_ind; 2638 } 2639 2640 /* Save some important PCI state. */ 2641 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2642 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2643 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2644 2645 pci_write_config(dev, BGE_PCI_MISC_CTL, 2646 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2647 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW| 2648 sc->bge_pci_miscctl, 4); 2649 2650 /* Disable fastboot on controllers that support it. */ 2651 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2652 BGE_IS_5755_PLUS(sc)) { 2653 if (bootverbose) 2654 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n"); 2655 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2656 } 2657 2658 /* 2659 * Write the magic number to SRAM at offset 0xB50. 2660 * When firmware finishes its initialization it will 2661 * write ~BGE_MAGIC_NUMBER to the same location. 2662 */ 2663 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2664 2665 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1); 2666 2667 /* XXX: Broadcom Linux driver. */ 2668 if (sc->bge_flags & BGE_FLAG_PCIE) { 2669 /* Force PCI-E 1.0a mode */ 2670 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 2671 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) == 2672 (BGE_PCIE_PHY_TSTCTL_PSCRAM | 2673 BGE_PCIE_PHY_TSTCTL_PCIE10)) { 2674 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL, 2675 BGE_PCIE_PHY_TSTCTL_PSCRAM); 2676 } 2677 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2678 /* Prevent PCIE link training during global reset */ 2679 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); 2680 reset |= (1<<29); 2681 } 2682 } 2683 2684 /* 2685 * Set GPHY Power Down Override to leave GPHY 2686 * powered up in D0 uninitialized. 2687 */ 2688 if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0) 2689 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 2690 2691 /* Issue global reset */ 2692 write_op(sc, BGE_MISC_CFG, reset); 2693 2694 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2695 uint32_t status, ctrl; 2696 2697 status = CSR_READ_4(sc, BGE_VCPU_STATUS); 2698 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2699 status | BGE_VCPU_STATUS_DRV_RESET); 2700 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2701 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2702 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2703 } 2704 2705 DELAY(1000); 2706 2707 /* XXX: Broadcom Linux driver. */ 2708 if (sc->bge_flags & BGE_FLAG_PCIE) { 2709 uint16_t devctl; 2710 2711 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2712 uint32_t v; 2713 2714 DELAY(500000); /* wait for link training to complete */ 2715 v = pci_read_config(dev, 0xc4, 4); 2716 pci_write_config(dev, 0xc4, v | (1<<15), 4); 2717 } 2718 2719 devctl = pci_read_config(dev, 2720 sc->bge_pciecap + PCIER_DEVCTRL, 2); 2721 2722 /* Disable no snoop and disable relaxed ordering. */ 2723 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP); 2724 2725 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */ 2726 if ((sc->bge_flags & BGE_FLAG_CPMU) == 0) { 2727 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK; 2728 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128; 2729 } 2730 2731 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL, 2732 devctl, 2); 2733 2734 /* Clear error status. */ 2735 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS, 2736 PCIEM_DEVSTS_CORR_ERR | 2737 PCIEM_DEVSTS_NFATAL_ERR | 2738 PCIEM_DEVSTS_FATAL_ERR | 2739 PCIEM_DEVSTS_UNSUPP_REQ, 2); 2740 } 2741 2742 /* Reset some of the PCI state that got zapped by reset */ 2743 pci_write_config(dev, BGE_PCI_MISC_CTL, 2744 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2745 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW| 2746 sc->bge_pci_miscctl, 4); 2747 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2748 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2749 write_op(sc, BGE_MISC_CFG, (65 << 1)); 2750 2751 /* 2752 * Disable PCI-X relaxed ordering to ensure status block update 2753 * comes first then packet buffer DMA. Otherwise driver may 2754 * read stale status block. 2755 */ 2756 if (sc->bge_flags & BGE_FLAG_PCIX) { 2757 uint16_t devctl; 2758 2759 devctl = pci_read_config(dev, 2760 sc->bge_pcixcap + PCIXR_COMMAND, 2); 2761 devctl &= ~PCIXM_COMMAND_ERO; 2762 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 2763 devctl &= ~PCIXM_COMMAND_MAX_READ; 2764 devctl |= PCIXM_COMMAND_MAX_READ_2048; 2765 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 2766 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 2767 PCIXM_COMMAND_MAX_READ); 2768 devctl |= PCIXM_COMMAND_MAX_READ_2048; 2769 } 2770 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 2771 devctl, 2); 2772 } 2773 2774 /* 2775 * Enable memory arbiter and re-enable MSI if necessary. 2776 */ 2777 if (BGE_IS_5714_FAMILY(sc)) { 2778 uint32_t val; 2779 2780 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) { 2781 /* 2782 * Resetting BCM5714 family will clear MSI 2783 * enable bit; restore it after resetting. 2784 */ 2785 PCI_SETBIT(sc->bge_dev, sc->bge_msicap + PCIR_MSI_CTRL, 2786 PCIM_MSICTRL_MSI_ENABLE, 2); 2787 BGE_SETBIT(sc, BGE_MSI_MODE, BGE_MSIMODE_ENABLE); 2788 } 2789 val = CSR_READ_4(sc, BGE_MARB_MODE); 2790 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 2791 } else { 2792 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2793 } 2794 2795 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2796 for (i = 0; i < BGE_TIMEOUT; i++) { 2797 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2798 if (val & BGE_VCPU_STATUS_INIT_DONE) 2799 break; 2800 DELAY(100); 2801 } 2802 if (i == BGE_TIMEOUT) { 2803 if_printf(&sc->arpcom.ac_if, "reset timed out\n"); 2804 return; 2805 } 2806 } else { 2807 /* 2808 * Poll until we see the 1's complement of the magic number. 2809 * This indicates that the firmware initialization 2810 * is complete. 2811 */ 2812 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) { 2813 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2814 if (val == ~BGE_MAGIC_NUMBER) 2815 break; 2816 DELAY(10); 2817 } 2818 if (i == BGE_FIRMWARE_TIMEOUT) { 2819 if_printf(&sc->arpcom.ac_if, "firmware handshake " 2820 "timed out, found 0x%08x\n", val); 2821 } 2822 } 2823 2824 /* 2825 * XXX Wait for the value of the PCISTATE register to 2826 * return to its original pre-reset state. This is a 2827 * fairly good indicator of reset completion. If we don't 2828 * wait for the reset to fully complete, trying to read 2829 * from the device's non-PCI registers may yield garbage 2830 * results. 2831 */ 2832 for (i = 0; i < BGE_TIMEOUT; i++) { 2833 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2834 break; 2835 DELAY(10); 2836 } 2837 2838 /* Fix up byte swapping */ 2839 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 2840 BGE_MODECTL_BYTESWAP_DATA); 2841 2842 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2843 2844 /* 2845 * The 5704 in TBI mode apparently needs some special 2846 * adjustment to insure the SERDES drive level is set 2847 * to 1.2V. 2848 */ 2849 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 2850 (sc->bge_flags & BGE_FLAG_TBI)) { 2851 uint32_t serdescfg; 2852 2853 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2854 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2855 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2856 } 2857 2858 CSR_WRITE_4(sc, BGE_MI_MODE, 2859 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 2860 DELAY(80); 2861 2862 /* XXX: Broadcom Linux driver. */ 2863 if ((sc->bge_flags & BGE_FLAG_PCIE) && 2864 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 2865 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 2866 uint32_t v; 2867 2868 /* Enable Data FIFO protection. */ 2869 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT); 2870 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25)); 2871 } 2872 2873 DELAY(10000); 2874 } 2875 2876 /* 2877 * Frame reception handling. This is called if there's a frame 2878 * on the receive return list. 2879 * 2880 * Note: we have to be able to handle two possibilities here: 2881 * 1) the frame is from the jumbo recieve ring 2882 * 2) the frame is from the standard receive ring 2883 */ 2884 2885 static void 2886 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod) 2887 { 2888 struct ifnet *ifp; 2889 int stdcnt = 0, jumbocnt = 0; 2890 2891 ifp = &sc->arpcom.ac_if; 2892 2893 while (sc->bge_rx_saved_considx != rx_prod) { 2894 struct bge_rx_bd *cur_rx; 2895 uint32_t rxidx; 2896 struct mbuf *m = NULL; 2897 uint16_t vlan_tag = 0; 2898 int have_tag = 0; 2899 2900 cur_rx = 2901 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 2902 2903 rxidx = cur_rx->bge_idx; 2904 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2905 logif(rx_pkt); 2906 2907 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2908 have_tag = 1; 2909 vlan_tag = cur_rx->bge_vlan_tag; 2910 } 2911 2912 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2913 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2914 jumbocnt++; 2915 2916 if (rxidx != sc->bge_jumbo) { 2917 ifp->if_ierrors++; 2918 if_printf(ifp, "sw jumbo index(%d) " 2919 "and hw jumbo index(%d) mismatch, drop!\n", 2920 sc->bge_jumbo, rxidx); 2921 bge_setup_rxdesc_jumbo(sc, rxidx); 2922 continue; 2923 } 2924 2925 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf; 2926 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2927 ifp->if_ierrors++; 2928 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo); 2929 continue; 2930 } 2931 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) { 2932 ifp->if_ierrors++; 2933 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo); 2934 continue; 2935 } 2936 } else { 2937 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2938 stdcnt++; 2939 2940 if (rxidx != sc->bge_std) { 2941 ifp->if_ierrors++; 2942 if_printf(ifp, "sw std index(%d) " 2943 "and hw std index(%d) mismatch, drop!\n", 2944 sc->bge_std, rxidx); 2945 bge_setup_rxdesc_std(sc, rxidx); 2946 continue; 2947 } 2948 2949 m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf; 2950 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2951 ifp->if_ierrors++; 2952 bge_setup_rxdesc_std(sc, sc->bge_std); 2953 continue; 2954 } 2955 if (bge_newbuf_std(sc, sc->bge_std, 0)) { 2956 ifp->if_ierrors++; 2957 bge_setup_rxdesc_std(sc, sc->bge_std); 2958 continue; 2959 } 2960 } 2961 2962 ifp->if_ipackets++; 2963 #if !defined(__i386__) && !defined(__x86_64__) 2964 /* 2965 * The x86 allows unaligned accesses, but for other 2966 * platforms we must make sure the payload is aligned. 2967 */ 2968 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 2969 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2970 cur_rx->bge_len); 2971 m->m_data += ETHER_ALIGN; 2972 } 2973 #endif 2974 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2975 m->m_pkthdr.rcvif = ifp; 2976 2977 if (ifp->if_capenable & IFCAP_RXCSUM) { 2978 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 2979 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2980 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2981 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2982 } 2983 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) && 2984 m->m_pkthdr.len >= BGE_MIN_FRAMELEN) { 2985 m->m_pkthdr.csum_data = 2986 cur_rx->bge_tcp_udp_csum; 2987 m->m_pkthdr.csum_flags |= 2988 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2989 } 2990 } 2991 2992 /* 2993 * If we received a packet with a vlan tag, pass it 2994 * to vlan_input() instead of ether_input(). 2995 */ 2996 if (have_tag) { 2997 m->m_flags |= M_VLANTAG; 2998 m->m_pkthdr.ether_vlantag = vlan_tag; 2999 have_tag = vlan_tag = 0; 3000 } 3001 ifp->if_input(ifp, m); 3002 } 3003 3004 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3005 if (stdcnt) 3006 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3007 if (jumbocnt) 3008 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3009 } 3010 3011 static void 3012 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 3013 { 3014 struct ifnet *ifp; 3015 3016 ifp = &sc->arpcom.ac_if; 3017 3018 /* 3019 * Go through our tx ring and free mbufs for those 3020 * frames that have been sent. 3021 */ 3022 while (sc->bge_tx_saved_considx != tx_cons) { 3023 uint32_t idx = 0; 3024 3025 idx = sc->bge_tx_saved_considx; 3026 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3027 ifp->if_opackets++; 3028 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 3029 sc->bge_cdata.bge_tx_dmamap[idx]); 3030 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3031 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3032 } 3033 sc->bge_txcnt--; 3034 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3035 logif(tx_pkt); 3036 } 3037 3038 if ((BGE_TX_RING_CNT - sc->bge_txcnt) >= 3039 (sc->bge_txrsvd + sc->bge_txspare)) 3040 ifp->if_flags &= ~IFF_OACTIVE; 3041 3042 if (sc->bge_txcnt == 0) 3043 ifp->if_timer = 0; 3044 3045 if (!ifq_is_empty(&ifp->if_snd)) 3046 if_devstart(ifp); 3047 } 3048 3049 #ifdef DEVICE_POLLING 3050 3051 static void 3052 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3053 { 3054 struct bge_softc *sc = ifp->if_softc; 3055 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3056 uint16_t rx_prod, tx_cons; 3057 3058 switch(cmd) { 3059 case POLL_REGISTER: 3060 bge_disable_intr(sc); 3061 break; 3062 case POLL_DEREGISTER: 3063 bge_enable_intr(sc); 3064 break; 3065 case POLL_AND_CHECK_STATUS: 3066 /* 3067 * Process link state changes. 3068 */ 3069 bge_link_poll(sc); 3070 /* Fall through */ 3071 case POLL_ONLY: 3072 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 3073 sc->bge_status_tag = sblk->bge_status_tag; 3074 /* 3075 * Use a load fence to ensure that status_tag 3076 * is saved before rx_prod and tx_cons. 3077 */ 3078 cpu_lfence(); 3079 } 3080 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3081 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3082 if (ifp->if_flags & IFF_RUNNING) { 3083 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3084 if (sc->bge_rx_saved_considx != rx_prod) 3085 bge_rxeof(sc, rx_prod); 3086 3087 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3088 if (sc->bge_tx_saved_considx != tx_cons) 3089 bge_txeof(sc, tx_cons); 3090 } 3091 break; 3092 } 3093 } 3094 3095 #endif 3096 3097 static void 3098 bge_intr_crippled(void *xsc) 3099 { 3100 struct bge_softc *sc = xsc; 3101 struct ifnet *ifp = &sc->arpcom.ac_if; 3102 3103 logif(intr); 3104 3105 /* 3106 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3107 * disable interrupts by writing nonzero like we used to, since with 3108 * our current organization this just gives complications and 3109 * pessimizations for re-enabling interrupts. We used to have races 3110 * instead of the necessary complications. Disabling interrupts 3111 * would just reduce the chance of a status update while we are 3112 * running (by switching to the interrupt-mode coalescence 3113 * parameters), but this chance is already very low so it is more 3114 * efficient to get another interrupt than prevent it. 3115 * 3116 * We do the ack first to ensure another interrupt if there is a 3117 * status update after the ack. We don't check for the status 3118 * changing later because it is more efficient to get another 3119 * interrupt than prevent it, not quite as above (not checking is 3120 * a smaller optimization than not toggling the interrupt enable, 3121 * since checking doesn't involve PCI accesses and toggling require 3122 * the status check). So toggling would probably be a pessimization 3123 * even with MSI. It would only be needed for using a task queue. 3124 */ 3125 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3126 3127 /* 3128 * Process link state changes. 3129 */ 3130 bge_link_poll(sc); 3131 3132 if (ifp->if_flags & IFF_RUNNING) { 3133 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3134 uint16_t rx_prod, tx_cons; 3135 3136 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3137 if (sc->bge_rx_saved_considx != rx_prod) 3138 bge_rxeof(sc, rx_prod); 3139 3140 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3141 if (sc->bge_tx_saved_considx != tx_cons) 3142 bge_txeof(sc, tx_cons); 3143 } 3144 3145 if (sc->bge_coal_chg) 3146 bge_coal_change(sc); 3147 } 3148 3149 static void 3150 bge_intr_legacy(void *xsc) 3151 { 3152 struct bge_softc *sc = xsc; 3153 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3154 3155 if (sc->bge_status_tag == sblk->bge_status_tag) { 3156 uint32_t val; 3157 3158 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3159 if (val & BGE_PCISTAT_INTR_NOTACT) 3160 return; 3161 } 3162 3163 /* 3164 * NOTE: 3165 * Interrupt will have to be disabled if tagged status 3166 * is used, else interrupt will always be asserted on 3167 * certain chips (at least on BCM5750 AX/BX). 3168 */ 3169 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3170 3171 bge_intr(sc); 3172 } 3173 3174 static void 3175 bge_msi(void *xsc) 3176 { 3177 struct bge_softc *sc = xsc; 3178 3179 /* Disable interrupt first */ 3180 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3181 bge_intr(sc); 3182 } 3183 3184 static void 3185 bge_msi_oneshot(void *xsc) 3186 { 3187 bge_intr(xsc); 3188 } 3189 3190 static void 3191 bge_intr(struct bge_softc *sc) 3192 { 3193 struct ifnet *ifp = &sc->arpcom.ac_if; 3194 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3195 uint16_t rx_prod, tx_cons; 3196 uint32_t status; 3197 3198 sc->bge_status_tag = sblk->bge_status_tag; 3199 /* 3200 * Use a load fence to ensure that status_tag is saved 3201 * before rx_prod, tx_cons and status. 3202 */ 3203 cpu_lfence(); 3204 3205 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3206 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3207 status = sblk->bge_status; 3208 3209 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt) 3210 bge_link_poll(sc); 3211 3212 if (ifp->if_flags & IFF_RUNNING) { 3213 if (sc->bge_rx_saved_considx != rx_prod) 3214 bge_rxeof(sc, rx_prod); 3215 3216 if (sc->bge_tx_saved_considx != tx_cons) 3217 bge_txeof(sc, tx_cons); 3218 } 3219 3220 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 3221 3222 if (sc->bge_coal_chg) 3223 bge_coal_change(sc); 3224 } 3225 3226 static void 3227 bge_tick(void *xsc) 3228 { 3229 struct bge_softc *sc = xsc; 3230 struct ifnet *ifp = &sc->arpcom.ac_if; 3231 3232 lwkt_serialize_enter(ifp->if_serializer); 3233 3234 if (BGE_IS_5705_PLUS(sc)) 3235 bge_stats_update_regs(sc); 3236 else 3237 bge_stats_update(sc); 3238 3239 if (sc->bge_flags & BGE_FLAG_TBI) { 3240 /* 3241 * Since in TBI mode auto-polling can't be used we should poll 3242 * link status manually. Here we register pending link event 3243 * and trigger interrupt. 3244 */ 3245 sc->bge_link_evt++; 3246 if (BGE_IS_CRIPPLED(sc)) 3247 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3248 else 3249 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3250 } else if (!sc->bge_link) { 3251 mii_tick(device_get_softc(sc->bge_miibus)); 3252 } 3253 3254 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 3255 3256 lwkt_serialize_exit(ifp->if_serializer); 3257 } 3258 3259 static void 3260 bge_stats_update_regs(struct bge_softc *sc) 3261 { 3262 struct ifnet *ifp = &sc->arpcom.ac_if; 3263 struct bge_mac_stats_regs stats; 3264 uint32_t *s; 3265 int i; 3266 3267 s = (uint32_t *)&stats; 3268 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 3269 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 3270 s++; 3271 } 3272 3273 ifp->if_collisions += 3274 (stats.dot3StatsSingleCollisionFrames + 3275 stats.dot3StatsMultipleCollisionFrames + 3276 stats.dot3StatsExcessiveCollisions + 3277 stats.dot3StatsLateCollisions) - 3278 ifp->if_collisions; 3279 } 3280 3281 static void 3282 bge_stats_update(struct bge_softc *sc) 3283 { 3284 struct ifnet *ifp = &sc->arpcom.ac_if; 3285 bus_size_t stats; 3286 3287 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3288 3289 #define READ_STAT(sc, stats, stat) \ 3290 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3291 3292 ifp->if_collisions += 3293 (READ_STAT(sc, stats, 3294 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) + 3295 READ_STAT(sc, stats, 3296 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3297 READ_STAT(sc, stats, 3298 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) + 3299 READ_STAT(sc, stats, 3300 txstats.dot3StatsLateCollisions.bge_addr_lo)) - 3301 ifp->if_collisions; 3302 3303 #undef READ_STAT 3304 3305 #ifdef notdef 3306 ifp->if_collisions += 3307 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3308 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3309 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3310 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3311 ifp->if_collisions; 3312 #endif 3313 } 3314 3315 /* 3316 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3317 * pointers to descriptors. 3318 */ 3319 static int 3320 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx) 3321 { 3322 struct bge_tx_bd *d = NULL, *last_d; 3323 uint16_t csum_flags = 0, mss = 0; 3324 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3325 bus_dmamap_t map; 3326 int error, maxsegs, nsegs, idx, i; 3327 struct mbuf *m_head = *m_head0, *m_new; 3328 3329 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3330 error = bge_setup_tso(sc, m_head0, &mss, &csum_flags); 3331 if (error) 3332 return ENOBUFS; 3333 m_head = *m_head0; 3334 } else if (m_head->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) { 3335 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3336 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3337 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3338 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3339 if (m_head->m_flags & M_LASTFRAG) 3340 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3341 else if (m_head->m_flags & M_FRAG) 3342 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3343 } 3344 3345 idx = *txidx; 3346 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3347 3348 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - sc->bge_txrsvd; 3349 KASSERT(maxsegs >= sc->bge_txspare, 3350 ("not enough segments %d", maxsegs)); 3351 3352 if (maxsegs > BGE_NSEG_NEW) 3353 maxsegs = BGE_NSEG_NEW; 3354 3355 /* 3356 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason. 3357 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN, 3358 * but when such padded frames employ the bge IP/TCP checksum 3359 * offload, the hardware checksum assist gives incorrect results 3360 * (possibly from incorporating its own padding into the UDP/TCP 3361 * checksum; who knows). If we pad such runts with zeros, the 3362 * onboard checksum comes out correct. 3363 */ 3364 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) && 3365 m_head->m_pkthdr.len < BGE_MIN_FRAMELEN) { 3366 error = m_devpad(m_head, BGE_MIN_FRAMELEN); 3367 if (error) 3368 goto back; 3369 } 3370 3371 if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) { 3372 m_new = bge_defrag_shortdma(m_head); 3373 if (m_new == NULL) { 3374 error = ENOBUFS; 3375 goto back; 3376 } 3377 *m_head0 = m_head = m_new; 3378 } 3379 if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 && 3380 sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) && 3381 m_head->m_next != NULL) { 3382 /* 3383 * Forcefully defragment mbuf chain to overcome hardware 3384 * limitation which only support a single outstanding 3385 * DMA read operation. If it fails, keep moving on using 3386 * the original mbuf chain. 3387 */ 3388 m_new = m_defrag(m_head, MB_DONTWAIT); 3389 if (m_new != NULL) 3390 *m_head0 = m_head = m_new; 3391 } 3392 3393 error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map, 3394 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 3395 if (error) 3396 goto back; 3397 3398 m_head = *m_head0; 3399 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 3400 3401 for (i = 0; ; i++) { 3402 d = &sc->bge_ldata.bge_tx_ring[idx]; 3403 3404 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3405 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3406 d->bge_len = segs[i].ds_len; 3407 d->bge_flags = csum_flags; 3408 d->bge_mss = mss; 3409 3410 if (i == nsegs - 1) 3411 break; 3412 BGE_INC(idx, BGE_TX_RING_CNT); 3413 } 3414 last_d = d; 3415 3416 /* Set vlan tag to the first segment of the packet. */ 3417 d = &sc->bge_ldata.bge_tx_ring[*txidx]; 3418 if (m_head->m_flags & M_VLANTAG) { 3419 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3420 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag; 3421 } else { 3422 d->bge_vlan_tag = 0; 3423 } 3424 3425 /* Mark the last segment as end of packet... */ 3426 last_d->bge_flags |= BGE_TXBDFLAG_END; 3427 3428 /* 3429 * Insure that the map for this transmission is placed at 3430 * the array index of the last descriptor in this chain. 3431 */ 3432 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3433 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3434 sc->bge_cdata.bge_tx_chain[idx] = m_head; 3435 sc->bge_txcnt += nsegs; 3436 3437 BGE_INC(idx, BGE_TX_RING_CNT); 3438 *txidx = idx; 3439 back: 3440 if (error) { 3441 m_freem(*m_head0); 3442 *m_head0 = NULL; 3443 } 3444 return error; 3445 } 3446 3447 /* 3448 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3449 * to the mbuf data regions directly in the transmit descriptors. 3450 */ 3451 static void 3452 bge_start(struct ifnet *ifp) 3453 { 3454 struct bge_softc *sc = ifp->if_softc; 3455 struct mbuf *m_head = NULL; 3456 uint32_t prodidx; 3457 int need_trans; 3458 3459 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3460 return; 3461 3462 prodidx = sc->bge_tx_prodidx; 3463 3464 need_trans = 0; 3465 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3466 m_head = ifq_dequeue(&ifp->if_snd, NULL); 3467 if (m_head == NULL) 3468 break; 3469 3470 /* 3471 * XXX 3472 * The code inside the if() block is never reached since we 3473 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3474 * requests to checksum TCP/UDP in a fragmented packet. 3475 * 3476 * XXX 3477 * safety overkill. If this is a fragmented packet chain 3478 * with delayed TCP/UDP checksums, then only encapsulate 3479 * it if we have enough descriptors to handle the entire 3480 * chain at once. 3481 * (paranoia -- may not actually be needed) 3482 */ 3483 if ((m_head->m_flags & M_FIRSTFRAG) && 3484 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) { 3485 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3486 m_head->m_pkthdr.csum_data + sc->bge_txrsvd) { 3487 ifp->if_flags |= IFF_OACTIVE; 3488 ifq_prepend(&ifp->if_snd, m_head); 3489 break; 3490 } 3491 } 3492 3493 /* 3494 * Sanity check: avoid coming within bge_txrsvd 3495 * descriptors of the end of the ring. Also make 3496 * sure there are bge_txspare descriptors for 3497 * jumbo buffers' defragmentation. 3498 */ 3499 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3500 (sc->bge_txrsvd + sc->bge_txspare)) { 3501 ifp->if_flags |= IFF_OACTIVE; 3502 ifq_prepend(&ifp->if_snd, m_head); 3503 break; 3504 } 3505 3506 /* 3507 * Pack the data into the transmit ring. If we 3508 * don't have room, set the OACTIVE flag and wait 3509 * for the NIC to drain the ring. 3510 */ 3511 if (bge_encap(sc, &m_head, &prodidx)) { 3512 ifp->if_flags |= IFF_OACTIVE; 3513 ifp->if_oerrors++; 3514 break; 3515 } 3516 need_trans = 1; 3517 3518 ETHER_BPF_MTAP(ifp, m_head); 3519 } 3520 3521 if (!need_trans) 3522 return; 3523 3524 /* Transmit */ 3525 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3526 /* 5700 b2 errata */ 3527 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3528 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3529 3530 sc->bge_tx_prodidx = prodidx; 3531 3532 /* 3533 * Set a timeout in case the chip goes out to lunch. 3534 */ 3535 ifp->if_timer = 5; 3536 } 3537 3538 static void 3539 bge_init(void *xsc) 3540 { 3541 struct bge_softc *sc = xsc; 3542 struct ifnet *ifp = &sc->arpcom.ac_if; 3543 uint16_t *m; 3544 uint32_t mode; 3545 3546 ASSERT_SERIALIZED(ifp->if_serializer); 3547 3548 /* Cancel pending I/O and flush buffers. */ 3549 bge_stop(sc); 3550 bge_reset(sc); 3551 bge_chipinit(sc); 3552 3553 /* 3554 * Init the various state machines, ring 3555 * control blocks and firmware. 3556 */ 3557 if (bge_blockinit(sc)) { 3558 if_printf(ifp, "initialization failure\n"); 3559 bge_stop(sc); 3560 return; 3561 } 3562 3563 /* Specify MTU. */ 3564 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3565 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN); 3566 3567 /* Load our MAC address. */ 3568 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 3569 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3570 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3571 3572 /* Enable or disable promiscuous mode as needed. */ 3573 bge_setpromisc(sc); 3574 3575 /* Program multicast filter. */ 3576 bge_setmulti(sc); 3577 3578 /* Init RX ring. */ 3579 if (bge_init_rx_ring_std(sc)) { 3580 if_printf(ifp, "RX ring initialization failed\n"); 3581 bge_stop(sc); 3582 return; 3583 } 3584 3585 /* 3586 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3587 * memory to insure that the chip has in fact read the first 3588 * entry of the ring. 3589 */ 3590 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3591 uint32_t v, i; 3592 for (i = 0; i < 10; i++) { 3593 DELAY(20); 3594 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3595 if (v == (MCLBYTES - ETHER_ALIGN)) 3596 break; 3597 } 3598 if (i == 10) 3599 if_printf(ifp, "5705 A0 chip failed to load RX ring\n"); 3600 } 3601 3602 /* Init jumbo RX ring. */ 3603 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) { 3604 if (bge_init_rx_ring_jumbo(sc)) { 3605 if_printf(ifp, "Jumbo RX ring initialization failed\n"); 3606 bge_stop(sc); 3607 return; 3608 } 3609 } 3610 3611 /* Init our RX return ring index */ 3612 sc->bge_rx_saved_considx = 0; 3613 3614 /* Init TX ring. */ 3615 bge_init_tx_ring(sc); 3616 3617 /* Enable TX MAC state machine lockup fix. */ 3618 mode = CSR_READ_4(sc, BGE_TX_MODE); 3619 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3620 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 3621 /* Turn on transmitter */ 3622 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 3623 3624 /* Turn on receiver */ 3625 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3626 3627 /* 3628 * Set the number of good frames to receive after RX MBUF 3629 * Low Watermark has been reached. After the RX MAC receives 3630 * this number of frames, it will drop subsequent incoming 3631 * frames until the MBUF High Watermark is reached. 3632 */ 3633 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3634 3635 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) { 3636 if (bootverbose) { 3637 if_printf(ifp, "MSI_MODE: %#x\n", 3638 CSR_READ_4(sc, BGE_MSI_MODE)); 3639 } 3640 3641 /* 3642 * XXX 3643 * Linux driver turns it on for all chips supporting MSI?! 3644 */ 3645 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 3646 /* 3647 * XXX 3648 * According to 5722-PG101-R, 3649 * BGE_PCIE_TRANSACT_ONESHOT_MSI applies only to 3650 * BCM5906. 3651 */ 3652 BGE_SETBIT(sc, BGE_PCIE_TRANSACT, 3653 BGE_PCIE_TRANSACT_ONESHOT_MSI); 3654 } 3655 } 3656 3657 /* Tell firmware we're alive. */ 3658 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3659 3660 /* Enable host interrupts if polling(4) is not enabled. */ 3661 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4); 3662 #ifdef DEVICE_POLLING 3663 if (ifp->if_flags & IFF_POLLING) 3664 bge_disable_intr(sc); 3665 else 3666 #endif 3667 bge_enable_intr(sc); 3668 3669 bge_ifmedia_upd(ifp); 3670 3671 ifp->if_flags |= IFF_RUNNING; 3672 ifp->if_flags &= ~IFF_OACTIVE; 3673 3674 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 3675 } 3676 3677 /* 3678 * Set media options. 3679 */ 3680 static int 3681 bge_ifmedia_upd(struct ifnet *ifp) 3682 { 3683 struct bge_softc *sc = ifp->if_softc; 3684 3685 /* If this is a 1000baseX NIC, enable the TBI port. */ 3686 if (sc->bge_flags & BGE_FLAG_TBI) { 3687 struct ifmedia *ifm = &sc->bge_ifmedia; 3688 3689 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3690 return(EINVAL); 3691 3692 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3693 case IFM_AUTO: 3694 /* 3695 * The BCM5704 ASIC appears to have a special 3696 * mechanism for programming the autoneg 3697 * advertisement registers in TBI mode. 3698 */ 3699 if (!bge_fake_autoneg && 3700 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3701 uint32_t sgdig; 3702 3703 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3704 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3705 sgdig |= BGE_SGDIGCFG_AUTO | 3706 BGE_SGDIGCFG_PAUSE_CAP | 3707 BGE_SGDIGCFG_ASYM_PAUSE; 3708 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3709 sgdig | BGE_SGDIGCFG_SEND); 3710 DELAY(5); 3711 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3712 } 3713 break; 3714 case IFM_1000_SX: 3715 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3716 BGE_CLRBIT(sc, BGE_MAC_MODE, 3717 BGE_MACMODE_HALF_DUPLEX); 3718 } else { 3719 BGE_SETBIT(sc, BGE_MAC_MODE, 3720 BGE_MACMODE_HALF_DUPLEX); 3721 } 3722 break; 3723 default: 3724 return(EINVAL); 3725 } 3726 } else { 3727 struct mii_data *mii = device_get_softc(sc->bge_miibus); 3728 3729 sc->bge_link_evt++; 3730 sc->bge_link = 0; 3731 if (mii->mii_instance) { 3732 struct mii_softc *miisc; 3733 3734 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3735 mii_phy_reset(miisc); 3736 } 3737 mii_mediachg(mii); 3738 3739 /* 3740 * Force an interrupt so that we will call bge_link_upd 3741 * if needed and clear any pending link state attention. 3742 * Without this we are not getting any further interrupts 3743 * for link state changes and thus will not UP the link and 3744 * not be able to send in bge_start. The only way to get 3745 * things working was to receive a packet and get an RX 3746 * intr. 3747 * 3748 * bge_tick should help for fiber cards and we might not 3749 * need to do this here if BGE_FLAG_TBI is set but as 3750 * we poll for fiber anyway it should not harm. 3751 */ 3752 if (BGE_IS_CRIPPLED(sc)) 3753 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3754 else 3755 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3756 } 3757 return(0); 3758 } 3759 3760 /* 3761 * Report current media status. 3762 */ 3763 static void 3764 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3765 { 3766 struct bge_softc *sc = ifp->if_softc; 3767 3768 if (sc->bge_flags & BGE_FLAG_TBI) { 3769 ifmr->ifm_status = IFM_AVALID; 3770 ifmr->ifm_active = IFM_ETHER; 3771 if (CSR_READ_4(sc, BGE_MAC_STS) & 3772 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3773 ifmr->ifm_status |= IFM_ACTIVE; 3774 } else { 3775 ifmr->ifm_active |= IFM_NONE; 3776 return; 3777 } 3778 3779 ifmr->ifm_active |= IFM_1000_SX; 3780 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3781 ifmr->ifm_active |= IFM_HDX; 3782 else 3783 ifmr->ifm_active |= IFM_FDX; 3784 } else { 3785 struct mii_data *mii = device_get_softc(sc->bge_miibus); 3786 3787 mii_pollstat(mii); 3788 ifmr->ifm_active = mii->mii_media_active; 3789 ifmr->ifm_status = mii->mii_media_status; 3790 } 3791 } 3792 3793 static int 3794 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3795 { 3796 struct bge_softc *sc = ifp->if_softc; 3797 struct ifreq *ifr = (struct ifreq *)data; 3798 int mask, error = 0; 3799 3800 ASSERT_SERIALIZED(ifp->if_serializer); 3801 3802 switch (command) { 3803 case SIOCSIFMTU: 3804 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) || 3805 (BGE_IS_JUMBO_CAPABLE(sc) && 3806 ifr->ifr_mtu > BGE_JUMBO_MTU)) { 3807 error = EINVAL; 3808 } else if (ifp->if_mtu != ifr->ifr_mtu) { 3809 ifp->if_mtu = ifr->ifr_mtu; 3810 if (ifp->if_flags & IFF_RUNNING) 3811 bge_init(sc); 3812 } 3813 break; 3814 case SIOCSIFFLAGS: 3815 if (ifp->if_flags & IFF_UP) { 3816 if (ifp->if_flags & IFF_RUNNING) { 3817 mask = ifp->if_flags ^ sc->bge_if_flags; 3818 3819 /* 3820 * If only the state of the PROMISC flag 3821 * changed, then just use the 'set promisc 3822 * mode' command instead of reinitializing 3823 * the entire NIC. Doing a full re-init 3824 * means reloading the firmware and waiting 3825 * for it to start up, which may take a 3826 * second or two. Similarly for ALLMULTI. 3827 */ 3828 if (mask & IFF_PROMISC) 3829 bge_setpromisc(sc); 3830 if (mask & IFF_ALLMULTI) 3831 bge_setmulti(sc); 3832 } else { 3833 bge_init(sc); 3834 } 3835 } else if (ifp->if_flags & IFF_RUNNING) { 3836 bge_stop(sc); 3837 } 3838 sc->bge_if_flags = ifp->if_flags; 3839 break; 3840 case SIOCADDMULTI: 3841 case SIOCDELMULTI: 3842 if (ifp->if_flags & IFF_RUNNING) 3843 bge_setmulti(sc); 3844 break; 3845 case SIOCSIFMEDIA: 3846 case SIOCGIFMEDIA: 3847 if (sc->bge_flags & BGE_FLAG_TBI) { 3848 error = ifmedia_ioctl(ifp, ifr, 3849 &sc->bge_ifmedia, command); 3850 } else { 3851 struct mii_data *mii; 3852 3853 mii = device_get_softc(sc->bge_miibus); 3854 error = ifmedia_ioctl(ifp, ifr, 3855 &mii->mii_media, command); 3856 } 3857 break; 3858 case SIOCSIFCAP: 3859 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3860 if (mask & IFCAP_HWCSUM) { 3861 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 3862 if (ifp->if_capenable & IFCAP_TXCSUM) 3863 ifp->if_hwassist |= BGE_CSUM_FEATURES; 3864 else 3865 ifp->if_hwassist &= ~BGE_CSUM_FEATURES; 3866 } 3867 if (mask & IFCAP_TSO) { 3868 ifp->if_capenable ^= IFCAP_TSO; 3869 if (ifp->if_capenable & IFCAP_TSO) 3870 ifp->if_hwassist |= CSUM_TSO; 3871 else 3872 ifp->if_hwassist &= ~CSUM_TSO; 3873 } 3874 break; 3875 default: 3876 error = ether_ioctl(ifp, command, data); 3877 break; 3878 } 3879 return error; 3880 } 3881 3882 static void 3883 bge_watchdog(struct ifnet *ifp) 3884 { 3885 struct bge_softc *sc = ifp->if_softc; 3886 3887 if_printf(ifp, "watchdog timeout -- resetting\n"); 3888 3889 bge_init(sc); 3890 3891 ifp->if_oerrors++; 3892 3893 if (!ifq_is_empty(&ifp->if_snd)) 3894 if_devstart(ifp); 3895 } 3896 3897 /* 3898 * Stop the adapter and free any mbufs allocated to the 3899 * RX and TX lists. 3900 */ 3901 static void 3902 bge_stop(struct bge_softc *sc) 3903 { 3904 struct ifnet *ifp = &sc->arpcom.ac_if; 3905 3906 ASSERT_SERIALIZED(ifp->if_serializer); 3907 3908 callout_stop(&sc->bge_stat_timer); 3909 3910 /* 3911 * Disable all of the receiver blocks 3912 */ 3913 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3914 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3915 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3916 if (BGE_IS_5700_FAMILY(sc)) 3917 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3918 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3919 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3920 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3921 3922 /* 3923 * Disable all of the transmit blocks 3924 */ 3925 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3926 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3927 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3928 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3929 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3930 if (BGE_IS_5700_FAMILY(sc)) 3931 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3932 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3933 3934 /* 3935 * Shut down all of the memory managers and related 3936 * state machines. 3937 */ 3938 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3939 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3940 if (BGE_IS_5700_FAMILY(sc)) 3941 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3942 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3943 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3944 if (!BGE_IS_5705_PLUS(sc)) { 3945 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3946 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3947 } 3948 3949 /* Disable host interrupts. */ 3950 bge_disable_intr(sc); 3951 3952 /* 3953 * Tell firmware we're shutting down. 3954 */ 3955 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3956 3957 /* Free the RX lists. */ 3958 bge_free_rx_ring_std(sc); 3959 3960 /* Free jumbo RX list. */ 3961 if (BGE_IS_JUMBO_CAPABLE(sc)) 3962 bge_free_rx_ring_jumbo(sc); 3963 3964 /* Free TX buffers. */ 3965 bge_free_tx_ring(sc); 3966 3967 sc->bge_status_tag = 0; 3968 sc->bge_link = 0; 3969 sc->bge_coal_chg = 0; 3970 3971 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3972 3973 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3974 ifp->if_timer = 0; 3975 } 3976 3977 /* 3978 * Stop all chip I/O so that the kernel's probe routines don't 3979 * get confused by errant DMAs when rebooting. 3980 */ 3981 static void 3982 bge_shutdown(device_t dev) 3983 { 3984 struct bge_softc *sc = device_get_softc(dev); 3985 struct ifnet *ifp = &sc->arpcom.ac_if; 3986 3987 lwkt_serialize_enter(ifp->if_serializer); 3988 bge_stop(sc); 3989 bge_reset(sc); 3990 lwkt_serialize_exit(ifp->if_serializer); 3991 } 3992 3993 static int 3994 bge_suspend(device_t dev) 3995 { 3996 struct bge_softc *sc = device_get_softc(dev); 3997 struct ifnet *ifp = &sc->arpcom.ac_if; 3998 3999 lwkt_serialize_enter(ifp->if_serializer); 4000 bge_stop(sc); 4001 lwkt_serialize_exit(ifp->if_serializer); 4002 4003 return 0; 4004 } 4005 4006 static int 4007 bge_resume(device_t dev) 4008 { 4009 struct bge_softc *sc = device_get_softc(dev); 4010 struct ifnet *ifp = &sc->arpcom.ac_if; 4011 4012 lwkt_serialize_enter(ifp->if_serializer); 4013 4014 if (ifp->if_flags & IFF_UP) { 4015 bge_init(sc); 4016 4017 if (!ifq_is_empty(&ifp->if_snd)) 4018 if_devstart(ifp); 4019 } 4020 4021 lwkt_serialize_exit(ifp->if_serializer); 4022 4023 return 0; 4024 } 4025 4026 static void 4027 bge_setpromisc(struct bge_softc *sc) 4028 { 4029 struct ifnet *ifp = &sc->arpcom.ac_if; 4030 4031 if (ifp->if_flags & IFF_PROMISC) 4032 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4033 else 4034 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4035 } 4036 4037 static void 4038 bge_dma_free(struct bge_softc *sc) 4039 { 4040 int i; 4041 4042 /* Destroy RX mbuf DMA stuffs. */ 4043 if (sc->bge_cdata.bge_rx_mtag != NULL) { 4044 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 4045 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 4046 sc->bge_cdata.bge_rx_std_dmamap[i]); 4047 } 4048 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 4049 sc->bge_cdata.bge_rx_tmpmap); 4050 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 4051 } 4052 4053 /* Destroy TX mbuf DMA stuffs. */ 4054 if (sc->bge_cdata.bge_tx_mtag != NULL) { 4055 for (i = 0; i < BGE_TX_RING_CNT; i++) { 4056 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 4057 sc->bge_cdata.bge_tx_dmamap[i]); 4058 } 4059 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 4060 } 4061 4062 /* Destroy standard RX ring */ 4063 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag, 4064 sc->bge_cdata.bge_rx_std_ring_map, 4065 sc->bge_ldata.bge_rx_std_ring); 4066 4067 if (BGE_IS_JUMBO_CAPABLE(sc)) 4068 bge_free_jumbo_mem(sc); 4069 4070 /* Destroy RX return ring */ 4071 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag, 4072 sc->bge_cdata.bge_rx_return_ring_map, 4073 sc->bge_ldata.bge_rx_return_ring); 4074 4075 /* Destroy TX ring */ 4076 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag, 4077 sc->bge_cdata.bge_tx_ring_map, 4078 sc->bge_ldata.bge_tx_ring); 4079 4080 /* Destroy status block */ 4081 bge_dma_block_free(sc->bge_cdata.bge_status_tag, 4082 sc->bge_cdata.bge_status_map, 4083 sc->bge_ldata.bge_status_block); 4084 4085 /* Destroy statistics block */ 4086 bge_dma_block_free(sc->bge_cdata.bge_stats_tag, 4087 sc->bge_cdata.bge_stats_map, 4088 sc->bge_ldata.bge_stats); 4089 4090 /* Destroy the parent tag */ 4091 if (sc->bge_cdata.bge_parent_tag != NULL) 4092 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 4093 } 4094 4095 static int 4096 bge_dma_alloc(struct bge_softc *sc) 4097 { 4098 struct ifnet *ifp = &sc->arpcom.ac_if; 4099 int i, error; 4100 bus_addr_t lowaddr; 4101 bus_size_t txmaxsz; 4102 4103 lowaddr = BUS_SPACE_MAXADDR; 4104 if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) 4105 lowaddr = BGE_DMA_MAXADDR_40BIT; 4106 4107 /* 4108 * Allocate the parent bus DMA tag appropriate for PCI. 4109 * 4110 * All of the NetExtreme/NetLink controllers have 4GB boundary 4111 * DMA bug. 4112 * Whenever an address crosses a multiple of the 4GB boundary 4113 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 4114 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 4115 * state machine will lockup and cause the device to hang. 4116 */ 4117 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G, 4118 lowaddr, BUS_SPACE_MAXADDR, 4119 NULL, NULL, 4120 BUS_SPACE_MAXSIZE_32BIT, 0, 4121 BUS_SPACE_MAXSIZE_32BIT, 4122 0, &sc->bge_cdata.bge_parent_tag); 4123 if (error) { 4124 if_printf(ifp, "could not allocate parent dma tag\n"); 4125 return error; 4126 } 4127 4128 /* 4129 * Create DMA tag and maps for RX mbufs. 4130 */ 4131 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0, 4132 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4133 NULL, NULL, MCLBYTES, 1, MCLBYTES, 4134 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 4135 &sc->bge_cdata.bge_rx_mtag); 4136 if (error) { 4137 if_printf(ifp, "could not allocate RX mbuf dma tag\n"); 4138 return error; 4139 } 4140 4141 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 4142 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap); 4143 if (error) { 4144 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 4145 sc->bge_cdata.bge_rx_mtag = NULL; 4146 return error; 4147 } 4148 4149 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 4150 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 4151 BUS_DMA_WAITOK, 4152 &sc->bge_cdata.bge_rx_std_dmamap[i]); 4153 if (error) { 4154 int j; 4155 4156 for (j = 0; j < i; ++j) { 4157 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 4158 sc->bge_cdata.bge_rx_std_dmamap[j]); 4159 } 4160 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 4161 sc->bge_cdata.bge_rx_mtag = NULL; 4162 4163 if_printf(ifp, "could not create DMA map for RX\n"); 4164 return error; 4165 } 4166 } 4167 4168 /* 4169 * Create DMA tag and maps for TX mbufs. 4170 */ 4171 if (sc->bge_flags & BGE_FLAG_TSO) 4172 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header); 4173 else 4174 txmaxsz = BGE_JUMBO_FRAMELEN; 4175 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0, 4176 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4177 NULL, NULL, 4178 txmaxsz, BGE_NSEG_NEW, PAGE_SIZE, 4179 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 4180 BUS_DMA_ONEBPAGE, 4181 &sc->bge_cdata.bge_tx_mtag); 4182 if (error) { 4183 if_printf(ifp, "could not allocate TX mbuf dma tag\n"); 4184 return error; 4185 } 4186 4187 for (i = 0; i < BGE_TX_RING_CNT; i++) { 4188 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 4189 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 4190 &sc->bge_cdata.bge_tx_dmamap[i]); 4191 if (error) { 4192 int j; 4193 4194 for (j = 0; j < i; ++j) { 4195 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 4196 sc->bge_cdata.bge_tx_dmamap[j]); 4197 } 4198 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 4199 sc->bge_cdata.bge_tx_mtag = NULL; 4200 4201 if_printf(ifp, "could not create DMA map for TX\n"); 4202 return error; 4203 } 4204 } 4205 4206 /* 4207 * Create DMA stuffs for standard RX ring. 4208 */ 4209 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ, 4210 &sc->bge_cdata.bge_rx_std_ring_tag, 4211 &sc->bge_cdata.bge_rx_std_ring_map, 4212 (void *)&sc->bge_ldata.bge_rx_std_ring, 4213 &sc->bge_ldata.bge_rx_std_ring_paddr); 4214 if (error) { 4215 if_printf(ifp, "could not create std RX ring\n"); 4216 return error; 4217 } 4218 4219 /* 4220 * Create jumbo buffer pool. 4221 */ 4222 if (BGE_IS_JUMBO_CAPABLE(sc)) { 4223 error = bge_alloc_jumbo_mem(sc); 4224 if (error) { 4225 if_printf(ifp, "could not create jumbo buffer pool\n"); 4226 return error; 4227 } 4228 } 4229 4230 /* 4231 * Create DMA stuffs for RX return ring. 4232 */ 4233 error = bge_dma_block_alloc(sc, 4234 BGE_RX_RTN_RING_SZ(sc->bge_return_ring_cnt), 4235 &sc->bge_cdata.bge_rx_return_ring_tag, 4236 &sc->bge_cdata.bge_rx_return_ring_map, 4237 (void *)&sc->bge_ldata.bge_rx_return_ring, 4238 &sc->bge_ldata.bge_rx_return_ring_paddr); 4239 if (error) { 4240 if_printf(ifp, "could not create RX ret ring\n"); 4241 return error; 4242 } 4243 4244 /* 4245 * Create DMA stuffs for TX ring. 4246 */ 4247 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ, 4248 &sc->bge_cdata.bge_tx_ring_tag, 4249 &sc->bge_cdata.bge_tx_ring_map, 4250 (void *)&sc->bge_ldata.bge_tx_ring, 4251 &sc->bge_ldata.bge_tx_ring_paddr); 4252 if (error) { 4253 if_printf(ifp, "could not create TX ring\n"); 4254 return error; 4255 } 4256 4257 /* 4258 * Create DMA stuffs for status block. 4259 */ 4260 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ, 4261 &sc->bge_cdata.bge_status_tag, 4262 &sc->bge_cdata.bge_status_map, 4263 (void *)&sc->bge_ldata.bge_status_block, 4264 &sc->bge_ldata.bge_status_block_paddr); 4265 if (error) { 4266 if_printf(ifp, "could not create status block\n"); 4267 return error; 4268 } 4269 4270 /* 4271 * Create DMA stuffs for statistics block. 4272 */ 4273 error = bge_dma_block_alloc(sc, BGE_STATS_SZ, 4274 &sc->bge_cdata.bge_stats_tag, 4275 &sc->bge_cdata.bge_stats_map, 4276 (void *)&sc->bge_ldata.bge_stats, 4277 &sc->bge_ldata.bge_stats_paddr); 4278 if (error) { 4279 if_printf(ifp, "could not create stats block\n"); 4280 return error; 4281 } 4282 return 0; 4283 } 4284 4285 static int 4286 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag, 4287 bus_dmamap_t *map, void **addr, bus_addr_t *paddr) 4288 { 4289 bus_dmamem_t dmem; 4290 int error; 4291 4292 error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0, 4293 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4294 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 4295 if (error) 4296 return error; 4297 4298 *tag = dmem.dmem_tag; 4299 *map = dmem.dmem_map; 4300 *addr = dmem.dmem_addr; 4301 *paddr = dmem.dmem_busaddr; 4302 4303 return 0; 4304 } 4305 4306 static void 4307 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr) 4308 { 4309 if (tag != NULL) { 4310 bus_dmamap_unload(tag, map); 4311 bus_dmamem_free(tag, addr, map); 4312 bus_dma_tag_destroy(tag); 4313 } 4314 } 4315 4316 /* 4317 * Grrr. The link status word in the status block does 4318 * not work correctly on the BCM5700 rev AX and BX chips, 4319 * according to all available information. Hence, we have 4320 * to enable MII interrupts in order to properly obtain 4321 * async link changes. Unfortunately, this also means that 4322 * we have to read the MAC status register to detect link 4323 * changes, thereby adding an additional register access to 4324 * the interrupt handler. 4325 * 4326 * XXX: perhaps link state detection procedure used for 4327 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4328 */ 4329 static void 4330 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused) 4331 { 4332 struct ifnet *ifp = &sc->arpcom.ac_if; 4333 struct mii_data *mii = device_get_softc(sc->bge_miibus); 4334 4335 mii_pollstat(mii); 4336 4337 if (!sc->bge_link && 4338 (mii->mii_media_status & IFM_ACTIVE) && 4339 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4340 sc->bge_link++; 4341 if (bootverbose) 4342 if_printf(ifp, "link UP\n"); 4343 } else if (sc->bge_link && 4344 (!(mii->mii_media_status & IFM_ACTIVE) || 4345 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4346 sc->bge_link = 0; 4347 if (bootverbose) 4348 if_printf(ifp, "link DOWN\n"); 4349 } 4350 4351 /* Clear the interrupt. */ 4352 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT); 4353 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4354 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS); 4355 } 4356 4357 static void 4358 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status) 4359 { 4360 struct ifnet *ifp = &sc->arpcom.ac_if; 4361 4362 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE) 4363 4364 /* 4365 * Sometimes PCS encoding errors are detected in 4366 * TBI mode (on fiber NICs), and for some reason 4367 * the chip will signal them as link changes. 4368 * If we get a link change event, but the 'PCS 4369 * encoding error' bit in the MAC status register 4370 * is set, don't bother doing a link check. 4371 * This avoids spurious "gigabit link up" messages 4372 * that sometimes appear on fiber NICs during 4373 * periods of heavy traffic. 4374 */ 4375 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4376 if (!sc->bge_link) { 4377 sc->bge_link++; 4378 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4379 BGE_CLRBIT(sc, BGE_MAC_MODE, 4380 BGE_MACMODE_TBI_SEND_CFGS); 4381 } 4382 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4383 4384 if (bootverbose) 4385 if_printf(ifp, "link UP\n"); 4386 4387 ifp->if_link_state = LINK_STATE_UP; 4388 if_link_state_change(ifp); 4389 } 4390 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) { 4391 if (sc->bge_link) { 4392 sc->bge_link = 0; 4393 4394 if (bootverbose) 4395 if_printf(ifp, "link DOWN\n"); 4396 4397 ifp->if_link_state = LINK_STATE_DOWN; 4398 if_link_state_change(ifp); 4399 } 4400 } 4401 4402 #undef PCS_ENCODE_ERR 4403 4404 /* Clear the attention. */ 4405 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4406 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4407 BGE_MACSTAT_LINK_CHANGED); 4408 } 4409 4410 static void 4411 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused) 4412 { 4413 struct ifnet *ifp = &sc->arpcom.ac_if; 4414 struct mii_data *mii = device_get_softc(sc->bge_miibus); 4415 4416 mii_pollstat(mii); 4417 bge_miibus_statchg(sc->bge_dev); 4418 4419 if (bootverbose) { 4420 if (sc->bge_link) 4421 if_printf(ifp, "link UP\n"); 4422 else 4423 if_printf(ifp, "link DOWN\n"); 4424 } 4425 4426 /* Clear the attention. */ 4427 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4428 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4429 BGE_MACSTAT_LINK_CHANGED); 4430 } 4431 4432 static void 4433 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused) 4434 { 4435 struct ifnet *ifp = &sc->arpcom.ac_if; 4436 struct mii_data *mii = device_get_softc(sc->bge_miibus); 4437 4438 mii_pollstat(mii); 4439 4440 if (!sc->bge_link && 4441 (mii->mii_media_status & IFM_ACTIVE) && 4442 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4443 sc->bge_link++; 4444 if (bootverbose) 4445 if_printf(ifp, "link UP\n"); 4446 } else if (sc->bge_link && 4447 (!(mii->mii_media_status & IFM_ACTIVE) || 4448 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4449 sc->bge_link = 0; 4450 if (bootverbose) 4451 if_printf(ifp, "link DOWN\n"); 4452 } 4453 4454 /* Clear the attention. */ 4455 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4456 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4457 BGE_MACSTAT_LINK_CHANGED); 4458 } 4459 4460 static int 4461 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS) 4462 { 4463 struct bge_softc *sc = arg1; 4464 4465 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4466 &sc->bge_rx_coal_ticks, 4467 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX, 4468 BGE_RX_COAL_TICKS_CHG); 4469 } 4470 4471 static int 4472 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS) 4473 { 4474 struct bge_softc *sc = arg1; 4475 4476 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4477 &sc->bge_tx_coal_ticks, 4478 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX, 4479 BGE_TX_COAL_TICKS_CHG); 4480 } 4481 4482 static int 4483 bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS) 4484 { 4485 struct bge_softc *sc = arg1; 4486 4487 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4488 &sc->bge_rx_coal_bds, 4489 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX, 4490 BGE_RX_COAL_BDS_CHG); 4491 } 4492 4493 static int 4494 bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS) 4495 { 4496 struct bge_softc *sc = arg1; 4497 4498 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4499 &sc->bge_tx_coal_bds, 4500 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX, 4501 BGE_TX_COAL_BDS_CHG); 4502 } 4503 4504 static int 4505 bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS) 4506 { 4507 struct bge_softc *sc = arg1; 4508 4509 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4510 &sc->bge_rx_coal_ticks_int, 4511 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX, 4512 BGE_RX_COAL_TICKS_INT_CHG); 4513 } 4514 4515 static int 4516 bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS) 4517 { 4518 struct bge_softc *sc = arg1; 4519 4520 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4521 &sc->bge_tx_coal_ticks_int, 4522 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX, 4523 BGE_TX_COAL_TICKS_INT_CHG); 4524 } 4525 4526 static int 4527 bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS) 4528 { 4529 struct bge_softc *sc = arg1; 4530 4531 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4532 &sc->bge_rx_coal_bds_int, 4533 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX, 4534 BGE_RX_COAL_BDS_INT_CHG); 4535 } 4536 4537 static int 4538 bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS) 4539 { 4540 struct bge_softc *sc = arg1; 4541 4542 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4543 &sc->bge_tx_coal_bds_int, 4544 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX, 4545 BGE_TX_COAL_BDS_INT_CHG); 4546 } 4547 4548 static int 4549 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal, 4550 int coal_min, int coal_max, uint32_t coal_chg_mask) 4551 { 4552 struct bge_softc *sc = arg1; 4553 struct ifnet *ifp = &sc->arpcom.ac_if; 4554 int error = 0, v; 4555 4556 lwkt_serialize_enter(ifp->if_serializer); 4557 4558 v = *coal; 4559 error = sysctl_handle_int(oidp, &v, 0, req); 4560 if (!error && req->newptr != NULL) { 4561 if (v < coal_min || v > coal_max) { 4562 error = EINVAL; 4563 } else { 4564 *coal = v; 4565 sc->bge_coal_chg |= coal_chg_mask; 4566 } 4567 } 4568 4569 lwkt_serialize_exit(ifp->if_serializer); 4570 return error; 4571 } 4572 4573 static void 4574 bge_coal_change(struct bge_softc *sc) 4575 { 4576 struct ifnet *ifp = &sc->arpcom.ac_if; 4577 uint32_t val; 4578 4579 ASSERT_SERIALIZED(ifp->if_serializer); 4580 4581 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) { 4582 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, 4583 sc->bge_rx_coal_ticks); 4584 DELAY(10); 4585 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4586 4587 if (bootverbose) { 4588 if_printf(ifp, "rx_coal_ticks -> %u\n", 4589 sc->bge_rx_coal_ticks); 4590 } 4591 } 4592 4593 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) { 4594 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, 4595 sc->bge_tx_coal_ticks); 4596 DELAY(10); 4597 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS); 4598 4599 if (bootverbose) { 4600 if_printf(ifp, "tx_coal_ticks -> %u\n", 4601 sc->bge_tx_coal_ticks); 4602 } 4603 } 4604 4605 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_CHG) { 4606 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, 4607 sc->bge_rx_coal_bds); 4608 DELAY(10); 4609 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4610 4611 if (bootverbose) { 4612 if_printf(ifp, "rx_coal_bds -> %u\n", 4613 sc->bge_rx_coal_bds); 4614 } 4615 } 4616 4617 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_CHG) { 4618 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, 4619 sc->bge_tx_coal_bds); 4620 DELAY(10); 4621 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS); 4622 4623 if (bootverbose) { 4624 if_printf(ifp, "tx_max_coal_bds -> %u\n", 4625 sc->bge_tx_coal_bds); 4626 } 4627 } 4628 4629 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_INT_CHG) { 4630 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 4631 sc->bge_rx_coal_ticks_int); 4632 DELAY(10); 4633 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS_INT); 4634 4635 if (bootverbose) { 4636 if_printf(ifp, "rx_coal_ticks_int -> %u\n", 4637 sc->bge_rx_coal_ticks_int); 4638 } 4639 } 4640 4641 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_INT_CHG) { 4642 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 4643 sc->bge_tx_coal_ticks_int); 4644 DELAY(10); 4645 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS_INT); 4646 4647 if (bootverbose) { 4648 if_printf(ifp, "tx_coal_ticks_int -> %u\n", 4649 sc->bge_tx_coal_ticks_int); 4650 } 4651 } 4652 4653 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_INT_CHG) { 4654 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 4655 sc->bge_rx_coal_bds_int); 4656 DELAY(10); 4657 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT); 4658 4659 if (bootverbose) { 4660 if_printf(ifp, "rx_coal_bds_int -> %u\n", 4661 sc->bge_rx_coal_bds_int); 4662 } 4663 } 4664 4665 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_INT_CHG) { 4666 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 4667 sc->bge_tx_coal_bds_int); 4668 DELAY(10); 4669 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT); 4670 4671 if (bootverbose) { 4672 if_printf(ifp, "tx_coal_bds_int -> %u\n", 4673 sc->bge_tx_coal_bds_int); 4674 } 4675 } 4676 4677 sc->bge_coal_chg = 0; 4678 } 4679 4680 static void 4681 bge_enable_intr(struct bge_softc *sc) 4682 { 4683 struct ifnet *ifp = &sc->arpcom.ac_if; 4684 4685 lwkt_serialize_handler_enable(ifp->if_serializer); 4686 4687 /* 4688 * Enable interrupt. 4689 */ 4690 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 4691 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 4692 /* XXX Linux driver */ 4693 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 4694 } 4695 4696 /* 4697 * Unmask the interrupt when we stop polling. 4698 */ 4699 PCI_CLRBIT(sc->bge_dev, BGE_PCI_MISC_CTL, 4700 BGE_PCIMISCCTL_MASK_PCI_INTR, 4); 4701 4702 /* 4703 * Trigger another interrupt, since above writing 4704 * to interrupt mailbox0 may acknowledge pending 4705 * interrupt. 4706 */ 4707 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4708 } 4709 4710 static void 4711 bge_disable_intr(struct bge_softc *sc) 4712 { 4713 struct ifnet *ifp = &sc->arpcom.ac_if; 4714 4715 /* 4716 * Mask the interrupt when we start polling. 4717 */ 4718 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, 4719 BGE_PCIMISCCTL_MASK_PCI_INTR, 4); 4720 4721 /* 4722 * Acknowledge possible asserted interrupt. 4723 */ 4724 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4725 4726 lwkt_serialize_handler_disable(ifp->if_serializer); 4727 } 4728 4729 static int 4730 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4731 { 4732 uint32_t mac_addr; 4733 int ret = 1; 4734 4735 mac_addr = bge_readmem_ind(sc, 0x0c14); 4736 if ((mac_addr >> 16) == 0x484b) { 4737 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4738 ether_addr[1] = (uint8_t)mac_addr; 4739 mac_addr = bge_readmem_ind(sc, 0x0c18); 4740 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4741 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4742 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4743 ether_addr[5] = (uint8_t)mac_addr; 4744 ret = 0; 4745 } 4746 return ret; 4747 } 4748 4749 static int 4750 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4751 { 4752 int mac_offset = BGE_EE_MAC_OFFSET; 4753 4754 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4755 mac_offset = BGE_EE_MAC_OFFSET_5906; 4756 4757 return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN); 4758 } 4759 4760 static int 4761 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4762 { 4763 if (sc->bge_flags & BGE_FLAG_NO_EEPROM) 4764 return 1; 4765 4766 return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4767 ETHER_ADDR_LEN); 4768 } 4769 4770 static int 4771 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4772 { 4773 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4774 /* NOTE: Order is critical */ 4775 bge_get_eaddr_mem, 4776 bge_get_eaddr_nvram, 4777 bge_get_eaddr_eeprom, 4778 NULL 4779 }; 4780 const bge_eaddr_fcn_t *func; 4781 4782 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4783 if ((*func)(sc, eaddr) == 0) 4784 break; 4785 } 4786 return (*func == NULL ? ENXIO : 0); 4787 } 4788 4789 /* 4790 * NOTE: 'm' is not freed upon failure 4791 */ 4792 struct mbuf * 4793 bge_defrag_shortdma(struct mbuf *m) 4794 { 4795 struct mbuf *n; 4796 int found; 4797 4798 /* 4799 * If device receive two back-to-back send BDs with less than 4800 * or equal to 8 total bytes then the device may hang. The two 4801 * back-to-back send BDs must in the same frame for this failure 4802 * to occur. Scan mbuf chains and see whether two back-to-back 4803 * send BDs are there. If this is the case, allocate new mbuf 4804 * and copy the frame to workaround the silicon bug. 4805 */ 4806 for (n = m, found = 0; n != NULL; n = n->m_next) { 4807 if (n->m_len < 8) { 4808 found++; 4809 if (found > 1) 4810 break; 4811 continue; 4812 } 4813 found = 0; 4814 } 4815 4816 if (found > 1) 4817 n = m_defrag(m, MB_DONTWAIT); 4818 else 4819 n = m; 4820 return n; 4821 } 4822 4823 static void 4824 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 4825 { 4826 int i; 4827 4828 BGE_CLRBIT(sc, reg, bit); 4829 for (i = 0; i < BGE_TIMEOUT; i++) { 4830 if ((CSR_READ_4(sc, reg) & bit) == 0) 4831 return; 4832 DELAY(100); 4833 } 4834 } 4835 4836 static void 4837 bge_link_poll(struct bge_softc *sc) 4838 { 4839 uint32_t status; 4840 4841 status = CSR_READ_4(sc, BGE_MAC_STS); 4842 if ((status & sc->bge_link_chg) || sc->bge_link_evt) { 4843 sc->bge_link_evt = 0; 4844 sc->bge_link_upd(sc, status); 4845 } 4846 } 4847 4848 static void 4849 bge_enable_msi(struct bge_softc *sc) 4850 { 4851 uint32_t msi_mode; 4852 4853 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE); 4854 msi_mode |= BGE_MSIMODE_ENABLE; 4855 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 4856 /* 4857 * According to all of the datasheets that are publicly 4858 * available, bit 5 of the MSI_MODE is defined to be 4859 * "MSI FIFO Underrun Attn" for BCM5755+ and BCM5906, on 4860 * which "oneshot MSI" is enabled. However, it is always 4861 * safe to clear it here. 4862 */ 4863 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE; 4864 } 4865 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode); 4866 } 4867 4868 static int 4869 bge_setup_tso(struct bge_softc *sc, struct mbuf **mp, 4870 uint16_t *mss0, uint16_t *flags0) 4871 { 4872 struct mbuf *m; 4873 struct ip *ip; 4874 struct tcphdr *th; 4875 int thoff, iphlen, hoff, hlen; 4876 uint16_t flags, mss; 4877 4878 m = *mp; 4879 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 4880 4881 hoff = m->m_pkthdr.csum_lhlen; 4882 iphlen = m->m_pkthdr.csum_iphlen; 4883 thoff = m->m_pkthdr.csum_thlen; 4884 4885 KASSERT(hoff > 0, ("invalid ether header len")); 4886 KASSERT(iphlen > 0, ("invalid ip header len")); 4887 KASSERT(thoff > 0, ("invalid tcp header len")); 4888 4889 if (__predict_false(m->m_len < hoff + iphlen + thoff)) { 4890 m = m_pullup(m, hoff + iphlen + thoff); 4891 if (m == NULL) { 4892 *mp = NULL; 4893 return ENOBUFS; 4894 } 4895 *mp = m; 4896 } 4897 ip = mtodoff(m, struct ip *, hoff); 4898 th = mtodoff(m, struct tcphdr *, hoff + iphlen); 4899 4900 mss = m->m_pkthdr.tso_segsz; 4901 flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA; 4902 4903 ip->ip_len = htons(mss + iphlen + thoff); 4904 th->th_sum = 0; 4905 4906 hlen = (iphlen + thoff) >> 2; 4907 mss |= (hlen << 11); 4908 4909 *mss0 = mss; 4910 *flags0 = flags; 4911 4912 return 0; 4913 } 4914