1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $ 34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.14 2004/02/10 21:14:14 hmp Exp $ 35 * 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Engineer, Wind River Systems 43 */ 44 45 /* 46 * The Broadcom BCM5700 is based on technology originally developed by 47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 51 * frames, highly configurable RX filtering, and 16 RX and TX queues 52 * (which, along with RX filter rules, can be used for QOS applications). 53 * Other features, such as TCP segmentation, may be available as part 54 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 55 * firmware images can be stored in hardware and need not be compiled 56 * into the driver. 57 * 58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 60 * 61 * The BCM5701 is a single-chip solution incorporating both the BCM5700 62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 63 * does not support external SSRAM. 64 * 65 * Broadcom also produces a variation of the BCM5700 under the "Altima" 66 * brand name, which is functionally similar but lacks PCI-X support. 67 * 68 * Without external SSRAM, you can only have at most 4 TX rings, 69 * and the use of the mini RX ring is disabled. This seems to imply 70 * that these features are simply not available on the BCM5701. As a 71 * result, this driver does not implement any support for the mini RX 72 * ring. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/sockio.h> 78 #include <sys/mbuf.h> 79 #include <sys/malloc.h> 80 #include <sys/kernel.h> 81 #include <sys/socket.h> 82 #include <sys/queue.h> 83 84 #include <net/if.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #include <net/bpf.h> 91 92 #include <net/if_types.h> 93 #include <net/vlan/if_vlan_var.h> 94 95 #include <netinet/in_systm.h> 96 #include <netinet/in.h> 97 #include <netinet/ip.h> 98 99 #include <vm/vm.h> /* for vtophys */ 100 #include <vm/pmap.h> /* for vtophys */ 101 #include <machine/clock.h> /* for DELAY */ 102 #include <machine/bus_memio.h> 103 #include <machine/bus.h> 104 #include <machine/resource.h> 105 #include <sys/bus.h> 106 #include <sys/rman.h> 107 108 #include <dev/netif/mii_layer/mii.h> 109 #include <dev/netif/mii_layer/miivar.h> 110 #include <dev/netif/mii_layer/miidevs.h> 111 #include <dev/netif/mii_layer/brgphyreg.h> 112 113 #include <bus/pci/pcireg.h> 114 #include <bus/pci/pcivar.h> 115 116 #include "if_bgereg.h" 117 118 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 /* 124 * Various supported device vendors/types and their names. Note: the 125 * spec seems to indicate that the hardware still has Alteon's vendor 126 * ID burned into it, though it will always be overriden by the vendor 127 * ID in the EEPROM. Just to be safe, we cover all possibilities. 128 */ 129 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 130 131 static struct bge_type bge_devs[] = { 132 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 133 "Broadcom BCM5700 Gigabit Ethernet" }, 134 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 135 "Broadcom BCM5701 Gigabit Ethernet" }, 136 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 137 "Broadcom BCM5700 Gigabit Ethernet" }, 138 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 139 "Broadcom BCM5701 Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702, 141 "Broadcom BCM5702 Gigabit Ethernet" }, 142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 143 "Broadcom BCM5702X Gigabit Ethernet" }, 144 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703, 145 "Broadcom BCM5703 Gigabit Ethernet" }, 146 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 147 "Broadcom BCM5703X Gigabit Ethernet" }, 148 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C, 149 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S, 151 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705, 153 "Broadcom BCM5705 Gigabit Ethernet" }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M, 155 "Broadcom BCM5705M Gigabit Ethernet" }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT, 157 "Broadcom BCM5705M Gigabit Ethernet" }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782, 159 "Broadcom BCM5782 Gigabit Ethernet" }, 160 { SK_VENDORID, SK_DEVICEID_ALTIMA, 161 "SysKonnect Gigabit Ethernet" }, 162 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 163 "Altima AC1000 Gigabit Ethernet" }, 164 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002, 165 "Altima AC1002 Gigabit Ethernet" }, 166 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 167 "Altima AC9100 Gigabit Ethernet" }, 168 { 0, 0, NULL } 169 }; 170 171 static int bge_probe (device_t); 172 static int bge_attach (device_t); 173 static int bge_detach (device_t); 174 static void bge_release_resources 175 (struct bge_softc *); 176 static void bge_txeof (struct bge_softc *); 177 static void bge_rxeof (struct bge_softc *); 178 179 static void bge_tick (void *); 180 static void bge_stats_update (struct bge_softc *); 181 static void bge_stats_update_regs 182 (struct bge_softc *); 183 static int bge_encap (struct bge_softc *, struct mbuf *, 184 u_int32_t *); 185 186 static void bge_intr (void *); 187 static void bge_start (struct ifnet *); 188 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 189 static void bge_init (void *); 190 static void bge_stop (struct bge_softc *); 191 static void bge_watchdog (struct ifnet *); 192 static void bge_shutdown (device_t); 193 static int bge_ifmedia_upd (struct ifnet *); 194 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 195 196 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, 197 int, u_int8_t *); 198 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 199 200 static u_int32_t bge_crc (caddr_t); 201 static void bge_setmulti (struct bge_softc *); 202 203 static void bge_handle_events (struct bge_softc *); 204 static int bge_alloc_jumbo_mem (struct bge_softc *); 205 static void bge_free_jumbo_mem (struct bge_softc *); 206 static void *bge_jalloc (struct bge_softc *); 207 static void bge_jfree (caddr_t, u_int); 208 static void bge_jref (caddr_t, u_int); 209 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 210 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 211 static int bge_init_rx_ring_std (struct bge_softc *); 212 static void bge_free_rx_ring_std (struct bge_softc *); 213 static int bge_init_rx_ring_jumbo (struct bge_softc *); 214 static void bge_free_rx_ring_jumbo (struct bge_softc *); 215 static void bge_free_tx_ring (struct bge_softc *); 216 static int bge_init_tx_ring (struct bge_softc *); 217 218 static int bge_chipinit (struct bge_softc *); 219 static int bge_blockinit (struct bge_softc *); 220 221 #ifdef notdef 222 static u_int8_t bge_vpd_readbyte (struct bge_softc *, int); 223 static void bge_vpd_read_res (struct bge_softc *, 224 struct vpd_res *, int); 225 static void bge_vpd_read (struct bge_softc *); 226 #endif 227 228 static u_int32_t bge_readmem_ind 229 (struct bge_softc *, int); 230 static void bge_writemem_ind (struct bge_softc *, int, int); 231 #ifdef notdef 232 static u_int32_t bge_readreg_ind 233 (struct bge_softc *, int); 234 #endif 235 static void bge_writereg_ind (struct bge_softc *, int, int); 236 237 static int bge_miibus_readreg (device_t, int, int); 238 static int bge_miibus_writereg (device_t, int, int, int); 239 static void bge_miibus_statchg (device_t); 240 241 static void bge_reset (struct bge_softc *); 242 243 static device_method_t bge_methods[] = { 244 /* Device interface */ 245 DEVMETHOD(device_probe, bge_probe), 246 DEVMETHOD(device_attach, bge_attach), 247 DEVMETHOD(device_detach, bge_detach), 248 DEVMETHOD(device_shutdown, bge_shutdown), 249 250 /* bus interface */ 251 DEVMETHOD(bus_print_child, bus_generic_print_child), 252 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 253 254 /* MII interface */ 255 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 256 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 257 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 258 259 { 0, 0 } 260 }; 261 262 static driver_t bge_driver = { 263 "bge", 264 bge_methods, 265 sizeof(struct bge_softc) 266 }; 267 268 static devclass_t bge_devclass; 269 270 DECLARE_DUMMY_MODULE(if_bge); 271 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 272 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 273 274 static u_int32_t 275 bge_readmem_ind(sc, off) 276 struct bge_softc *sc; 277 int off; 278 { 279 device_t dev; 280 281 dev = sc->bge_dev; 282 283 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 284 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 285 } 286 287 static void 288 bge_writemem_ind(sc, off, val) 289 struct bge_softc *sc; 290 int off, val; 291 { 292 device_t dev; 293 294 dev = sc->bge_dev; 295 296 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 297 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 298 299 return; 300 } 301 302 #ifdef notdef 303 static u_int32_t 304 bge_readreg_ind(sc, off) 305 struct bge_softc *sc; 306 int off; 307 { 308 device_t dev; 309 310 dev = sc->bge_dev; 311 312 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 313 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 314 } 315 #endif 316 317 static void 318 bge_writereg_ind(sc, off, val) 319 struct bge_softc *sc; 320 int off, val; 321 { 322 device_t dev; 323 324 dev = sc->bge_dev; 325 326 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 327 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 328 329 return; 330 } 331 332 #ifdef notdef 333 static u_int8_t 334 bge_vpd_readbyte(sc, addr) 335 struct bge_softc *sc; 336 int addr; 337 { 338 int i; 339 device_t dev; 340 u_int32_t val; 341 342 dev = sc->bge_dev; 343 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 344 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 345 DELAY(10); 346 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 347 break; 348 } 349 350 if (i == BGE_TIMEOUT) { 351 printf("bge%d: VPD read timed out\n", sc->bge_unit); 352 return(0); 353 } 354 355 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 356 357 return((val >> ((addr % 4) * 8)) & 0xFF); 358 } 359 360 static void 361 bge_vpd_read_res(sc, res, addr) 362 struct bge_softc *sc; 363 struct vpd_res *res; 364 int addr; 365 { 366 int i; 367 u_int8_t *ptr; 368 369 ptr = (u_int8_t *)res; 370 for (i = 0; i < sizeof(struct vpd_res); i++) 371 ptr[i] = bge_vpd_readbyte(sc, i + addr); 372 373 return; 374 } 375 376 static void 377 bge_vpd_read(sc) 378 struct bge_softc *sc; 379 { 380 int pos = 0, i; 381 struct vpd_res res; 382 383 if (sc->bge_vpd_prodname != NULL) 384 free(sc->bge_vpd_prodname, M_DEVBUF); 385 if (sc->bge_vpd_readonly != NULL) 386 free(sc->bge_vpd_readonly, M_DEVBUF); 387 sc->bge_vpd_prodname = NULL; 388 sc->bge_vpd_readonly = NULL; 389 390 bge_vpd_read_res(sc, &res, pos); 391 392 if (res.vr_id != VPD_RES_ID) { 393 printf("bge%d: bad VPD resource id: expected %x got %x\n", 394 sc->bge_unit, VPD_RES_ID, res.vr_id); 395 return; 396 } 397 398 pos += sizeof(res); 399 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 400 for (i = 0; i < res.vr_len; i++) 401 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 402 sc->bge_vpd_prodname[i] = '\0'; 403 pos += i; 404 405 bge_vpd_read_res(sc, &res, pos); 406 407 if (res.vr_id != VPD_RES_READ) { 408 printf("bge%d: bad VPD resource id: expected %x got %x\n", 409 sc->bge_unit, VPD_RES_READ, res.vr_id); 410 return; 411 } 412 413 pos += sizeof(res); 414 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 415 for (i = 0; i < res.vr_len + 1; i++) 416 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 417 418 return; 419 } 420 #endif 421 422 /* 423 * Read a byte of data stored in the EEPROM at address 'addr.' The 424 * BCM570x supports both the traditional bitbang interface and an 425 * auto access interface for reading the EEPROM. We use the auto 426 * access method. 427 */ 428 static u_int8_t 429 bge_eeprom_getbyte(sc, addr, dest) 430 struct bge_softc *sc; 431 int addr; 432 u_int8_t *dest; 433 { 434 int i; 435 u_int32_t byte = 0; 436 437 /* 438 * Enable use of auto EEPROM access so we can avoid 439 * having to use the bitbang method. 440 */ 441 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 442 443 /* Reset the EEPROM, load the clock period. */ 444 CSR_WRITE_4(sc, BGE_EE_ADDR, 445 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 446 DELAY(20); 447 448 /* Issue the read EEPROM command. */ 449 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 450 451 /* Wait for completion */ 452 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 453 DELAY(10); 454 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 455 break; 456 } 457 458 if (i == BGE_TIMEOUT) { 459 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 460 return(0); 461 } 462 463 /* Get result. */ 464 byte = CSR_READ_4(sc, BGE_EE_DATA); 465 466 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 467 468 return(0); 469 } 470 471 /* 472 * Read a sequence of bytes from the EEPROM. 473 */ 474 static int 475 bge_read_eeprom(sc, dest, off, cnt) 476 struct bge_softc *sc; 477 caddr_t dest; 478 int off; 479 int cnt; 480 { 481 int err = 0, i; 482 u_int8_t byte = 0; 483 484 for (i = 0; i < cnt; i++) { 485 err = bge_eeprom_getbyte(sc, off + i, &byte); 486 if (err) 487 break; 488 *(dest + i) = byte; 489 } 490 491 return(err ? 1 : 0); 492 } 493 494 static int 495 bge_miibus_readreg(dev, phy, reg) 496 device_t dev; 497 int phy, reg; 498 { 499 struct bge_softc *sc; 500 struct ifnet *ifp; 501 u_int32_t val, autopoll; 502 int i; 503 504 sc = device_get_softc(dev); 505 ifp = &sc->arpcom.ac_if; 506 507 /* 508 * Broadcom's own driver always assumes the internal 509 * PHY is at GMII address 1. On some chips, the PHY responds 510 * to accesses at all addresses, which could cause us to 511 * bogusly attach the PHY 32 times at probe type. Always 512 * restricting the lookup to address 1 is simpler than 513 * trying to figure out which chips revisions should be 514 * special-cased. 515 */ 516 if (phy != 1) 517 return(0); 518 519 /* Reading with autopolling on may trigger PCI errors */ 520 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 521 if (autopoll & BGE_MIMODE_AUTOPOLL) { 522 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 523 DELAY(40); 524 } 525 526 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 527 BGE_MIPHY(phy)|BGE_MIREG(reg)); 528 529 for (i = 0; i < BGE_TIMEOUT; i++) { 530 val = CSR_READ_4(sc, BGE_MI_COMM); 531 if (!(val & BGE_MICOMM_BUSY)) 532 break; 533 } 534 535 if (i == BGE_TIMEOUT) { 536 printf("bge%d: PHY read timed out\n", sc->bge_unit); 537 val = 0; 538 goto done; 539 } 540 541 val = CSR_READ_4(sc, BGE_MI_COMM); 542 543 done: 544 if (autopoll & BGE_MIMODE_AUTOPOLL) { 545 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 546 DELAY(40); 547 } 548 549 if (val & BGE_MICOMM_READFAIL) 550 return(0); 551 552 return(val & 0xFFFF); 553 } 554 555 static int 556 bge_miibus_writereg(dev, phy, reg, val) 557 device_t dev; 558 int phy, reg, val; 559 { 560 struct bge_softc *sc; 561 u_int32_t autopoll; 562 int i; 563 564 sc = device_get_softc(dev); 565 566 /* Reading with autopolling on may trigger PCI errors */ 567 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 568 if (autopoll & BGE_MIMODE_AUTOPOLL) { 569 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 570 DELAY(40); 571 } 572 573 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 574 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 575 576 for (i = 0; i < BGE_TIMEOUT; i++) { 577 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 578 break; 579 } 580 581 if (autopoll & BGE_MIMODE_AUTOPOLL) { 582 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 583 DELAY(40); 584 } 585 586 if (i == BGE_TIMEOUT) { 587 printf("bge%d: PHY read timed out\n", sc->bge_unit); 588 return(0); 589 } 590 591 return(0); 592 } 593 594 static void 595 bge_miibus_statchg(dev) 596 device_t dev; 597 { 598 struct bge_softc *sc; 599 struct mii_data *mii; 600 601 sc = device_get_softc(dev); 602 mii = device_get_softc(sc->bge_miibus); 603 604 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 605 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) { 606 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 607 } else { 608 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 609 } 610 611 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 612 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 613 } else { 614 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 615 } 616 617 return; 618 } 619 620 /* 621 * Handle events that have triggered interrupts. 622 */ 623 static void 624 bge_handle_events(sc) 625 struct bge_softc *sc; 626 { 627 628 return; 629 } 630 631 /* 632 * Memory management for jumbo frames. 633 */ 634 635 static int 636 bge_alloc_jumbo_mem(sc) 637 struct bge_softc *sc; 638 { 639 caddr_t ptr; 640 int i; 641 struct bge_jpool_entry *entry; 642 643 /* Grab a big chunk o' storage. */ 644 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 645 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 646 647 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 648 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 649 return(ENOBUFS); 650 } 651 652 SLIST_INIT(&sc->bge_jfree_listhead); 653 SLIST_INIT(&sc->bge_jinuse_listhead); 654 655 /* 656 * Now divide it up into 9K pieces and save the addresses 657 * in an array. Note that we play an evil trick here by using 658 * the first few bytes in the buffer to hold the the address 659 * of the softc structure for this interface. This is because 660 * bge_jfree() needs it, but it is called by the mbuf management 661 * code which will not pass it to us explicitly. 662 */ 663 ptr = sc->bge_cdata.bge_jumbo_buf; 664 for (i = 0; i < BGE_JSLOTS; i++) { 665 u_int64_t **aptr; 666 aptr = (u_int64_t **)ptr; 667 aptr[0] = (u_int64_t *)sc; 668 ptr += sizeof(u_int64_t); 669 sc->bge_cdata.bge_jslots[i].bge_buf = ptr; 670 sc->bge_cdata.bge_jslots[i].bge_inuse = 0; 671 ptr += (BGE_JLEN - sizeof(u_int64_t)); 672 entry = malloc(sizeof(struct bge_jpool_entry), 673 M_DEVBUF, M_NOWAIT); 674 if (entry == NULL) { 675 contigfree(sc->bge_cdata.bge_jumbo_buf, 676 BGE_JMEM, M_DEVBUF); 677 sc->bge_cdata.bge_jumbo_buf = NULL; 678 printf("bge%d: no memory for jumbo " 679 "buffer queue!\n", sc->bge_unit); 680 return(ENOBUFS); 681 } 682 entry->slot = i; 683 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 684 entry, jpool_entries); 685 } 686 687 return(0); 688 } 689 690 static void 691 bge_free_jumbo_mem(sc) 692 struct bge_softc *sc; 693 { 694 int i; 695 struct bge_jpool_entry *entry; 696 697 for (i = 0; i < BGE_JSLOTS; i++) { 698 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 699 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 700 free(entry, M_DEVBUF); 701 } 702 703 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 704 705 return; 706 } 707 708 /* 709 * Allocate a jumbo buffer. 710 */ 711 static void * 712 bge_jalloc(sc) 713 struct bge_softc *sc; 714 { 715 struct bge_jpool_entry *entry; 716 717 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 718 719 if (entry == NULL) { 720 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 721 return(NULL); 722 } 723 724 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 725 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 726 sc->bge_cdata.bge_jslots[entry->slot].bge_inuse = 1; 727 return(sc->bge_cdata.bge_jslots[entry->slot].bge_buf); 728 } 729 730 /* 731 * Adjust usage count on a jumbo buffer. 732 */ 733 static void 734 bge_jref(buf, size) 735 caddr_t buf; 736 u_int size; 737 { 738 struct bge_softc *sc; 739 u_int64_t **aptr; 740 int i; 741 742 /* Extract the softc struct pointer. */ 743 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 744 sc = (struct bge_softc *)(aptr[0]); 745 746 if (sc == NULL) 747 panic("bge_jref: can't find softc pointer!"); 748 749 if (size != BGE_JUMBO_FRAMELEN) 750 panic("bge_jref: adjusting refcount of buf of wrong size!"); 751 752 /* calculate the slot this buffer belongs to */ 753 754 i = ((vm_offset_t)aptr 755 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 756 757 if ((i < 0) || (i >= BGE_JSLOTS)) 758 panic("bge_jref: asked to reference buffer " 759 "that we don't manage!"); 760 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0) 761 panic("bge_jref: buffer already free!"); 762 else 763 sc->bge_cdata.bge_jslots[i].bge_inuse++; 764 765 return; 766 } 767 768 /* 769 * Release a jumbo buffer. 770 */ 771 static void 772 bge_jfree(buf, size) 773 caddr_t buf; 774 u_int size; 775 { 776 struct bge_softc *sc; 777 u_int64_t **aptr; 778 int i; 779 struct bge_jpool_entry *entry; 780 781 /* Extract the softc struct pointer. */ 782 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 783 sc = (struct bge_softc *)(aptr[0]); 784 785 if (sc == NULL) 786 panic("bge_jfree: can't find softc pointer!"); 787 788 if (size != BGE_JUMBO_FRAMELEN) 789 panic("bge_jfree: freeing buffer of wrong size!"); 790 791 /* calculate the slot this buffer belongs to */ 792 793 i = ((vm_offset_t)aptr 794 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 795 796 if ((i < 0) || (i >= BGE_JSLOTS)) 797 panic("bge_jfree: asked to free buffer that we don't manage!"); 798 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0) 799 panic("bge_jfree: buffer already free!"); 800 else { 801 sc->bge_cdata.bge_jslots[i].bge_inuse--; 802 if(sc->bge_cdata.bge_jslots[i].bge_inuse == 0) { 803 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 804 if (entry == NULL) 805 panic("bge_jfree: buffer not in use!"); 806 entry->slot = i; 807 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, 808 jpool_entries); 809 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 810 entry, jpool_entries); 811 } 812 } 813 814 return; 815 } 816 817 818 /* 819 * Intialize a standard receive ring descriptor. 820 */ 821 static int 822 bge_newbuf_std(sc, i, m) 823 struct bge_softc *sc; 824 int i; 825 struct mbuf *m; 826 { 827 struct mbuf *m_new = NULL; 828 struct bge_rx_bd *r; 829 830 if (m == NULL) { 831 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 832 if (m_new == NULL) { 833 return(ENOBUFS); 834 } 835 836 MCLGET(m_new, M_DONTWAIT); 837 if (!(m_new->m_flags & M_EXT)) { 838 m_freem(m_new); 839 return(ENOBUFS); 840 } 841 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 842 } else { 843 m_new = m; 844 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 845 m_new->m_data = m_new->m_ext.ext_buf; 846 } 847 848 if (!sc->bge_rx_alignment_bug) 849 m_adj(m_new, ETHER_ALIGN); 850 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 851 r = &sc->bge_rdata->bge_rx_std_ring[i]; 852 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 853 r->bge_flags = BGE_RXBDFLAG_END; 854 r->bge_len = m_new->m_len; 855 r->bge_idx = i; 856 857 return(0); 858 } 859 860 /* 861 * Initialize a jumbo receive ring descriptor. This allocates 862 * a jumbo buffer from the pool managed internally by the driver. 863 */ 864 static int 865 bge_newbuf_jumbo(sc, i, m) 866 struct bge_softc *sc; 867 int i; 868 struct mbuf *m; 869 { 870 struct mbuf *m_new = NULL; 871 struct bge_rx_bd *r; 872 873 if (m == NULL) { 874 caddr_t *buf = NULL; 875 876 /* Allocate the mbuf. */ 877 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 878 if (m_new == NULL) { 879 return(ENOBUFS); 880 } 881 882 /* Allocate the jumbo buffer */ 883 buf = bge_jalloc(sc); 884 if (buf == NULL) { 885 m_freem(m_new); 886 printf("bge%d: jumbo allocation failed " 887 "-- packet dropped!\n", sc->bge_unit); 888 return(ENOBUFS); 889 } 890 891 /* Attach the buffer to the mbuf. */ 892 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 893 m_new->m_flags |= M_EXT; 894 m_new->m_len = m_new->m_pkthdr.len = 895 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 896 m_new->m_ext.ext_free = bge_jfree; 897 m_new->m_ext.ext_ref = bge_jref; 898 } else { 899 m_new = m; 900 m_new->m_data = m_new->m_ext.ext_buf; 901 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 902 } 903 904 if (!sc->bge_rx_alignment_bug) 905 m_adj(m_new, ETHER_ALIGN); 906 /* Set up the descriptor. */ 907 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 908 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 909 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 910 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 911 r->bge_len = m_new->m_len; 912 r->bge_idx = i; 913 914 return(0); 915 } 916 917 /* 918 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 919 * that's 1MB or memory, which is a lot. For now, we fill only the first 920 * 256 ring entries and hope that our CPU is fast enough to keep up with 921 * the NIC. 922 */ 923 static int 924 bge_init_rx_ring_std(sc) 925 struct bge_softc *sc; 926 { 927 int i; 928 929 for (i = 0; i < BGE_SSLOTS; i++) { 930 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 931 return(ENOBUFS); 932 }; 933 934 sc->bge_std = i - 1; 935 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 936 937 return(0); 938 } 939 940 static void 941 bge_free_rx_ring_std(sc) 942 struct bge_softc *sc; 943 { 944 int i; 945 946 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 947 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 948 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 949 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 950 } 951 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 952 sizeof(struct bge_rx_bd)); 953 } 954 955 return; 956 } 957 958 static int 959 bge_init_rx_ring_jumbo(sc) 960 struct bge_softc *sc; 961 { 962 int i; 963 struct bge_rcb *rcb; 964 965 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 966 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 967 return(ENOBUFS); 968 }; 969 970 sc->bge_jumbo = i - 1; 971 972 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 973 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 974 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 975 976 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 977 978 return(0); 979 } 980 981 static void 982 bge_free_rx_ring_jumbo(sc) 983 struct bge_softc *sc; 984 { 985 int i; 986 987 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 988 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 989 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 990 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 991 } 992 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 993 sizeof(struct bge_rx_bd)); 994 } 995 996 return; 997 } 998 999 static void 1000 bge_free_tx_ring(sc) 1001 struct bge_softc *sc; 1002 { 1003 int i; 1004 1005 if (sc->bge_rdata->bge_tx_ring == NULL) 1006 return; 1007 1008 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1009 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1010 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1011 sc->bge_cdata.bge_tx_chain[i] = NULL; 1012 } 1013 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 1014 sizeof(struct bge_tx_bd)); 1015 } 1016 1017 return; 1018 } 1019 1020 static int 1021 bge_init_tx_ring(sc) 1022 struct bge_softc *sc; 1023 { 1024 sc->bge_txcnt = 0; 1025 sc->bge_tx_saved_considx = 0; 1026 1027 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1028 /* 5700 b2 errata */ 1029 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1030 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1031 1032 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1033 /* 5700 b2 errata */ 1034 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1035 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1036 1037 return(0); 1038 } 1039 1040 #define BGE_POLY 0xEDB88320 1041 1042 static u_int32_t 1043 bge_crc(addr) 1044 caddr_t addr; 1045 { 1046 u_int32_t idx, bit, data, crc; 1047 1048 /* Compute CRC for the address value. */ 1049 crc = 0xFFFFFFFF; /* initial value */ 1050 1051 for (idx = 0; idx < 6; idx++) { 1052 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1053 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 1054 } 1055 1056 return(crc & 0x7F); 1057 } 1058 1059 static void 1060 bge_setmulti(sc) 1061 struct bge_softc *sc; 1062 { 1063 struct ifnet *ifp; 1064 struct ifmultiaddr *ifma; 1065 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1066 int h, i; 1067 1068 ifp = &sc->arpcom.ac_if; 1069 1070 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1071 for (i = 0; i < 4; i++) 1072 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1073 return; 1074 } 1075 1076 /* First, zot all the existing filters. */ 1077 for (i = 0; i < 4; i++) 1078 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1079 1080 /* Now program new ones. */ 1081 for (ifma = ifp->if_multiaddrs.lh_first; 1082 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1083 if (ifma->ifma_addr->sa_family != AF_LINK) 1084 continue; 1085 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1086 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1087 } 1088 1089 for (i = 0; i < 4; i++) 1090 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1091 1092 return; 1093 } 1094 1095 /* 1096 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1097 * self-test results. 1098 */ 1099 static int 1100 bge_chipinit(sc) 1101 struct bge_softc *sc; 1102 { 1103 int i; 1104 u_int32_t dma_rw_ctl; 1105 1106 /* Set endianness before we access any non-PCI registers. */ 1107 #if BYTE_ORDER == BIG_ENDIAN 1108 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1109 BGE_BIGENDIAN_INIT, 4); 1110 #else 1111 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1112 BGE_LITTLEENDIAN_INIT, 4); 1113 #endif 1114 1115 /* 1116 * Check the 'ROM failed' bit on the RX CPU to see if 1117 * self-tests passed. 1118 */ 1119 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1120 printf("bge%d: RX CPU self-diagnostics failed!\n", 1121 sc->bge_unit); 1122 return(ENODEV); 1123 } 1124 1125 /* Clear the MAC control register */ 1126 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1127 1128 /* 1129 * Clear the MAC statistics block in the NIC's 1130 * internal memory. 1131 */ 1132 for (i = BGE_STATS_BLOCK; 1133 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1134 BGE_MEMWIN_WRITE(sc, i, 0); 1135 1136 for (i = BGE_STATUS_BLOCK; 1137 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1138 BGE_MEMWIN_WRITE(sc, i, 0); 1139 1140 /* Set up the PCI DMA control register. */ 1141 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1142 BGE_PCISTATE_PCI_BUSMODE) { 1143 /* Conventional PCI bus */ 1144 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1145 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1146 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1147 (0x0F); 1148 } else { 1149 /* PCI-X bus */ 1150 /* 1151 * The 5704 uses a different encoding of read/write 1152 * watermarks. 1153 */ 1154 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1155 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1156 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1157 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1158 else 1159 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1160 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1161 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1162 (0x0F); 1163 1164 /* 1165 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1166 * for hardware bugs. 1167 */ 1168 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1169 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1170 u_int32_t tmp; 1171 1172 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1173 if (tmp == 0x6 || tmp == 0x7) 1174 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1175 } 1176 } 1177 1178 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1179 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1180 sc->bge_asicrev == BGE_ASICREV_BCM5705) 1181 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1182 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1183 1184 /* 1185 * Set up general mode register. 1186 */ 1187 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1188 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1189 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1190 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1191 1192 /* 1193 * Disable memory write invalidate. Apparently it is not supported 1194 * properly by these devices. 1195 */ 1196 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1197 1198 #ifdef __brokenalpha__ 1199 /* 1200 * Must insure that we do not cross an 8K (bytes) boundary 1201 * for DMA reads. Our highest limit is 1K bytes. This is a 1202 * restriction on some ALPHA platforms with early revision 1203 * 21174 PCI chipsets, such as the AlphaPC 164lx 1204 */ 1205 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1206 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1207 #endif 1208 1209 /* Set the timer prescaler (always 66Mhz) */ 1210 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1211 1212 return(0); 1213 } 1214 1215 static int 1216 bge_blockinit(sc) 1217 struct bge_softc *sc; 1218 { 1219 struct bge_rcb *rcb; 1220 volatile struct bge_rcb *vrcb; 1221 int i; 1222 1223 /* 1224 * Initialize the memory window pointer register so that 1225 * we can access the first 32K of internal NIC RAM. This will 1226 * allow us to set up the TX send ring RCBs and the RX return 1227 * ring RCBs, plus other things which live in NIC memory. 1228 */ 1229 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1230 1231 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1232 1233 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1234 /* Configure mbuf memory pool */ 1235 if (sc->bge_extram) { 1236 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1237 BGE_EXT_SSRAM); 1238 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1239 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1240 else 1241 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1242 } else { 1243 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1244 BGE_BUFFPOOL_1); 1245 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1246 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1247 else 1248 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1249 } 1250 1251 /* Configure DMA resource pool */ 1252 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1253 BGE_DMA_DESCRIPTORS); 1254 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1255 } 1256 1257 /* Configure mbuf pool watermarks */ 1258 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 1259 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1260 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1261 } else { 1262 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1263 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1264 } 1265 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1266 1267 /* Configure DMA resource watermarks */ 1268 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1269 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1270 1271 /* Enable buffer manager */ 1272 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1273 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1274 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1275 1276 /* Poll for buffer manager start indication */ 1277 for (i = 0; i < BGE_TIMEOUT; i++) { 1278 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1279 break; 1280 DELAY(10); 1281 } 1282 1283 if (i == BGE_TIMEOUT) { 1284 printf("bge%d: buffer manager failed to start\n", 1285 sc->bge_unit); 1286 return(ENXIO); 1287 } 1288 } 1289 1290 /* Enable flow-through queues */ 1291 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1292 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1293 1294 /* Wait until queue initialization is complete */ 1295 for (i = 0; i < BGE_TIMEOUT; i++) { 1296 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1297 break; 1298 DELAY(10); 1299 } 1300 1301 if (i == BGE_TIMEOUT) { 1302 printf("bge%d: flow-through queue init failed\n", 1303 sc->bge_unit); 1304 return(ENXIO); 1305 } 1306 1307 /* Initialize the standard RX ring control block */ 1308 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1309 BGE_HOSTADDR(rcb->bge_hostaddr, 1310 vtophys(&sc->bge_rdata->bge_rx_std_ring)); 1311 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1312 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1313 else 1314 rcb->bge_maxlen_flags = 1315 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1316 if (sc->bge_extram) 1317 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1318 else 1319 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1320 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1321 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1322 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1323 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1324 1325 /* 1326 * Initialize the jumbo RX ring control block 1327 * We set the 'ring disabled' bit in the flags 1328 * field until we're actually ready to start 1329 * using this ring (i.e. once we set the MTU 1330 * high enough to require it). 1331 */ 1332 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1333 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1334 BGE_HOSTADDR(rcb->bge_hostaddr, 1335 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring)); 1336 rcb->bge_maxlen_flags = 1337 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1338 BGE_RCB_FLAG_RING_DISABLED); 1339 if (sc->bge_extram) 1340 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1341 else 1342 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1343 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1344 rcb->bge_hostaddr.bge_addr_hi); 1345 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1346 rcb->bge_hostaddr.bge_addr_lo); 1347 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1348 rcb->bge_maxlen_flags); 1349 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1350 1351 /* Set up dummy disabled mini ring RCB */ 1352 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1353 rcb->bge_maxlen_flags = 1354 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1355 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1356 rcb->bge_maxlen_flags); 1357 } 1358 1359 /* 1360 * Set the BD ring replentish thresholds. The recommended 1361 * values are 1/8th the number of descriptors allocated to 1362 * each ring. 1363 */ 1364 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1365 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1366 1367 /* 1368 * Disable all unused send rings by setting the 'ring disabled' 1369 * bit in the flags field of all the TX send ring control blocks. 1370 * These are located in NIC memory. 1371 */ 1372 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1373 BGE_SEND_RING_RCB); 1374 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1375 vrcb->bge_maxlen_flags = 1376 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1377 vrcb->bge_nicaddr = 0; 1378 vrcb++; 1379 } 1380 1381 /* Configure TX RCB 0 (we use only the first ring) */ 1382 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1383 BGE_SEND_RING_RCB); 1384 vrcb->bge_hostaddr.bge_addr_hi = 0; 1385 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring)); 1386 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1387 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1388 vrcb->bge_maxlen_flags = 1389 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1390 1391 /* Disable all unused RX return rings */ 1392 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1393 BGE_RX_RETURN_RING_RCB); 1394 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1395 vrcb->bge_hostaddr.bge_addr_hi = 0; 1396 vrcb->bge_hostaddr.bge_addr_lo = 0; 1397 vrcb->bge_maxlen_flags = 1398 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1399 BGE_RCB_FLAG_RING_DISABLED); 1400 vrcb->bge_nicaddr = 0; 1401 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1402 (i * (sizeof(u_int64_t))), 0); 1403 vrcb++; 1404 } 1405 1406 /* Initialize RX ring indexes */ 1407 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1408 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1409 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1410 1411 /* 1412 * Set up RX return ring 0 1413 * Note that the NIC address for RX return rings is 0x00000000. 1414 * The return rings live entirely within the host, so the 1415 * nicaddr field in the RCB isn't used. 1416 */ 1417 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1418 BGE_RX_RETURN_RING_RCB); 1419 vrcb->bge_hostaddr.bge_addr_hi = 0; 1420 BGE_HOSTADDR(vrcb->bge_hostaddr, 1421 vtophys(&sc->bge_rdata->bge_rx_return_ring)); 1422 vrcb->bge_nicaddr = 0x00000000; 1423 vrcb->bge_maxlen_flags = 1424 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0); 1425 1426 /* Set random backoff seed for TX */ 1427 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1428 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1429 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1430 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1431 BGE_TX_BACKOFF_SEED_MASK); 1432 1433 /* Set inter-packet gap */ 1434 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1435 1436 /* 1437 * Specify which ring to use for packets that don't match 1438 * any RX rules. 1439 */ 1440 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1441 1442 /* 1443 * Configure number of RX lists. One interrupt distribution 1444 * list, sixteen active lists, one bad frames class. 1445 */ 1446 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1447 1448 /* Inialize RX list placement stats mask. */ 1449 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1450 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1451 1452 /* Disable host coalescing until we get it set up */ 1453 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1454 1455 /* Poll to make sure it's shut down. */ 1456 for (i = 0; i < BGE_TIMEOUT; i++) { 1457 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1458 break; 1459 DELAY(10); 1460 } 1461 1462 if (i == BGE_TIMEOUT) { 1463 printf("bge%d: host coalescing engine failed to idle\n", 1464 sc->bge_unit); 1465 return(ENXIO); 1466 } 1467 1468 /* Set up host coalescing defaults */ 1469 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1470 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1471 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1472 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1473 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1474 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1475 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1476 } 1477 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1478 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1479 1480 /* Set up address of statistics block */ 1481 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1482 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1483 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1484 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1485 1486 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1487 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1488 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1489 } 1490 1491 /* Set up address of status block */ 1492 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1493 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1494 vtophys(&sc->bge_rdata->bge_status_block)); 1495 1496 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1497 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1498 1499 /* Turn on host coalescing state machine */ 1500 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1501 1502 /* Turn on RX BD completion state machine and enable attentions */ 1503 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1504 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1505 1506 /* Turn on RX list placement state machine */ 1507 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1508 1509 /* Turn on RX list selector state machine. */ 1510 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1511 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1512 1513 /* Turn on DMA, clear stats */ 1514 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1515 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1516 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1517 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1518 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1519 1520 /* Set misc. local control, enable interrupts on attentions */ 1521 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1522 1523 #ifdef notdef 1524 /* Assert GPIO pins for PHY reset */ 1525 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1526 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1527 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1528 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1529 #endif 1530 1531 /* Turn on DMA completion state machine */ 1532 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1533 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1534 1535 /* Turn on write DMA state machine */ 1536 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1537 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1538 1539 /* Turn on read DMA state machine */ 1540 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1541 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1542 1543 /* Turn on RX data completion state machine */ 1544 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1545 1546 /* Turn on RX BD initiator state machine */ 1547 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1548 1549 /* Turn on RX data and RX BD initiator state machine */ 1550 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1551 1552 /* Turn on Mbuf cluster free state machine */ 1553 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1554 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1555 1556 /* Turn on send BD completion state machine */ 1557 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1558 1559 /* Turn on send data completion state machine */ 1560 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1561 1562 /* Turn on send data initiator state machine */ 1563 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1564 1565 /* Turn on send BD initiator state machine */ 1566 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1567 1568 /* Turn on send BD selector state machine */ 1569 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1570 1571 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1572 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1573 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1574 1575 /* ack/clear link change events */ 1576 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1577 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1578 BGE_MACSTAT_LINK_CHANGED); 1579 1580 /* Enable PHY auto polling (for MII/GMII only) */ 1581 if (sc->bge_tbi) { 1582 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1583 } else { 1584 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1585 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1586 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1587 BGE_EVTENB_MI_INTERRUPT); 1588 } 1589 1590 /* Enable link state change attentions. */ 1591 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1592 1593 return(0); 1594 } 1595 1596 /* 1597 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1598 * against our list and return its name if we find a match. Note 1599 * that since the Broadcom controller contains VPD support, we 1600 * can get the device name string from the controller itself instead 1601 * of the compiled-in string. This is a little slow, but it guarantees 1602 * we'll always announce the right product name. 1603 */ 1604 static int 1605 bge_probe(dev) 1606 device_t dev; 1607 { 1608 struct bge_type *t; 1609 struct bge_softc *sc; 1610 char *descbuf; 1611 1612 t = bge_devs; 1613 1614 sc = device_get_softc(dev); 1615 bzero(sc, sizeof(struct bge_softc)); 1616 sc->bge_unit = device_get_unit(dev); 1617 sc->bge_dev = dev; 1618 1619 while(t->bge_name != NULL) { 1620 if ((pci_get_vendor(dev) == t->bge_vid) && 1621 (pci_get_device(dev) == t->bge_did)) { 1622 #ifdef notdef 1623 bge_vpd_read(sc); 1624 device_set_desc(dev, sc->bge_vpd_prodname); 1625 #endif 1626 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1627 if (descbuf == NULL) 1628 return(ENOMEM); 1629 snprintf(descbuf, BGE_DEVDESC_MAX, 1630 "%s, ASIC rev. %#04x", t->bge_name, 1631 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1632 device_set_desc_copy(dev, descbuf); 1633 if (pci_get_subvendor(dev) == DELL_VENDORID) 1634 sc->bge_no_3_led = 1; 1635 free(descbuf, M_TEMP); 1636 return(0); 1637 } 1638 t++; 1639 } 1640 1641 return(ENXIO); 1642 } 1643 1644 static int 1645 bge_attach(dev) 1646 device_t dev; 1647 { 1648 int s; 1649 u_int32_t command; 1650 struct ifnet *ifp; 1651 struct bge_softc *sc; 1652 u_int32_t hwcfg = 0; 1653 u_int32_t mac_addr = 0; 1654 int unit, error = 0, rid; 1655 1656 s = splimp(); 1657 1658 sc = device_get_softc(dev); 1659 unit = device_get_unit(dev); 1660 sc->bge_dev = dev; 1661 sc->bge_unit = unit; 1662 1663 /* 1664 * Map control/status registers. 1665 */ 1666 command = pci_read_config(dev, PCIR_COMMAND, 4); 1667 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1668 pci_write_config(dev, PCIR_COMMAND, command, 4); 1669 command = pci_read_config(dev, PCIR_COMMAND, 4); 1670 1671 if (!(command & PCIM_CMD_MEMEN)) { 1672 printf("bge%d: failed to enable memory mapping!\n", unit); 1673 error = ENXIO; 1674 goto fail; 1675 } 1676 1677 rid = BGE_PCI_BAR0; 1678 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1679 0, ~0, 1, RF_ACTIVE); 1680 1681 if (sc->bge_res == NULL) { 1682 printf ("bge%d: couldn't map memory\n", unit); 1683 error = ENXIO; 1684 goto fail; 1685 } 1686 1687 sc->bge_btag = rman_get_bustag(sc->bge_res); 1688 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1689 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1690 1691 /* 1692 * XXX FIXME: rman_get_virtual() on the alpha is currently 1693 * broken and returns a physical address instead of a kernel 1694 * virtual address. Consequently, we need to do a little 1695 * extra mangling of the vhandle on the alpha. This should 1696 * eventually be fixed! The whole idea here is to get rid 1697 * of platform dependencies. 1698 */ 1699 #ifdef __alpha__ 1700 if (pci_cvt_to_bwx(sc->bge_vhandle)) 1701 sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle); 1702 else 1703 sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle); 1704 sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle); 1705 #endif 1706 1707 /* Allocate interrupt */ 1708 rid = 0; 1709 1710 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1711 RF_SHAREABLE | RF_ACTIVE); 1712 1713 if (sc->bge_irq == NULL) { 1714 printf("bge%d: couldn't map interrupt\n", unit); 1715 error = ENXIO; 1716 goto fail; 1717 } 1718 1719 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1720 bge_intr, sc, &sc->bge_intrhand); 1721 1722 if (error) { 1723 bge_release_resources(sc); 1724 printf("bge%d: couldn't set up irq\n", unit); 1725 goto fail; 1726 } 1727 1728 sc->bge_unit = unit; 1729 1730 /* Try to reset the chip. */ 1731 bge_reset(sc); 1732 1733 if (bge_chipinit(sc)) { 1734 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1735 bge_release_resources(sc); 1736 error = ENXIO; 1737 goto fail; 1738 } 1739 1740 /* 1741 * Get station address from the EEPROM. 1742 */ 1743 mac_addr = bge_readmem_ind(sc, 0x0c14); 1744 if ((mac_addr >> 16) == 0x484b) { 1745 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 1746 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 1747 mac_addr = bge_readmem_ind(sc, 0x0c18); 1748 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 1749 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 1750 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 1751 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 1752 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1753 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1754 printf("bge%d: failed to read station address\n", unit); 1755 bge_release_resources(sc); 1756 error = ENXIO; 1757 goto fail; 1758 } 1759 1760 /* 1761 * A Broadcom chip was detected. Inform the world. 1762 */ 1763 printf("bge%d: Ethernet address: %6D\n", unit, 1764 sc->arpcom.ac_enaddr, ":"); 1765 1766 /* Allocate the general information block and ring buffers. */ 1767 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1768 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1769 1770 if (sc->bge_rdata == NULL) { 1771 bge_release_resources(sc); 1772 error = ENXIO; 1773 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1774 goto fail; 1775 } 1776 1777 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1778 1779 /* Save ASIC rev. */ 1780 1781 sc->bge_chipid = 1782 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1783 BGE_PCIMISCCTL_ASICREV; 1784 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 1785 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 1786 1787 /* 1788 * Try to allocate memory for jumbo buffers. 1789 * The 5705 does not appear to support jumbo frames. 1790 */ 1791 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1792 if (bge_alloc_jumbo_mem(sc)) { 1793 printf("bge%d: jumbo buffer allocation " 1794 "failed\n", sc->bge_unit); 1795 bge_release_resources(sc); 1796 error = ENXIO; 1797 goto fail; 1798 } 1799 } 1800 1801 /* Set default tuneable values. */ 1802 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1803 sc->bge_rx_coal_ticks = 150; 1804 sc->bge_tx_coal_ticks = 150; 1805 sc->bge_rx_max_coal_bds = 64; 1806 sc->bge_tx_max_coal_bds = 128; 1807 1808 /* 5705 limits RX return ring to 512 entries. */ 1809 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1810 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1811 else 1812 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1813 1814 /* Set up ifnet structure */ 1815 ifp = &sc->arpcom.ac_if; 1816 ifp->if_softc = sc; 1817 if_initname(ifp, "bge", sc->bge_unit); 1818 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1819 ifp->if_ioctl = bge_ioctl; 1820 ifp->if_output = ether_output; 1821 ifp->if_start = bge_start; 1822 ifp->if_watchdog = bge_watchdog; 1823 ifp->if_init = bge_init; 1824 ifp->if_mtu = ETHERMTU; 1825 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1826 ifp->if_hwassist = BGE_CSUM_FEATURES; 1827 ifp->if_capabilities = IFCAP_HWCSUM; 1828 ifp->if_capenable = ifp->if_capabilities; 1829 1830 /* 1831 * Figure out what sort of media we have by checking the 1832 * hardware config word in the first 32k of NIC internal memory, 1833 * or fall back to examining the EEPROM if necessary. 1834 * Note: on some BCM5700 cards, this value appears to be unset. 1835 * If that's the case, we have to rely on identifying the NIC 1836 * by its PCI subsystem ID, as we do below for the SysKonnect 1837 * SK-9D41. 1838 */ 1839 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 1840 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 1841 else { 1842 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1843 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1844 hwcfg = ntohl(hwcfg); 1845 } 1846 1847 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1848 sc->bge_tbi = 1; 1849 1850 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1851 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1852 sc->bge_tbi = 1; 1853 1854 if (sc->bge_tbi) { 1855 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1856 bge_ifmedia_upd, bge_ifmedia_sts); 1857 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1858 ifmedia_add(&sc->bge_ifmedia, 1859 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1860 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1861 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1862 } else { 1863 /* 1864 * Do transceiver setup. 1865 */ 1866 if (mii_phy_probe(dev, &sc->bge_miibus, 1867 bge_ifmedia_upd, bge_ifmedia_sts)) { 1868 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1869 bge_release_resources(sc); 1870 bge_free_jumbo_mem(sc); 1871 error = ENXIO; 1872 goto fail; 1873 } 1874 } 1875 1876 /* 1877 * When using the BCM5701 in PCI-X mode, data corruption has 1878 * been observed in the first few bytes of some received packets. 1879 * Aligning the packet buffer in memory eliminates the corruption. 1880 * Unfortunately, this misaligns the packet payloads. On platforms 1881 * which do not support unaligned accesses, we will realign the 1882 * payloads by copying the received packets. 1883 */ 1884 switch (sc->bge_chipid) { 1885 case BGE_CHIPID_BCM5701_A0: 1886 case BGE_CHIPID_BCM5701_B0: 1887 case BGE_CHIPID_BCM5701_B2: 1888 case BGE_CHIPID_BCM5701_B5: 1889 /* If in PCI-X mode, work around the alignment bug. */ 1890 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1891 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1892 BGE_PCISTATE_PCI_BUSSPEED) 1893 sc->bge_rx_alignment_bug = 1; 1894 break; 1895 } 1896 1897 /* 1898 * Call MI attach routine. 1899 */ 1900 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1901 callout_handle_init(&sc->bge_stat_ch); 1902 1903 fail: 1904 splx(s); 1905 1906 return(error); 1907 } 1908 1909 static int 1910 bge_detach(dev) 1911 device_t dev; 1912 { 1913 struct bge_softc *sc; 1914 struct ifnet *ifp; 1915 int s; 1916 1917 s = splimp(); 1918 1919 sc = device_get_softc(dev); 1920 ifp = &sc->arpcom.ac_if; 1921 1922 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1923 bge_stop(sc); 1924 bge_reset(sc); 1925 1926 if (sc->bge_tbi) { 1927 ifmedia_removeall(&sc->bge_ifmedia); 1928 } else { 1929 bus_generic_detach(dev); 1930 device_delete_child(dev, sc->bge_miibus); 1931 } 1932 1933 bge_release_resources(sc); 1934 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1935 bge_free_jumbo_mem(sc); 1936 1937 splx(s); 1938 1939 return(0); 1940 } 1941 1942 static void 1943 bge_release_resources(sc) 1944 struct bge_softc *sc; 1945 { 1946 device_t dev; 1947 1948 dev = sc->bge_dev; 1949 1950 if (sc->bge_vpd_prodname != NULL) 1951 free(sc->bge_vpd_prodname, M_DEVBUF); 1952 1953 if (sc->bge_vpd_readonly != NULL) 1954 free(sc->bge_vpd_readonly, M_DEVBUF); 1955 1956 if (sc->bge_intrhand != NULL) 1957 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1958 1959 if (sc->bge_irq != NULL) 1960 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1961 1962 if (sc->bge_res != NULL) 1963 bus_release_resource(dev, SYS_RES_MEMORY, 1964 BGE_PCI_BAR0, sc->bge_res); 1965 1966 if (sc->bge_rdata != NULL) 1967 contigfree(sc->bge_rdata, 1968 sizeof(struct bge_ring_data), M_DEVBUF); 1969 1970 return; 1971 } 1972 1973 static void 1974 bge_reset(sc) 1975 struct bge_softc *sc; 1976 { 1977 device_t dev; 1978 u_int32_t cachesize, command, pcistate; 1979 int i, val = 0; 1980 1981 dev = sc->bge_dev; 1982 1983 /* Save some important PCI state. */ 1984 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1985 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1986 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1987 1988 pci_write_config(dev, BGE_PCI_MISC_CTL, 1989 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1990 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1991 1992 /* Issue global reset */ 1993 bge_writereg_ind(sc, BGE_MISC_CFG, 1994 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1995 1996 DELAY(1000); 1997 1998 /* Reset some of the PCI state that got zapped by reset */ 1999 pci_write_config(dev, BGE_PCI_MISC_CTL, 2000 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2001 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2002 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2003 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2004 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2005 2006 /* 2007 * Prevent PXE restart: write a magic number to the 2008 * general communications memory at 0xB50. 2009 */ 2010 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2011 /* 2012 * Poll the value location we just wrote until 2013 * we see the 1's complement of the magic number. 2014 * This indicates that the firmware initialization 2015 * is complete. 2016 */ 2017 for (i = 0; i < BGE_TIMEOUT; i++) { 2018 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2019 if (val == ~BGE_MAGIC_NUMBER) 2020 break; 2021 DELAY(10); 2022 } 2023 2024 if (i == BGE_TIMEOUT) { 2025 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 2026 return; 2027 } 2028 2029 /* 2030 * XXX Wait for the value of the PCISTATE register to 2031 * return to its original pre-reset state. This is a 2032 * fairly good indicator of reset completion. If we don't 2033 * wait for the reset to fully complete, trying to read 2034 * from the device's non-PCI registers may yield garbage 2035 * results. 2036 */ 2037 for (i = 0; i < BGE_TIMEOUT; i++) { 2038 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2039 break; 2040 DELAY(10); 2041 } 2042 2043 /* Enable memory arbiter. */ 2044 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2045 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2046 2047 /* Fix up byte swapping */ 2048 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 2049 BGE_MODECTL_BYTESWAP_DATA); 2050 2051 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2052 2053 DELAY(10000); 2054 2055 return; 2056 } 2057 2058 /* 2059 * Frame reception handling. This is called if there's a frame 2060 * on the receive return list. 2061 * 2062 * Note: we have to be able to handle two possibilities here: 2063 * 1) the frame is from the jumbo recieve ring 2064 * 2) the frame is from the standard receive ring 2065 */ 2066 2067 static void 2068 bge_rxeof(sc) 2069 struct bge_softc *sc; 2070 { 2071 struct ifnet *ifp; 2072 int stdcnt = 0, jumbocnt = 0; 2073 2074 ifp = &sc->arpcom.ac_if; 2075 2076 while(sc->bge_rx_saved_considx != 2077 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2078 struct bge_rx_bd *cur_rx; 2079 u_int32_t rxidx; 2080 struct ether_header *eh; 2081 struct mbuf *m = NULL; 2082 u_int16_t vlan_tag = 0; 2083 int have_tag = 0; 2084 2085 cur_rx = 2086 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 2087 2088 rxidx = cur_rx->bge_idx; 2089 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2090 2091 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2092 have_tag = 1; 2093 vlan_tag = cur_rx->bge_vlan_tag; 2094 } 2095 2096 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2097 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2098 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2099 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2100 jumbocnt++; 2101 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2102 ifp->if_ierrors++; 2103 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2104 continue; 2105 } 2106 if (bge_newbuf_jumbo(sc, 2107 sc->bge_jumbo, NULL) == ENOBUFS) { 2108 ifp->if_ierrors++; 2109 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2110 continue; 2111 } 2112 } else { 2113 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2114 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2115 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2116 stdcnt++; 2117 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2118 ifp->if_ierrors++; 2119 bge_newbuf_std(sc, sc->bge_std, m); 2120 continue; 2121 } 2122 if (bge_newbuf_std(sc, sc->bge_std, 2123 NULL) == ENOBUFS) { 2124 ifp->if_ierrors++; 2125 bge_newbuf_std(sc, sc->bge_std, m); 2126 continue; 2127 } 2128 } 2129 2130 ifp->if_ipackets++; 2131 #ifndef __i386__ 2132 /* 2133 * The i386 allows unaligned accesses, but for other 2134 * platforms we must make sure the payload is aligned. 2135 */ 2136 if (sc->bge_rx_alignment_bug) { 2137 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2138 cur_rx->bge_len); 2139 m->m_data += ETHER_ALIGN; 2140 } 2141 #endif 2142 eh = mtod(m, struct ether_header *); 2143 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2144 m->m_pkthdr.rcvif = ifp; 2145 2146 /* Remove header from mbuf and pass it on. */ 2147 m_adj(m, sizeof(struct ether_header)); 2148 2149 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2150 if (ifp->if_hwassist) { 2151 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2152 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2153 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2154 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2155 m->m_pkthdr.csum_data = 2156 cur_rx->bge_tcp_udp_csum; 2157 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2158 } 2159 } 2160 #endif 2161 2162 /* 2163 * If we received a packet with a vlan tag, pass it 2164 * to vlan_input() instead of ether_input(). 2165 */ 2166 if (have_tag) { 2167 VLAN_INPUT_TAG(eh, m, vlan_tag); 2168 have_tag = vlan_tag = 0; 2169 continue; 2170 } 2171 2172 ether_input(ifp, eh, m); 2173 } 2174 2175 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2176 if (stdcnt) 2177 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2178 if (jumbocnt) 2179 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2180 2181 return; 2182 } 2183 2184 static void 2185 bge_txeof(sc) 2186 struct bge_softc *sc; 2187 { 2188 struct bge_tx_bd *cur_tx = NULL; 2189 struct ifnet *ifp; 2190 2191 ifp = &sc->arpcom.ac_if; 2192 2193 /* 2194 * Go through our tx ring and free mbufs for those 2195 * frames that have been sent. 2196 */ 2197 while (sc->bge_tx_saved_considx != 2198 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2199 u_int32_t idx = 0; 2200 2201 idx = sc->bge_tx_saved_considx; 2202 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2203 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2204 ifp->if_opackets++; 2205 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2206 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2207 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2208 } 2209 sc->bge_txcnt--; 2210 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2211 ifp->if_timer = 0; 2212 } 2213 2214 if (cur_tx != NULL) 2215 ifp->if_flags &= ~IFF_OACTIVE; 2216 2217 return; 2218 } 2219 2220 static void 2221 bge_intr(xsc) 2222 void *xsc; 2223 { 2224 struct bge_softc *sc; 2225 struct ifnet *ifp; 2226 u_int32_t status; 2227 2228 sc = xsc; 2229 ifp = &sc->arpcom.ac_if; 2230 2231 #ifdef notdef 2232 /* Avoid this for now -- checking this register is expensive. */ 2233 /* Make sure this is really our interrupt. */ 2234 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2235 return; 2236 #endif 2237 /* Ack interrupt and stop others from occuring. */ 2238 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2239 2240 /* 2241 * Process link state changes. 2242 * Grrr. The link status word in the status block does 2243 * not work correctly on the BCM5700 rev AX and BX chips, 2244 * according to all available information. Hence, we have 2245 * to enable MII interrupts in order to properly obtain 2246 * async link changes. Unfortunately, this also means that 2247 * we have to read the MAC status register to detect link 2248 * changes, thereby adding an additional register access to 2249 * the interrupt handler. 2250 */ 2251 2252 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2253 status = CSR_READ_4(sc, BGE_MAC_STS); 2254 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2255 sc->bge_link = 0; 2256 untimeout(bge_tick, sc, sc->bge_stat_ch); 2257 bge_tick(sc); 2258 /* Clear the interrupt */ 2259 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2260 BGE_EVTENB_MI_INTERRUPT); 2261 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2262 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2263 BRGPHY_INTRS); 2264 } 2265 } else { 2266 if ((sc->bge_rdata->bge_status_block.bge_status & 2267 BGE_STATFLAG_UPDATED) && 2268 (sc->bge_rdata->bge_status_block.bge_status & 2269 BGE_STATFLAG_LINKSTATE_CHANGED)) { 2270 sc->bge_rdata->bge_status_block.bge_status &= 2271 ~(BGE_STATFLAG_UPDATED| 2272 BGE_STATFLAG_LINKSTATE_CHANGED); 2273 /* 2274 * Sometime PCS encoding errors are detected in 2275 * TBI mode (on fiber NICs), and for some reason 2276 * the chip will signal them as link changes. 2277 * If we get a link change event, but the 'PCS 2278 * encoding error' bit in the MAC status register 2279 * is set, don't bother doing a link check. 2280 * This avoids spurious "gigabit link up" messages 2281 * that sometimes appear on fiber NIC's during 2282 * periods of heavy traffic. (There should be no 2283 * effect on copper NICs.) 2284 */ 2285 status = CSR_READ_4(sc, BGE_MAC_STS); 2286 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR| 2287 BGE_MACSTAT_MI_COMPLETE))) { 2288 sc->bge_link = 0; 2289 untimeout(bge_tick, sc, sc->bge_stat_ch); 2290 bge_tick(sc); 2291 } 2292 sc->bge_link = 0; 2293 untimeout(bge_tick, sc, sc->bge_stat_ch); 2294 bge_tick(sc); 2295 /* Clear the interrupt */ 2296 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2297 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2298 BGE_MACSTAT_LINK_CHANGED); 2299 2300 /* Force flush the status block cached by PCI bridge */ 2301 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2302 } 2303 } 2304 2305 if (ifp->if_flags & IFF_RUNNING) { 2306 /* Check RX return ring producer/consumer */ 2307 bge_rxeof(sc); 2308 2309 /* Check TX ring producer/consumer */ 2310 bge_txeof(sc); 2311 } 2312 2313 bge_handle_events(sc); 2314 2315 /* Re-enable interrupts. */ 2316 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2317 2318 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2319 bge_start(ifp); 2320 2321 return; 2322 } 2323 2324 static void 2325 bge_tick(xsc) 2326 void *xsc; 2327 { 2328 struct bge_softc *sc; 2329 struct mii_data *mii = NULL; 2330 struct ifmedia *ifm = NULL; 2331 struct ifnet *ifp; 2332 int s; 2333 2334 sc = xsc; 2335 ifp = &sc->arpcom.ac_if; 2336 2337 s = splimp(); 2338 2339 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2340 bge_stats_update_regs(sc); 2341 else 2342 bge_stats_update(sc); 2343 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2344 if (sc->bge_link) { 2345 splx(s); 2346 return; 2347 } 2348 2349 if (sc->bge_tbi) { 2350 ifm = &sc->bge_ifmedia; 2351 if (CSR_READ_4(sc, BGE_MAC_STS) & 2352 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2353 sc->bge_link++; 2354 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2355 printf("bge%d: gigabit link up\n", sc->bge_unit); 2356 if (ifp->if_snd.ifq_head != NULL) 2357 bge_start(ifp); 2358 } 2359 splx(s); 2360 return; 2361 } 2362 2363 mii = device_get_softc(sc->bge_miibus); 2364 mii_tick(mii); 2365 2366 if (!sc->bge_link) { 2367 mii_pollstat(mii); 2368 if (mii->mii_media_status & IFM_ACTIVE && 2369 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2370 sc->bge_link++; 2371 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 2372 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2373 printf("bge%d: gigabit link up\n", 2374 sc->bge_unit); 2375 if (ifp->if_snd.ifq_head != NULL) 2376 bge_start(ifp); 2377 } 2378 } 2379 2380 splx(s); 2381 2382 return; 2383 } 2384 2385 static void 2386 bge_stats_update_regs(sc) 2387 struct bge_softc *sc; 2388 { 2389 struct ifnet *ifp; 2390 struct bge_mac_stats_regs stats; 2391 u_int32_t *s; 2392 int i; 2393 2394 ifp = &sc->arpcom.ac_if; 2395 2396 s = (u_int32_t *)&stats; 2397 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 2398 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 2399 s++; 2400 } 2401 2402 ifp->if_collisions += 2403 (stats.dot3StatsSingleCollisionFrames + 2404 stats.dot3StatsMultipleCollisionFrames + 2405 stats.dot3StatsExcessiveCollisions + 2406 stats.dot3StatsLateCollisions) - 2407 ifp->if_collisions; 2408 2409 return; 2410 } 2411 2412 static void 2413 bge_stats_update(sc) 2414 struct bge_softc *sc; 2415 { 2416 struct ifnet *ifp; 2417 struct bge_stats *stats; 2418 2419 ifp = &sc->arpcom.ac_if; 2420 2421 stats = (struct bge_stats *)(sc->bge_vhandle + 2422 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2423 2424 ifp->if_collisions += 2425 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo + 2426 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo + 2427 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo + 2428 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) - 2429 ifp->if_collisions; 2430 2431 #ifdef notdef 2432 ifp->if_collisions += 2433 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2434 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2435 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2436 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2437 ifp->if_collisions; 2438 #endif 2439 2440 return; 2441 } 2442 2443 /* 2444 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2445 * pointers to descriptors. 2446 */ 2447 static int 2448 bge_encap(sc, m_head, txidx) 2449 struct bge_softc *sc; 2450 struct mbuf *m_head; 2451 u_int32_t *txidx; 2452 { 2453 struct bge_tx_bd *f = NULL; 2454 struct mbuf *m; 2455 u_int32_t frag, cur, cnt = 0; 2456 u_int16_t csum_flags = 0; 2457 struct ifvlan *ifv = NULL; 2458 2459 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2460 m_head->m_pkthdr.rcvif != NULL && 2461 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 2462 ifv = m_head->m_pkthdr.rcvif->if_softc; 2463 2464 m = m_head; 2465 cur = frag = *txidx; 2466 2467 if (m_head->m_pkthdr.csum_flags) { 2468 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2469 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2470 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2471 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2472 if (m_head->m_flags & M_LASTFRAG) 2473 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2474 else if (m_head->m_flags & M_FRAG) 2475 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2476 } 2477 /* 2478 * Start packing the mbufs in this chain into 2479 * the fragment pointers. Stop when we run out 2480 * of fragments or hit the end of the mbuf chain. 2481 */ 2482 for (m = m_head; m != NULL; m = m->m_next) { 2483 if (m->m_len != 0) { 2484 f = &sc->bge_rdata->bge_tx_ring[frag]; 2485 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2486 break; 2487 BGE_HOSTADDR(f->bge_addr, 2488 vtophys(mtod(m, vm_offset_t))); 2489 f->bge_len = m->m_len; 2490 f->bge_flags = csum_flags; 2491 if (ifv != NULL) { 2492 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2493 f->bge_vlan_tag = ifv->ifv_tag; 2494 } else { 2495 f->bge_vlan_tag = 0; 2496 } 2497 /* 2498 * Sanity check: avoid coming within 16 descriptors 2499 * of the end of the ring. 2500 */ 2501 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2502 return(ENOBUFS); 2503 cur = frag; 2504 BGE_INC(frag, BGE_TX_RING_CNT); 2505 cnt++; 2506 } 2507 } 2508 2509 if (m != NULL) 2510 return(ENOBUFS); 2511 2512 if (frag == sc->bge_tx_saved_considx) 2513 return(ENOBUFS); 2514 2515 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2516 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2517 sc->bge_txcnt += cnt; 2518 2519 *txidx = frag; 2520 2521 return(0); 2522 } 2523 2524 /* 2525 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2526 * to the mbuf data regions directly in the transmit descriptors. 2527 */ 2528 static void 2529 bge_start(ifp) 2530 struct ifnet *ifp; 2531 { 2532 struct bge_softc *sc; 2533 struct mbuf *m_head = NULL; 2534 u_int32_t prodidx = 0; 2535 2536 sc = ifp->if_softc; 2537 2538 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2539 return; 2540 2541 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2542 2543 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2544 IF_DEQUEUE(&ifp->if_snd, m_head); 2545 if (m_head == NULL) 2546 break; 2547 2548 /* 2549 * XXX 2550 * safety overkill. If this is a fragmented packet chain 2551 * with delayed TCP/UDP checksums, then only encapsulate 2552 * it if we have enough descriptors to handle the entire 2553 * chain at once. 2554 * (paranoia -- may not actually be needed) 2555 */ 2556 if (m_head->m_flags & M_FIRSTFRAG && 2557 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2558 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2559 m_head->m_pkthdr.csum_data + 16) { 2560 IF_PREPEND(&ifp->if_snd, m_head); 2561 ifp->if_flags |= IFF_OACTIVE; 2562 break; 2563 } 2564 } 2565 2566 /* 2567 * Pack the data into the transmit ring. If we 2568 * don't have room, set the OACTIVE flag and wait 2569 * for the NIC to drain the ring. 2570 */ 2571 if (bge_encap(sc, m_head, &prodidx)) { 2572 IF_PREPEND(&ifp->if_snd, m_head); 2573 ifp->if_flags |= IFF_OACTIVE; 2574 break; 2575 } 2576 2577 /* 2578 * If there's a BPF listener, bounce a copy of this frame 2579 * to him. 2580 */ 2581 if (ifp->if_bpf) 2582 bpf_mtap(ifp, m_head); 2583 } 2584 2585 /* Transmit */ 2586 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2587 /* 5700 b2 errata */ 2588 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 2589 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2590 2591 /* 2592 * Set a timeout in case the chip goes out to lunch. 2593 */ 2594 ifp->if_timer = 5; 2595 2596 return; 2597 } 2598 2599 static void 2600 bge_init(xsc) 2601 void *xsc; 2602 { 2603 struct bge_softc *sc = xsc; 2604 struct ifnet *ifp; 2605 u_int16_t *m; 2606 int s; 2607 2608 s = splimp(); 2609 2610 ifp = &sc->arpcom.ac_if; 2611 2612 if (ifp->if_flags & IFF_RUNNING) { 2613 splx(s); 2614 return; 2615 } 2616 2617 /* Cancel pending I/O and flush buffers. */ 2618 bge_stop(sc); 2619 bge_reset(sc); 2620 bge_chipinit(sc); 2621 2622 /* 2623 * Init the various state machines, ring 2624 * control blocks and firmware. 2625 */ 2626 if (bge_blockinit(sc)) { 2627 printf("bge%d: initialization failure\n", sc->bge_unit); 2628 splx(s); 2629 return; 2630 } 2631 2632 ifp = &sc->arpcom.ac_if; 2633 2634 /* Specify MTU. */ 2635 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2636 ETHER_HDR_LEN + ETHER_CRC_LEN); 2637 2638 /* Load our MAC address. */ 2639 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2640 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2641 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2642 2643 /* Enable or disable promiscuous mode as needed. */ 2644 if (ifp->if_flags & IFF_PROMISC) { 2645 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2646 } else { 2647 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2648 } 2649 2650 /* Program multicast filter. */ 2651 bge_setmulti(sc); 2652 2653 /* Init RX ring. */ 2654 bge_init_rx_ring_std(sc); 2655 2656 /* 2657 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 2658 * memory to insure that the chip has in fact read the first 2659 * entry of the ring. 2660 */ 2661 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 2662 u_int32_t v, i; 2663 for (i = 0; i < 10; i++) { 2664 DELAY(20); 2665 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 2666 if (v == (MCLBYTES - ETHER_ALIGN)) 2667 break; 2668 } 2669 if (i == 10) 2670 printf ("bge%d: 5705 A0 chip failed to load RX ring\n", 2671 sc->bge_unit); 2672 } 2673 2674 /* Init jumbo RX ring. */ 2675 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2676 bge_init_rx_ring_jumbo(sc); 2677 2678 /* Init our RX return ring index */ 2679 sc->bge_rx_saved_considx = 0; 2680 2681 /* Init TX ring. */ 2682 bge_init_tx_ring(sc); 2683 2684 /* Turn on transmitter */ 2685 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2686 2687 /* Turn on receiver */ 2688 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2689 2690 /* Tell firmware we're alive. */ 2691 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2692 2693 /* Enable host interrupts. */ 2694 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2695 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2696 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2697 2698 bge_ifmedia_upd(ifp); 2699 2700 ifp->if_flags |= IFF_RUNNING; 2701 ifp->if_flags &= ~IFF_OACTIVE; 2702 2703 splx(s); 2704 2705 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2706 2707 return; 2708 } 2709 2710 /* 2711 * Set media options. 2712 */ 2713 static int 2714 bge_ifmedia_upd(ifp) 2715 struct ifnet *ifp; 2716 { 2717 struct bge_softc *sc; 2718 struct mii_data *mii; 2719 struct ifmedia *ifm; 2720 2721 sc = ifp->if_softc; 2722 ifm = &sc->bge_ifmedia; 2723 2724 /* If this is a 1000baseX NIC, enable the TBI port. */ 2725 if (sc->bge_tbi) { 2726 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2727 return(EINVAL); 2728 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2729 case IFM_AUTO: 2730 break; 2731 case IFM_1000_SX: 2732 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2733 BGE_CLRBIT(sc, BGE_MAC_MODE, 2734 BGE_MACMODE_HALF_DUPLEX); 2735 } else { 2736 BGE_SETBIT(sc, BGE_MAC_MODE, 2737 BGE_MACMODE_HALF_DUPLEX); 2738 } 2739 break; 2740 default: 2741 return(EINVAL); 2742 } 2743 return(0); 2744 } 2745 2746 mii = device_get_softc(sc->bge_miibus); 2747 sc->bge_link = 0; 2748 if (mii->mii_instance) { 2749 struct mii_softc *miisc; 2750 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2751 miisc = LIST_NEXT(miisc, mii_list)) 2752 mii_phy_reset(miisc); 2753 } 2754 mii_mediachg(mii); 2755 2756 return(0); 2757 } 2758 2759 /* 2760 * Report current media status. 2761 */ 2762 static void 2763 bge_ifmedia_sts(ifp, ifmr) 2764 struct ifnet *ifp; 2765 struct ifmediareq *ifmr; 2766 { 2767 struct bge_softc *sc; 2768 struct mii_data *mii; 2769 2770 sc = ifp->if_softc; 2771 2772 if (sc->bge_tbi) { 2773 ifmr->ifm_status = IFM_AVALID; 2774 ifmr->ifm_active = IFM_ETHER; 2775 if (CSR_READ_4(sc, BGE_MAC_STS) & 2776 BGE_MACSTAT_TBI_PCS_SYNCHED) 2777 ifmr->ifm_status |= IFM_ACTIVE; 2778 ifmr->ifm_active |= IFM_1000_SX; 2779 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2780 ifmr->ifm_active |= IFM_HDX; 2781 else 2782 ifmr->ifm_active |= IFM_FDX; 2783 return; 2784 } 2785 2786 mii = device_get_softc(sc->bge_miibus); 2787 mii_pollstat(mii); 2788 ifmr->ifm_active = mii->mii_media_active; 2789 ifmr->ifm_status = mii->mii_media_status; 2790 2791 return; 2792 } 2793 2794 static int 2795 bge_ioctl(ifp, command, data) 2796 struct ifnet *ifp; 2797 u_long command; 2798 caddr_t data; 2799 { 2800 struct bge_softc *sc = ifp->if_softc; 2801 struct ifreq *ifr = (struct ifreq *) data; 2802 int s, mask, error = 0; 2803 struct mii_data *mii; 2804 2805 s = splimp(); 2806 2807 switch(command) { 2808 case SIOCSIFADDR: 2809 case SIOCGIFADDR: 2810 error = ether_ioctl(ifp, command, data); 2811 break; 2812 case SIOCSIFMTU: 2813 /* Disallow jumbo frames on 5705. */ 2814 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2815 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU) 2816 error = EINVAL; 2817 else { 2818 ifp->if_mtu = ifr->ifr_mtu; 2819 ifp->if_flags &= ~IFF_RUNNING; 2820 bge_init(sc); 2821 } 2822 break; 2823 case SIOCSIFFLAGS: 2824 if (ifp->if_flags & IFF_UP) { 2825 /* 2826 * If only the state of the PROMISC flag changed, 2827 * then just use the 'set promisc mode' command 2828 * instead of reinitializing the entire NIC. Doing 2829 * a full re-init means reloading the firmware and 2830 * waiting for it to start up, which may take a 2831 * second or two. 2832 */ 2833 if (ifp->if_flags & IFF_RUNNING && 2834 ifp->if_flags & IFF_PROMISC && 2835 !(sc->bge_if_flags & IFF_PROMISC)) { 2836 BGE_SETBIT(sc, BGE_RX_MODE, 2837 BGE_RXMODE_RX_PROMISC); 2838 } else if (ifp->if_flags & IFF_RUNNING && 2839 !(ifp->if_flags & IFF_PROMISC) && 2840 sc->bge_if_flags & IFF_PROMISC) { 2841 BGE_CLRBIT(sc, BGE_RX_MODE, 2842 BGE_RXMODE_RX_PROMISC); 2843 } else 2844 bge_init(sc); 2845 } else { 2846 if (ifp->if_flags & IFF_RUNNING) { 2847 bge_stop(sc); 2848 } 2849 } 2850 sc->bge_if_flags = ifp->if_flags; 2851 error = 0; 2852 break; 2853 case SIOCADDMULTI: 2854 case SIOCDELMULTI: 2855 if (ifp->if_flags & IFF_RUNNING) { 2856 bge_setmulti(sc); 2857 error = 0; 2858 } 2859 break; 2860 case SIOCSIFMEDIA: 2861 case SIOCGIFMEDIA: 2862 if (sc->bge_tbi) { 2863 error = ifmedia_ioctl(ifp, ifr, 2864 &sc->bge_ifmedia, command); 2865 } else { 2866 mii = device_get_softc(sc->bge_miibus); 2867 error = ifmedia_ioctl(ifp, ifr, 2868 &mii->mii_media, command); 2869 } 2870 break; 2871 case SIOCSIFCAP: 2872 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2873 if (mask & IFCAP_HWCSUM) { 2874 if (IFCAP_HWCSUM & ifp->if_capenable) 2875 ifp->if_capenable &= ~IFCAP_HWCSUM; 2876 else 2877 ifp->if_capenable |= IFCAP_HWCSUM; 2878 } 2879 error = 0; 2880 break; 2881 default: 2882 error = EINVAL; 2883 break; 2884 } 2885 2886 (void)splx(s); 2887 2888 return(error); 2889 } 2890 2891 static void 2892 bge_watchdog(ifp) 2893 struct ifnet *ifp; 2894 { 2895 struct bge_softc *sc; 2896 2897 sc = ifp->if_softc; 2898 2899 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2900 2901 ifp->if_flags &= ~IFF_RUNNING; 2902 bge_init(sc); 2903 2904 ifp->if_oerrors++; 2905 2906 return; 2907 } 2908 2909 /* 2910 * Stop the adapter and free any mbufs allocated to the 2911 * RX and TX lists. 2912 */ 2913 static void 2914 bge_stop(sc) 2915 struct bge_softc *sc; 2916 { 2917 struct ifnet *ifp; 2918 struct ifmedia_entry *ifm; 2919 struct mii_data *mii = NULL; 2920 int mtmp, itmp; 2921 2922 ifp = &sc->arpcom.ac_if; 2923 2924 if (!sc->bge_tbi) 2925 mii = device_get_softc(sc->bge_miibus); 2926 2927 untimeout(bge_tick, sc, sc->bge_stat_ch); 2928 2929 /* 2930 * Disable all of the receiver blocks 2931 */ 2932 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2933 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2934 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2935 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2936 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2937 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2938 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2939 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2940 2941 /* 2942 * Disable all of the transmit blocks 2943 */ 2944 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2945 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2946 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2947 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2948 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2949 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2950 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2951 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2952 2953 /* 2954 * Shut down all of the memory managers and related 2955 * state machines. 2956 */ 2957 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2958 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2959 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2960 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2961 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2962 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2963 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2964 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2965 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2966 } 2967 2968 /* Disable host interrupts. */ 2969 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2970 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2971 2972 /* 2973 * Tell firmware we're shutting down. 2974 */ 2975 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2976 2977 /* Free the RX lists. */ 2978 bge_free_rx_ring_std(sc); 2979 2980 /* Free jumbo RX list. */ 2981 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2982 bge_free_rx_ring_jumbo(sc); 2983 2984 /* Free TX buffers. */ 2985 bge_free_tx_ring(sc); 2986 2987 /* 2988 * Isolate/power down the PHY, but leave the media selection 2989 * unchanged so that things will be put back to normal when 2990 * we bring the interface back up. 2991 */ 2992 if (!sc->bge_tbi) { 2993 itmp = ifp->if_flags; 2994 ifp->if_flags |= IFF_UP; 2995 ifm = mii->mii_media.ifm_cur; 2996 mtmp = ifm->ifm_media; 2997 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2998 mii_mediachg(mii); 2999 ifm->ifm_media = mtmp; 3000 ifp->if_flags = itmp; 3001 } 3002 3003 sc->bge_link = 0; 3004 3005 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3006 3007 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3008 3009 return; 3010 } 3011 3012 /* 3013 * Stop all chip I/O so that the kernel's probe routines don't 3014 * get confused by errant DMAs when rebooting. 3015 */ 3016 static void 3017 bge_shutdown(dev) 3018 device_t dev; 3019 { 3020 struct bge_softc *sc; 3021 3022 sc = device_get_softc(dev); 3023 3024 bge_stop(sc); 3025 bge_reset(sc); 3026 3027 return; 3028 } 3029