1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $ 34 */ 35 36 /* 37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Engineer, Wind River Systems 41 */ 42 43 /* 44 * The Broadcom BCM5700 is based on technology originally developed by 45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 49 * frames, highly configurable RX filtering, and 16 RX and TX queues 50 * (which, along with RX filter rules, can be used for QOS applications). 51 * Other features, such as TCP segmentation, may be available as part 52 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 53 * firmware images can be stored in hardware and need not be compiled 54 * into the driver. 55 * 56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 58 * 59 * The BCM5701 is a single-chip solution incorporating both the BCM5700 60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 61 * does not support external SSRAM. 62 * 63 * Broadcom also produces a variation of the BCM5700 under the "Altima" 64 * brand name, which is functionally similar but lacks PCI-X support. 65 * 66 * Without external SSRAM, you can only have at most 4 TX rings, 67 * and the use of the mini RX ring is disabled. This seems to imply 68 * that these features are simply not available on the BCM5701. As a 69 * result, this driver does not implement any support for the mini RX 70 * ring. 71 */ 72 73 #include "opt_ifpoll.h" 74 75 #include <sys/param.h> 76 #include <sys/bus.h> 77 #include <sys/endian.h> 78 #include <sys/kernel.h> 79 #include <sys/ktr.h> 80 #include <sys/interrupt.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/queue.h> 84 #include <sys/rman.h> 85 #include <sys/serialize.h> 86 #include <sys/socket.h> 87 #include <sys/sockio.h> 88 #include <sys/sysctl.h> 89 90 #include <netinet/ip.h> 91 #include <netinet/tcp.h> 92 93 #include <net/bpf.h> 94 #include <net/ethernet.h> 95 #include <net/if.h> 96 #include <net/if_arp.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 #include <net/if_poll.h> 100 #include <net/if_types.h> 101 #include <net/ifq_var.h> 102 #include <net/vlan/if_vlan_var.h> 103 #include <net/vlan/if_vlan_ether.h> 104 105 #include <dev/netif/mii_layer/mii.h> 106 #include <dev/netif/mii_layer/miivar.h> 107 #include <dev/netif/mii_layer/brgphyreg.h> 108 109 #include <bus/pci/pcidevs.h> 110 #include <bus/pci/pcireg.h> 111 #include <bus/pci/pcivar.h> 112 113 #include <dev/netif/bge/if_bgereg.h> 114 #include <dev/netif/bge/if_bgevar.h> 115 116 /* "device miibus" required. See GENERIC if you get errors here. */ 117 #include "miibus_if.h" 118 119 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 120 121 static const struct bge_type { 122 uint16_t bge_vid; 123 uint16_t bge_did; 124 char *bge_name; 125 } bge_devs[] = { 126 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996, 127 "3COM 3C996 Gigabit Ethernet" }, 128 129 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700, 130 "Alteon BCM5700 Gigabit Ethernet" }, 131 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701, 132 "Alteon BCM5701 Gigabit Ethernet" }, 133 134 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000, 135 "Altima AC1000 Gigabit Ethernet" }, 136 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001, 137 "Altima AC1002 Gigabit Ethernet" }, 138 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100, 139 "Altima AC9100 Gigabit Ethernet" }, 140 141 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701, 142 "Apple BCM5701 Gigabit Ethernet" }, 143 144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700, 145 "Broadcom BCM5700 Gigabit Ethernet" }, 146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701, 147 "Broadcom BCM5701 Gigabit Ethernet" }, 148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702, 149 "Broadcom BCM5702 Gigabit Ethernet" }, 150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X, 151 "Broadcom BCM5702X Gigabit Ethernet" }, 152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT, 153 "Broadcom BCM5702 Gigabit Ethernet" }, 154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703, 155 "Broadcom BCM5703 Gigabit Ethernet" }, 156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X, 157 "Broadcom BCM5703X Gigabit Ethernet" }, 158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3, 159 "Broadcom BCM5703 Gigabit Ethernet" }, 160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C, 161 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S, 163 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT, 165 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705, 167 "Broadcom BCM5705 Gigabit Ethernet" }, 168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F, 169 "Broadcom BCM5705F Gigabit Ethernet" }, 170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K, 171 "Broadcom BCM5705K Gigabit Ethernet" }, 172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M, 173 "Broadcom BCM5705M Gigabit Ethernet" }, 174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 175 "Broadcom BCM5705M Gigabit Ethernet" }, 176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714, 177 "Broadcom BCM5714C Gigabit Ethernet" }, 178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S, 179 "Broadcom BCM5714S Gigabit Ethernet" }, 180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715, 181 "Broadcom BCM5715 Gigabit Ethernet" }, 182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S, 183 "Broadcom BCM5715S Gigabit Ethernet" }, 184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720, 185 "Broadcom BCM5720 Gigabit Ethernet" }, 186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721, 187 "Broadcom BCM5721 Gigabit Ethernet" }, 188 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722, 189 "Broadcom BCM5722 Gigabit Ethernet" }, 190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723, 191 "Broadcom BCM5723 Gigabit Ethernet" }, 192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750, 193 "Broadcom BCM5750 Gigabit Ethernet" }, 194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M, 195 "Broadcom BCM5750M Gigabit Ethernet" }, 196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751, 197 "Broadcom BCM5751 Gigabit Ethernet" }, 198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F, 199 "Broadcom BCM5751F Gigabit Ethernet" }, 200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M, 201 "Broadcom BCM5751M Gigabit Ethernet" }, 202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752, 203 "Broadcom BCM5752 Gigabit Ethernet" }, 204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M, 205 "Broadcom BCM5752M Gigabit Ethernet" }, 206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753, 207 "Broadcom BCM5753 Gigabit Ethernet" }, 208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F, 209 "Broadcom BCM5753F Gigabit Ethernet" }, 210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M, 211 "Broadcom BCM5753M Gigabit Ethernet" }, 212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754, 213 "Broadcom BCM5754 Gigabit Ethernet" }, 214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M, 215 "Broadcom BCM5754M Gigabit Ethernet" }, 216 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755, 217 "Broadcom BCM5755 Gigabit Ethernet" }, 218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M, 219 "Broadcom BCM5755M Gigabit Ethernet" }, 220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756, 221 "Broadcom BCM5756 Gigabit Ethernet" }, 222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761, 223 "Broadcom BCM5761 Gigabit Ethernet" }, 224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E, 225 "Broadcom BCM5761E Gigabit Ethernet" }, 226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S, 227 "Broadcom BCM5761S Gigabit Ethernet" }, 228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE, 229 "Broadcom BCM5761SE Gigabit Ethernet" }, 230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764, 231 "Broadcom BCM5764 Gigabit Ethernet" }, 232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780, 233 "Broadcom BCM5780 Gigabit Ethernet" }, 234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S, 235 "Broadcom BCM5780S Gigabit Ethernet" }, 236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781, 237 "Broadcom BCM5781 Gigabit Ethernet" }, 238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782, 239 "Broadcom BCM5782 Gigabit Ethernet" }, 240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784, 241 "Broadcom BCM5784 Gigabit Ethernet" }, 242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F, 243 "Broadcom BCM5785F Gigabit Ethernet" }, 244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G, 245 "Broadcom BCM5785G Gigabit Ethernet" }, 246 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786, 247 "Broadcom BCM5786 Gigabit Ethernet" }, 248 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787, 249 "Broadcom BCM5787 Gigabit Ethernet" }, 250 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F, 251 "Broadcom BCM5787F Gigabit Ethernet" }, 252 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M, 253 "Broadcom BCM5787M Gigabit Ethernet" }, 254 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788, 255 "Broadcom BCM5788 Gigabit Ethernet" }, 256 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789, 257 "Broadcom BCM5789 Gigabit Ethernet" }, 258 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901, 259 "Broadcom BCM5901 Fast Ethernet" }, 260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2, 261 "Broadcom BCM5901A2 Fast Ethernet" }, 262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M, 263 "Broadcom BCM5903M Fast Ethernet" }, 264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906, 265 "Broadcom BCM5906 Fast Ethernet"}, 266 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M, 267 "Broadcom BCM5906M Fast Ethernet"}, 268 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760, 269 "Broadcom BCM57760 Gigabit Ethernet"}, 270 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780, 271 "Broadcom BCM57780 Gigabit Ethernet"}, 272 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788, 273 "Broadcom BCM57788 Gigabit Ethernet"}, 274 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790, 275 "Broadcom BCM57790 Gigabit Ethernet"}, 276 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 277 "SysKonnect Gigabit Ethernet" }, 278 279 { 0, 0, NULL } 280 }; 281 282 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 283 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 284 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 285 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 286 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 287 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 288 #define BGE_IS_5788(sc) ((sc)->bge_flags & BGE_FLAG_5788) 289 290 #define BGE_IS_CRIPPLED(sc) \ 291 (BGE_IS_5788((sc)) || (sc)->bge_asicrev == BGE_ASICREV_BCM5700) 292 293 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 294 295 static int bge_probe(device_t); 296 static int bge_attach(device_t); 297 static int bge_detach(device_t); 298 static void bge_txeof(struct bge_softc *, uint16_t); 299 static void bge_rxeof(struct bge_softc *, uint16_t, int); 300 301 static void bge_tick(void *); 302 static void bge_stats_update(struct bge_softc *); 303 static void bge_stats_update_regs(struct bge_softc *); 304 static struct mbuf * 305 bge_defrag_shortdma(struct mbuf *); 306 static int bge_encap(struct bge_softc *, struct mbuf **, 307 uint32_t *, int *); 308 static void bge_xmit(struct bge_softc *, uint32_t); 309 static int bge_setup_tso(struct bge_softc *, struct mbuf **, 310 uint16_t *, uint16_t *); 311 312 #ifdef IFPOLL_ENABLE 313 static void bge_npoll(struct ifnet *, struct ifpoll_info *); 314 static void bge_npoll_compat(struct ifnet *, void *, int ); 315 #endif 316 static void bge_intr_crippled(void *); 317 static void bge_intr_legacy(void *); 318 static void bge_msi(void *); 319 static void bge_msi_oneshot(void *); 320 static void bge_intr(struct bge_softc *); 321 static void bge_enable_intr(struct bge_softc *); 322 static void bge_disable_intr(struct bge_softc *); 323 static void bge_start(struct ifnet *); 324 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 325 static void bge_init(void *); 326 static void bge_stop(struct bge_softc *); 327 static void bge_watchdog(struct ifnet *); 328 static void bge_shutdown(device_t); 329 static int bge_suspend(device_t); 330 static int bge_resume(device_t); 331 static int bge_ifmedia_upd(struct ifnet *); 332 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 333 334 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 335 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 336 337 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *); 338 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t); 339 340 static void bge_setmulti(struct bge_softc *); 341 static void bge_setpromisc(struct bge_softc *); 342 static void bge_enable_msi(struct bge_softc *sc); 343 344 static int bge_alloc_jumbo_mem(struct bge_softc *); 345 static void bge_free_jumbo_mem(struct bge_softc *); 346 static struct bge_jslot 347 *bge_jalloc(struct bge_softc *); 348 static void bge_jfree(void *); 349 static void bge_jref(void *); 350 static int bge_newbuf_std(struct bge_softc *, int, int); 351 static int bge_newbuf_jumbo(struct bge_softc *, int, int); 352 static void bge_setup_rxdesc_std(struct bge_softc *, int); 353 static void bge_setup_rxdesc_jumbo(struct bge_softc *, int); 354 static int bge_init_rx_ring_std(struct bge_softc *); 355 static void bge_free_rx_ring_std(struct bge_softc *); 356 static int bge_init_rx_ring_jumbo(struct bge_softc *); 357 static void bge_free_rx_ring_jumbo(struct bge_softc *); 358 static void bge_free_tx_ring(struct bge_softc *); 359 static int bge_init_tx_ring(struct bge_softc *); 360 361 static int bge_chipinit(struct bge_softc *); 362 static int bge_blockinit(struct bge_softc *); 363 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 364 365 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t); 366 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t); 367 #ifdef notdef 368 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t); 369 #endif 370 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t); 371 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t); 372 static void bge_writembx(struct bge_softc *, int, int); 373 374 static int bge_miibus_readreg(device_t, int, int); 375 static int bge_miibus_writereg(device_t, int, int, int); 376 static void bge_miibus_statchg(device_t); 377 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t); 378 static void bge_tbi_link_upd(struct bge_softc *, uint32_t); 379 static void bge_copper_link_upd(struct bge_softc *, uint32_t); 380 static void bge_autopoll_link_upd(struct bge_softc *, uint32_t); 381 static void bge_link_poll(struct bge_softc *); 382 383 static void bge_reset(struct bge_softc *); 384 385 static int bge_dma_alloc(struct bge_softc *); 386 static void bge_dma_free(struct bge_softc *); 387 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t, 388 bus_dma_tag_t *, bus_dmamap_t *, 389 void **, bus_addr_t *); 390 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *); 391 392 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 393 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 394 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 395 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 396 397 static void bge_coal_change(struct bge_softc *); 398 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS); 399 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS); 400 static int bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS); 401 static int bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS); 402 static int bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS); 403 static int bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS); 404 static int bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS); 405 static int bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS); 406 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, 407 int, int, uint32_t); 408 409 /* 410 * Set following tunable to 1 for some IBM blade servers with the DNLK 411 * switch module. Auto negotiation is broken for those configurations. 412 */ 413 static int bge_fake_autoneg = 0; 414 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg); 415 416 static int bge_msi_enable = 1; 417 TUNABLE_INT("hw.bge.msi.enable", &bge_msi_enable); 418 419 #if !defined(KTR_IF_BGE) 420 #define KTR_IF_BGE KTR_ALL 421 #endif 422 KTR_INFO_MASTER(if_bge); 423 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr"); 424 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt"); 425 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt"); 426 #define logif(name) KTR_LOG(if_bge_ ## name) 427 428 static device_method_t bge_methods[] = { 429 /* Device interface */ 430 DEVMETHOD(device_probe, bge_probe), 431 DEVMETHOD(device_attach, bge_attach), 432 DEVMETHOD(device_detach, bge_detach), 433 DEVMETHOD(device_shutdown, bge_shutdown), 434 DEVMETHOD(device_suspend, bge_suspend), 435 DEVMETHOD(device_resume, bge_resume), 436 437 /* bus interface */ 438 DEVMETHOD(bus_print_child, bus_generic_print_child), 439 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 440 441 /* MII interface */ 442 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 443 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 444 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 445 446 { 0, 0 } 447 }; 448 449 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc)); 450 static devclass_t bge_devclass; 451 452 DECLARE_DUMMY_MODULE(if_bge); 453 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL); 454 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL); 455 456 static uint32_t 457 bge_readmem_ind(struct bge_softc *sc, uint32_t off) 458 { 459 device_t dev = sc->bge_dev; 460 uint32_t val; 461 462 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 463 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 464 return 0; 465 466 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 467 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 468 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 469 return (val); 470 } 471 472 static void 473 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val) 474 { 475 device_t dev = sc->bge_dev; 476 477 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 478 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 479 return; 480 481 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 482 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 483 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 484 } 485 486 #ifdef notdef 487 static uint32_t 488 bge_readreg_ind(struct bge_softc *sc, uin32_t off) 489 { 490 device_t dev = sc->bge_dev; 491 492 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 493 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 494 } 495 #endif 496 497 static void 498 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val) 499 { 500 device_t dev = sc->bge_dev; 501 502 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 503 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 504 } 505 506 static void 507 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val) 508 { 509 CSR_WRITE_4(sc, off, val); 510 } 511 512 static void 513 bge_writembx(struct bge_softc *sc, int off, int val) 514 { 515 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 516 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 517 518 CSR_WRITE_4(sc, off, val); 519 if (sc->bge_mbox_reorder) 520 CSR_READ_4(sc, off); 521 } 522 523 static uint8_t 524 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 525 { 526 uint32_t access, byte = 0; 527 int i; 528 529 /* Lock. */ 530 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 531 for (i = 0; i < 8000; i++) { 532 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 533 break; 534 DELAY(20); 535 } 536 if (i == 8000) 537 return (1); 538 539 /* Enable access. */ 540 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 541 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 542 543 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 544 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 545 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 546 DELAY(10); 547 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 548 DELAY(10); 549 break; 550 } 551 } 552 553 if (i == BGE_TIMEOUT * 10) { 554 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n"); 555 return (1); 556 } 557 558 /* Get result. */ 559 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 560 561 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 562 563 /* Disable access. */ 564 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 565 566 /* Unlock. */ 567 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 568 CSR_READ_4(sc, BGE_NVRAM_SWARB); 569 570 return (0); 571 } 572 573 /* 574 * Read a sequence of bytes from NVRAM. 575 */ 576 static int 577 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 578 { 579 int err = 0, i; 580 uint8_t byte = 0; 581 582 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 583 return (1); 584 585 for (i = 0; i < cnt; i++) { 586 err = bge_nvram_getbyte(sc, off + i, &byte); 587 if (err) 588 break; 589 *(dest + i) = byte; 590 } 591 592 return (err ? 1 : 0); 593 } 594 595 /* 596 * Read a byte of data stored in the EEPROM at address 'addr.' The 597 * BCM570x supports both the traditional bitbang interface and an 598 * auto access interface for reading the EEPROM. We use the auto 599 * access method. 600 */ 601 static uint8_t 602 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest) 603 { 604 int i; 605 uint32_t byte = 0; 606 607 /* 608 * Enable use of auto EEPROM access so we can avoid 609 * having to use the bitbang method. 610 */ 611 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 612 613 /* Reset the EEPROM, load the clock period. */ 614 CSR_WRITE_4(sc, BGE_EE_ADDR, 615 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 616 DELAY(20); 617 618 /* Issue the read EEPROM command. */ 619 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 620 621 /* Wait for completion */ 622 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 623 DELAY(10); 624 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 625 break; 626 } 627 628 if (i == BGE_TIMEOUT) { 629 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n"); 630 return(1); 631 } 632 633 /* Get result. */ 634 byte = CSR_READ_4(sc, BGE_EE_DATA); 635 636 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 637 638 return(0); 639 } 640 641 /* 642 * Read a sequence of bytes from the EEPROM. 643 */ 644 static int 645 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len) 646 { 647 size_t i; 648 int err; 649 uint8_t byte; 650 651 for (byte = 0, err = 0, i = 0; i < len; i++) { 652 err = bge_eeprom_getbyte(sc, off + i, &byte); 653 if (err) 654 break; 655 *(dest + i) = byte; 656 } 657 658 return(err ? 1 : 0); 659 } 660 661 static int 662 bge_miibus_readreg(device_t dev, int phy, int reg) 663 { 664 struct bge_softc *sc = device_get_softc(dev); 665 uint32_t val; 666 int i; 667 668 KASSERT(phy == sc->bge_phyno, 669 ("invalid phyno %d, should be %d", phy, sc->bge_phyno)); 670 671 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 672 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 673 CSR_WRITE_4(sc, BGE_MI_MODE, 674 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 675 DELAY(80); 676 } 677 678 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 679 BGE_MIPHY(phy) | BGE_MIREG(reg)); 680 681 /* Poll for the PHY register access to complete. */ 682 for (i = 0; i < BGE_TIMEOUT; i++) { 683 DELAY(10); 684 val = CSR_READ_4(sc, BGE_MI_COMM); 685 if ((val & BGE_MICOMM_BUSY) == 0) { 686 DELAY(5); 687 val = CSR_READ_4(sc, BGE_MI_COMM); 688 break; 689 } 690 } 691 if (i == BGE_TIMEOUT) { 692 if_printf(&sc->arpcom.ac_if, "PHY read timed out " 693 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val); 694 val = 0; 695 } 696 697 /* Restore the autopoll bit if necessary. */ 698 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 699 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 700 DELAY(80); 701 } 702 703 if (val & BGE_MICOMM_READFAIL) 704 return 0; 705 706 return (val & 0xFFFF); 707 } 708 709 static int 710 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 711 { 712 struct bge_softc *sc = device_get_softc(dev); 713 int i; 714 715 KASSERT(phy == sc->bge_phyno, 716 ("invalid phyno %d, should be %d", phy, sc->bge_phyno)); 717 718 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 719 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 720 return 0; 721 722 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 723 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 724 CSR_WRITE_4(sc, BGE_MI_MODE, 725 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 726 DELAY(80); 727 } 728 729 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 730 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 731 732 for (i = 0; i < BGE_TIMEOUT; i++) { 733 DELAY(10); 734 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 735 DELAY(5); 736 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 737 break; 738 } 739 } 740 if (i == BGE_TIMEOUT) { 741 if_printf(&sc->arpcom.ac_if, "PHY write timed out " 742 "(phy %d, reg %d, val %d)\n", phy, reg, val); 743 } 744 745 /* Restore the autopoll bit if necessary. */ 746 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 747 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 748 DELAY(80); 749 } 750 751 return 0; 752 } 753 754 static void 755 bge_miibus_statchg(device_t dev) 756 { 757 struct bge_softc *sc; 758 struct mii_data *mii; 759 760 sc = device_get_softc(dev); 761 mii = device_get_softc(sc->bge_miibus); 762 763 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 764 (IFM_ACTIVE | IFM_AVALID)) { 765 switch (IFM_SUBTYPE(mii->mii_media_active)) { 766 case IFM_10_T: 767 case IFM_100_TX: 768 sc->bge_link = 1; 769 break; 770 case IFM_1000_T: 771 case IFM_1000_SX: 772 case IFM_2500_SX: 773 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 774 sc->bge_link = 1; 775 else 776 sc->bge_link = 0; 777 break; 778 default: 779 sc->bge_link = 0; 780 break; 781 } 782 } else { 783 sc->bge_link = 0; 784 } 785 if (sc->bge_link == 0) 786 return; 787 788 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 789 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 790 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 791 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 792 } else { 793 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 794 } 795 796 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 797 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 798 } else { 799 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 800 } 801 } 802 803 /* 804 * Memory management for jumbo frames. 805 */ 806 static int 807 bge_alloc_jumbo_mem(struct bge_softc *sc) 808 { 809 struct ifnet *ifp = &sc->arpcom.ac_if; 810 struct bge_jslot *entry; 811 uint8_t *ptr; 812 bus_addr_t paddr; 813 int i, error; 814 815 /* 816 * Create tag for jumbo mbufs. 817 * This is really a bit of a kludge. We allocate a special 818 * jumbo buffer pool which (thanks to the way our DMA 819 * memory allocation works) will consist of contiguous 820 * pages. This means that even though a jumbo buffer might 821 * be larger than a page size, we don't really need to 822 * map it into more than one DMA segment. However, the 823 * default mbuf tag will result in multi-segment mappings, 824 * so we have to create a special jumbo mbuf tag that 825 * lets us get away with mapping the jumbo buffers as 826 * a single segment. I think eventually the driver should 827 * be changed so that it uses ordinary mbufs and cluster 828 * buffers, i.e. jumbo frames can span multiple DMA 829 * descriptors. But that's a project for another day. 830 */ 831 832 /* 833 * Create DMA stuffs for jumbo RX ring. 834 */ 835 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ, 836 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 837 &sc->bge_cdata.bge_rx_jumbo_ring_map, 838 (void *)&sc->bge_ldata.bge_rx_jumbo_ring, 839 &sc->bge_ldata.bge_rx_jumbo_ring_paddr); 840 if (error) { 841 if_printf(ifp, "could not create jumbo RX ring\n"); 842 return error; 843 } 844 845 /* 846 * Create DMA stuffs for jumbo buffer block. 847 */ 848 error = bge_dma_block_alloc(sc, BGE_JMEM, 849 &sc->bge_cdata.bge_jumbo_tag, 850 &sc->bge_cdata.bge_jumbo_map, 851 (void **)&sc->bge_ldata.bge_jumbo_buf, 852 &paddr); 853 if (error) { 854 if_printf(ifp, "could not create jumbo buffer\n"); 855 return error; 856 } 857 858 SLIST_INIT(&sc->bge_jfree_listhead); 859 860 /* 861 * Now divide it up into 9K pieces and save the addresses 862 * in an array. Note that we play an evil trick here by using 863 * the first few bytes in the buffer to hold the the address 864 * of the softc structure for this interface. This is because 865 * bge_jfree() needs it, but it is called by the mbuf management 866 * code which will not pass it to us explicitly. 867 */ 868 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) { 869 entry = &sc->bge_cdata.bge_jslots[i]; 870 entry->bge_sc = sc; 871 entry->bge_buf = ptr; 872 entry->bge_paddr = paddr; 873 entry->bge_inuse = 0; 874 entry->bge_slot = i; 875 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link); 876 877 ptr += BGE_JLEN; 878 paddr += BGE_JLEN; 879 } 880 return 0; 881 } 882 883 static void 884 bge_free_jumbo_mem(struct bge_softc *sc) 885 { 886 /* Destroy jumbo RX ring. */ 887 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 888 sc->bge_cdata.bge_rx_jumbo_ring_map, 889 sc->bge_ldata.bge_rx_jumbo_ring); 890 891 /* Destroy jumbo buffer block. */ 892 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag, 893 sc->bge_cdata.bge_jumbo_map, 894 sc->bge_ldata.bge_jumbo_buf); 895 } 896 897 /* 898 * Allocate a jumbo buffer. 899 */ 900 static struct bge_jslot * 901 bge_jalloc(struct bge_softc *sc) 902 { 903 struct bge_jslot *entry; 904 905 lwkt_serialize_enter(&sc->bge_jslot_serializer); 906 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 907 if (entry) { 908 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link); 909 entry->bge_inuse = 1; 910 } else { 911 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n"); 912 } 913 lwkt_serialize_exit(&sc->bge_jslot_serializer); 914 return(entry); 915 } 916 917 /* 918 * Adjust usage count on a jumbo buffer. 919 */ 920 static void 921 bge_jref(void *arg) 922 { 923 struct bge_jslot *entry = (struct bge_jslot *)arg; 924 struct bge_softc *sc = entry->bge_sc; 925 926 if (sc == NULL) 927 panic("bge_jref: can't find softc pointer!"); 928 929 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) { 930 panic("bge_jref: asked to reference buffer " 931 "that we don't manage!"); 932 } else if (entry->bge_inuse == 0) { 933 panic("bge_jref: buffer already free!"); 934 } else { 935 atomic_add_int(&entry->bge_inuse, 1); 936 } 937 } 938 939 /* 940 * Release a jumbo buffer. 941 */ 942 static void 943 bge_jfree(void *arg) 944 { 945 struct bge_jslot *entry = (struct bge_jslot *)arg; 946 struct bge_softc *sc = entry->bge_sc; 947 948 if (sc == NULL) 949 panic("bge_jfree: can't find softc pointer!"); 950 951 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) { 952 panic("bge_jfree: asked to free buffer that we don't manage!"); 953 } else if (entry->bge_inuse == 0) { 954 panic("bge_jfree: buffer already free!"); 955 } else { 956 /* 957 * Possible MP race to 0, use the serializer. The atomic insn 958 * is still needed for races against bge_jref(). 959 */ 960 lwkt_serialize_enter(&sc->bge_jslot_serializer); 961 atomic_subtract_int(&entry->bge_inuse, 1); 962 if (entry->bge_inuse == 0) { 963 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 964 entry, jslot_link); 965 } 966 lwkt_serialize_exit(&sc->bge_jslot_serializer); 967 } 968 } 969 970 971 /* 972 * Intialize a standard receive ring descriptor. 973 */ 974 static int 975 bge_newbuf_std(struct bge_softc *sc, int i, int init) 976 { 977 struct mbuf *m_new = NULL; 978 bus_dma_segment_t seg; 979 bus_dmamap_t map; 980 int error, nsegs; 981 982 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 983 if (m_new == NULL) 984 return ENOBUFS; 985 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 986 987 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 988 m_adj(m_new, ETHER_ALIGN); 989 990 error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag, 991 sc->bge_cdata.bge_rx_tmpmap, m_new, 992 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 993 if (error) { 994 m_freem(m_new); 995 return error; 996 } 997 998 if (!init) { 999 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1000 sc->bge_cdata.bge_rx_std_dmamap[i], 1001 BUS_DMASYNC_POSTREAD); 1002 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1003 sc->bge_cdata.bge_rx_std_dmamap[i]); 1004 } 1005 1006 map = sc->bge_cdata.bge_rx_tmpmap; 1007 sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i]; 1008 sc->bge_cdata.bge_rx_std_dmamap[i] = map; 1009 1010 sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new; 1011 sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr; 1012 1013 bge_setup_rxdesc_std(sc, i); 1014 return 0; 1015 } 1016 1017 static void 1018 bge_setup_rxdesc_std(struct bge_softc *sc, int i) 1019 { 1020 struct bge_rxchain *rc; 1021 struct bge_rx_bd *r; 1022 1023 rc = &sc->bge_cdata.bge_rx_std_chain[i]; 1024 r = &sc->bge_ldata.bge_rx_std_ring[i]; 1025 1026 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr); 1027 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr); 1028 r->bge_len = rc->bge_mbuf->m_len; 1029 r->bge_idx = i; 1030 r->bge_flags = BGE_RXBDFLAG_END; 1031 } 1032 1033 /* 1034 * Initialize a jumbo receive ring descriptor. This allocates 1035 * a jumbo buffer from the pool managed internally by the driver. 1036 */ 1037 static int 1038 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init) 1039 { 1040 struct mbuf *m_new = NULL; 1041 struct bge_jslot *buf; 1042 bus_addr_t paddr; 1043 1044 /* Allocate the mbuf. */ 1045 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 1046 if (m_new == NULL) 1047 return ENOBUFS; 1048 1049 /* Allocate the jumbo buffer */ 1050 buf = bge_jalloc(sc); 1051 if (buf == NULL) { 1052 m_freem(m_new); 1053 return ENOBUFS; 1054 } 1055 1056 /* Attach the buffer to the mbuf. */ 1057 m_new->m_ext.ext_arg = buf; 1058 m_new->m_ext.ext_buf = buf->bge_buf; 1059 m_new->m_ext.ext_free = bge_jfree; 1060 m_new->m_ext.ext_ref = bge_jref; 1061 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1062 1063 m_new->m_flags |= M_EXT; 1064 1065 m_new->m_data = m_new->m_ext.ext_buf; 1066 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 1067 1068 paddr = buf->bge_paddr; 1069 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) { 1070 m_adj(m_new, ETHER_ALIGN); 1071 paddr += ETHER_ALIGN; 1072 } 1073 1074 /* Save necessary information */ 1075 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new; 1076 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr; 1077 1078 /* Set up the descriptor. */ 1079 bge_setup_rxdesc_jumbo(sc, i); 1080 return 0; 1081 } 1082 1083 static void 1084 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i) 1085 { 1086 struct bge_rx_bd *r; 1087 struct bge_rxchain *rc; 1088 1089 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 1090 rc = &sc->bge_cdata.bge_rx_jumbo_chain[i]; 1091 1092 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr); 1093 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr); 1094 r->bge_len = rc->bge_mbuf->m_len; 1095 r->bge_idx = i; 1096 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1097 } 1098 1099 static int 1100 bge_init_rx_ring_std(struct bge_softc *sc) 1101 { 1102 int i, error; 1103 1104 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1105 error = bge_newbuf_std(sc, i, 1); 1106 if (error) 1107 return error; 1108 } 1109 1110 sc->bge_std = BGE_STD_RX_RING_CNT - 1; 1111 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1112 1113 return(0); 1114 } 1115 1116 static void 1117 bge_free_rx_ring_std(struct bge_softc *sc) 1118 { 1119 int i; 1120 1121 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1122 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i]; 1123 1124 if (rc->bge_mbuf != NULL) { 1125 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1126 sc->bge_cdata.bge_rx_std_dmamap[i]); 1127 m_freem(rc->bge_mbuf); 1128 rc->bge_mbuf = NULL; 1129 } 1130 bzero(&sc->bge_ldata.bge_rx_std_ring[i], 1131 sizeof(struct bge_rx_bd)); 1132 } 1133 } 1134 1135 static int 1136 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1137 { 1138 struct bge_rcb *rcb; 1139 int i, error; 1140 1141 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1142 error = bge_newbuf_jumbo(sc, i, 1); 1143 if (error) 1144 return error; 1145 } 1146 1147 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1; 1148 1149 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1150 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 1151 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1152 1153 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1154 1155 return(0); 1156 } 1157 1158 static void 1159 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1160 { 1161 int i; 1162 1163 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1164 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i]; 1165 1166 if (rc->bge_mbuf != NULL) { 1167 m_freem(rc->bge_mbuf); 1168 rc->bge_mbuf = NULL; 1169 } 1170 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i], 1171 sizeof(struct bge_rx_bd)); 1172 } 1173 } 1174 1175 static void 1176 bge_free_tx_ring(struct bge_softc *sc) 1177 { 1178 int i; 1179 1180 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1181 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1182 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1183 sc->bge_cdata.bge_tx_dmamap[i]); 1184 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1185 sc->bge_cdata.bge_tx_chain[i] = NULL; 1186 } 1187 bzero(&sc->bge_ldata.bge_tx_ring[i], 1188 sizeof(struct bge_tx_bd)); 1189 } 1190 } 1191 1192 static int 1193 bge_init_tx_ring(struct bge_softc *sc) 1194 { 1195 sc->bge_txcnt = 0; 1196 sc->bge_tx_saved_considx = 0; 1197 sc->bge_tx_prodidx = 0; 1198 1199 /* Initialize transmit producer index for host-memory send ring. */ 1200 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1201 1202 /* 5700 b2 errata */ 1203 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1204 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1205 1206 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1207 /* 5700 b2 errata */ 1208 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1209 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1210 1211 return(0); 1212 } 1213 1214 static void 1215 bge_setmulti(struct bge_softc *sc) 1216 { 1217 struct ifnet *ifp; 1218 struct ifmultiaddr *ifma; 1219 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1220 int h, i; 1221 1222 ifp = &sc->arpcom.ac_if; 1223 1224 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1225 for (i = 0; i < 4; i++) 1226 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1227 return; 1228 } 1229 1230 /* First, zot all the existing filters. */ 1231 for (i = 0; i < 4; i++) 1232 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1233 1234 /* Now program new ones. */ 1235 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1236 if (ifma->ifma_addr->sa_family != AF_LINK) 1237 continue; 1238 h = ether_crc32_le( 1239 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1240 ETHER_ADDR_LEN) & 0x7f; 1241 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1242 } 1243 1244 for (i = 0; i < 4; i++) 1245 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1246 } 1247 1248 /* 1249 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1250 * self-test results. 1251 */ 1252 static int 1253 bge_chipinit(struct bge_softc *sc) 1254 { 1255 int i; 1256 uint32_t dma_rw_ctl; 1257 uint16_t val; 1258 1259 /* Set endian type before we access any non-PCI registers. */ 1260 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1261 BGE_INIT | sc->bge_pci_miscctl, 4); 1262 1263 /* Clear the MAC control register */ 1264 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1265 1266 /* 1267 * Clear the MAC statistics block in the NIC's 1268 * internal memory. 1269 */ 1270 for (i = BGE_STATS_BLOCK; 1271 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1272 BGE_MEMWIN_WRITE(sc, i, 0); 1273 1274 for (i = BGE_STATUS_BLOCK; 1275 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1276 BGE_MEMWIN_WRITE(sc, i, 0); 1277 1278 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1279 /* 1280 * Fix data corruption caused by non-qword write with WB. 1281 * Fix master abort in PCI mode. 1282 * Fix PCI latency timer. 1283 */ 1284 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1285 val |= (1 << 10) | (1 << 12) | (1 << 13); 1286 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1287 } 1288 1289 /* Set up the PCI DMA control register. */ 1290 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1291 if (sc->bge_flags & BGE_FLAG_PCIE) { 1292 /* PCI-E bus */ 1293 /* DMA read watermark not used on PCI-E */ 1294 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1295 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1296 /* PCI-X bus */ 1297 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) { 1298 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1299 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1300 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1301 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5714) { 1302 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1303 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1304 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1305 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1306 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1307 uint32_t rd_wat = 0x7; 1308 uint32_t clkctl; 1309 1310 clkctl = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1311 if ((sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) && 1312 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1313 dma_rw_ctl |= 1314 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1315 } else if (clkctl == 0x6 || clkctl == 0x7) { 1316 dma_rw_ctl |= 1317 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1318 } 1319 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) 1320 rd_wat = 0x4; 1321 1322 dma_rw_ctl |= (rd_wat << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1323 (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1324 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1325 } else { 1326 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1327 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1328 dma_rw_ctl |= 0xf; 1329 } 1330 } else { 1331 /* Conventional PCI bus */ 1332 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1333 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1334 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1335 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1336 dma_rw_ctl |= 0xf; 1337 } 1338 1339 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1340 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1341 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1342 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1343 sc->bge_asicrev == BGE_ASICREV_BCM5701) { 1344 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1345 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1346 } 1347 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1348 1349 /* 1350 * Set up general mode register. 1351 */ 1352 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1353 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1354 BGE_MODECTL_TX_NO_PHDR_CSUM); 1355 1356 /* 1357 * BCM5701 B5 have a bug causing data corruption when using 1358 * 64-bit DMA reads, which can be terminated early and then 1359 * completed later as 32-bit accesses, in combination with 1360 * certain bridges. 1361 */ 1362 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1363 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1364 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1365 1366 /* 1367 * Disable memory write invalidate. Apparently it is not supported 1368 * properly by these devices. Also ensure that INTx isn't disabled, 1369 * as these chips need it even when using MSI. 1370 */ 1371 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1372 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4); 1373 1374 /* Set the timer prescaler (always 66Mhz) */ 1375 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1376 1377 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1378 DELAY(40); /* XXX */ 1379 1380 /* Put PHY into ready state */ 1381 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1382 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1383 DELAY(40); 1384 } 1385 1386 return(0); 1387 } 1388 1389 static int 1390 bge_blockinit(struct bge_softc *sc) 1391 { 1392 struct bge_rcb *rcb; 1393 bus_size_t vrcb; 1394 bge_hostaddr taddr; 1395 uint32_t val; 1396 int i, limit; 1397 1398 /* 1399 * Initialize the memory window pointer register so that 1400 * we can access the first 32K of internal NIC RAM. This will 1401 * allow us to set up the TX send ring RCBs and the RX return 1402 * ring RCBs, plus other things which live in NIC memory. 1403 */ 1404 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1405 1406 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1407 1408 if (!BGE_IS_5705_PLUS(sc)) { 1409 /* Configure mbuf memory pool */ 1410 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1411 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1412 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1413 else 1414 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1415 1416 /* Configure DMA resource pool */ 1417 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1418 BGE_DMA_DESCRIPTORS); 1419 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1420 } 1421 1422 /* Configure mbuf pool watermarks */ 1423 if (!BGE_IS_5705_PLUS(sc)) { 1424 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1425 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1426 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1427 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1428 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1429 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1430 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1431 } else { 1432 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1433 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1434 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1435 } 1436 1437 /* Configure DMA resource watermarks */ 1438 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1439 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1440 1441 /* Enable buffer manager */ 1442 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1443 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1444 1445 /* Poll for buffer manager start indication */ 1446 for (i = 0; i < BGE_TIMEOUT; i++) { 1447 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1448 break; 1449 DELAY(10); 1450 } 1451 1452 if (i == BGE_TIMEOUT) { 1453 if_printf(&sc->arpcom.ac_if, 1454 "buffer manager failed to start\n"); 1455 return(ENXIO); 1456 } 1457 1458 /* Enable flow-through queues */ 1459 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1460 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1461 1462 /* Wait until queue initialization is complete */ 1463 for (i = 0; i < BGE_TIMEOUT; i++) { 1464 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1465 break; 1466 DELAY(10); 1467 } 1468 1469 if (i == BGE_TIMEOUT) { 1470 if_printf(&sc->arpcom.ac_if, 1471 "flow-through queue init failed\n"); 1472 return(ENXIO); 1473 } 1474 1475 /* 1476 * Summary of rings supported by the controller: 1477 * 1478 * Standard Receive Producer Ring 1479 * - This ring is used to feed receive buffers for "standard" 1480 * sized frames (typically 1536 bytes) to the controller. 1481 * 1482 * Jumbo Receive Producer Ring 1483 * - This ring is used to feed receive buffers for jumbo sized 1484 * frames (i.e. anything bigger than the "standard" frames) 1485 * to the controller. 1486 * 1487 * Mini Receive Producer Ring 1488 * - This ring is used to feed receive buffers for "mini" 1489 * sized frames to the controller. 1490 * - This feature required external memory for the controller 1491 * but was never used in a production system. Should always 1492 * be disabled. 1493 * 1494 * Receive Return Ring 1495 * - After the controller has placed an incoming frame into a 1496 * receive buffer that buffer is moved into a receive return 1497 * ring. The driver is then responsible to passing the 1498 * buffer up to the stack. Many versions of the controller 1499 * support multiple RR rings. 1500 * 1501 * Send Ring 1502 * - This ring is used for outgoing frames. Many versions of 1503 * the controller support multiple send rings. 1504 */ 1505 1506 /* Initialize the standard receive producer ring control block. */ 1507 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1508 rcb->bge_hostaddr.bge_addr_lo = 1509 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1510 rcb->bge_hostaddr.bge_addr_hi = 1511 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1512 if (BGE_IS_5705_PLUS(sc)) { 1513 /* 1514 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 1515 * Bits 15-2 : Reserved (should be 0) 1516 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1517 * Bit 0 : Reserved 1518 */ 1519 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1520 } else { 1521 /* 1522 * Ring size is always XXX entries 1523 * Bits 31-16: Maximum RX frame size 1524 * Bits 15-2 : Reserved (should be 0) 1525 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1526 * Bit 0 : Reserved 1527 */ 1528 rcb->bge_maxlen_flags = 1529 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1530 } 1531 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1532 /* Write the standard receive producer ring control block. */ 1533 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1534 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1535 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1536 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1537 /* Reset the standard receive producer ring producer index. */ 1538 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1539 1540 /* 1541 * Initialize the jumbo RX producer ring control 1542 * block. We set the 'ring disabled' bit in the 1543 * flags field until we're actually ready to start 1544 * using this ring (i.e. once we set the MTU 1545 * high enough to require it). 1546 */ 1547 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1548 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1549 /* Get the jumbo receive producer ring RCB parameters. */ 1550 rcb->bge_hostaddr.bge_addr_lo = 1551 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1552 rcb->bge_hostaddr.bge_addr_hi = 1553 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1554 rcb->bge_maxlen_flags = 1555 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1556 BGE_RCB_FLAG_RING_DISABLED); 1557 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1558 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1559 rcb->bge_hostaddr.bge_addr_hi); 1560 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1561 rcb->bge_hostaddr.bge_addr_lo); 1562 /* Program the jumbo receive producer ring RCB parameters. */ 1563 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1564 rcb->bge_maxlen_flags); 1565 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1566 /* Reset the jumbo receive producer ring producer index. */ 1567 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1568 } 1569 1570 /* Disable the mini receive producer ring RCB. */ 1571 if (BGE_IS_5700_FAMILY(sc)) { 1572 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1573 rcb->bge_maxlen_flags = 1574 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1575 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1576 rcb->bge_maxlen_flags); 1577 /* Reset the mini receive producer ring producer index. */ 1578 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1579 } 1580 1581 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 1582 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1583 (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 1584 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 1585 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) { 1586 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 1587 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 1588 } 1589 1590 /* 1591 * The BD ring replenish thresholds control how often the 1592 * hardware fetches new BD's from the producer rings in host 1593 * memory. Setting the value too low on a busy system can 1594 * starve the hardware and recue the throughpout. 1595 * 1596 * Set the BD ring replentish thresholds. The recommended 1597 * values are 1/8th the number of descriptors allocated to 1598 * each ring. 1599 */ 1600 if (BGE_IS_5705_PLUS(sc)) 1601 val = 8; 1602 else 1603 val = BGE_STD_RX_RING_CNT / 8; 1604 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1605 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1606 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1607 BGE_JUMBO_RX_RING_CNT/8); 1608 } 1609 1610 /* 1611 * Disable all send rings by setting the 'ring disabled' bit 1612 * in the flags field of all the TX send ring control blocks, 1613 * located in NIC memory. 1614 */ 1615 if (!BGE_IS_5705_PLUS(sc)) { 1616 /* 5700 to 5704 had 16 send rings. */ 1617 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 1618 } else { 1619 limit = 1; 1620 } 1621 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1622 for (i = 0; i < limit; i++) { 1623 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1624 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1625 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1626 vrcb += sizeof(struct bge_rcb); 1627 } 1628 1629 /* Configure send ring RCB 0 (we use only the first ring) */ 1630 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1631 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1632 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1633 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1634 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1635 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1636 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1637 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1638 1639 /* 1640 * Disable all receive return rings by setting the 1641 * 'ring diabled' bit in the flags field of all the receive 1642 * return ring control blocks, located in NIC memory. 1643 */ 1644 if (!BGE_IS_5705_PLUS(sc)) 1645 limit = BGE_RX_RINGS_MAX; 1646 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755) 1647 limit = 4; 1648 else 1649 limit = 1; 1650 /* Disable all receive return rings. */ 1651 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1652 for (i = 0; i < limit; i++) { 1653 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1654 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1655 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1656 BGE_RCB_FLAG_RING_DISABLED); 1657 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1658 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1659 (i * (sizeof(uint64_t))), 0); 1660 vrcb += sizeof(struct bge_rcb); 1661 } 1662 1663 /* 1664 * Set up receive return ring 0. Note that the NIC address 1665 * for RX return rings is 0x0. The return rings live entirely 1666 * within the host, so the nicaddr field in the RCB isn't used. 1667 */ 1668 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1669 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1670 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1671 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1672 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1673 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1674 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1675 1676 /* Set random backoff seed for TX */ 1677 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1678 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1679 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1680 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1681 BGE_TX_BACKOFF_SEED_MASK); 1682 1683 /* Set inter-packet gap */ 1684 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1685 1686 /* 1687 * Specify which ring to use for packets that don't match 1688 * any RX rules. 1689 */ 1690 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1691 1692 /* 1693 * Configure number of RX lists. One interrupt distribution 1694 * list, sixteen active lists, one bad frames class. 1695 */ 1696 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1697 1698 /* Inialize RX list placement stats mask. */ 1699 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1700 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1701 1702 /* Disable host coalescing until we get it set up */ 1703 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1704 1705 /* Poll to make sure it's shut down. */ 1706 for (i = 0; i < BGE_TIMEOUT; i++) { 1707 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1708 break; 1709 DELAY(10); 1710 } 1711 1712 if (i == BGE_TIMEOUT) { 1713 if_printf(&sc->arpcom.ac_if, 1714 "host coalescing engine failed to idle\n"); 1715 return(ENXIO); 1716 } 1717 1718 /* Set up host coalescing defaults */ 1719 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1720 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1721 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds); 1722 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds); 1723 if (!BGE_IS_5705_PLUS(sc)) { 1724 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 1725 sc->bge_rx_coal_ticks_int); 1726 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 1727 sc->bge_tx_coal_ticks_int); 1728 } 1729 /* 1730 * NOTE: 1731 * The datasheet (57XX-PG105-R) says BCM5705+ do not 1732 * have following two registers; obviously it is wrong. 1733 */ 1734 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int); 1735 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int); 1736 1737 /* Set up address of statistics block */ 1738 if (!BGE_IS_5705_PLUS(sc)) { 1739 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1740 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1741 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1742 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1743 1744 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1745 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1746 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1747 } 1748 1749 /* Set up address of status block */ 1750 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 1751 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1752 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1753 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1754 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1755 1756 /* 1757 * Set up status block partail update size. 1758 * 1759 * Because only single TX ring, RX produce ring and Rx return ring 1760 * are used, ask device to update only minimum part of status block 1761 * except for BCM5700 AX/BX, whose status block partial update size 1762 * can't be configured. 1763 */ 1764 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1765 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 1766 /* XXX Actually reserved on BCM5700 AX/BX */ 1767 val = BGE_STATBLKSZ_FULL; 1768 } else { 1769 val = BGE_STATBLKSZ_32BYTE; 1770 } 1771 #if 0 1772 /* 1773 * Does not seem to have visible effect in both 1774 * bulk data (1472B UDP datagram) and tiny data 1775 * (18B UDP datagram) TX tests. 1776 */ 1777 if (!BGE_IS_CRIPPLED(sc)) 1778 val |= BGE_HCCMODE_CLRTICK_TX; 1779 #endif 1780 1781 /* Turn on host coalescing state machine */ 1782 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 1783 1784 /* Turn on RX BD completion state machine and enable attentions */ 1785 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1786 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1787 1788 /* Turn on RX list placement state machine */ 1789 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1790 1791 /* Turn on RX list selector state machine. */ 1792 if (!BGE_IS_5705_PLUS(sc)) 1793 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1794 1795 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 1796 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 1797 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 1798 BGE_MACMODE_FRMHDR_DMA_ENB; 1799 1800 if (sc->bge_flags & BGE_FLAG_TBI) 1801 val |= BGE_PORTMODE_TBI; 1802 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 1803 val |= BGE_PORTMODE_GMII; 1804 else 1805 val |= BGE_PORTMODE_MII; 1806 1807 /* Turn on DMA, clear stats */ 1808 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 1809 1810 /* Set misc. local control, enable interrupts on attentions */ 1811 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1812 1813 #ifdef notdef 1814 /* Assert GPIO pins for PHY reset */ 1815 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1816 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1817 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1818 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1819 #endif 1820 1821 /* Turn on DMA completion state machine */ 1822 if (!BGE_IS_5705_PLUS(sc)) 1823 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1824 1825 /* Turn on write DMA state machine */ 1826 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 1827 if (BGE_IS_5755_PLUS(sc)) { 1828 /* Enable host coalescing bug fix. */ 1829 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1830 } 1831 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) { 1832 /* Request larger DMA burst size to get better performance. */ 1833 val |= BGE_WDMAMODE_BURST_ALL_DATA; 1834 } 1835 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1836 DELAY(40); 1837 1838 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 1839 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1840 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1841 sc->bge_asicrev == BGE_ASICREV_BCM57780) { 1842 /* 1843 * Enable fix for read DMA FIFO overruns. 1844 * The fix is to limit the number of RX BDs 1845 * the hardware would fetch at a fime. 1846 */ 1847 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 1848 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, 1849 val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 1850 } 1851 1852 /* Turn on read DMA state machine */ 1853 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1854 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1855 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1856 sc->bge_asicrev == BGE_ASICREV_BCM57780) 1857 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1858 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1859 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 1860 if (sc->bge_flags & BGE_FLAG_PCIE) 1861 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1862 if (sc->bge_flags & BGE_FLAG_TSO) 1863 val |= BGE_RDMAMODE_TSO4_ENABLE; 1864 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1865 DELAY(40); 1866 1867 /* Turn on RX data completion state machine */ 1868 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1869 1870 /* Turn on RX BD initiator state machine */ 1871 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1872 1873 /* Turn on RX data and RX BD initiator state machine */ 1874 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1875 1876 /* Turn on Mbuf cluster free state machine */ 1877 if (!BGE_IS_5705_PLUS(sc)) 1878 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1879 1880 /* Turn on send BD completion state machine */ 1881 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1882 1883 /* Turn on send data completion state machine */ 1884 val = BGE_SDCMODE_ENABLE; 1885 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 1886 val |= BGE_SDCMODE_CDELAY; 1887 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 1888 1889 /* Turn on send data initiator state machine */ 1890 if (sc->bge_flags & BGE_FLAG_TSO) 1891 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 1892 BGE_SDIMODE_HW_LSO_PRE_DMA); 1893 else 1894 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1895 1896 /* Turn on send BD initiator state machine */ 1897 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1898 1899 /* Turn on send BD selector state machine */ 1900 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1901 1902 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1903 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1904 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1905 1906 /* ack/clear link change events */ 1907 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1908 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1909 BGE_MACSTAT_LINK_CHANGED); 1910 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1911 1912 /* 1913 * Enable attention when the link has changed state for 1914 * devices that use auto polling. 1915 */ 1916 if (sc->bge_flags & BGE_FLAG_TBI) { 1917 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1918 } else { 1919 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 1920 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1921 DELAY(80); 1922 } 1923 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1924 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 1925 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1926 BGE_EVTENB_MI_INTERRUPT); 1927 } 1928 } 1929 1930 /* 1931 * Clear any pending link state attention. 1932 * Otherwise some link state change events may be lost until attention 1933 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence. 1934 * It's not necessary on newer BCM chips - perhaps enabling link 1935 * state change attentions implies clearing pending attention. 1936 */ 1937 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1938 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1939 BGE_MACSTAT_LINK_CHANGED); 1940 1941 /* Enable link state change attentions. */ 1942 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1943 1944 return(0); 1945 } 1946 1947 /* 1948 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1949 * against our list and return its name if we find a match. Note 1950 * that since the Broadcom controller contains VPD support, we 1951 * can get the device name string from the controller itself instead 1952 * of the compiled-in string. This is a little slow, but it guarantees 1953 * we'll always announce the right product name. 1954 */ 1955 static int 1956 bge_probe(device_t dev) 1957 { 1958 const struct bge_type *t; 1959 uint16_t product, vendor; 1960 1961 product = pci_get_device(dev); 1962 vendor = pci_get_vendor(dev); 1963 1964 for (t = bge_devs; t->bge_name != NULL; t++) { 1965 if (vendor == t->bge_vid && product == t->bge_did) 1966 break; 1967 } 1968 if (t->bge_name == NULL) 1969 return(ENXIO); 1970 1971 device_set_desc(dev, t->bge_name); 1972 return(0); 1973 } 1974 1975 static int 1976 bge_attach(device_t dev) 1977 { 1978 struct ifnet *ifp; 1979 struct bge_softc *sc; 1980 uint32_t hwcfg = 0, misccfg; 1981 int error = 0, rid, capmask; 1982 uint8_t ether_addr[ETHER_ADDR_LEN]; 1983 uint16_t product, vendor; 1984 driver_intr_t *intr_func; 1985 uintptr_t mii_priv = 0; 1986 u_int intr_flags; 1987 int msi_enable; 1988 1989 sc = device_get_softc(dev); 1990 sc->bge_dev = dev; 1991 callout_init_mp(&sc->bge_stat_timer); 1992 lwkt_serialize_init(&sc->bge_jslot_serializer); 1993 1994 product = pci_get_device(dev); 1995 vendor = pci_get_vendor(dev); 1996 1997 #ifndef BURN_BRIDGES 1998 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1999 uint32_t irq, mem; 2000 2001 irq = pci_read_config(dev, PCIR_INTLINE, 4); 2002 mem = pci_read_config(dev, BGE_PCI_BAR0, 4); 2003 2004 device_printf(dev, "chip is in D%d power mode " 2005 "-- setting to D0\n", pci_get_powerstate(dev)); 2006 2007 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2008 2009 pci_write_config(dev, PCIR_INTLINE, irq, 4); 2010 pci_write_config(dev, BGE_PCI_BAR0, mem, 4); 2011 } 2012 #endif /* !BURN_BRIDGE */ 2013 2014 /* 2015 * Map control/status registers. 2016 */ 2017 pci_enable_busmaster(dev); 2018 2019 rid = BGE_PCI_BAR0; 2020 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2021 RF_ACTIVE); 2022 2023 if (sc->bge_res == NULL) { 2024 device_printf(dev, "couldn't map memory\n"); 2025 return ENXIO; 2026 } 2027 2028 sc->bge_btag = rman_get_bustag(sc->bge_res); 2029 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2030 2031 /* Save various chip information */ 2032 sc->bge_chipid = 2033 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2034 BGE_PCIMISCCTL_ASICREV_SHIFT; 2035 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2036 /* All chips, which use BGE_PCI_PRODID_ASICREV, have CPMU */ 2037 sc->bge_flags |= BGE_FLAG_CPMU; 2038 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2039 } 2040 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2041 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2042 2043 /* Save chipset family. */ 2044 switch (sc->bge_asicrev) { 2045 case BGE_ASICREV_BCM5755: 2046 case BGE_ASICREV_BCM5761: 2047 case BGE_ASICREV_BCM5784: 2048 case BGE_ASICREV_BCM5785: 2049 case BGE_ASICREV_BCM5787: 2050 case BGE_ASICREV_BCM57780: 2051 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2052 BGE_FLAG_5705_PLUS; 2053 break; 2054 2055 case BGE_ASICREV_BCM5700: 2056 case BGE_ASICREV_BCM5701: 2057 case BGE_ASICREV_BCM5703: 2058 case BGE_ASICREV_BCM5704: 2059 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2060 break; 2061 2062 case BGE_ASICREV_BCM5714_A0: 2063 case BGE_ASICREV_BCM5780: 2064 case BGE_ASICREV_BCM5714: 2065 sc->bge_flags |= BGE_FLAG_5714_FAMILY; 2066 /* Fall through */ 2067 2068 case BGE_ASICREV_BCM5750: 2069 case BGE_ASICREV_BCM5752: 2070 case BGE_ASICREV_BCM5906: 2071 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2072 /* Fall through */ 2073 2074 case BGE_ASICREV_BCM5705: 2075 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2076 break; 2077 } 2078 2079 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 2080 sc->bge_flags |= BGE_FLAG_NO_EEPROM; 2081 2082 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 2083 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2084 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2085 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2086 sc->bge_flags |= BGE_FLAG_5788; 2087 2088 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 2089 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 2090 sc->bge_flags |= BGE_FLAG_SHORTDMA; 2091 2092 /* 2093 * Check if this is a PCI-X or PCI Express device. 2094 */ 2095 if (BGE_IS_5705_PLUS(sc)) { 2096 if (pci_is_pcie(dev)) { 2097 sc->bge_flags |= BGE_FLAG_PCIE; 2098 sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev); 2099 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096); 2100 } 2101 } else { 2102 /* 2103 * Check if the device is in PCI-X Mode. 2104 * (This bit is not valid on PCI Express controllers.) 2105 */ 2106 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 2107 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2108 sc->bge_flags |= BGE_FLAG_PCIX; 2109 sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev); 2110 sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev, 2111 "mbox_reorder", 0); 2112 } 2113 } 2114 device_printf(dev, "CHIP ID 0x%08x; " 2115 "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 2116 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 2117 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" 2118 : ((sc->bge_flags & BGE_FLAG_PCIE) ? 2119 "PCI-E" : "PCI")); 2120 2121 /* 2122 * The 40bit DMA bug applies to the 5714/5715 controllers and is 2123 * not actually a MAC controller bug but an issue with the embedded 2124 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 2125 */ 2126 if ((sc->bge_flags & BGE_FLAG_PCIX) && 2127 (BGE_IS_5714_FAMILY(sc) || device_getenv_int(dev, "dma40b", 0))) 2128 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT; 2129 2130 /* 2131 * When using the BCM5701 in PCI-X mode, data corruption has 2132 * been observed in the first few bytes of some received packets. 2133 * Aligning the packet buffer in memory eliminates the corruption. 2134 * Unfortunately, this misaligns the packet payloads. On platforms 2135 * which do not support unaligned accesses, we will realign the 2136 * payloads by copying the received packets. 2137 */ 2138 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2139 (sc->bge_flags & BGE_FLAG_PCIX)) 2140 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2141 2142 if (!BGE_IS_CRIPPLED(sc)) { 2143 if (device_getenv_int(dev, "status_tag", 1)) { 2144 sc->bge_flags |= BGE_FLAG_STATUS_TAG; 2145 sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS; 2146 if (bootverbose) 2147 device_printf(dev, "enable status tag\n"); 2148 } 2149 } 2150 2151 if (BGE_IS_5755_PLUS(sc)) { 2152 /* 2153 * BCM5754 and BCM5787 shares the same ASIC id so 2154 * explicit device id check is required. 2155 * Due to unknown reason TSO does not work on BCM5755M. 2156 */ 2157 if (product != PCI_PRODUCT_BROADCOM_BCM5754 && 2158 product != PCI_PRODUCT_BROADCOM_BCM5754M && 2159 product != PCI_PRODUCT_BROADCOM_BCM5755M) 2160 sc->bge_flags |= BGE_FLAG_TSO; 2161 } 2162 2163 /* 2164 * Set various PHY quirk flags. 2165 */ 2166 2167 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 || 2168 sc->bge_asicrev == BGE_ASICREV_BCM5701) && 2169 pci_get_subvendor(dev) == PCI_VENDOR_DELL) 2170 mii_priv |= BRGPHY_FLAG_NO_3LED; 2171 2172 capmask = MII_CAPMASK_DEFAULT; 2173 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 2174 (misccfg == 0x4000 || misccfg == 0x8000)) || 2175 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2176 vendor == PCI_VENDOR_BROADCOM && 2177 (product == PCI_PRODUCT_BROADCOM_BCM5901 || 2178 product == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2179 product == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2180 (vendor == PCI_VENDOR_BROADCOM && 2181 (product == PCI_PRODUCT_BROADCOM_BCM5751F || 2182 product == PCI_PRODUCT_BROADCOM_BCM5753F || 2183 product == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2184 product == PCI_PRODUCT_BROADCOM_BCM57790 || 2185 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2186 /* 10/100 only */ 2187 capmask &= ~BMSR_EXTSTAT; 2188 } 2189 2190 mii_priv |= BRGPHY_FLAG_WIRESPEED; 2191 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 2192 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2193 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2194 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2195 sc->bge_asicrev == BGE_ASICREV_BCM5906) 2196 mii_priv &= ~BRGPHY_FLAG_WIRESPEED; 2197 2198 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2199 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2200 mii_priv |= BRGPHY_FLAG_CRC_BUG; 2201 2202 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2203 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2204 mii_priv |= BRGPHY_FLAG_ADC_BUG; 2205 2206 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2207 mii_priv |= BRGPHY_FLAG_5704_A0; 2208 2209 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 2210 mii_priv |= BRGPHY_FLAG_5906; 2211 2212 if (BGE_IS_5705_PLUS(sc) && 2213 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2214 /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */ 2215 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 2216 /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */ 2217 sc->bge_asicrev != BGE_ASICREV_BCM57780) { 2218 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2219 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2220 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2221 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2222 if (product != PCI_PRODUCT_BROADCOM_BCM5722 && 2223 product != PCI_PRODUCT_BROADCOM_BCM5756) 2224 mii_priv |= BRGPHY_FLAG_JITTER_BUG; 2225 if (product == PCI_PRODUCT_BROADCOM_BCM5755M) 2226 mii_priv |= BRGPHY_FLAG_ADJUST_TRIM; 2227 } else { 2228 mii_priv |= BRGPHY_FLAG_BER_BUG; 2229 } 2230 } 2231 2232 /* 2233 * Allocate interrupt 2234 */ 2235 msi_enable = bge_msi_enable; 2236 if ((sc->bge_flags & BGE_FLAG_STATUS_TAG) == 0) { 2237 /* If "tagged status" is disabled, don't enable MSI */ 2238 msi_enable = 0; 2239 } else if (msi_enable) { 2240 msi_enable = 0; /* Disable by default */ 2241 if (BGE_IS_575X_PLUS(sc)) { 2242 msi_enable = 1; 2243 /* XXX we filter all 5714 chips */ 2244 if (sc->bge_asicrev == BGE_ASICREV_BCM5714 || 2245 (sc->bge_asicrev == BGE_ASICREV_BCM5750 && 2246 (sc->bge_chiprev == BGE_CHIPREV_5750_AX || 2247 sc->bge_chiprev == BGE_CHIPREV_5750_BX))) 2248 msi_enable = 0; 2249 else if (BGE_IS_5755_PLUS(sc) || 2250 sc->bge_asicrev == BGE_ASICREV_BCM5906) 2251 sc->bge_flags |= BGE_FLAG_ONESHOT_MSI; 2252 } 2253 } 2254 if (msi_enable) { 2255 if (pci_find_extcap(dev, PCIY_MSI, &sc->bge_msicap)) { 2256 device_printf(dev, "no MSI capability\n"); 2257 msi_enable = 0; 2258 } 2259 } 2260 2261 sc->bge_irq_type = pci_alloc_1intr(dev, msi_enable, &sc->bge_irq_rid, 2262 &intr_flags); 2263 2264 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bge_irq_rid, 2265 intr_flags); 2266 if (sc->bge_irq == NULL) { 2267 device_printf(dev, "couldn't map interrupt\n"); 2268 error = ENXIO; 2269 goto fail; 2270 } 2271 2272 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) 2273 bge_enable_msi(sc); 2274 else 2275 sc->bge_flags &= ~BGE_FLAG_ONESHOT_MSI; 2276 2277 /* Initialize if_name earlier, so if_printf could be used */ 2278 ifp = &sc->arpcom.ac_if; 2279 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2280 2281 /* Try to reset the chip. */ 2282 bge_reset(sc); 2283 2284 if (bge_chipinit(sc)) { 2285 device_printf(dev, "chip initialization failed\n"); 2286 error = ENXIO; 2287 goto fail; 2288 } 2289 2290 /* 2291 * Get station address 2292 */ 2293 error = bge_get_eaddr(sc, ether_addr); 2294 if (error) { 2295 device_printf(dev, "failed to read station address\n"); 2296 goto fail; 2297 } 2298 2299 /* 5705/5750 limits RX return ring to 512 entries. */ 2300 if (BGE_IS_5705_PLUS(sc)) 2301 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2302 else 2303 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2304 2305 error = bge_dma_alloc(sc); 2306 if (error) 2307 goto fail; 2308 2309 /* Set default tuneable values. */ 2310 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2311 sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF; 2312 sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF; 2313 sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF; 2314 sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF; 2315 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 2316 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF; 2317 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF; 2318 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF; 2319 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF; 2320 } else { 2321 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN; 2322 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN; 2323 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN; 2324 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN; 2325 } 2326 sc->bge_tx_wreg = 16; 2327 2328 /* Set up TX spare and reserved descriptor count */ 2329 if (sc->bge_flags & BGE_FLAG_TSO) { 2330 sc->bge_txspare = BGE_NSEG_SPARE_TSO; 2331 sc->bge_txrsvd = BGE_NSEG_RSVD_TSO; 2332 } else { 2333 sc->bge_txspare = BGE_NSEG_SPARE; 2334 sc->bge_txrsvd = BGE_NSEG_RSVD; 2335 } 2336 2337 /* Set up ifnet structure */ 2338 ifp->if_softc = sc; 2339 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2340 ifp->if_ioctl = bge_ioctl; 2341 ifp->if_start = bge_start; 2342 #ifdef IFPOLL_ENABLE 2343 ifp->if_npoll = bge_npoll; 2344 #endif 2345 ifp->if_watchdog = bge_watchdog; 2346 ifp->if_init = bge_init; 2347 ifp->if_mtu = ETHERMTU; 2348 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2349 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1); 2350 ifq_set_ready(&ifp->if_snd); 2351 2352 /* 2353 * 5700 B0 chips do not support checksumming correctly due 2354 * to hardware bugs. 2355 */ 2356 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) { 2357 ifp->if_capabilities |= IFCAP_HWCSUM; 2358 ifp->if_hwassist |= BGE_CSUM_FEATURES; 2359 } 2360 if (sc->bge_flags & BGE_FLAG_TSO) { 2361 ifp->if_capabilities |= IFCAP_TSO; 2362 ifp->if_hwassist |= CSUM_TSO; 2363 } 2364 ifp->if_capenable = ifp->if_capabilities; 2365 2366 /* 2367 * Figure out what sort of media we have by checking the 2368 * hardware config word in the first 32k of NIC internal memory, 2369 * or fall back to examining the EEPROM if necessary. 2370 * Note: on some BCM5700 cards, this value appears to be unset. 2371 * If that's the case, we have to rely on identifying the NIC 2372 * by its PCI subsystem ID, as we do below for the SysKonnect 2373 * SK-9D41. 2374 */ 2375 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2376 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2377 } else { 2378 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2379 sizeof(hwcfg))) { 2380 device_printf(dev, "failed to read EEPROM\n"); 2381 error = ENXIO; 2382 goto fail; 2383 } 2384 hwcfg = ntohl(hwcfg); 2385 } 2386 2387 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2388 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 || 2389 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2390 if (BGE_IS_5714_FAMILY(sc)) 2391 sc->bge_flags |= BGE_FLAG_MII_SERDES; 2392 else 2393 sc->bge_flags |= BGE_FLAG_TBI; 2394 } 2395 2396 /* Setup MI MODE */ 2397 if (sc->bge_flags & BGE_FLAG_CPMU) 2398 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 2399 else 2400 sc->bge_mi_mode = BGE_MIMODE_BASE; 2401 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) { 2402 /* Enable auto polling for BCM570[0-5]. */ 2403 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 2404 } 2405 2406 /* Setup link status update stuffs */ 2407 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2408 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 2409 sc->bge_link_upd = bge_bcm5700_link_upd; 2410 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT; 2411 } else if (sc->bge_flags & BGE_FLAG_TBI) { 2412 sc->bge_link_upd = bge_tbi_link_upd; 2413 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED; 2414 } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2415 sc->bge_link_upd = bge_autopoll_link_upd; 2416 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED; 2417 } else { 2418 sc->bge_link_upd = bge_copper_link_upd; 2419 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED; 2420 } 2421 2422 /* 2423 * Broadcom's own driver always assumes the internal 2424 * PHY is at GMII address 1. On some chips, the PHY responds 2425 * to accesses at all addresses, which could cause us to 2426 * bogusly attach the PHY 32 times at probe type. Always 2427 * restricting the lookup to address 1 is simpler than 2428 * trying to figure out which chips revisions should be 2429 * special-cased. 2430 */ 2431 sc->bge_phyno = 1; 2432 2433 if (sc->bge_flags & BGE_FLAG_TBI) { 2434 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 2435 bge_ifmedia_upd, bge_ifmedia_sts); 2436 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2437 ifmedia_add(&sc->bge_ifmedia, 2438 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2439 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2440 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2441 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2442 } else { 2443 struct mii_probe_args mii_args; 2444 2445 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts); 2446 mii_args.mii_probemask = 1 << sc->bge_phyno; 2447 mii_args.mii_capmask = capmask; 2448 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY; 2449 mii_args.mii_priv = mii_priv; 2450 2451 error = mii_probe(dev, &sc->bge_miibus, &mii_args); 2452 if (error) { 2453 device_printf(dev, "MII without any PHY!\n"); 2454 goto fail; 2455 } 2456 } 2457 2458 /* 2459 * Create sysctl nodes. 2460 */ 2461 sysctl_ctx_init(&sc->bge_sysctl_ctx); 2462 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx, 2463 SYSCTL_STATIC_CHILDREN(_hw), 2464 OID_AUTO, 2465 device_get_nameunit(dev), 2466 CTLFLAG_RD, 0, ""); 2467 if (sc->bge_sysctl_tree == NULL) { 2468 device_printf(dev, "can't add sysctl node\n"); 2469 error = ENXIO; 2470 goto fail; 2471 } 2472 2473 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2474 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2475 OID_AUTO, "rx_coal_ticks", 2476 CTLTYPE_INT | CTLFLAG_RW, 2477 sc, 0, bge_sysctl_rx_coal_ticks, "I", 2478 "Receive coalescing ticks (usec)."); 2479 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2480 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2481 OID_AUTO, "tx_coal_ticks", 2482 CTLTYPE_INT | CTLFLAG_RW, 2483 sc, 0, bge_sysctl_tx_coal_ticks, "I", 2484 "Transmit coalescing ticks (usec)."); 2485 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2486 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2487 OID_AUTO, "rx_coal_bds", 2488 CTLTYPE_INT | CTLFLAG_RW, 2489 sc, 0, bge_sysctl_rx_coal_bds, "I", 2490 "Receive max coalesced BD count."); 2491 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2492 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2493 OID_AUTO, "tx_coal_bds", 2494 CTLTYPE_INT | CTLFLAG_RW, 2495 sc, 0, bge_sysctl_tx_coal_bds, "I", 2496 "Transmit max coalesced BD count."); 2497 2498 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx, 2499 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2500 OID_AUTO, "tx_wreg", CTLFLAG_RW, 2501 &sc->bge_tx_wreg, 0, 2502 "# of segments before writing to hardware register"); 2503 2504 if (sc->bge_flags & BGE_FLAG_PCIE) { 2505 /* 2506 * A common design characteristic for many Broadcom 2507 * client controllers is that they only support a 2508 * single outstanding DMA read operation on the PCIe 2509 * bus. This means that it will take twice as long to 2510 * fetch a TX frame that is split into header and 2511 * payload buffers as it does to fetch a single, 2512 * contiguous TX frame (2 reads vs. 1 read). For these 2513 * controllers, coalescing buffers to reduce the number 2514 * of memory reads is effective way to get maximum 2515 * performance(about 940Mbps). Without collapsing TX 2516 * buffers the maximum TCP bulk transfer performance 2517 * is about 850Mbps. However forcing coalescing mbufs 2518 * consumes a lot of CPU cycles, so leave it off by 2519 * default. 2520 */ 2521 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx, 2522 SYSCTL_CHILDREN(sc->bge_sysctl_tree), 2523 OID_AUTO, "force_defrag", CTLFLAG_RW, 2524 &sc->bge_force_defrag, 0, 2525 "Force defragment on TX path"); 2526 } 2527 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 2528 if (!BGE_IS_5705_PLUS(sc)) { 2529 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2530 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO, 2531 "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW, 2532 sc, 0, bge_sysctl_rx_coal_ticks_int, "I", 2533 "Receive coalescing ticks " 2534 "during interrupt (usec)."); 2535 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2536 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO, 2537 "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW, 2538 sc, 0, bge_sysctl_tx_coal_ticks_int, "I", 2539 "Transmit coalescing ticks " 2540 "during interrupt (usec)."); 2541 } 2542 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2543 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO, 2544 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW, 2545 sc, 0, bge_sysctl_rx_coal_bds_int, "I", 2546 "Receive max coalesced BD count during interrupt."); 2547 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx, 2548 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO, 2549 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW, 2550 sc, 0, bge_sysctl_tx_coal_bds_int, "I", 2551 "Transmit max coalesced BD count during interrupt."); 2552 } 2553 2554 /* 2555 * Call MI attach routine. 2556 */ 2557 ether_ifattach(ifp, ether_addr, NULL); 2558 2559 #ifdef IFPOLL_ENABLE 2560 /* Polling setup */ 2561 ifpoll_compat_setup(&sc->bge_npoll, 2562 &sc->bge_sysctl_ctx, sc->bge_sysctl_tree, device_get_unit(dev), 2563 ifp->if_serializer); 2564 #endif 2565 2566 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) { 2567 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 2568 intr_func = bge_msi_oneshot; 2569 if (bootverbose) 2570 device_printf(dev, "oneshot MSI\n"); 2571 } else { 2572 intr_func = bge_msi; 2573 } 2574 } else if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 2575 intr_func = bge_intr_legacy; 2576 } else { 2577 intr_func = bge_intr_crippled; 2578 } 2579 error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc, 2580 &sc->bge_intrhand, ifp->if_serializer); 2581 if (error) { 2582 ether_ifdetach(ifp); 2583 device_printf(dev, "couldn't set up irq\n"); 2584 goto fail; 2585 } 2586 2587 ifp->if_cpuid = rman_get_cpuid(sc->bge_irq); 2588 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 2589 2590 return(0); 2591 fail: 2592 bge_detach(dev); 2593 return(error); 2594 } 2595 2596 static int 2597 bge_detach(device_t dev) 2598 { 2599 struct bge_softc *sc = device_get_softc(dev); 2600 2601 if (device_is_attached(dev)) { 2602 struct ifnet *ifp = &sc->arpcom.ac_if; 2603 2604 lwkt_serialize_enter(ifp->if_serializer); 2605 bge_stop(sc); 2606 bge_reset(sc); 2607 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2608 lwkt_serialize_exit(ifp->if_serializer); 2609 2610 ether_ifdetach(ifp); 2611 } 2612 2613 if (sc->bge_flags & BGE_FLAG_TBI) 2614 ifmedia_removeall(&sc->bge_ifmedia); 2615 if (sc->bge_miibus) 2616 device_delete_child(dev, sc->bge_miibus); 2617 bus_generic_detach(dev); 2618 2619 if (sc->bge_irq != NULL) { 2620 bus_release_resource(dev, SYS_RES_IRQ, sc->bge_irq_rid, 2621 sc->bge_irq); 2622 } 2623 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) 2624 pci_release_msi(dev); 2625 2626 if (sc->bge_res != NULL) { 2627 bus_release_resource(dev, SYS_RES_MEMORY, 2628 BGE_PCI_BAR0, sc->bge_res); 2629 } 2630 2631 if (sc->bge_sysctl_tree != NULL) 2632 sysctl_ctx_free(&sc->bge_sysctl_ctx); 2633 2634 bge_dma_free(sc); 2635 2636 return 0; 2637 } 2638 2639 static void 2640 bge_reset(struct bge_softc *sc) 2641 { 2642 device_t dev; 2643 uint32_t cachesize, command, pcistate, reset; 2644 void (*write_op)(struct bge_softc *, uint32_t, uint32_t); 2645 int i, val = 0; 2646 2647 dev = sc->bge_dev; 2648 2649 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 2650 sc->bge_asicrev != BGE_ASICREV_BCM5906) { 2651 if (sc->bge_flags & BGE_FLAG_PCIE) 2652 write_op = bge_writemem_direct; 2653 else 2654 write_op = bge_writemem_ind; 2655 } else { 2656 write_op = bge_writereg_ind; 2657 } 2658 2659 /* Save some important PCI state. */ 2660 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2661 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2662 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2663 2664 pci_write_config(dev, BGE_PCI_MISC_CTL, 2665 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2666 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW| 2667 sc->bge_pci_miscctl, 4); 2668 2669 /* Disable fastboot on controllers that support it. */ 2670 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2671 BGE_IS_5755_PLUS(sc)) { 2672 if (bootverbose) 2673 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n"); 2674 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2675 } 2676 2677 /* 2678 * Write the magic number to SRAM at offset 0xB50. 2679 * When firmware finishes its initialization it will 2680 * write ~BGE_MAGIC_NUMBER to the same location. 2681 */ 2682 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2683 2684 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1); 2685 2686 /* XXX: Broadcom Linux driver. */ 2687 if (sc->bge_flags & BGE_FLAG_PCIE) { 2688 /* Force PCI-E 1.0a mode */ 2689 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 2690 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) == 2691 (BGE_PCIE_PHY_TSTCTL_PSCRAM | 2692 BGE_PCIE_PHY_TSTCTL_PCIE10)) { 2693 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL, 2694 BGE_PCIE_PHY_TSTCTL_PSCRAM); 2695 } 2696 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2697 /* Prevent PCIE link training during global reset */ 2698 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); 2699 reset |= (1<<29); 2700 } 2701 } 2702 2703 /* 2704 * Set GPHY Power Down Override to leave GPHY 2705 * powered up in D0 uninitialized. 2706 */ 2707 if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0) 2708 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 2709 2710 /* Issue global reset */ 2711 write_op(sc, BGE_MISC_CFG, reset); 2712 2713 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2714 uint32_t status, ctrl; 2715 2716 status = CSR_READ_4(sc, BGE_VCPU_STATUS); 2717 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2718 status | BGE_VCPU_STATUS_DRV_RESET); 2719 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2720 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2721 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2722 } 2723 2724 DELAY(1000); 2725 2726 /* XXX: Broadcom Linux driver. */ 2727 if (sc->bge_flags & BGE_FLAG_PCIE) { 2728 uint16_t devctl; 2729 2730 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2731 uint32_t v; 2732 2733 DELAY(500000); /* wait for link training to complete */ 2734 v = pci_read_config(dev, 0xc4, 4); 2735 pci_write_config(dev, 0xc4, v | (1<<15), 4); 2736 } 2737 2738 devctl = pci_read_config(dev, 2739 sc->bge_pciecap + PCIER_DEVCTRL, 2); 2740 2741 /* Disable no snoop and disable relaxed ordering. */ 2742 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP); 2743 2744 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */ 2745 if ((sc->bge_flags & BGE_FLAG_CPMU) == 0) { 2746 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK; 2747 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128; 2748 } 2749 2750 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL, 2751 devctl, 2); 2752 2753 /* Clear error status. */ 2754 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS, 2755 PCIEM_DEVSTS_CORR_ERR | 2756 PCIEM_DEVSTS_NFATAL_ERR | 2757 PCIEM_DEVSTS_FATAL_ERR | 2758 PCIEM_DEVSTS_UNSUPP_REQ, 2); 2759 } 2760 2761 /* Reset some of the PCI state that got zapped by reset */ 2762 pci_write_config(dev, BGE_PCI_MISC_CTL, 2763 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2764 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW| 2765 sc->bge_pci_miscctl, 4); 2766 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2767 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2768 write_op(sc, BGE_MISC_CFG, (65 << 1)); 2769 2770 /* 2771 * Disable PCI-X relaxed ordering to ensure status block update 2772 * comes first then packet buffer DMA. Otherwise driver may 2773 * read stale status block. 2774 */ 2775 if (sc->bge_flags & BGE_FLAG_PCIX) { 2776 uint16_t devctl; 2777 2778 devctl = pci_read_config(dev, 2779 sc->bge_pcixcap + PCIXR_COMMAND, 2); 2780 devctl &= ~PCIXM_COMMAND_ERO; 2781 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 2782 devctl &= ~PCIXM_COMMAND_MAX_READ; 2783 devctl |= PCIXM_COMMAND_MAX_READ_2048; 2784 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 2785 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 2786 PCIXM_COMMAND_MAX_READ); 2787 devctl |= PCIXM_COMMAND_MAX_READ_2048; 2788 } 2789 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 2790 devctl, 2); 2791 } 2792 2793 /* 2794 * Enable memory arbiter and re-enable MSI if necessary. 2795 */ 2796 if (BGE_IS_5714_FAMILY(sc)) { 2797 uint32_t val; 2798 2799 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) { 2800 /* 2801 * Resetting BCM5714 family will clear MSI 2802 * enable bit; restore it after resetting. 2803 */ 2804 PCI_SETBIT(sc->bge_dev, sc->bge_msicap + PCIR_MSI_CTRL, 2805 PCIM_MSICTRL_MSI_ENABLE, 2); 2806 BGE_SETBIT(sc, BGE_MSI_MODE, BGE_MSIMODE_ENABLE); 2807 } 2808 val = CSR_READ_4(sc, BGE_MARB_MODE); 2809 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 2810 } else { 2811 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2812 } 2813 2814 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2815 for (i = 0; i < BGE_TIMEOUT; i++) { 2816 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2817 if (val & BGE_VCPU_STATUS_INIT_DONE) 2818 break; 2819 DELAY(100); 2820 } 2821 if (i == BGE_TIMEOUT) { 2822 if_printf(&sc->arpcom.ac_if, "reset timed out\n"); 2823 return; 2824 } 2825 } else { 2826 /* 2827 * Poll until we see the 1's complement of the magic number. 2828 * This indicates that the firmware initialization 2829 * is complete. 2830 */ 2831 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) { 2832 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2833 if (val == ~BGE_MAGIC_NUMBER) 2834 break; 2835 DELAY(10); 2836 } 2837 if (i == BGE_FIRMWARE_TIMEOUT) { 2838 if_printf(&sc->arpcom.ac_if, "firmware handshake " 2839 "timed out, found 0x%08x\n", val); 2840 } 2841 } 2842 2843 /* 2844 * XXX Wait for the value of the PCISTATE register to 2845 * return to its original pre-reset state. This is a 2846 * fairly good indicator of reset completion. If we don't 2847 * wait for the reset to fully complete, trying to read 2848 * from the device's non-PCI registers may yield garbage 2849 * results. 2850 */ 2851 for (i = 0; i < BGE_TIMEOUT; i++) { 2852 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2853 break; 2854 DELAY(10); 2855 } 2856 2857 /* Fix up byte swapping */ 2858 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 2859 BGE_MODECTL_BYTESWAP_DATA); 2860 2861 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2862 2863 /* 2864 * The 5704 in TBI mode apparently needs some special 2865 * adjustment to insure the SERDES drive level is set 2866 * to 1.2V. 2867 */ 2868 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 2869 (sc->bge_flags & BGE_FLAG_TBI)) { 2870 uint32_t serdescfg; 2871 2872 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2873 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2874 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2875 } 2876 2877 /* XXX: Broadcom Linux driver. */ 2878 if ((sc->bge_flags & BGE_FLAG_PCIE) && 2879 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 2880 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 2881 uint32_t v; 2882 2883 /* Enable Data FIFO protection. */ 2884 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT); 2885 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25)); 2886 } 2887 2888 DELAY(10000); 2889 } 2890 2891 /* 2892 * Frame reception handling. This is called if there's a frame 2893 * on the receive return list. 2894 * 2895 * Note: we have to be able to handle two possibilities here: 2896 * 1) the frame is from the jumbo recieve ring 2897 * 2) the frame is from the standard receive ring 2898 */ 2899 2900 static void 2901 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int count) 2902 { 2903 struct ifnet *ifp; 2904 int stdcnt = 0, jumbocnt = 0; 2905 2906 ifp = &sc->arpcom.ac_if; 2907 2908 while (sc->bge_rx_saved_considx != rx_prod && count != 0) { 2909 struct bge_rx_bd *cur_rx; 2910 uint32_t rxidx; 2911 struct mbuf *m = NULL; 2912 uint16_t vlan_tag = 0; 2913 int have_tag = 0; 2914 2915 --count; 2916 2917 cur_rx = 2918 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 2919 2920 rxidx = cur_rx->bge_idx; 2921 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2922 logif(rx_pkt); 2923 2924 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2925 have_tag = 1; 2926 vlan_tag = cur_rx->bge_vlan_tag; 2927 } 2928 2929 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2930 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2931 jumbocnt++; 2932 2933 if (rxidx != sc->bge_jumbo) { 2934 ifp->if_ierrors++; 2935 if_printf(ifp, "sw jumbo index(%d) " 2936 "and hw jumbo index(%d) mismatch, drop!\n", 2937 sc->bge_jumbo, rxidx); 2938 bge_setup_rxdesc_jumbo(sc, rxidx); 2939 continue; 2940 } 2941 2942 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf; 2943 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2944 ifp->if_ierrors++; 2945 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo); 2946 continue; 2947 } 2948 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) { 2949 ifp->if_ierrors++; 2950 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo); 2951 continue; 2952 } 2953 } else { 2954 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2955 stdcnt++; 2956 2957 if (rxidx != sc->bge_std) { 2958 ifp->if_ierrors++; 2959 if_printf(ifp, "sw std index(%d) " 2960 "and hw std index(%d) mismatch, drop!\n", 2961 sc->bge_std, rxidx); 2962 bge_setup_rxdesc_std(sc, rxidx); 2963 continue; 2964 } 2965 2966 m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf; 2967 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2968 ifp->if_ierrors++; 2969 bge_setup_rxdesc_std(sc, sc->bge_std); 2970 continue; 2971 } 2972 if (bge_newbuf_std(sc, sc->bge_std, 0)) { 2973 ifp->if_ierrors++; 2974 bge_setup_rxdesc_std(sc, sc->bge_std); 2975 continue; 2976 } 2977 } 2978 2979 ifp->if_ipackets++; 2980 #if !defined(__i386__) && !defined(__x86_64__) 2981 /* 2982 * The x86 allows unaligned accesses, but for other 2983 * platforms we must make sure the payload is aligned. 2984 */ 2985 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 2986 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2987 cur_rx->bge_len); 2988 m->m_data += ETHER_ALIGN; 2989 } 2990 #endif 2991 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2992 m->m_pkthdr.rcvif = ifp; 2993 2994 if (ifp->if_capenable & IFCAP_RXCSUM) { 2995 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 2996 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2997 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2998 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2999 } 3000 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) && 3001 m->m_pkthdr.len >= BGE_MIN_FRAMELEN) { 3002 m->m_pkthdr.csum_data = 3003 cur_rx->bge_tcp_udp_csum; 3004 m->m_pkthdr.csum_flags |= 3005 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 3006 } 3007 } 3008 3009 /* 3010 * If we received a packet with a vlan tag, pass it 3011 * to vlan_input() instead of ether_input(). 3012 */ 3013 if (have_tag) { 3014 m->m_flags |= M_VLANTAG; 3015 m->m_pkthdr.ether_vlantag = vlan_tag; 3016 } 3017 ifp->if_input(ifp, m); 3018 } 3019 3020 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3021 if (stdcnt) 3022 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3023 if (jumbocnt) 3024 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3025 } 3026 3027 static void 3028 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 3029 { 3030 struct ifnet *ifp; 3031 3032 ifp = &sc->arpcom.ac_if; 3033 3034 /* 3035 * Go through our tx ring and free mbufs for those 3036 * frames that have been sent. 3037 */ 3038 while (sc->bge_tx_saved_considx != tx_cons) { 3039 uint32_t idx = 0; 3040 3041 idx = sc->bge_tx_saved_considx; 3042 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3043 ifp->if_opackets++; 3044 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 3045 sc->bge_cdata.bge_tx_dmamap[idx]); 3046 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3047 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3048 } 3049 sc->bge_txcnt--; 3050 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3051 logif(tx_pkt); 3052 } 3053 3054 if ((BGE_TX_RING_CNT - sc->bge_txcnt) >= 3055 (sc->bge_txrsvd + sc->bge_txspare)) 3056 ifq_clr_oactive(&ifp->if_snd); 3057 3058 if (sc->bge_txcnt == 0) 3059 ifp->if_timer = 0; 3060 3061 if (!ifq_is_empty(&ifp->if_snd)) 3062 if_devstart(ifp); 3063 } 3064 3065 #ifdef IFPOLL_ENABLE 3066 3067 static void 3068 bge_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycles) 3069 { 3070 struct bge_softc *sc = ifp->if_softc; 3071 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3072 uint16_t rx_prod, tx_cons; 3073 3074 ASSERT_SERIALIZED(ifp->if_serializer); 3075 3076 if (sc->bge_npoll.ifpc_stcount-- == 0) { 3077 sc->bge_npoll.ifpc_stcount = sc->bge_npoll.ifpc_stfrac; 3078 /* 3079 * Process link state changes. 3080 */ 3081 bge_link_poll(sc); 3082 } 3083 3084 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) { 3085 sc->bge_status_tag = sblk->bge_status_tag; 3086 /* 3087 * Use a load fence to ensure that status_tag 3088 * is saved before rx_prod and tx_cons. 3089 */ 3090 cpu_lfence(); 3091 } 3092 3093 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3094 if (sc->bge_rx_saved_considx != rx_prod) 3095 bge_rxeof(sc, rx_prod, cycles); 3096 3097 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3098 if (sc->bge_tx_saved_considx != tx_cons) 3099 bge_txeof(sc, tx_cons); 3100 3101 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) 3102 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 3103 3104 if (sc->bge_coal_chg) 3105 bge_coal_change(sc); 3106 } 3107 3108 static void 3109 bge_npoll(struct ifnet *ifp, struct ifpoll_info *info) 3110 { 3111 struct bge_softc *sc = ifp->if_softc; 3112 3113 ASSERT_SERIALIZED(ifp->if_serializer); 3114 3115 if (info != NULL) { 3116 int cpuid = sc->bge_npoll.ifpc_cpuid; 3117 3118 info->ifpi_rx[cpuid].poll_func = bge_npoll_compat; 3119 info->ifpi_rx[cpuid].arg = NULL; 3120 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 3121 3122 if (ifp->if_flags & IFF_RUNNING) 3123 bge_disable_intr(sc); 3124 ifp->if_npoll_cpuid = cpuid; 3125 } else { 3126 if (ifp->if_flags & IFF_RUNNING) 3127 bge_enable_intr(sc); 3128 ifp->if_npoll_cpuid = -1; 3129 } 3130 } 3131 3132 #endif /* IFPOLL_ENABLE */ 3133 3134 static void 3135 bge_intr_crippled(void *xsc) 3136 { 3137 struct bge_softc *sc = xsc; 3138 struct ifnet *ifp = &sc->arpcom.ac_if; 3139 3140 logif(intr); 3141 3142 /* 3143 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3144 * disable interrupts by writing nonzero like we used to, since with 3145 * our current organization this just gives complications and 3146 * pessimizations for re-enabling interrupts. We used to have races 3147 * instead of the necessary complications. Disabling interrupts 3148 * would just reduce the chance of a status update while we are 3149 * running (by switching to the interrupt-mode coalescence 3150 * parameters), but this chance is already very low so it is more 3151 * efficient to get another interrupt than prevent it. 3152 * 3153 * We do the ack first to ensure another interrupt if there is a 3154 * status update after the ack. We don't check for the status 3155 * changing later because it is more efficient to get another 3156 * interrupt than prevent it, not quite as above (not checking is 3157 * a smaller optimization than not toggling the interrupt enable, 3158 * since checking doesn't involve PCI accesses and toggling require 3159 * the status check). So toggling would probably be a pessimization 3160 * even with MSI. It would only be needed for using a task queue. 3161 */ 3162 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3163 3164 /* 3165 * Process link state changes. 3166 */ 3167 bge_link_poll(sc); 3168 3169 if (ifp->if_flags & IFF_RUNNING) { 3170 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3171 uint16_t rx_prod, tx_cons; 3172 3173 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3174 if (sc->bge_rx_saved_considx != rx_prod) 3175 bge_rxeof(sc, rx_prod, -1); 3176 3177 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3178 if (sc->bge_tx_saved_considx != tx_cons) 3179 bge_txeof(sc, tx_cons); 3180 } 3181 3182 if (sc->bge_coal_chg) 3183 bge_coal_change(sc); 3184 } 3185 3186 static void 3187 bge_intr_legacy(void *xsc) 3188 { 3189 struct bge_softc *sc = xsc; 3190 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3191 3192 if (sc->bge_status_tag == sblk->bge_status_tag) { 3193 uint32_t val; 3194 3195 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3196 if (val & BGE_PCISTAT_INTR_NOTACT) 3197 return; 3198 } 3199 3200 /* 3201 * NOTE: 3202 * Interrupt will have to be disabled if tagged status 3203 * is used, else interrupt will always be asserted on 3204 * certain chips (at least on BCM5750 AX/BX). 3205 */ 3206 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3207 3208 bge_intr(sc); 3209 } 3210 3211 static void 3212 bge_msi(void *xsc) 3213 { 3214 struct bge_softc *sc = xsc; 3215 3216 /* Disable interrupt first */ 3217 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3218 bge_intr(sc); 3219 } 3220 3221 static void 3222 bge_msi_oneshot(void *xsc) 3223 { 3224 bge_intr(xsc); 3225 } 3226 3227 static void 3228 bge_intr(struct bge_softc *sc) 3229 { 3230 struct ifnet *ifp = &sc->arpcom.ac_if; 3231 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block; 3232 uint16_t rx_prod, tx_cons; 3233 uint32_t status; 3234 3235 sc->bge_status_tag = sblk->bge_status_tag; 3236 /* 3237 * Use a load fence to ensure that status_tag is saved 3238 * before rx_prod, tx_cons and status. 3239 */ 3240 cpu_lfence(); 3241 3242 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx; 3243 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx; 3244 status = sblk->bge_status; 3245 3246 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt) 3247 bge_link_poll(sc); 3248 3249 if (ifp->if_flags & IFF_RUNNING) { 3250 if (sc->bge_rx_saved_considx != rx_prod) 3251 bge_rxeof(sc, rx_prod, -1); 3252 3253 if (sc->bge_tx_saved_considx != tx_cons) 3254 bge_txeof(sc, tx_cons); 3255 } 3256 3257 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 3258 3259 if (sc->bge_coal_chg) 3260 bge_coal_change(sc); 3261 } 3262 3263 static void 3264 bge_tick(void *xsc) 3265 { 3266 struct bge_softc *sc = xsc; 3267 struct ifnet *ifp = &sc->arpcom.ac_if; 3268 3269 lwkt_serialize_enter(ifp->if_serializer); 3270 3271 if (BGE_IS_5705_PLUS(sc)) 3272 bge_stats_update_regs(sc); 3273 else 3274 bge_stats_update(sc); 3275 3276 if (sc->bge_flags & BGE_FLAG_TBI) { 3277 /* 3278 * Since in TBI mode auto-polling can't be used we should poll 3279 * link status manually. Here we register pending link event 3280 * and trigger interrupt. 3281 */ 3282 sc->bge_link_evt++; 3283 if (BGE_IS_CRIPPLED(sc)) 3284 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3285 else 3286 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3287 } else if (!sc->bge_link) { 3288 mii_tick(device_get_softc(sc->bge_miibus)); 3289 } 3290 3291 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 3292 3293 lwkt_serialize_exit(ifp->if_serializer); 3294 } 3295 3296 static void 3297 bge_stats_update_regs(struct bge_softc *sc) 3298 { 3299 struct ifnet *ifp = &sc->arpcom.ac_if; 3300 struct bge_mac_stats_regs stats; 3301 uint32_t *s; 3302 int i; 3303 3304 s = (uint32_t *)&stats; 3305 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 3306 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 3307 s++; 3308 } 3309 3310 ifp->if_collisions += 3311 (stats.dot3StatsSingleCollisionFrames + 3312 stats.dot3StatsMultipleCollisionFrames + 3313 stats.dot3StatsExcessiveCollisions + 3314 stats.dot3StatsLateCollisions) - 3315 ifp->if_collisions; 3316 } 3317 3318 static void 3319 bge_stats_update(struct bge_softc *sc) 3320 { 3321 struct ifnet *ifp = &sc->arpcom.ac_if; 3322 bus_size_t stats; 3323 3324 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3325 3326 #define READ_STAT(sc, stats, stat) \ 3327 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3328 3329 ifp->if_collisions += 3330 (READ_STAT(sc, stats, 3331 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) + 3332 READ_STAT(sc, stats, 3333 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3334 READ_STAT(sc, stats, 3335 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) + 3336 READ_STAT(sc, stats, 3337 txstats.dot3StatsLateCollisions.bge_addr_lo)) - 3338 ifp->if_collisions; 3339 3340 #undef READ_STAT 3341 3342 #ifdef notdef 3343 ifp->if_collisions += 3344 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3345 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3346 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3347 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3348 ifp->if_collisions; 3349 #endif 3350 } 3351 3352 /* 3353 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3354 * pointers to descriptors. 3355 */ 3356 static int 3357 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx, 3358 int *segs_used) 3359 { 3360 struct bge_tx_bd *d = NULL, *last_d; 3361 uint16_t csum_flags = 0, mss = 0; 3362 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3363 bus_dmamap_t map; 3364 int error, maxsegs, nsegs, idx, i; 3365 struct mbuf *m_head = *m_head0, *m_new; 3366 3367 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3368 error = bge_setup_tso(sc, m_head0, &mss, &csum_flags); 3369 if (error) 3370 return ENOBUFS; 3371 m_head = *m_head0; 3372 } else if (m_head->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) { 3373 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3374 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3375 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3376 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3377 if (m_head->m_flags & M_LASTFRAG) 3378 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3379 else if (m_head->m_flags & M_FRAG) 3380 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3381 } 3382 3383 idx = *txidx; 3384 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3385 3386 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - sc->bge_txrsvd; 3387 KASSERT(maxsegs >= sc->bge_txspare, 3388 ("not enough segments %d", maxsegs)); 3389 3390 if (maxsegs > BGE_NSEG_NEW) 3391 maxsegs = BGE_NSEG_NEW; 3392 3393 /* 3394 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason. 3395 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN, 3396 * but when such padded frames employ the bge IP/TCP checksum 3397 * offload, the hardware checksum assist gives incorrect results 3398 * (possibly from incorporating its own padding into the UDP/TCP 3399 * checksum; who knows). If we pad such runts with zeros, the 3400 * onboard checksum comes out correct. 3401 */ 3402 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) && 3403 m_head->m_pkthdr.len < BGE_MIN_FRAMELEN) { 3404 error = m_devpad(m_head, BGE_MIN_FRAMELEN); 3405 if (error) 3406 goto back; 3407 } 3408 3409 if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) { 3410 m_new = bge_defrag_shortdma(m_head); 3411 if (m_new == NULL) { 3412 error = ENOBUFS; 3413 goto back; 3414 } 3415 *m_head0 = m_head = m_new; 3416 } 3417 if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 && 3418 sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) && 3419 m_head->m_next != NULL) { 3420 /* 3421 * Forcefully defragment mbuf chain to overcome hardware 3422 * limitation which only support a single outstanding 3423 * DMA read operation. If it fails, keep moving on using 3424 * the original mbuf chain. 3425 */ 3426 m_new = m_defrag(m_head, MB_DONTWAIT); 3427 if (m_new != NULL) 3428 *m_head0 = m_head = m_new; 3429 } 3430 3431 error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map, 3432 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 3433 if (error) 3434 goto back; 3435 *segs_used += nsegs; 3436 3437 m_head = *m_head0; 3438 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 3439 3440 for (i = 0; ; i++) { 3441 d = &sc->bge_ldata.bge_tx_ring[idx]; 3442 3443 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3444 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3445 d->bge_len = segs[i].ds_len; 3446 d->bge_flags = csum_flags; 3447 d->bge_mss = mss; 3448 3449 if (i == nsegs - 1) 3450 break; 3451 BGE_INC(idx, BGE_TX_RING_CNT); 3452 } 3453 last_d = d; 3454 3455 /* Set vlan tag to the first segment of the packet. */ 3456 d = &sc->bge_ldata.bge_tx_ring[*txidx]; 3457 if (m_head->m_flags & M_VLANTAG) { 3458 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3459 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag; 3460 } else { 3461 d->bge_vlan_tag = 0; 3462 } 3463 3464 /* Mark the last segment as end of packet... */ 3465 last_d->bge_flags |= BGE_TXBDFLAG_END; 3466 3467 /* 3468 * Insure that the map for this transmission is placed at 3469 * the array index of the last descriptor in this chain. 3470 */ 3471 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3472 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3473 sc->bge_cdata.bge_tx_chain[idx] = m_head; 3474 sc->bge_txcnt += nsegs; 3475 3476 BGE_INC(idx, BGE_TX_RING_CNT); 3477 *txidx = idx; 3478 back: 3479 if (error) { 3480 m_freem(*m_head0); 3481 *m_head0 = NULL; 3482 } 3483 return error; 3484 } 3485 3486 static void 3487 bge_xmit(struct bge_softc *sc, uint32_t prodidx) 3488 { 3489 /* Transmit */ 3490 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3491 /* 5700 b2 errata */ 3492 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3493 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3494 } 3495 3496 /* 3497 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3498 * to the mbuf data regions directly in the transmit descriptors. 3499 */ 3500 static void 3501 bge_start(struct ifnet *ifp) 3502 { 3503 struct bge_softc *sc = ifp->if_softc; 3504 struct mbuf *m_head = NULL; 3505 uint32_t prodidx; 3506 int nsegs = 0; 3507 3508 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 3509 return; 3510 3511 prodidx = sc->bge_tx_prodidx; 3512 3513 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3514 m_head = ifq_dequeue(&ifp->if_snd, NULL); 3515 if (m_head == NULL) 3516 break; 3517 3518 /* 3519 * XXX 3520 * The code inside the if() block is never reached since we 3521 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3522 * requests to checksum TCP/UDP in a fragmented packet. 3523 * 3524 * XXX 3525 * safety overkill. If this is a fragmented packet chain 3526 * with delayed TCP/UDP checksums, then only encapsulate 3527 * it if we have enough descriptors to handle the entire 3528 * chain at once. 3529 * (paranoia -- may not actually be needed) 3530 */ 3531 if ((m_head->m_flags & M_FIRSTFRAG) && 3532 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) { 3533 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3534 m_head->m_pkthdr.csum_data + sc->bge_txrsvd) { 3535 ifq_set_oactive(&ifp->if_snd); 3536 ifq_prepend(&ifp->if_snd, m_head); 3537 break; 3538 } 3539 } 3540 3541 /* 3542 * Sanity check: avoid coming within bge_txrsvd 3543 * descriptors of the end of the ring. Also make 3544 * sure there are bge_txspare descriptors for 3545 * jumbo buffers' defragmentation. 3546 */ 3547 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3548 (sc->bge_txrsvd + sc->bge_txspare)) { 3549 ifq_set_oactive(&ifp->if_snd); 3550 ifq_prepend(&ifp->if_snd, m_head); 3551 break; 3552 } 3553 3554 /* 3555 * Pack the data into the transmit ring. If we 3556 * don't have room, set the OACTIVE flag and wait 3557 * for the NIC to drain the ring. 3558 */ 3559 if (bge_encap(sc, &m_head, &prodidx, &nsegs)) { 3560 ifq_set_oactive(&ifp->if_snd); 3561 ifp->if_oerrors++; 3562 break; 3563 } 3564 3565 if (nsegs >= sc->bge_tx_wreg) { 3566 bge_xmit(sc, prodidx); 3567 nsegs = 0; 3568 } 3569 3570 ETHER_BPF_MTAP(ifp, m_head); 3571 3572 /* 3573 * Set a timeout in case the chip goes out to lunch. 3574 */ 3575 ifp->if_timer = 5; 3576 } 3577 3578 if (nsegs > 0) 3579 bge_xmit(sc, prodidx); 3580 sc->bge_tx_prodidx = prodidx; 3581 } 3582 3583 static void 3584 bge_init(void *xsc) 3585 { 3586 struct bge_softc *sc = xsc; 3587 struct ifnet *ifp = &sc->arpcom.ac_if; 3588 uint16_t *m; 3589 uint32_t mode; 3590 3591 ASSERT_SERIALIZED(ifp->if_serializer); 3592 3593 /* Cancel pending I/O and flush buffers. */ 3594 bge_stop(sc); 3595 bge_reset(sc); 3596 bge_chipinit(sc); 3597 3598 /* 3599 * Init the various state machines, ring 3600 * control blocks and firmware. 3601 */ 3602 if (bge_blockinit(sc)) { 3603 if_printf(ifp, "initialization failure\n"); 3604 bge_stop(sc); 3605 return; 3606 } 3607 3608 /* Specify MTU. */ 3609 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3610 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN); 3611 3612 /* Load our MAC address. */ 3613 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 3614 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3615 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3616 3617 /* Enable or disable promiscuous mode as needed. */ 3618 bge_setpromisc(sc); 3619 3620 /* Program multicast filter. */ 3621 bge_setmulti(sc); 3622 3623 /* Init RX ring. */ 3624 if (bge_init_rx_ring_std(sc)) { 3625 if_printf(ifp, "RX ring initialization failed\n"); 3626 bge_stop(sc); 3627 return; 3628 } 3629 3630 /* 3631 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3632 * memory to insure that the chip has in fact read the first 3633 * entry of the ring. 3634 */ 3635 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3636 uint32_t v, i; 3637 for (i = 0; i < 10; i++) { 3638 DELAY(20); 3639 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3640 if (v == (MCLBYTES - ETHER_ALIGN)) 3641 break; 3642 } 3643 if (i == 10) 3644 if_printf(ifp, "5705 A0 chip failed to load RX ring\n"); 3645 } 3646 3647 /* Init jumbo RX ring. */ 3648 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) { 3649 if (bge_init_rx_ring_jumbo(sc)) { 3650 if_printf(ifp, "Jumbo RX ring initialization failed\n"); 3651 bge_stop(sc); 3652 return; 3653 } 3654 } 3655 3656 /* Init our RX return ring index */ 3657 sc->bge_rx_saved_considx = 0; 3658 3659 /* Init TX ring. */ 3660 bge_init_tx_ring(sc); 3661 3662 /* Enable TX MAC state machine lockup fix. */ 3663 mode = CSR_READ_4(sc, BGE_TX_MODE); 3664 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3665 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 3666 /* Turn on transmitter */ 3667 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 3668 3669 /* Turn on receiver */ 3670 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3671 3672 /* 3673 * Set the number of good frames to receive after RX MBUF 3674 * Low Watermark has been reached. After the RX MAC receives 3675 * this number of frames, it will drop subsequent incoming 3676 * frames until the MBUF High Watermark is reached. 3677 */ 3678 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3679 3680 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) { 3681 if (bootverbose) { 3682 if_printf(ifp, "MSI_MODE: %#x\n", 3683 CSR_READ_4(sc, BGE_MSI_MODE)); 3684 } 3685 3686 /* 3687 * XXX 3688 * Linux driver turns it on for all chips supporting MSI?! 3689 */ 3690 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 3691 /* 3692 * XXX 3693 * According to 5722-PG101-R, 3694 * BGE_PCIE_TRANSACT_ONESHOT_MSI applies only to 3695 * BCM5906. 3696 */ 3697 BGE_SETBIT(sc, BGE_PCIE_TRANSACT, 3698 BGE_PCIE_TRANSACT_ONESHOT_MSI); 3699 } 3700 } 3701 3702 /* Tell firmware we're alive. */ 3703 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3704 3705 /* Enable host interrupts if polling(4) is not enabled. */ 3706 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4); 3707 #ifdef IFPOLL_ENABLE 3708 if (ifp->if_flags & IFF_NPOLLING) 3709 bge_disable_intr(sc); 3710 else 3711 #endif 3712 bge_enable_intr(sc); 3713 3714 bge_ifmedia_upd(ifp); 3715 3716 ifp->if_flags |= IFF_RUNNING; 3717 ifq_clr_oactive(&ifp->if_snd); 3718 3719 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 3720 } 3721 3722 /* 3723 * Set media options. 3724 */ 3725 static int 3726 bge_ifmedia_upd(struct ifnet *ifp) 3727 { 3728 struct bge_softc *sc = ifp->if_softc; 3729 3730 /* If this is a 1000baseX NIC, enable the TBI port. */ 3731 if (sc->bge_flags & BGE_FLAG_TBI) { 3732 struct ifmedia *ifm = &sc->bge_ifmedia; 3733 3734 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3735 return(EINVAL); 3736 3737 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3738 case IFM_AUTO: 3739 /* 3740 * The BCM5704 ASIC appears to have a special 3741 * mechanism for programming the autoneg 3742 * advertisement registers in TBI mode. 3743 */ 3744 if (!bge_fake_autoneg && 3745 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3746 uint32_t sgdig; 3747 3748 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3749 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3750 sgdig |= BGE_SGDIGCFG_AUTO | 3751 BGE_SGDIGCFG_PAUSE_CAP | 3752 BGE_SGDIGCFG_ASYM_PAUSE; 3753 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3754 sgdig | BGE_SGDIGCFG_SEND); 3755 DELAY(5); 3756 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3757 } 3758 break; 3759 case IFM_1000_SX: 3760 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3761 BGE_CLRBIT(sc, BGE_MAC_MODE, 3762 BGE_MACMODE_HALF_DUPLEX); 3763 } else { 3764 BGE_SETBIT(sc, BGE_MAC_MODE, 3765 BGE_MACMODE_HALF_DUPLEX); 3766 } 3767 break; 3768 default: 3769 return(EINVAL); 3770 } 3771 } else { 3772 struct mii_data *mii = device_get_softc(sc->bge_miibus); 3773 3774 sc->bge_link_evt++; 3775 sc->bge_link = 0; 3776 if (mii->mii_instance) { 3777 struct mii_softc *miisc; 3778 3779 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3780 mii_phy_reset(miisc); 3781 } 3782 mii_mediachg(mii); 3783 3784 /* 3785 * Force an interrupt so that we will call bge_link_upd 3786 * if needed and clear any pending link state attention. 3787 * Without this we are not getting any further interrupts 3788 * for link state changes and thus will not UP the link and 3789 * not be able to send in bge_start. The only way to get 3790 * things working was to receive a packet and get an RX 3791 * intr. 3792 * 3793 * bge_tick should help for fiber cards and we might not 3794 * need to do this here if BGE_FLAG_TBI is set but as 3795 * we poll for fiber anyway it should not harm. 3796 */ 3797 if (BGE_IS_CRIPPLED(sc)) 3798 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3799 else 3800 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3801 } 3802 return(0); 3803 } 3804 3805 /* 3806 * Report current media status. 3807 */ 3808 static void 3809 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3810 { 3811 struct bge_softc *sc = ifp->if_softc; 3812 3813 if (sc->bge_flags & BGE_FLAG_TBI) { 3814 ifmr->ifm_status = IFM_AVALID; 3815 ifmr->ifm_active = IFM_ETHER; 3816 if (CSR_READ_4(sc, BGE_MAC_STS) & 3817 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3818 ifmr->ifm_status |= IFM_ACTIVE; 3819 } else { 3820 ifmr->ifm_active |= IFM_NONE; 3821 return; 3822 } 3823 3824 ifmr->ifm_active |= IFM_1000_SX; 3825 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3826 ifmr->ifm_active |= IFM_HDX; 3827 else 3828 ifmr->ifm_active |= IFM_FDX; 3829 } else { 3830 struct mii_data *mii = device_get_softc(sc->bge_miibus); 3831 3832 mii_pollstat(mii); 3833 ifmr->ifm_active = mii->mii_media_active; 3834 ifmr->ifm_status = mii->mii_media_status; 3835 } 3836 } 3837 3838 static int 3839 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3840 { 3841 struct bge_softc *sc = ifp->if_softc; 3842 struct ifreq *ifr = (struct ifreq *)data; 3843 int mask, error = 0; 3844 3845 ASSERT_SERIALIZED(ifp->if_serializer); 3846 3847 switch (command) { 3848 case SIOCSIFMTU: 3849 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) || 3850 (BGE_IS_JUMBO_CAPABLE(sc) && 3851 ifr->ifr_mtu > BGE_JUMBO_MTU)) { 3852 error = EINVAL; 3853 } else if (ifp->if_mtu != ifr->ifr_mtu) { 3854 ifp->if_mtu = ifr->ifr_mtu; 3855 if (ifp->if_flags & IFF_RUNNING) 3856 bge_init(sc); 3857 } 3858 break; 3859 case SIOCSIFFLAGS: 3860 if (ifp->if_flags & IFF_UP) { 3861 if (ifp->if_flags & IFF_RUNNING) { 3862 mask = ifp->if_flags ^ sc->bge_if_flags; 3863 3864 /* 3865 * If only the state of the PROMISC flag 3866 * changed, then just use the 'set promisc 3867 * mode' command instead of reinitializing 3868 * the entire NIC. Doing a full re-init 3869 * means reloading the firmware and waiting 3870 * for it to start up, which may take a 3871 * second or two. Similarly for ALLMULTI. 3872 */ 3873 if (mask & IFF_PROMISC) 3874 bge_setpromisc(sc); 3875 if (mask & IFF_ALLMULTI) 3876 bge_setmulti(sc); 3877 } else { 3878 bge_init(sc); 3879 } 3880 } else if (ifp->if_flags & IFF_RUNNING) { 3881 bge_stop(sc); 3882 } 3883 sc->bge_if_flags = ifp->if_flags; 3884 break; 3885 case SIOCADDMULTI: 3886 case SIOCDELMULTI: 3887 if (ifp->if_flags & IFF_RUNNING) 3888 bge_setmulti(sc); 3889 break; 3890 case SIOCSIFMEDIA: 3891 case SIOCGIFMEDIA: 3892 if (sc->bge_flags & BGE_FLAG_TBI) { 3893 error = ifmedia_ioctl(ifp, ifr, 3894 &sc->bge_ifmedia, command); 3895 } else { 3896 struct mii_data *mii; 3897 3898 mii = device_get_softc(sc->bge_miibus); 3899 error = ifmedia_ioctl(ifp, ifr, 3900 &mii->mii_media, command); 3901 } 3902 break; 3903 case SIOCSIFCAP: 3904 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3905 if (mask & IFCAP_HWCSUM) { 3906 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 3907 if (ifp->if_capenable & IFCAP_TXCSUM) 3908 ifp->if_hwassist |= BGE_CSUM_FEATURES; 3909 else 3910 ifp->if_hwassist &= ~BGE_CSUM_FEATURES; 3911 } 3912 if (mask & IFCAP_TSO) { 3913 ifp->if_capenable ^= IFCAP_TSO; 3914 if (ifp->if_capenable & IFCAP_TSO) 3915 ifp->if_hwassist |= CSUM_TSO; 3916 else 3917 ifp->if_hwassist &= ~CSUM_TSO; 3918 } 3919 break; 3920 default: 3921 error = ether_ioctl(ifp, command, data); 3922 break; 3923 } 3924 return error; 3925 } 3926 3927 static void 3928 bge_watchdog(struct ifnet *ifp) 3929 { 3930 struct bge_softc *sc = ifp->if_softc; 3931 3932 if_printf(ifp, "watchdog timeout -- resetting\n"); 3933 3934 bge_init(sc); 3935 3936 ifp->if_oerrors++; 3937 3938 if (!ifq_is_empty(&ifp->if_snd)) 3939 if_devstart(ifp); 3940 } 3941 3942 /* 3943 * Stop the adapter and free any mbufs allocated to the 3944 * RX and TX lists. 3945 */ 3946 static void 3947 bge_stop(struct bge_softc *sc) 3948 { 3949 struct ifnet *ifp = &sc->arpcom.ac_if; 3950 3951 ASSERT_SERIALIZED(ifp->if_serializer); 3952 3953 callout_stop(&sc->bge_stat_timer); 3954 3955 /* 3956 * Disable all of the receiver blocks 3957 */ 3958 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3959 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3960 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3961 if (BGE_IS_5700_FAMILY(sc)) 3962 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3963 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3964 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3965 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3966 3967 /* 3968 * Disable all of the transmit blocks 3969 */ 3970 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3971 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3972 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3973 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3974 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3975 if (BGE_IS_5700_FAMILY(sc)) 3976 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3977 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3978 3979 /* 3980 * Shut down all of the memory managers and related 3981 * state machines. 3982 */ 3983 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3984 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3985 if (BGE_IS_5700_FAMILY(sc)) 3986 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3987 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3988 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3989 if (!BGE_IS_5705_PLUS(sc)) { 3990 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3991 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3992 } 3993 3994 /* Disable host interrupts. */ 3995 bge_disable_intr(sc); 3996 3997 /* 3998 * Tell firmware we're shutting down. 3999 */ 4000 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4001 4002 /* Free the RX lists. */ 4003 bge_free_rx_ring_std(sc); 4004 4005 /* Free jumbo RX list. */ 4006 if (BGE_IS_JUMBO_CAPABLE(sc)) 4007 bge_free_rx_ring_jumbo(sc); 4008 4009 /* Free TX buffers. */ 4010 bge_free_tx_ring(sc); 4011 4012 sc->bge_status_tag = 0; 4013 sc->bge_link = 0; 4014 sc->bge_coal_chg = 0; 4015 4016 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4017 4018 ifp->if_flags &= ~IFF_RUNNING; 4019 ifq_clr_oactive(&ifp->if_snd); 4020 ifp->if_timer = 0; 4021 } 4022 4023 /* 4024 * Stop all chip I/O so that the kernel's probe routines don't 4025 * get confused by errant DMAs when rebooting. 4026 */ 4027 static void 4028 bge_shutdown(device_t dev) 4029 { 4030 struct bge_softc *sc = device_get_softc(dev); 4031 struct ifnet *ifp = &sc->arpcom.ac_if; 4032 4033 lwkt_serialize_enter(ifp->if_serializer); 4034 bge_stop(sc); 4035 bge_reset(sc); 4036 lwkt_serialize_exit(ifp->if_serializer); 4037 } 4038 4039 static int 4040 bge_suspend(device_t dev) 4041 { 4042 struct bge_softc *sc = device_get_softc(dev); 4043 struct ifnet *ifp = &sc->arpcom.ac_if; 4044 4045 lwkt_serialize_enter(ifp->if_serializer); 4046 bge_stop(sc); 4047 lwkt_serialize_exit(ifp->if_serializer); 4048 4049 return 0; 4050 } 4051 4052 static int 4053 bge_resume(device_t dev) 4054 { 4055 struct bge_softc *sc = device_get_softc(dev); 4056 struct ifnet *ifp = &sc->arpcom.ac_if; 4057 4058 lwkt_serialize_enter(ifp->if_serializer); 4059 4060 if (ifp->if_flags & IFF_UP) { 4061 bge_init(sc); 4062 4063 if (!ifq_is_empty(&ifp->if_snd)) 4064 if_devstart(ifp); 4065 } 4066 4067 lwkt_serialize_exit(ifp->if_serializer); 4068 4069 return 0; 4070 } 4071 4072 static void 4073 bge_setpromisc(struct bge_softc *sc) 4074 { 4075 struct ifnet *ifp = &sc->arpcom.ac_if; 4076 4077 if (ifp->if_flags & IFF_PROMISC) 4078 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4079 else 4080 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4081 } 4082 4083 static void 4084 bge_dma_free(struct bge_softc *sc) 4085 { 4086 int i; 4087 4088 /* Destroy RX mbuf DMA stuffs. */ 4089 if (sc->bge_cdata.bge_rx_mtag != NULL) { 4090 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 4091 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 4092 sc->bge_cdata.bge_rx_std_dmamap[i]); 4093 } 4094 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 4095 sc->bge_cdata.bge_rx_tmpmap); 4096 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 4097 } 4098 4099 /* Destroy TX mbuf DMA stuffs. */ 4100 if (sc->bge_cdata.bge_tx_mtag != NULL) { 4101 for (i = 0; i < BGE_TX_RING_CNT; i++) { 4102 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 4103 sc->bge_cdata.bge_tx_dmamap[i]); 4104 } 4105 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 4106 } 4107 4108 /* Destroy standard RX ring */ 4109 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag, 4110 sc->bge_cdata.bge_rx_std_ring_map, 4111 sc->bge_ldata.bge_rx_std_ring); 4112 4113 if (BGE_IS_JUMBO_CAPABLE(sc)) 4114 bge_free_jumbo_mem(sc); 4115 4116 /* Destroy RX return ring */ 4117 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag, 4118 sc->bge_cdata.bge_rx_return_ring_map, 4119 sc->bge_ldata.bge_rx_return_ring); 4120 4121 /* Destroy TX ring */ 4122 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag, 4123 sc->bge_cdata.bge_tx_ring_map, 4124 sc->bge_ldata.bge_tx_ring); 4125 4126 /* Destroy status block */ 4127 bge_dma_block_free(sc->bge_cdata.bge_status_tag, 4128 sc->bge_cdata.bge_status_map, 4129 sc->bge_ldata.bge_status_block); 4130 4131 /* Destroy statistics block */ 4132 bge_dma_block_free(sc->bge_cdata.bge_stats_tag, 4133 sc->bge_cdata.bge_stats_map, 4134 sc->bge_ldata.bge_stats); 4135 4136 /* Destroy the parent tag */ 4137 if (sc->bge_cdata.bge_parent_tag != NULL) 4138 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 4139 } 4140 4141 static int 4142 bge_dma_alloc(struct bge_softc *sc) 4143 { 4144 struct ifnet *ifp = &sc->arpcom.ac_if; 4145 int i, error; 4146 bus_addr_t lowaddr; 4147 bus_size_t txmaxsz; 4148 4149 lowaddr = BUS_SPACE_MAXADDR; 4150 if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) 4151 lowaddr = BGE_DMA_MAXADDR_40BIT; 4152 4153 /* 4154 * Allocate the parent bus DMA tag appropriate for PCI. 4155 * 4156 * All of the NetExtreme/NetLink controllers have 4GB boundary 4157 * DMA bug. 4158 * Whenever an address crosses a multiple of the 4GB boundary 4159 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 4160 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 4161 * state machine will lockup and cause the device to hang. 4162 */ 4163 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G, 4164 lowaddr, BUS_SPACE_MAXADDR, 4165 NULL, NULL, 4166 BUS_SPACE_MAXSIZE_32BIT, 0, 4167 BUS_SPACE_MAXSIZE_32BIT, 4168 0, &sc->bge_cdata.bge_parent_tag); 4169 if (error) { 4170 if_printf(ifp, "could not allocate parent dma tag\n"); 4171 return error; 4172 } 4173 4174 /* 4175 * Create DMA tag and maps for RX mbufs. 4176 */ 4177 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0, 4178 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4179 NULL, NULL, MCLBYTES, 1, MCLBYTES, 4180 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 4181 &sc->bge_cdata.bge_rx_mtag); 4182 if (error) { 4183 if_printf(ifp, "could not allocate RX mbuf dma tag\n"); 4184 return error; 4185 } 4186 4187 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 4188 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap); 4189 if (error) { 4190 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 4191 sc->bge_cdata.bge_rx_mtag = NULL; 4192 return error; 4193 } 4194 4195 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 4196 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 4197 BUS_DMA_WAITOK, 4198 &sc->bge_cdata.bge_rx_std_dmamap[i]); 4199 if (error) { 4200 int j; 4201 4202 for (j = 0; j < i; ++j) { 4203 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 4204 sc->bge_cdata.bge_rx_std_dmamap[j]); 4205 } 4206 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 4207 sc->bge_cdata.bge_rx_mtag = NULL; 4208 4209 if_printf(ifp, "could not create DMA map for RX\n"); 4210 return error; 4211 } 4212 } 4213 4214 /* 4215 * Create DMA tag and maps for TX mbufs. 4216 */ 4217 if (sc->bge_flags & BGE_FLAG_TSO) 4218 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header); 4219 else 4220 txmaxsz = BGE_JUMBO_FRAMELEN; 4221 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0, 4222 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4223 NULL, NULL, 4224 txmaxsz, BGE_NSEG_NEW, PAGE_SIZE, 4225 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 4226 BUS_DMA_ONEBPAGE, 4227 &sc->bge_cdata.bge_tx_mtag); 4228 if (error) { 4229 if_printf(ifp, "could not allocate TX mbuf dma tag\n"); 4230 return error; 4231 } 4232 4233 for (i = 0; i < BGE_TX_RING_CNT; i++) { 4234 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 4235 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 4236 &sc->bge_cdata.bge_tx_dmamap[i]); 4237 if (error) { 4238 int j; 4239 4240 for (j = 0; j < i; ++j) { 4241 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 4242 sc->bge_cdata.bge_tx_dmamap[j]); 4243 } 4244 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 4245 sc->bge_cdata.bge_tx_mtag = NULL; 4246 4247 if_printf(ifp, "could not create DMA map for TX\n"); 4248 return error; 4249 } 4250 } 4251 4252 /* 4253 * Create DMA stuffs for standard RX ring. 4254 */ 4255 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ, 4256 &sc->bge_cdata.bge_rx_std_ring_tag, 4257 &sc->bge_cdata.bge_rx_std_ring_map, 4258 (void *)&sc->bge_ldata.bge_rx_std_ring, 4259 &sc->bge_ldata.bge_rx_std_ring_paddr); 4260 if (error) { 4261 if_printf(ifp, "could not create std RX ring\n"); 4262 return error; 4263 } 4264 4265 /* 4266 * Create jumbo buffer pool. 4267 */ 4268 if (BGE_IS_JUMBO_CAPABLE(sc)) { 4269 error = bge_alloc_jumbo_mem(sc); 4270 if (error) { 4271 if_printf(ifp, "could not create jumbo buffer pool\n"); 4272 return error; 4273 } 4274 } 4275 4276 /* 4277 * Create DMA stuffs for RX return ring. 4278 */ 4279 error = bge_dma_block_alloc(sc, 4280 BGE_RX_RTN_RING_SZ(sc->bge_return_ring_cnt), 4281 &sc->bge_cdata.bge_rx_return_ring_tag, 4282 &sc->bge_cdata.bge_rx_return_ring_map, 4283 (void *)&sc->bge_ldata.bge_rx_return_ring, 4284 &sc->bge_ldata.bge_rx_return_ring_paddr); 4285 if (error) { 4286 if_printf(ifp, "could not create RX ret ring\n"); 4287 return error; 4288 } 4289 4290 /* 4291 * Create DMA stuffs for TX ring. 4292 */ 4293 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ, 4294 &sc->bge_cdata.bge_tx_ring_tag, 4295 &sc->bge_cdata.bge_tx_ring_map, 4296 (void *)&sc->bge_ldata.bge_tx_ring, 4297 &sc->bge_ldata.bge_tx_ring_paddr); 4298 if (error) { 4299 if_printf(ifp, "could not create TX ring\n"); 4300 return error; 4301 } 4302 4303 /* 4304 * Create DMA stuffs for status block. 4305 */ 4306 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ, 4307 &sc->bge_cdata.bge_status_tag, 4308 &sc->bge_cdata.bge_status_map, 4309 (void *)&sc->bge_ldata.bge_status_block, 4310 &sc->bge_ldata.bge_status_block_paddr); 4311 if (error) { 4312 if_printf(ifp, "could not create status block\n"); 4313 return error; 4314 } 4315 4316 /* 4317 * Create DMA stuffs for statistics block. 4318 */ 4319 error = bge_dma_block_alloc(sc, BGE_STATS_SZ, 4320 &sc->bge_cdata.bge_stats_tag, 4321 &sc->bge_cdata.bge_stats_map, 4322 (void *)&sc->bge_ldata.bge_stats, 4323 &sc->bge_ldata.bge_stats_paddr); 4324 if (error) { 4325 if_printf(ifp, "could not create stats block\n"); 4326 return error; 4327 } 4328 return 0; 4329 } 4330 4331 static int 4332 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag, 4333 bus_dmamap_t *map, void **addr, bus_addr_t *paddr) 4334 { 4335 bus_dmamem_t dmem; 4336 int error; 4337 4338 error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0, 4339 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 4340 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 4341 if (error) 4342 return error; 4343 4344 *tag = dmem.dmem_tag; 4345 *map = dmem.dmem_map; 4346 *addr = dmem.dmem_addr; 4347 *paddr = dmem.dmem_busaddr; 4348 4349 return 0; 4350 } 4351 4352 static void 4353 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr) 4354 { 4355 if (tag != NULL) { 4356 bus_dmamap_unload(tag, map); 4357 bus_dmamem_free(tag, addr, map); 4358 bus_dma_tag_destroy(tag); 4359 } 4360 } 4361 4362 /* 4363 * Grrr. The link status word in the status block does 4364 * not work correctly on the BCM5700 rev AX and BX chips, 4365 * according to all available information. Hence, we have 4366 * to enable MII interrupts in order to properly obtain 4367 * async link changes. Unfortunately, this also means that 4368 * we have to read the MAC status register to detect link 4369 * changes, thereby adding an additional register access to 4370 * the interrupt handler. 4371 * 4372 * XXX: perhaps link state detection procedure used for 4373 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4374 */ 4375 static void 4376 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused) 4377 { 4378 struct ifnet *ifp = &sc->arpcom.ac_if; 4379 struct mii_data *mii = device_get_softc(sc->bge_miibus); 4380 4381 mii_pollstat(mii); 4382 4383 if (!sc->bge_link && 4384 (mii->mii_media_status & IFM_ACTIVE) && 4385 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4386 sc->bge_link++; 4387 if (bootverbose) 4388 if_printf(ifp, "link UP\n"); 4389 } else if (sc->bge_link && 4390 (!(mii->mii_media_status & IFM_ACTIVE) || 4391 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4392 sc->bge_link = 0; 4393 if (bootverbose) 4394 if_printf(ifp, "link DOWN\n"); 4395 } 4396 4397 /* Clear the interrupt. */ 4398 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT); 4399 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4400 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS); 4401 } 4402 4403 static void 4404 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status) 4405 { 4406 struct ifnet *ifp = &sc->arpcom.ac_if; 4407 4408 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE) 4409 4410 /* 4411 * Sometimes PCS encoding errors are detected in 4412 * TBI mode (on fiber NICs), and for some reason 4413 * the chip will signal them as link changes. 4414 * If we get a link change event, but the 'PCS 4415 * encoding error' bit in the MAC status register 4416 * is set, don't bother doing a link check. 4417 * This avoids spurious "gigabit link up" messages 4418 * that sometimes appear on fiber NICs during 4419 * periods of heavy traffic. 4420 */ 4421 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4422 if (!sc->bge_link) { 4423 sc->bge_link++; 4424 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4425 BGE_CLRBIT(sc, BGE_MAC_MODE, 4426 BGE_MACMODE_TBI_SEND_CFGS); 4427 } 4428 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4429 4430 if (bootverbose) 4431 if_printf(ifp, "link UP\n"); 4432 4433 ifp->if_link_state = LINK_STATE_UP; 4434 if_link_state_change(ifp); 4435 } 4436 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) { 4437 if (sc->bge_link) { 4438 sc->bge_link = 0; 4439 4440 if (bootverbose) 4441 if_printf(ifp, "link DOWN\n"); 4442 4443 ifp->if_link_state = LINK_STATE_DOWN; 4444 if_link_state_change(ifp); 4445 } 4446 } 4447 4448 #undef PCS_ENCODE_ERR 4449 4450 /* Clear the attention. */ 4451 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4452 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4453 BGE_MACSTAT_LINK_CHANGED); 4454 } 4455 4456 static void 4457 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused) 4458 { 4459 struct ifnet *ifp = &sc->arpcom.ac_if; 4460 struct mii_data *mii = device_get_softc(sc->bge_miibus); 4461 4462 mii_pollstat(mii); 4463 bge_miibus_statchg(sc->bge_dev); 4464 4465 if (bootverbose) { 4466 if (sc->bge_link) 4467 if_printf(ifp, "link UP\n"); 4468 else 4469 if_printf(ifp, "link DOWN\n"); 4470 } 4471 4472 /* Clear the attention. */ 4473 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4474 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4475 BGE_MACSTAT_LINK_CHANGED); 4476 } 4477 4478 static void 4479 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused) 4480 { 4481 struct ifnet *ifp = &sc->arpcom.ac_if; 4482 struct mii_data *mii = device_get_softc(sc->bge_miibus); 4483 4484 mii_pollstat(mii); 4485 4486 if (!sc->bge_link && 4487 (mii->mii_media_status & IFM_ACTIVE) && 4488 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4489 sc->bge_link++; 4490 if (bootverbose) 4491 if_printf(ifp, "link UP\n"); 4492 } else if (sc->bge_link && 4493 (!(mii->mii_media_status & IFM_ACTIVE) || 4494 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4495 sc->bge_link = 0; 4496 if (bootverbose) 4497 if_printf(ifp, "link DOWN\n"); 4498 } 4499 4500 /* Clear the attention. */ 4501 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4502 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4503 BGE_MACSTAT_LINK_CHANGED); 4504 } 4505 4506 static int 4507 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS) 4508 { 4509 struct bge_softc *sc = arg1; 4510 4511 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4512 &sc->bge_rx_coal_ticks, 4513 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX, 4514 BGE_RX_COAL_TICKS_CHG); 4515 } 4516 4517 static int 4518 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS) 4519 { 4520 struct bge_softc *sc = arg1; 4521 4522 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4523 &sc->bge_tx_coal_ticks, 4524 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX, 4525 BGE_TX_COAL_TICKS_CHG); 4526 } 4527 4528 static int 4529 bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS) 4530 { 4531 struct bge_softc *sc = arg1; 4532 4533 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4534 &sc->bge_rx_coal_bds, 4535 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX, 4536 BGE_RX_COAL_BDS_CHG); 4537 } 4538 4539 static int 4540 bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS) 4541 { 4542 struct bge_softc *sc = arg1; 4543 4544 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4545 &sc->bge_tx_coal_bds, 4546 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX, 4547 BGE_TX_COAL_BDS_CHG); 4548 } 4549 4550 static int 4551 bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS) 4552 { 4553 struct bge_softc *sc = arg1; 4554 4555 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4556 &sc->bge_rx_coal_ticks_int, 4557 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX, 4558 BGE_RX_COAL_TICKS_INT_CHG); 4559 } 4560 4561 static int 4562 bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS) 4563 { 4564 struct bge_softc *sc = arg1; 4565 4566 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4567 &sc->bge_tx_coal_ticks_int, 4568 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX, 4569 BGE_TX_COAL_TICKS_INT_CHG); 4570 } 4571 4572 static int 4573 bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS) 4574 { 4575 struct bge_softc *sc = arg1; 4576 4577 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4578 &sc->bge_rx_coal_bds_int, 4579 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX, 4580 BGE_RX_COAL_BDS_INT_CHG); 4581 } 4582 4583 static int 4584 bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS) 4585 { 4586 struct bge_softc *sc = arg1; 4587 4588 return bge_sysctl_coal_chg(oidp, arg1, arg2, req, 4589 &sc->bge_tx_coal_bds_int, 4590 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX, 4591 BGE_TX_COAL_BDS_INT_CHG); 4592 } 4593 4594 static int 4595 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal, 4596 int coal_min, int coal_max, uint32_t coal_chg_mask) 4597 { 4598 struct bge_softc *sc = arg1; 4599 struct ifnet *ifp = &sc->arpcom.ac_if; 4600 int error = 0, v; 4601 4602 lwkt_serialize_enter(ifp->if_serializer); 4603 4604 v = *coal; 4605 error = sysctl_handle_int(oidp, &v, 0, req); 4606 if (!error && req->newptr != NULL) { 4607 if (v < coal_min || v > coal_max) { 4608 error = EINVAL; 4609 } else { 4610 *coal = v; 4611 sc->bge_coal_chg |= coal_chg_mask; 4612 } 4613 } 4614 4615 lwkt_serialize_exit(ifp->if_serializer); 4616 return error; 4617 } 4618 4619 static void 4620 bge_coal_change(struct bge_softc *sc) 4621 { 4622 struct ifnet *ifp = &sc->arpcom.ac_if; 4623 uint32_t val; 4624 4625 ASSERT_SERIALIZED(ifp->if_serializer); 4626 4627 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) { 4628 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, 4629 sc->bge_rx_coal_ticks); 4630 DELAY(10); 4631 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 4632 4633 if (bootverbose) { 4634 if_printf(ifp, "rx_coal_ticks -> %u\n", 4635 sc->bge_rx_coal_ticks); 4636 } 4637 } 4638 4639 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) { 4640 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, 4641 sc->bge_tx_coal_ticks); 4642 DELAY(10); 4643 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS); 4644 4645 if (bootverbose) { 4646 if_printf(ifp, "tx_coal_ticks -> %u\n", 4647 sc->bge_tx_coal_ticks); 4648 } 4649 } 4650 4651 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_CHG) { 4652 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, 4653 sc->bge_rx_coal_bds); 4654 DELAY(10); 4655 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 4656 4657 if (bootverbose) { 4658 if_printf(ifp, "rx_coal_bds -> %u\n", 4659 sc->bge_rx_coal_bds); 4660 } 4661 } 4662 4663 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_CHG) { 4664 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, 4665 sc->bge_tx_coal_bds); 4666 DELAY(10); 4667 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS); 4668 4669 if (bootverbose) { 4670 if_printf(ifp, "tx_max_coal_bds -> %u\n", 4671 sc->bge_tx_coal_bds); 4672 } 4673 } 4674 4675 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_INT_CHG) { 4676 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 4677 sc->bge_rx_coal_ticks_int); 4678 DELAY(10); 4679 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS_INT); 4680 4681 if (bootverbose) { 4682 if_printf(ifp, "rx_coal_ticks_int -> %u\n", 4683 sc->bge_rx_coal_ticks_int); 4684 } 4685 } 4686 4687 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_INT_CHG) { 4688 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 4689 sc->bge_tx_coal_ticks_int); 4690 DELAY(10); 4691 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS_INT); 4692 4693 if (bootverbose) { 4694 if_printf(ifp, "tx_coal_ticks_int -> %u\n", 4695 sc->bge_tx_coal_ticks_int); 4696 } 4697 } 4698 4699 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_INT_CHG) { 4700 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 4701 sc->bge_rx_coal_bds_int); 4702 DELAY(10); 4703 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT); 4704 4705 if (bootverbose) { 4706 if_printf(ifp, "rx_coal_bds_int -> %u\n", 4707 sc->bge_rx_coal_bds_int); 4708 } 4709 } 4710 4711 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_INT_CHG) { 4712 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 4713 sc->bge_tx_coal_bds_int); 4714 DELAY(10); 4715 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT); 4716 4717 if (bootverbose) { 4718 if_printf(ifp, "tx_coal_bds_int -> %u\n", 4719 sc->bge_tx_coal_bds_int); 4720 } 4721 } 4722 4723 sc->bge_coal_chg = 0; 4724 } 4725 4726 static void 4727 bge_enable_intr(struct bge_softc *sc) 4728 { 4729 struct ifnet *ifp = &sc->arpcom.ac_if; 4730 4731 lwkt_serialize_handler_enable(ifp->if_serializer); 4732 4733 /* 4734 * Enable interrupt. 4735 */ 4736 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 4737 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 4738 /* XXX Linux driver */ 4739 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24); 4740 } 4741 4742 /* 4743 * Unmask the interrupt when we stop polling. 4744 */ 4745 PCI_CLRBIT(sc->bge_dev, BGE_PCI_MISC_CTL, 4746 BGE_PCIMISCCTL_MASK_PCI_INTR, 4); 4747 4748 /* 4749 * Trigger another interrupt, since above writing 4750 * to interrupt mailbox0 may acknowledge pending 4751 * interrupt. 4752 */ 4753 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4754 } 4755 4756 static void 4757 bge_disable_intr(struct bge_softc *sc) 4758 { 4759 struct ifnet *ifp = &sc->arpcom.ac_if; 4760 4761 /* 4762 * Mask the interrupt when we start polling. 4763 */ 4764 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, 4765 BGE_PCIMISCCTL_MASK_PCI_INTR, 4); 4766 4767 /* 4768 * Acknowledge possible asserted interrupt. 4769 */ 4770 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4771 4772 sc->bge_npoll.ifpc_stcount = 0; 4773 4774 lwkt_serialize_handler_disable(ifp->if_serializer); 4775 } 4776 4777 static int 4778 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4779 { 4780 uint32_t mac_addr; 4781 int ret = 1; 4782 4783 mac_addr = bge_readmem_ind(sc, 0x0c14); 4784 if ((mac_addr >> 16) == 0x484b) { 4785 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4786 ether_addr[1] = (uint8_t)mac_addr; 4787 mac_addr = bge_readmem_ind(sc, 0x0c18); 4788 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4789 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4790 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4791 ether_addr[5] = (uint8_t)mac_addr; 4792 ret = 0; 4793 } 4794 return ret; 4795 } 4796 4797 static int 4798 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4799 { 4800 int mac_offset = BGE_EE_MAC_OFFSET; 4801 4802 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4803 mac_offset = BGE_EE_MAC_OFFSET_5906; 4804 4805 return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN); 4806 } 4807 4808 static int 4809 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4810 { 4811 if (sc->bge_flags & BGE_FLAG_NO_EEPROM) 4812 return 1; 4813 4814 return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4815 ETHER_ADDR_LEN); 4816 } 4817 4818 static int 4819 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4820 { 4821 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4822 /* NOTE: Order is critical */ 4823 bge_get_eaddr_mem, 4824 bge_get_eaddr_nvram, 4825 bge_get_eaddr_eeprom, 4826 NULL 4827 }; 4828 const bge_eaddr_fcn_t *func; 4829 4830 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4831 if ((*func)(sc, eaddr) == 0) 4832 break; 4833 } 4834 return (*func == NULL ? ENXIO : 0); 4835 } 4836 4837 /* 4838 * NOTE: 'm' is not freed upon failure 4839 */ 4840 struct mbuf * 4841 bge_defrag_shortdma(struct mbuf *m) 4842 { 4843 struct mbuf *n; 4844 int found; 4845 4846 /* 4847 * If device receive two back-to-back send BDs with less than 4848 * or equal to 8 total bytes then the device may hang. The two 4849 * back-to-back send BDs must in the same frame for this failure 4850 * to occur. Scan mbuf chains and see whether two back-to-back 4851 * send BDs are there. If this is the case, allocate new mbuf 4852 * and copy the frame to workaround the silicon bug. 4853 */ 4854 for (n = m, found = 0; n != NULL; n = n->m_next) { 4855 if (n->m_len < 8) { 4856 found++; 4857 if (found > 1) 4858 break; 4859 continue; 4860 } 4861 found = 0; 4862 } 4863 4864 if (found > 1) 4865 n = m_defrag(m, MB_DONTWAIT); 4866 else 4867 n = m; 4868 return n; 4869 } 4870 4871 static void 4872 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 4873 { 4874 int i; 4875 4876 BGE_CLRBIT(sc, reg, bit); 4877 for (i = 0; i < BGE_TIMEOUT; i++) { 4878 if ((CSR_READ_4(sc, reg) & bit) == 0) 4879 return; 4880 DELAY(100); 4881 } 4882 } 4883 4884 static void 4885 bge_link_poll(struct bge_softc *sc) 4886 { 4887 uint32_t status; 4888 4889 status = CSR_READ_4(sc, BGE_MAC_STS); 4890 if ((status & sc->bge_link_chg) || sc->bge_link_evt) { 4891 sc->bge_link_evt = 0; 4892 sc->bge_link_upd(sc, status); 4893 } 4894 } 4895 4896 static void 4897 bge_enable_msi(struct bge_softc *sc) 4898 { 4899 uint32_t msi_mode; 4900 4901 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE); 4902 msi_mode |= BGE_MSIMODE_ENABLE; 4903 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) { 4904 /* 4905 * According to all of the datasheets that are publicly 4906 * available, bit 5 of the MSI_MODE is defined to be 4907 * "MSI FIFO Underrun Attn" for BCM5755+ and BCM5906, on 4908 * which "oneshot MSI" is enabled. However, it is always 4909 * safe to clear it here. 4910 */ 4911 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE; 4912 } 4913 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode); 4914 } 4915 4916 static int 4917 bge_setup_tso(struct bge_softc *sc, struct mbuf **mp, 4918 uint16_t *mss0, uint16_t *flags0) 4919 { 4920 struct mbuf *m; 4921 struct ip *ip; 4922 struct tcphdr *th; 4923 int thoff, iphlen, hoff, hlen; 4924 uint16_t flags, mss; 4925 4926 m = *mp; 4927 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 4928 4929 hoff = m->m_pkthdr.csum_lhlen; 4930 iphlen = m->m_pkthdr.csum_iphlen; 4931 thoff = m->m_pkthdr.csum_thlen; 4932 4933 KASSERT(hoff > 0, ("invalid ether header len")); 4934 KASSERT(iphlen > 0, ("invalid ip header len")); 4935 KASSERT(thoff > 0, ("invalid tcp header len")); 4936 4937 if (__predict_false(m->m_len < hoff + iphlen + thoff)) { 4938 m = m_pullup(m, hoff + iphlen + thoff); 4939 if (m == NULL) { 4940 *mp = NULL; 4941 return ENOBUFS; 4942 } 4943 *mp = m; 4944 } 4945 ip = mtodoff(m, struct ip *, hoff); 4946 th = mtodoff(m, struct tcphdr *, hoff + iphlen); 4947 4948 mss = m->m_pkthdr.tso_segsz; 4949 flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA; 4950 4951 ip->ip_len = htons(mss + iphlen + thoff); 4952 th->th_sum = 0; 4953 4954 hlen = (iphlen + thoff) >> 2; 4955 mss |= (hlen << 11); 4956 4957 *mss0 = mss; 4958 *flags0 = flags; 4959 4960 return 0; 4961 } 4962