1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $ 34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.28 2005/05/05 22:57:44 swildner Exp $ 35 * 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Engineer, Wind River Systems 43 */ 44 45 /* 46 * The Broadcom BCM5700 is based on technology originally developed by 47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 51 * frames, highly configurable RX filtering, and 16 RX and TX queues 52 * (which, along with RX filter rules, can be used for QOS applications). 53 * Other features, such as TCP segmentation, may be available as part 54 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 55 * firmware images can be stored in hardware and need not be compiled 56 * into the driver. 57 * 58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 60 * 61 * The BCM5701 is a single-chip solution incorporating both the BCM5700 62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 63 * does not support external SSRAM. 64 * 65 * Broadcom also produces a variation of the BCM5700 under the "Altima" 66 * brand name, which is functionally similar but lacks PCI-X support. 67 * 68 * Without external SSRAM, you can only have at most 4 TX rings, 69 * and the use of the mini RX ring is disabled. This seems to imply 70 * that these features are simply not available on the BCM5701. As a 71 * result, this driver does not implement any support for the mini RX 72 * ring. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/sockio.h> 78 #include <sys/mbuf.h> 79 #include <sys/malloc.h> 80 #include <sys/kernel.h> 81 #include <sys/socket.h> 82 #include <sys/queue.h> 83 84 #include <net/if.h> 85 #include <net/ifq_var.h> 86 #include <net/if_arp.h> 87 #include <net/ethernet.h> 88 #include <net/if_dl.h> 89 #include <net/if_media.h> 90 91 #include <net/bpf.h> 92 93 #include <net/if_types.h> 94 #include <net/vlan/if_vlan_var.h> 95 96 #include <netinet/in_systm.h> 97 #include <netinet/in.h> 98 #include <netinet/ip.h> 99 100 #include <vm/vm.h> /* for vtophys */ 101 #include <vm/pmap.h> /* for vtophys */ 102 #include <machine/clock.h> /* for DELAY */ 103 #include <machine/bus_memio.h> 104 #include <machine/bus.h> 105 #include <machine/resource.h> 106 #include <sys/bus.h> 107 #include <sys/rman.h> 108 109 #include <dev/netif/mii_layer/mii.h> 110 #include <dev/netif/mii_layer/miivar.h> 111 #include <dev/netif/mii_layer/miidevs.h> 112 #include <dev/netif/mii_layer/brgphyreg.h> 113 114 #include <bus/pci/pcidevs.h> 115 #include <bus/pci/pcireg.h> 116 #include <bus/pci/pcivar.h> 117 118 #include "if_bgereg.h" 119 120 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 121 122 /* "controller miibus0" required. See GENERIC if you get errors here. */ 123 #include "miibus_if.h" 124 125 /* 126 * Various supported device vendors/types and their names. Note: the 127 * spec seems to indicate that the hardware still has Alteon's vendor 128 * ID burned into it, though it will always be overriden by the vendor 129 * ID in the EEPROM. Just to be safe, we cover all possibilities. 130 */ 131 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 132 133 static struct bge_type bge_devs[] = { 134 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700, 135 "Broadcom BCM5700 Gigabit Ethernet" }, 136 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700, 137 "Broadcom BCM5701 Gigabit Ethernet" }, 138 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700, 139 "Broadcom BCM5700 Gigabit Ethernet" }, 140 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701, 141 "Broadcom BCM5701 Gigabit Ethernet" }, 142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X, 143 "Broadcom BCM5702X Gigabit Ethernet" }, 144 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5702X, 145 "Broadcom BCM5702X Gigabit Ethernet" }, 146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X, 147 "Broadcom BCM5703X Gigabit Ethernet" }, 148 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5703X, 149 "Broadcom BCM5703X Gigabit Ethernet" }, 150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C, 151 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S, 153 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705, 155 "Broadcom BCM5705 Gigabit Ethernet" }, 156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M, 157 "Broadcom BCM5705M Gigabit Ethernet" }, 158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705_ALT, 159 "Broadcom BCM5705M Gigabit Ethernet" }, 160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782, 161 "Broadcom BCM5782 Gigabit Ethernet" }, 162 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5788, 163 "Broadcom BCM5788 Gigabit Ethernet" }, 164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901, 165 "Broadcom BCM5901 Fast Ethernet" }, 166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2, 167 "Broadcom BCM5901A2 Fast Ethernet" }, 168 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 169 "SysKonnect Gigabit Ethernet" }, 170 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000, 171 "Altima AC1000 Gigabit Ethernet" }, 172 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001, 173 "Altima AC1002 Gigabit Ethernet" }, 174 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100, 175 "Altima AC9100 Gigabit Ethernet" }, 176 { 0, 0, NULL } 177 }; 178 179 static int bge_probe (device_t); 180 static int bge_attach (device_t); 181 static int bge_detach (device_t); 182 static void bge_release_resources 183 (struct bge_softc *); 184 static void bge_txeof (struct bge_softc *); 185 static void bge_rxeof (struct bge_softc *); 186 187 static void bge_tick (void *); 188 static void bge_stats_update (struct bge_softc *); 189 static void bge_stats_update_regs 190 (struct bge_softc *); 191 static int bge_encap (struct bge_softc *, struct mbuf *, 192 u_int32_t *); 193 194 static void bge_intr (void *); 195 static void bge_start (struct ifnet *); 196 static int bge_ioctl (struct ifnet *, u_long, caddr_t, 197 struct ucred *); 198 static void bge_init (void *); 199 static void bge_stop (struct bge_softc *); 200 static void bge_watchdog (struct ifnet *); 201 static void bge_shutdown (device_t); 202 static int bge_ifmedia_upd (struct ifnet *); 203 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 204 205 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, 206 int, u_int8_t *); 207 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 208 209 static u_int32_t bge_crc (caddr_t); 210 static void bge_setmulti (struct bge_softc *); 211 212 static void bge_handle_events (struct bge_softc *); 213 static int bge_alloc_jumbo_mem (struct bge_softc *); 214 static void bge_free_jumbo_mem (struct bge_softc *); 215 static void *bge_jalloc (struct bge_softc *); 216 static void bge_jfree (caddr_t, u_int); 217 static void bge_jref (caddr_t, u_int); 218 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 219 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 220 static int bge_init_rx_ring_std (struct bge_softc *); 221 static void bge_free_rx_ring_std (struct bge_softc *); 222 static int bge_init_rx_ring_jumbo (struct bge_softc *); 223 static void bge_free_rx_ring_jumbo (struct bge_softc *); 224 static void bge_free_tx_ring (struct bge_softc *); 225 static int bge_init_tx_ring (struct bge_softc *); 226 227 static int bge_chipinit (struct bge_softc *); 228 static int bge_blockinit (struct bge_softc *); 229 230 #ifdef notdef 231 static u_int8_t bge_vpd_readbyte (struct bge_softc *, int); 232 static void bge_vpd_read_res (struct bge_softc *, 233 struct vpd_res *, int); 234 static void bge_vpd_read (struct bge_softc *); 235 #endif 236 237 static u_int32_t bge_readmem_ind 238 (struct bge_softc *, int); 239 static void bge_writemem_ind (struct bge_softc *, int, int); 240 #ifdef notdef 241 static u_int32_t bge_readreg_ind 242 (struct bge_softc *, int); 243 #endif 244 static void bge_writereg_ind (struct bge_softc *, int, int); 245 246 static int bge_miibus_readreg (device_t, int, int); 247 static int bge_miibus_writereg (device_t, int, int, int); 248 static void bge_miibus_statchg (device_t); 249 250 static void bge_reset (struct bge_softc *); 251 252 static device_method_t bge_methods[] = { 253 /* Device interface */ 254 DEVMETHOD(device_probe, bge_probe), 255 DEVMETHOD(device_attach, bge_attach), 256 DEVMETHOD(device_detach, bge_detach), 257 DEVMETHOD(device_shutdown, bge_shutdown), 258 259 /* bus interface */ 260 DEVMETHOD(bus_print_child, bus_generic_print_child), 261 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 262 263 /* MII interface */ 264 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 265 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 266 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 267 268 { 0, 0 } 269 }; 270 271 static driver_t bge_driver = { 272 "bge", 273 bge_methods, 274 sizeof(struct bge_softc) 275 }; 276 277 static devclass_t bge_devclass; 278 279 DECLARE_DUMMY_MODULE(if_bge); 280 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 281 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 282 283 static u_int32_t 284 bge_readmem_ind(sc, off) 285 struct bge_softc *sc; 286 int off; 287 { 288 device_t dev; 289 290 dev = sc->bge_dev; 291 292 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 293 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 294 } 295 296 static void 297 bge_writemem_ind(sc, off, val) 298 struct bge_softc *sc; 299 int off, val; 300 { 301 device_t dev; 302 303 dev = sc->bge_dev; 304 305 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 306 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 307 308 return; 309 } 310 311 #ifdef notdef 312 static u_int32_t 313 bge_readreg_ind(sc, off) 314 struct bge_softc *sc; 315 int off; 316 { 317 device_t dev; 318 319 dev = sc->bge_dev; 320 321 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 322 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 323 } 324 #endif 325 326 static void 327 bge_writereg_ind(sc, off, val) 328 struct bge_softc *sc; 329 int off, val; 330 { 331 device_t dev; 332 333 dev = sc->bge_dev; 334 335 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 336 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 337 338 return; 339 } 340 341 #ifdef notdef 342 static u_int8_t 343 bge_vpd_readbyte(sc, addr) 344 struct bge_softc *sc; 345 int addr; 346 { 347 int i; 348 device_t dev; 349 u_int32_t val; 350 351 dev = sc->bge_dev; 352 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 353 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 354 DELAY(10); 355 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 356 break; 357 } 358 359 if (i == BGE_TIMEOUT) { 360 printf("bge%d: VPD read timed out\n", sc->bge_unit); 361 return(0); 362 } 363 364 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 365 366 return((val >> ((addr % 4) * 8)) & 0xFF); 367 } 368 369 static void 370 bge_vpd_read_res(sc, res, addr) 371 struct bge_softc *sc; 372 struct vpd_res *res; 373 int addr; 374 { 375 int i; 376 u_int8_t *ptr; 377 378 ptr = (u_int8_t *)res; 379 for (i = 0; i < sizeof(struct vpd_res); i++) 380 ptr[i] = bge_vpd_readbyte(sc, i + addr); 381 382 return; 383 } 384 385 static void 386 bge_vpd_read(sc) 387 struct bge_softc *sc; 388 { 389 int pos = 0, i; 390 struct vpd_res res; 391 392 if (sc->bge_vpd_prodname != NULL) 393 free(sc->bge_vpd_prodname, M_DEVBUF); 394 if (sc->bge_vpd_readonly != NULL) 395 free(sc->bge_vpd_readonly, M_DEVBUF); 396 sc->bge_vpd_prodname = NULL; 397 sc->bge_vpd_readonly = NULL; 398 399 bge_vpd_read_res(sc, &res, pos); 400 401 if (res.vr_id != VPD_RES_ID) { 402 printf("bge%d: bad VPD resource id: expected %x got %x\n", 403 sc->bge_unit, VPD_RES_ID, res.vr_id); 404 return; 405 } 406 407 pos += sizeof(res); 408 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT); 409 for (i = 0; i < res.vr_len; i++) 410 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 411 sc->bge_vpd_prodname[i] = '\0'; 412 pos += i; 413 414 bge_vpd_read_res(sc, &res, pos); 415 416 if (res.vr_id != VPD_RES_READ) { 417 printf("bge%d: bad VPD resource id: expected %x got %x\n", 418 sc->bge_unit, VPD_RES_READ, res.vr_id); 419 return; 420 } 421 422 pos += sizeof(res); 423 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT); 424 for (i = 0; i < res.vr_len + 1; i++) 425 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 426 427 return; 428 } 429 #endif 430 431 /* 432 * Read a byte of data stored in the EEPROM at address 'addr.' The 433 * BCM570x supports both the traditional bitbang interface and an 434 * auto access interface for reading the EEPROM. We use the auto 435 * access method. 436 */ 437 static u_int8_t 438 bge_eeprom_getbyte(sc, addr, dest) 439 struct bge_softc *sc; 440 int addr; 441 u_int8_t *dest; 442 { 443 int i; 444 u_int32_t byte = 0; 445 446 /* 447 * Enable use of auto EEPROM access so we can avoid 448 * having to use the bitbang method. 449 */ 450 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 451 452 /* Reset the EEPROM, load the clock period. */ 453 CSR_WRITE_4(sc, BGE_EE_ADDR, 454 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 455 DELAY(20); 456 457 /* Issue the read EEPROM command. */ 458 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 459 460 /* Wait for completion */ 461 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 462 DELAY(10); 463 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 464 break; 465 } 466 467 if (i == BGE_TIMEOUT) { 468 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 469 return(0); 470 } 471 472 /* Get result. */ 473 byte = CSR_READ_4(sc, BGE_EE_DATA); 474 475 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 476 477 return(0); 478 } 479 480 /* 481 * Read a sequence of bytes from the EEPROM. 482 */ 483 static int 484 bge_read_eeprom(sc, dest, off, cnt) 485 struct bge_softc *sc; 486 caddr_t dest; 487 int off; 488 int cnt; 489 { 490 int err = 0, i; 491 u_int8_t byte = 0; 492 493 for (i = 0; i < cnt; i++) { 494 err = bge_eeprom_getbyte(sc, off + i, &byte); 495 if (err) 496 break; 497 *(dest + i) = byte; 498 } 499 500 return(err ? 1 : 0); 501 } 502 503 static int 504 bge_miibus_readreg(dev, phy, reg) 505 device_t dev; 506 int phy, reg; 507 { 508 struct bge_softc *sc; 509 struct ifnet *ifp; 510 u_int32_t val, autopoll; 511 int i; 512 513 sc = device_get_softc(dev); 514 ifp = &sc->arpcom.ac_if; 515 516 /* 517 * Broadcom's own driver always assumes the internal 518 * PHY is at GMII address 1. On some chips, the PHY responds 519 * to accesses at all addresses, which could cause us to 520 * bogusly attach the PHY 32 times at probe type. Always 521 * restricting the lookup to address 1 is simpler than 522 * trying to figure out which chips revisions should be 523 * special-cased. 524 */ 525 if (phy != 1) 526 return(0); 527 528 /* Reading with autopolling on may trigger PCI errors */ 529 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 530 if (autopoll & BGE_MIMODE_AUTOPOLL) { 531 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 532 DELAY(40); 533 } 534 535 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 536 BGE_MIPHY(phy)|BGE_MIREG(reg)); 537 538 for (i = 0; i < BGE_TIMEOUT; i++) { 539 val = CSR_READ_4(sc, BGE_MI_COMM); 540 if (!(val & BGE_MICOMM_BUSY)) 541 break; 542 } 543 544 if (i == BGE_TIMEOUT) { 545 printf("bge%d: PHY read timed out\n", sc->bge_unit); 546 val = 0; 547 goto done; 548 } 549 550 val = CSR_READ_4(sc, BGE_MI_COMM); 551 552 done: 553 if (autopoll & BGE_MIMODE_AUTOPOLL) { 554 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 555 DELAY(40); 556 } 557 558 if (val & BGE_MICOMM_READFAIL) 559 return(0); 560 561 return(val & 0xFFFF); 562 } 563 564 static int 565 bge_miibus_writereg(dev, phy, reg, val) 566 device_t dev; 567 int phy, reg, val; 568 { 569 struct bge_softc *sc; 570 u_int32_t autopoll; 571 int i; 572 573 sc = device_get_softc(dev); 574 575 /* Reading with autopolling on may trigger PCI errors */ 576 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 577 if (autopoll & BGE_MIMODE_AUTOPOLL) { 578 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 579 DELAY(40); 580 } 581 582 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 583 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 584 585 for (i = 0; i < BGE_TIMEOUT; i++) { 586 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 587 break; 588 } 589 590 if (autopoll & BGE_MIMODE_AUTOPOLL) { 591 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 592 DELAY(40); 593 } 594 595 if (i == BGE_TIMEOUT) { 596 printf("bge%d: PHY read timed out\n", sc->bge_unit); 597 return(0); 598 } 599 600 return(0); 601 } 602 603 static void 604 bge_miibus_statchg(dev) 605 device_t dev; 606 { 607 struct bge_softc *sc; 608 struct mii_data *mii; 609 610 sc = device_get_softc(dev); 611 mii = device_get_softc(sc->bge_miibus); 612 613 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 614 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 615 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 616 } else { 617 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 618 } 619 620 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 621 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 622 } else { 623 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 624 } 625 626 return; 627 } 628 629 /* 630 * Handle events that have triggered interrupts. 631 */ 632 static void 633 bge_handle_events(sc) 634 struct bge_softc *sc; 635 { 636 637 return; 638 } 639 640 /* 641 * Memory management for jumbo frames. 642 */ 643 644 static int 645 bge_alloc_jumbo_mem(sc) 646 struct bge_softc *sc; 647 { 648 caddr_t ptr; 649 int i; 650 struct bge_jpool_entry *entry; 651 652 /* Grab a big chunk o' storage. */ 653 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 654 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 655 656 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 657 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 658 return(ENOBUFS); 659 } 660 661 SLIST_INIT(&sc->bge_jfree_listhead); 662 SLIST_INIT(&sc->bge_jinuse_listhead); 663 664 /* 665 * Now divide it up into 9K pieces and save the addresses 666 * in an array. Note that we play an evil trick here by using 667 * the first few bytes in the buffer to hold the the address 668 * of the softc structure for this interface. This is because 669 * bge_jfree() needs it, but it is called by the mbuf management 670 * code which will not pass it to us explicitly. 671 */ 672 ptr = sc->bge_cdata.bge_jumbo_buf; 673 for (i = 0; i < BGE_JSLOTS; i++) { 674 u_int64_t **aptr; 675 aptr = (u_int64_t **)ptr; 676 aptr[0] = (u_int64_t *)sc; 677 ptr += sizeof(u_int64_t); 678 sc->bge_cdata.bge_jslots[i].bge_buf = ptr; 679 sc->bge_cdata.bge_jslots[i].bge_inuse = 0; 680 ptr += (BGE_JLEN - sizeof(u_int64_t)); 681 entry = malloc(sizeof(struct bge_jpool_entry), 682 M_DEVBUF, M_INTWAIT); 683 entry->slot = i; 684 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 685 entry, jpool_entries); 686 } 687 688 return(0); 689 } 690 691 static void 692 bge_free_jumbo_mem(sc) 693 struct bge_softc *sc; 694 { 695 int i; 696 struct bge_jpool_entry *entry; 697 698 for (i = 0; i < BGE_JSLOTS; i++) { 699 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 700 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 701 free(entry, M_DEVBUF); 702 } 703 704 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 705 706 return; 707 } 708 709 /* 710 * Allocate a jumbo buffer. 711 */ 712 static void * 713 bge_jalloc(sc) 714 struct bge_softc *sc; 715 { 716 struct bge_jpool_entry *entry; 717 718 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 719 720 if (entry == NULL) { 721 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 722 return(NULL); 723 } 724 725 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 726 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 727 sc->bge_cdata.bge_jslots[entry->slot].bge_inuse = 1; 728 return(sc->bge_cdata.bge_jslots[entry->slot].bge_buf); 729 } 730 731 /* 732 * Adjust usage count on a jumbo buffer. 733 */ 734 static void 735 bge_jref(buf, size) 736 caddr_t buf; 737 u_int size; 738 { 739 struct bge_softc *sc; 740 u_int64_t **aptr; 741 int i; 742 743 /* Extract the softc struct pointer. */ 744 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 745 sc = (struct bge_softc *)(aptr[0]); 746 747 if (sc == NULL) 748 panic("bge_jref: can't find softc pointer!"); 749 750 if (size != BGE_JUMBO_FRAMELEN) 751 panic("bge_jref: adjusting refcount of buf of wrong size!"); 752 753 /* calculate the slot this buffer belongs to */ 754 755 i = ((vm_offset_t)aptr 756 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 757 758 if ((i < 0) || (i >= BGE_JSLOTS)) 759 panic("bge_jref: asked to reference buffer " 760 "that we don't manage!"); 761 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0) 762 panic("bge_jref: buffer already free!"); 763 else 764 sc->bge_cdata.bge_jslots[i].bge_inuse++; 765 766 return; 767 } 768 769 /* 770 * Release a jumbo buffer. 771 */ 772 static void 773 bge_jfree(buf, size) 774 caddr_t buf; 775 u_int size; 776 { 777 struct bge_softc *sc; 778 u_int64_t **aptr; 779 int i; 780 struct bge_jpool_entry *entry; 781 782 /* Extract the softc struct pointer. */ 783 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 784 sc = (struct bge_softc *)(aptr[0]); 785 786 if (sc == NULL) 787 panic("bge_jfree: can't find softc pointer!"); 788 789 if (size != BGE_JUMBO_FRAMELEN) 790 panic("bge_jfree: freeing buffer of wrong size!"); 791 792 /* calculate the slot this buffer belongs to */ 793 794 i = ((vm_offset_t)aptr 795 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 796 797 if ((i < 0) || (i >= BGE_JSLOTS)) 798 panic("bge_jfree: asked to free buffer that we don't manage!"); 799 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0) 800 panic("bge_jfree: buffer already free!"); 801 else { 802 sc->bge_cdata.bge_jslots[i].bge_inuse--; 803 if(sc->bge_cdata.bge_jslots[i].bge_inuse == 0) { 804 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 805 if (entry == NULL) 806 panic("bge_jfree: buffer not in use!"); 807 entry->slot = i; 808 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, 809 jpool_entries); 810 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 811 entry, jpool_entries); 812 } 813 } 814 815 return; 816 } 817 818 819 /* 820 * Intialize a standard receive ring descriptor. 821 */ 822 static int 823 bge_newbuf_std(sc, i, m) 824 struct bge_softc *sc; 825 int i; 826 struct mbuf *m; 827 { 828 struct mbuf *m_new = NULL; 829 struct bge_rx_bd *r; 830 831 if (m == NULL) { 832 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 833 if (m_new == NULL) { 834 return(ENOBUFS); 835 } 836 837 MCLGET(m_new, MB_DONTWAIT); 838 if (!(m_new->m_flags & M_EXT)) { 839 m_freem(m_new); 840 return(ENOBUFS); 841 } 842 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 843 } else { 844 m_new = m; 845 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 846 m_new->m_data = m_new->m_ext.ext_buf; 847 } 848 849 if (!sc->bge_rx_alignment_bug) 850 m_adj(m_new, ETHER_ALIGN); 851 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 852 r = &sc->bge_rdata->bge_rx_std_ring[i]; 853 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 854 r->bge_flags = BGE_RXBDFLAG_END; 855 r->bge_len = m_new->m_len; 856 r->bge_idx = i; 857 858 return(0); 859 } 860 861 /* 862 * Initialize a jumbo receive ring descriptor. This allocates 863 * a jumbo buffer from the pool managed internally by the driver. 864 */ 865 static int 866 bge_newbuf_jumbo(sc, i, m) 867 struct bge_softc *sc; 868 int i; 869 struct mbuf *m; 870 { 871 struct mbuf *m_new = NULL; 872 struct bge_rx_bd *r; 873 874 if (m == NULL) { 875 caddr_t *buf = NULL; 876 877 /* Allocate the mbuf. */ 878 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 879 if (m_new == NULL) { 880 return(ENOBUFS); 881 } 882 883 /* Allocate the jumbo buffer */ 884 buf = bge_jalloc(sc); 885 if (buf == NULL) { 886 m_freem(m_new); 887 printf("bge%d: jumbo allocation failed " 888 "-- packet dropped!\n", sc->bge_unit); 889 return(ENOBUFS); 890 } 891 892 /* Attach the buffer to the mbuf. */ 893 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 894 m_new->m_flags |= M_EXT | M_EXT_OLD; 895 m_new->m_len = m_new->m_pkthdr.len = 896 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 897 m_new->m_ext.ext_nfree.old = bge_jfree; 898 m_new->m_ext.ext_nref.old = bge_jref; 899 } else { 900 m_new = m; 901 m_new->m_data = m_new->m_ext.ext_buf; 902 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 903 } 904 905 if (!sc->bge_rx_alignment_bug) 906 m_adj(m_new, ETHER_ALIGN); 907 /* Set up the descriptor. */ 908 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 909 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 910 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 911 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 912 r->bge_len = m_new->m_len; 913 r->bge_idx = i; 914 915 return(0); 916 } 917 918 /* 919 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 920 * that's 1MB or memory, which is a lot. For now, we fill only the first 921 * 256 ring entries and hope that our CPU is fast enough to keep up with 922 * the NIC. 923 */ 924 static int 925 bge_init_rx_ring_std(sc) 926 struct bge_softc *sc; 927 { 928 int i; 929 930 for (i = 0; i < BGE_SSLOTS; i++) { 931 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 932 return(ENOBUFS); 933 }; 934 935 sc->bge_std = i - 1; 936 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 937 938 return(0); 939 } 940 941 static void 942 bge_free_rx_ring_std(sc) 943 struct bge_softc *sc; 944 { 945 int i; 946 947 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 948 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 949 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 950 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 951 } 952 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 953 sizeof(struct bge_rx_bd)); 954 } 955 956 return; 957 } 958 959 static int 960 bge_init_rx_ring_jumbo(sc) 961 struct bge_softc *sc; 962 { 963 int i; 964 struct bge_rcb *rcb; 965 966 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 967 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 968 return(ENOBUFS); 969 }; 970 971 sc->bge_jumbo = i - 1; 972 973 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 974 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 975 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 976 977 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 978 979 return(0); 980 } 981 982 static void 983 bge_free_rx_ring_jumbo(sc) 984 struct bge_softc *sc; 985 { 986 int i; 987 988 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 989 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 990 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 991 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 992 } 993 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 994 sizeof(struct bge_rx_bd)); 995 } 996 997 return; 998 } 999 1000 static void 1001 bge_free_tx_ring(sc) 1002 struct bge_softc *sc; 1003 { 1004 int i; 1005 1006 if (sc->bge_rdata->bge_tx_ring == NULL) 1007 return; 1008 1009 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1010 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1011 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1012 sc->bge_cdata.bge_tx_chain[i] = NULL; 1013 } 1014 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 1015 sizeof(struct bge_tx_bd)); 1016 } 1017 1018 return; 1019 } 1020 1021 static int 1022 bge_init_tx_ring(sc) 1023 struct bge_softc *sc; 1024 { 1025 sc->bge_txcnt = 0; 1026 sc->bge_tx_saved_considx = 0; 1027 1028 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1029 /* 5700 b2 errata */ 1030 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1031 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1032 1033 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1034 /* 5700 b2 errata */ 1035 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1036 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1037 1038 return(0); 1039 } 1040 1041 #define BGE_POLY 0xEDB88320 1042 1043 static u_int32_t 1044 bge_crc(addr) 1045 caddr_t addr; 1046 { 1047 u_int32_t idx, bit, data, crc; 1048 1049 /* Compute CRC for the address value. */ 1050 crc = 0xFFFFFFFF; /* initial value */ 1051 1052 for (idx = 0; idx < 6; idx++) { 1053 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1054 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 1055 } 1056 1057 return(crc & 0x7F); 1058 } 1059 1060 static void 1061 bge_setmulti(sc) 1062 struct bge_softc *sc; 1063 { 1064 struct ifnet *ifp; 1065 struct ifmultiaddr *ifma; 1066 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1067 int h, i; 1068 1069 ifp = &sc->arpcom.ac_if; 1070 1071 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1072 for (i = 0; i < 4; i++) 1073 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1074 return; 1075 } 1076 1077 /* First, zot all the existing filters. */ 1078 for (i = 0; i < 4; i++) 1079 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1080 1081 /* Now program new ones. */ 1082 for (ifma = ifp->if_multiaddrs.lh_first; 1083 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1084 if (ifma->ifma_addr->sa_family != AF_LINK) 1085 continue; 1086 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1087 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1088 } 1089 1090 for (i = 0; i < 4; i++) 1091 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1092 1093 return; 1094 } 1095 1096 /* 1097 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1098 * self-test results. 1099 */ 1100 static int 1101 bge_chipinit(sc) 1102 struct bge_softc *sc; 1103 { 1104 int i; 1105 u_int32_t dma_rw_ctl; 1106 1107 /* Set endianness before we access any non-PCI registers. */ 1108 #if BYTE_ORDER == BIG_ENDIAN 1109 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1110 BGE_BIGENDIAN_INIT, 4); 1111 #else 1112 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1113 BGE_LITTLEENDIAN_INIT, 4); 1114 #endif 1115 1116 /* 1117 * Check the 'ROM failed' bit on the RX CPU to see if 1118 * self-tests passed. 1119 */ 1120 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1121 printf("bge%d: RX CPU self-diagnostics failed!\n", 1122 sc->bge_unit); 1123 return(ENODEV); 1124 } 1125 1126 /* Clear the MAC control register */ 1127 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1128 1129 /* 1130 * Clear the MAC statistics block in the NIC's 1131 * internal memory. 1132 */ 1133 for (i = BGE_STATS_BLOCK; 1134 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1135 BGE_MEMWIN_WRITE(sc, i, 0); 1136 1137 for (i = BGE_STATUS_BLOCK; 1138 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1139 BGE_MEMWIN_WRITE(sc, i, 0); 1140 1141 /* Set up the PCI DMA control register. */ 1142 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1143 BGE_PCISTATE_PCI_BUSMODE) { 1144 /* Conventional PCI bus */ 1145 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1146 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1147 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1148 (0x0F); 1149 } else { 1150 /* PCI-X bus */ 1151 /* 1152 * The 5704 uses a different encoding of read/write 1153 * watermarks. 1154 */ 1155 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1156 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1157 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1158 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1159 else 1160 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1161 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1162 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1163 (0x0F); 1164 1165 /* 1166 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1167 * for hardware bugs. 1168 */ 1169 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1170 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1171 u_int32_t tmp; 1172 1173 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1174 if (tmp == 0x6 || tmp == 0x7) 1175 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1176 } 1177 } 1178 1179 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1180 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1181 sc->bge_asicrev == BGE_ASICREV_BCM5705) 1182 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1183 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1184 1185 /* 1186 * Set up general mode register. 1187 */ 1188 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1189 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1190 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1191 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1192 1193 /* 1194 * Disable memory write invalidate. Apparently it is not supported 1195 * properly by these devices. 1196 */ 1197 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1198 1199 /* Set the timer prescaler (always 66Mhz) */ 1200 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1201 1202 return(0); 1203 } 1204 1205 static int 1206 bge_blockinit(sc) 1207 struct bge_softc *sc; 1208 { 1209 struct bge_rcb *rcb; 1210 volatile struct bge_rcb *vrcb; 1211 int i; 1212 1213 /* 1214 * Initialize the memory window pointer register so that 1215 * we can access the first 32K of internal NIC RAM. This will 1216 * allow us to set up the TX send ring RCBs and the RX return 1217 * ring RCBs, plus other things which live in NIC memory. 1218 */ 1219 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1220 1221 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1222 1223 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1224 /* Configure mbuf memory pool */ 1225 if (sc->bge_extram) { 1226 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1227 BGE_EXT_SSRAM); 1228 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1229 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1230 else 1231 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1232 } else { 1233 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1234 BGE_BUFFPOOL_1); 1235 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1236 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1237 else 1238 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1239 } 1240 1241 /* Configure DMA resource pool */ 1242 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1243 BGE_DMA_DESCRIPTORS); 1244 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1245 } 1246 1247 /* Configure mbuf pool watermarks */ 1248 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 1249 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1250 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1251 } else { 1252 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1253 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1254 } 1255 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1256 1257 /* Configure DMA resource watermarks */ 1258 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1259 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1260 1261 /* Enable buffer manager */ 1262 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1263 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1264 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1265 1266 /* Poll for buffer manager start indication */ 1267 for (i = 0; i < BGE_TIMEOUT; i++) { 1268 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1269 break; 1270 DELAY(10); 1271 } 1272 1273 if (i == BGE_TIMEOUT) { 1274 printf("bge%d: buffer manager failed to start\n", 1275 sc->bge_unit); 1276 return(ENXIO); 1277 } 1278 } 1279 1280 /* Enable flow-through queues */ 1281 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1282 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1283 1284 /* Wait until queue initialization is complete */ 1285 for (i = 0; i < BGE_TIMEOUT; i++) { 1286 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1287 break; 1288 DELAY(10); 1289 } 1290 1291 if (i == BGE_TIMEOUT) { 1292 printf("bge%d: flow-through queue init failed\n", 1293 sc->bge_unit); 1294 return(ENXIO); 1295 } 1296 1297 /* Initialize the standard RX ring control block */ 1298 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1299 BGE_HOSTADDR(rcb->bge_hostaddr, 1300 vtophys(&sc->bge_rdata->bge_rx_std_ring)); 1301 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1302 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1303 else 1304 rcb->bge_maxlen_flags = 1305 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1306 if (sc->bge_extram) 1307 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1308 else 1309 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1310 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1311 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1312 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1313 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1314 1315 /* 1316 * Initialize the jumbo RX ring control block 1317 * We set the 'ring disabled' bit in the flags 1318 * field until we're actually ready to start 1319 * using this ring (i.e. once we set the MTU 1320 * high enough to require it). 1321 */ 1322 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1323 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1324 BGE_HOSTADDR(rcb->bge_hostaddr, 1325 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring)); 1326 rcb->bge_maxlen_flags = 1327 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1328 BGE_RCB_FLAG_RING_DISABLED); 1329 if (sc->bge_extram) 1330 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1331 else 1332 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1333 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1334 rcb->bge_hostaddr.bge_addr_hi); 1335 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1336 rcb->bge_hostaddr.bge_addr_lo); 1337 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1338 rcb->bge_maxlen_flags); 1339 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1340 1341 /* Set up dummy disabled mini ring RCB */ 1342 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1343 rcb->bge_maxlen_flags = 1344 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1345 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1346 rcb->bge_maxlen_flags); 1347 } 1348 1349 /* 1350 * Set the BD ring replentish thresholds. The recommended 1351 * values are 1/8th the number of descriptors allocated to 1352 * each ring. 1353 */ 1354 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1355 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1356 1357 /* 1358 * Disable all unused send rings by setting the 'ring disabled' 1359 * bit in the flags field of all the TX send ring control blocks. 1360 * These are located in NIC memory. 1361 */ 1362 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1363 BGE_SEND_RING_RCB); 1364 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1365 vrcb->bge_maxlen_flags = 1366 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1367 vrcb->bge_nicaddr = 0; 1368 vrcb++; 1369 } 1370 1371 /* Configure TX RCB 0 (we use only the first ring) */ 1372 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1373 BGE_SEND_RING_RCB); 1374 vrcb->bge_hostaddr.bge_addr_hi = 0; 1375 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring)); 1376 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1377 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1378 vrcb->bge_maxlen_flags = 1379 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1380 1381 /* Disable all unused RX return rings */ 1382 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1383 BGE_RX_RETURN_RING_RCB); 1384 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1385 vrcb->bge_hostaddr.bge_addr_hi = 0; 1386 vrcb->bge_hostaddr.bge_addr_lo = 0; 1387 vrcb->bge_maxlen_flags = 1388 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1389 BGE_RCB_FLAG_RING_DISABLED); 1390 vrcb->bge_nicaddr = 0; 1391 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1392 (i * (sizeof(u_int64_t))), 0); 1393 vrcb++; 1394 } 1395 1396 /* Initialize RX ring indexes */ 1397 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1398 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1399 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1400 1401 /* 1402 * Set up RX return ring 0 1403 * Note that the NIC address for RX return rings is 0x00000000. 1404 * The return rings live entirely within the host, so the 1405 * nicaddr field in the RCB isn't used. 1406 */ 1407 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1408 BGE_RX_RETURN_RING_RCB); 1409 vrcb->bge_hostaddr.bge_addr_hi = 0; 1410 BGE_HOSTADDR(vrcb->bge_hostaddr, 1411 vtophys(&sc->bge_rdata->bge_rx_return_ring)); 1412 vrcb->bge_nicaddr = 0x00000000; 1413 vrcb->bge_maxlen_flags = 1414 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0); 1415 1416 /* Set random backoff seed for TX */ 1417 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1418 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1419 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1420 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1421 BGE_TX_BACKOFF_SEED_MASK); 1422 1423 /* Set inter-packet gap */ 1424 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1425 1426 /* 1427 * Specify which ring to use for packets that don't match 1428 * any RX rules. 1429 */ 1430 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1431 1432 /* 1433 * Configure number of RX lists. One interrupt distribution 1434 * list, sixteen active lists, one bad frames class. 1435 */ 1436 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1437 1438 /* Inialize RX list placement stats mask. */ 1439 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1440 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1441 1442 /* Disable host coalescing until we get it set up */ 1443 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1444 1445 /* Poll to make sure it's shut down. */ 1446 for (i = 0; i < BGE_TIMEOUT; i++) { 1447 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1448 break; 1449 DELAY(10); 1450 } 1451 1452 if (i == BGE_TIMEOUT) { 1453 printf("bge%d: host coalescing engine failed to idle\n", 1454 sc->bge_unit); 1455 return(ENXIO); 1456 } 1457 1458 /* Set up host coalescing defaults */ 1459 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1460 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1461 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1462 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1463 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1464 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1465 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1466 } 1467 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1468 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1469 1470 /* Set up address of statistics block */ 1471 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1472 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1473 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1474 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1475 1476 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1477 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1478 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1479 } 1480 1481 /* Set up address of status block */ 1482 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1483 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1484 vtophys(&sc->bge_rdata->bge_status_block)); 1485 1486 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1487 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1488 1489 /* Turn on host coalescing state machine */ 1490 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1491 1492 /* Turn on RX BD completion state machine and enable attentions */ 1493 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1494 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1495 1496 /* Turn on RX list placement state machine */ 1497 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1498 1499 /* Turn on RX list selector state machine. */ 1500 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1501 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1502 1503 /* Turn on DMA, clear stats */ 1504 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1505 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1506 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1507 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1508 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1509 1510 /* Set misc. local control, enable interrupts on attentions */ 1511 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1512 1513 #ifdef notdef 1514 /* Assert GPIO pins for PHY reset */ 1515 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1516 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1517 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1518 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1519 #endif 1520 1521 /* Turn on DMA completion state machine */ 1522 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1523 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1524 1525 /* Turn on write DMA state machine */ 1526 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1527 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1528 1529 /* Turn on read DMA state machine */ 1530 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1531 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1532 1533 /* Turn on RX data completion state machine */ 1534 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1535 1536 /* Turn on RX BD initiator state machine */ 1537 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1538 1539 /* Turn on RX data and RX BD initiator state machine */ 1540 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1541 1542 /* Turn on Mbuf cluster free state machine */ 1543 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1544 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1545 1546 /* Turn on send BD completion state machine */ 1547 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1548 1549 /* Turn on send data completion state machine */ 1550 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1551 1552 /* Turn on send data initiator state machine */ 1553 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1554 1555 /* Turn on send BD initiator state machine */ 1556 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1557 1558 /* Turn on send BD selector state machine */ 1559 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1560 1561 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1562 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1563 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1564 1565 /* ack/clear link change events */ 1566 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1567 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1568 BGE_MACSTAT_LINK_CHANGED); 1569 1570 /* Enable PHY auto polling (for MII/GMII only) */ 1571 if (sc->bge_tbi) { 1572 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1573 } else { 1574 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1575 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1576 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1577 BGE_EVTENB_MI_INTERRUPT); 1578 } 1579 1580 /* Enable link state change attentions. */ 1581 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1582 1583 return(0); 1584 } 1585 1586 /* 1587 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1588 * against our list and return its name if we find a match. Note 1589 * that since the Broadcom controller contains VPD support, we 1590 * can get the device name string from the controller itself instead 1591 * of the compiled-in string. This is a little slow, but it guarantees 1592 * we'll always announce the right product name. 1593 */ 1594 static int 1595 bge_probe(dev) 1596 device_t dev; 1597 { 1598 struct bge_type *t; 1599 struct bge_softc *sc; 1600 char *descbuf; 1601 1602 t = bge_devs; 1603 1604 sc = device_get_softc(dev); 1605 bzero(sc, sizeof(struct bge_softc)); 1606 sc->bge_unit = device_get_unit(dev); 1607 sc->bge_dev = dev; 1608 1609 while(t->bge_name != NULL) { 1610 if ((pci_get_vendor(dev) == t->bge_vid) && 1611 (pci_get_device(dev) == t->bge_did)) { 1612 #ifdef notdef 1613 bge_vpd_read(sc); 1614 device_set_desc(dev, sc->bge_vpd_prodname); 1615 #endif 1616 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_INTWAIT); 1617 snprintf(descbuf, BGE_DEVDESC_MAX, 1618 "%s, ASIC rev. %#04x", t->bge_name, 1619 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1620 device_set_desc_copy(dev, descbuf); 1621 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) 1622 sc->bge_no_3_led = 1; 1623 free(descbuf, M_TEMP); 1624 return(0); 1625 } 1626 t++; 1627 } 1628 1629 return(ENXIO); 1630 } 1631 1632 static int 1633 bge_attach(dev) 1634 device_t dev; 1635 { 1636 int s; 1637 u_int32_t command; 1638 struct ifnet *ifp; 1639 struct bge_softc *sc; 1640 u_int32_t hwcfg = 0; 1641 u_int32_t mac_addr = 0; 1642 int unit, error = 0, rid; 1643 uint8_t ether_addr[ETHER_ADDR_LEN]; 1644 1645 s = splimp(); 1646 1647 sc = device_get_softc(dev); 1648 unit = device_get_unit(dev); 1649 sc->bge_dev = dev; 1650 sc->bge_unit = unit; 1651 callout_init(&sc->bge_stat_timer); 1652 1653 /* 1654 * Map control/status registers. 1655 */ 1656 command = pci_read_config(dev, PCIR_COMMAND, 4); 1657 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1658 pci_write_config(dev, PCIR_COMMAND, command, 4); 1659 command = pci_read_config(dev, PCIR_COMMAND, 4); 1660 1661 if (!(command & PCIM_CMD_MEMEN)) { 1662 printf("bge%d: failed to enable memory mapping!\n", unit); 1663 error = ENXIO; 1664 goto fail; 1665 } 1666 1667 rid = BGE_PCI_BAR0; 1668 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1669 0, ~0, 1, RF_ACTIVE); 1670 1671 if (sc->bge_res == NULL) { 1672 printf ("bge%d: couldn't map memory\n", unit); 1673 error = ENXIO; 1674 goto fail; 1675 } 1676 1677 sc->bge_btag = rman_get_bustag(sc->bge_res); 1678 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1679 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1680 1681 /* Allocate interrupt */ 1682 rid = 0; 1683 1684 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1685 RF_SHAREABLE | RF_ACTIVE); 1686 1687 if (sc->bge_irq == NULL) { 1688 printf("bge%d: couldn't map interrupt\n", unit); 1689 error = ENXIO; 1690 goto fail; 1691 } 1692 1693 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1694 bge_intr, sc, &sc->bge_intrhand); 1695 1696 if (error) { 1697 bge_release_resources(sc); 1698 printf("bge%d: couldn't set up irq\n", unit); 1699 goto fail; 1700 } 1701 1702 sc->bge_unit = unit; 1703 1704 /* Try to reset the chip. */ 1705 bge_reset(sc); 1706 1707 if (bge_chipinit(sc)) { 1708 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1709 bge_release_resources(sc); 1710 error = ENXIO; 1711 goto fail; 1712 } 1713 1714 /* 1715 * Get station address from the EEPROM. 1716 */ 1717 mac_addr = bge_readmem_ind(sc, 0x0c14); 1718 if ((mac_addr >> 16) == 0x484b) { 1719 ether_addr[0] = (uint8_t)(mac_addr >> 8); 1720 ether_addr[1] = (uint8_t)mac_addr; 1721 mac_addr = bge_readmem_ind(sc, 0x0c18); 1722 ether_addr[2] = (uint8_t)(mac_addr >> 24); 1723 ether_addr[3] = (uint8_t)(mac_addr >> 16); 1724 ether_addr[4] = (uint8_t)(mac_addr >> 8); 1725 ether_addr[5] = (uint8_t)mac_addr; 1726 } else if (bge_read_eeprom(sc, ether_addr, 1727 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1728 printf("bge%d: failed to read station address\n", unit); 1729 bge_release_resources(sc); 1730 error = ENXIO; 1731 goto fail; 1732 } 1733 1734 /* Allocate the general information block and ring buffers. */ 1735 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1736 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1737 1738 if (sc->bge_rdata == NULL) { 1739 bge_release_resources(sc); 1740 error = ENXIO; 1741 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1742 goto fail; 1743 } 1744 1745 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1746 1747 /* Save ASIC rev. */ 1748 1749 sc->bge_chipid = 1750 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1751 BGE_PCIMISCCTL_ASICREV; 1752 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 1753 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 1754 1755 /* 1756 * Try to allocate memory for jumbo buffers. 1757 * The 5705 does not appear to support jumbo frames. 1758 */ 1759 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1760 if (bge_alloc_jumbo_mem(sc)) { 1761 printf("bge%d: jumbo buffer allocation " 1762 "failed\n", sc->bge_unit); 1763 bge_release_resources(sc); 1764 error = ENXIO; 1765 goto fail; 1766 } 1767 } 1768 1769 /* Set default tuneable values. */ 1770 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1771 sc->bge_rx_coal_ticks = 150; 1772 sc->bge_tx_coal_ticks = 150; 1773 sc->bge_rx_max_coal_bds = 64; 1774 sc->bge_tx_max_coal_bds = 128; 1775 1776 /* 5705 limits RX return ring to 512 entries. */ 1777 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1778 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1779 else 1780 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1781 1782 /* Set up ifnet structure */ 1783 ifp = &sc->arpcom.ac_if; 1784 ifp->if_softc = sc; 1785 if_initname(ifp, "bge", sc->bge_unit); 1786 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1787 ifp->if_ioctl = bge_ioctl; 1788 ifp->if_start = bge_start; 1789 ifp->if_watchdog = bge_watchdog; 1790 ifp->if_init = bge_init; 1791 ifp->if_mtu = ETHERMTU; 1792 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1); 1793 ifq_set_ready(&ifp->if_snd); 1794 ifp->if_hwassist = BGE_CSUM_FEATURES; 1795 ifp->if_capabilities = IFCAP_HWCSUM; 1796 ifp->if_capenable = ifp->if_capabilities; 1797 1798 /* 1799 * Figure out what sort of media we have by checking the 1800 * hardware config word in the first 32k of NIC internal memory, 1801 * or fall back to examining the EEPROM if necessary. 1802 * Note: on some BCM5700 cards, this value appears to be unset. 1803 * If that's the case, we have to rely on identifying the NIC 1804 * by its PCI subsystem ID, as we do below for the SysKonnect 1805 * SK-9D41. 1806 */ 1807 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 1808 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 1809 else { 1810 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1811 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1812 hwcfg = ntohl(hwcfg); 1813 } 1814 1815 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1816 sc->bge_tbi = 1; 1817 1818 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1819 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 1820 PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41) 1821 sc->bge_tbi = 1; 1822 1823 if (sc->bge_tbi) { 1824 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1825 bge_ifmedia_upd, bge_ifmedia_sts); 1826 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1827 ifmedia_add(&sc->bge_ifmedia, 1828 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1829 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1830 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1831 } else { 1832 /* 1833 * Do transceiver setup. 1834 */ 1835 if (mii_phy_probe(dev, &sc->bge_miibus, 1836 bge_ifmedia_upd, bge_ifmedia_sts)) { 1837 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1838 bge_release_resources(sc); 1839 bge_free_jumbo_mem(sc); 1840 error = ENXIO; 1841 goto fail; 1842 } 1843 } 1844 1845 /* 1846 * When using the BCM5701 in PCI-X mode, data corruption has 1847 * been observed in the first few bytes of some received packets. 1848 * Aligning the packet buffer in memory eliminates the corruption. 1849 * Unfortunately, this misaligns the packet payloads. On platforms 1850 * which do not support unaligned accesses, we will realign the 1851 * payloads by copying the received packets. 1852 */ 1853 switch (sc->bge_chipid) { 1854 case BGE_CHIPID_BCM5701_A0: 1855 case BGE_CHIPID_BCM5701_B0: 1856 case BGE_CHIPID_BCM5701_B2: 1857 case BGE_CHIPID_BCM5701_B5: 1858 /* If in PCI-X mode, work around the alignment bug. */ 1859 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1860 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1861 BGE_PCISTATE_PCI_BUSSPEED) 1862 sc->bge_rx_alignment_bug = 1; 1863 break; 1864 } 1865 1866 /* 1867 * Call MI attach routine. 1868 */ 1869 ether_ifattach(ifp, ether_addr); 1870 1871 fail: 1872 splx(s); 1873 1874 return(error); 1875 } 1876 1877 static int 1878 bge_detach(dev) 1879 device_t dev; 1880 { 1881 struct bge_softc *sc; 1882 struct ifnet *ifp; 1883 int s; 1884 1885 s = splimp(); 1886 1887 sc = device_get_softc(dev); 1888 ifp = &sc->arpcom.ac_if; 1889 1890 ether_ifdetach(ifp); 1891 bge_stop(sc); 1892 bge_reset(sc); 1893 1894 if (sc->bge_tbi) { 1895 ifmedia_removeall(&sc->bge_ifmedia); 1896 } else { 1897 bus_generic_detach(dev); 1898 device_delete_child(dev, sc->bge_miibus); 1899 } 1900 1901 bge_release_resources(sc); 1902 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1903 bge_free_jumbo_mem(sc); 1904 1905 splx(s); 1906 1907 return(0); 1908 } 1909 1910 static void 1911 bge_release_resources(sc) 1912 struct bge_softc *sc; 1913 { 1914 device_t dev; 1915 1916 dev = sc->bge_dev; 1917 1918 if (sc->bge_vpd_prodname != NULL) 1919 free(sc->bge_vpd_prodname, M_DEVBUF); 1920 1921 if (sc->bge_vpd_readonly != NULL) 1922 free(sc->bge_vpd_readonly, M_DEVBUF); 1923 1924 if (sc->bge_intrhand != NULL) 1925 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1926 1927 if (sc->bge_irq != NULL) 1928 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1929 1930 if (sc->bge_res != NULL) 1931 bus_release_resource(dev, SYS_RES_MEMORY, 1932 BGE_PCI_BAR0, sc->bge_res); 1933 1934 if (sc->bge_rdata != NULL) 1935 contigfree(sc->bge_rdata, 1936 sizeof(struct bge_ring_data), M_DEVBUF); 1937 1938 return; 1939 } 1940 1941 static void 1942 bge_reset(sc) 1943 struct bge_softc *sc; 1944 { 1945 device_t dev; 1946 u_int32_t cachesize, command, pcistate; 1947 int i, val = 0; 1948 1949 dev = sc->bge_dev; 1950 1951 /* Save some important PCI state. */ 1952 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1953 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1954 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1955 1956 pci_write_config(dev, BGE_PCI_MISC_CTL, 1957 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1958 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1959 1960 /* Issue global reset */ 1961 bge_writereg_ind(sc, BGE_MISC_CFG, 1962 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1963 1964 DELAY(1000); 1965 1966 /* Reset some of the PCI state that got zapped by reset */ 1967 pci_write_config(dev, BGE_PCI_MISC_CTL, 1968 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1969 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1970 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1971 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1972 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1973 1974 /* 1975 * Prevent PXE restart: write a magic number to the 1976 * general communications memory at 0xB50. 1977 */ 1978 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1979 /* 1980 * Poll the value location we just wrote until 1981 * we see the 1's complement of the magic number. 1982 * This indicates that the firmware initialization 1983 * is complete. 1984 */ 1985 for (i = 0; i < BGE_TIMEOUT; i++) { 1986 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1987 if (val == ~BGE_MAGIC_NUMBER) 1988 break; 1989 DELAY(10); 1990 } 1991 1992 if (i == BGE_TIMEOUT) { 1993 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1994 return; 1995 } 1996 1997 /* 1998 * XXX Wait for the value of the PCISTATE register to 1999 * return to its original pre-reset state. This is a 2000 * fairly good indicator of reset completion. If we don't 2001 * wait for the reset to fully complete, trying to read 2002 * from the device's non-PCI registers may yield garbage 2003 * results. 2004 */ 2005 for (i = 0; i < BGE_TIMEOUT; i++) { 2006 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2007 break; 2008 DELAY(10); 2009 } 2010 2011 /* Enable memory arbiter. */ 2012 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2013 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2014 2015 /* Fix up byte swapping */ 2016 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 2017 BGE_MODECTL_BYTESWAP_DATA); 2018 2019 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2020 2021 DELAY(10000); 2022 2023 return; 2024 } 2025 2026 /* 2027 * Frame reception handling. This is called if there's a frame 2028 * on the receive return list. 2029 * 2030 * Note: we have to be able to handle two possibilities here: 2031 * 1) the frame is from the jumbo recieve ring 2032 * 2) the frame is from the standard receive ring 2033 */ 2034 2035 static void 2036 bge_rxeof(sc) 2037 struct bge_softc *sc; 2038 { 2039 struct ifnet *ifp; 2040 int stdcnt = 0, jumbocnt = 0; 2041 2042 ifp = &sc->arpcom.ac_if; 2043 2044 while(sc->bge_rx_saved_considx != 2045 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2046 struct bge_rx_bd *cur_rx; 2047 u_int32_t rxidx; 2048 struct mbuf *m = NULL; 2049 u_int16_t vlan_tag = 0; 2050 int have_tag = 0; 2051 2052 cur_rx = 2053 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 2054 2055 rxidx = cur_rx->bge_idx; 2056 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2057 2058 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2059 have_tag = 1; 2060 vlan_tag = cur_rx->bge_vlan_tag; 2061 } 2062 2063 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2064 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2065 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2066 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2067 jumbocnt++; 2068 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2069 ifp->if_ierrors++; 2070 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2071 continue; 2072 } 2073 if (bge_newbuf_jumbo(sc, 2074 sc->bge_jumbo, NULL) == ENOBUFS) { 2075 ifp->if_ierrors++; 2076 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2077 continue; 2078 } 2079 } else { 2080 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2081 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2082 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2083 stdcnt++; 2084 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2085 ifp->if_ierrors++; 2086 bge_newbuf_std(sc, sc->bge_std, m); 2087 continue; 2088 } 2089 if (bge_newbuf_std(sc, sc->bge_std, 2090 NULL) == ENOBUFS) { 2091 ifp->if_ierrors++; 2092 bge_newbuf_std(sc, sc->bge_std, m); 2093 continue; 2094 } 2095 } 2096 2097 ifp->if_ipackets++; 2098 #ifndef __i386__ 2099 /* 2100 * The i386 allows unaligned accesses, but for other 2101 * platforms we must make sure the payload is aligned. 2102 */ 2103 if (sc->bge_rx_alignment_bug) { 2104 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2105 cur_rx->bge_len); 2106 m->m_data += ETHER_ALIGN; 2107 } 2108 #endif 2109 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2110 m->m_pkthdr.rcvif = ifp; 2111 2112 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2113 if (ifp->if_hwassist) { 2114 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2115 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2116 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2117 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2118 m->m_pkthdr.csum_data = 2119 cur_rx->bge_tcp_udp_csum; 2120 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2121 } 2122 } 2123 #endif 2124 2125 /* 2126 * If we received a packet with a vlan tag, pass it 2127 * to vlan_input() instead of ether_input(). 2128 */ 2129 if (have_tag) { 2130 VLAN_INPUT_TAG(m, vlan_tag); 2131 have_tag = vlan_tag = 0; 2132 continue; 2133 } 2134 2135 (*ifp->if_input)(ifp, m); 2136 } 2137 2138 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2139 if (stdcnt) 2140 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2141 if (jumbocnt) 2142 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2143 2144 return; 2145 } 2146 2147 static void 2148 bge_txeof(sc) 2149 struct bge_softc *sc; 2150 { 2151 struct bge_tx_bd *cur_tx = NULL; 2152 struct ifnet *ifp; 2153 2154 ifp = &sc->arpcom.ac_if; 2155 2156 /* 2157 * Go through our tx ring and free mbufs for those 2158 * frames that have been sent. 2159 */ 2160 while (sc->bge_tx_saved_considx != 2161 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2162 u_int32_t idx = 0; 2163 2164 idx = sc->bge_tx_saved_considx; 2165 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2166 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2167 ifp->if_opackets++; 2168 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2169 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2170 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2171 } 2172 sc->bge_txcnt--; 2173 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2174 ifp->if_timer = 0; 2175 } 2176 2177 if (cur_tx != NULL) 2178 ifp->if_flags &= ~IFF_OACTIVE; 2179 2180 return; 2181 } 2182 2183 static void 2184 bge_intr(xsc) 2185 void *xsc; 2186 { 2187 struct bge_softc *sc; 2188 struct ifnet *ifp; 2189 u_int32_t status; 2190 2191 sc = xsc; 2192 ifp = &sc->arpcom.ac_if; 2193 2194 #ifdef notdef 2195 /* Avoid this for now -- checking this register is expensive. */ 2196 /* Make sure this is really our interrupt. */ 2197 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2198 return; 2199 #endif 2200 /* Ack interrupt and stop others from occuring. */ 2201 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2202 2203 /* 2204 * Process link state changes. 2205 * Grrr. The link status word in the status block does 2206 * not work correctly on the BCM5700 rev AX and BX chips, 2207 * according to all available information. Hence, we have 2208 * to enable MII interrupts in order to properly obtain 2209 * async link changes. Unfortunately, this also means that 2210 * we have to read the MAC status register to detect link 2211 * changes, thereby adding an additional register access to 2212 * the interrupt handler. 2213 */ 2214 2215 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2216 status = CSR_READ_4(sc, BGE_MAC_STS); 2217 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2218 sc->bge_link = 0; 2219 callout_stop(&sc->bge_stat_timer); 2220 bge_tick(sc); 2221 /* Clear the interrupt */ 2222 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2223 BGE_EVTENB_MI_INTERRUPT); 2224 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2225 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2226 BRGPHY_INTRS); 2227 } 2228 } else { 2229 if ((sc->bge_rdata->bge_status_block.bge_status & 2230 BGE_STATFLAG_UPDATED) && 2231 (sc->bge_rdata->bge_status_block.bge_status & 2232 BGE_STATFLAG_LINKSTATE_CHANGED)) { 2233 sc->bge_rdata->bge_status_block.bge_status &= 2234 ~(BGE_STATFLAG_UPDATED| 2235 BGE_STATFLAG_LINKSTATE_CHANGED); 2236 /* 2237 * Sometimes PCS encoding errors are detected in 2238 * TBI mode (on fiber NICs), and for some reason 2239 * the chip will signal them as link changes. 2240 * If we get a link change event, but the 'PCS 2241 * encoding error' bit in the MAC status register 2242 * is set, don't bother doing a link check. 2243 * This avoids spurious "gigabit link up" messages 2244 * that sometimes appear on fiber NICs during 2245 * periods of heavy traffic. (There should be no 2246 * effect on copper NICs.) 2247 */ 2248 status = CSR_READ_4(sc, BGE_MAC_STS); 2249 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR| 2250 BGE_MACSTAT_MI_COMPLETE))) { 2251 sc->bge_link = 0; 2252 callout_stop(&sc->bge_stat_timer); 2253 bge_tick(sc); 2254 } 2255 sc->bge_link = 0; 2256 callout_stop(&sc->bge_stat_timer); 2257 bge_tick(sc); 2258 /* Clear the interrupt */ 2259 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2260 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2261 BGE_MACSTAT_LINK_CHANGED); 2262 2263 /* Force flush the status block cached by PCI bridge */ 2264 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2265 } 2266 } 2267 2268 if (ifp->if_flags & IFF_RUNNING) { 2269 /* Check RX return ring producer/consumer */ 2270 bge_rxeof(sc); 2271 2272 /* Check TX ring producer/consumer */ 2273 bge_txeof(sc); 2274 } 2275 2276 bge_handle_events(sc); 2277 2278 /* Re-enable interrupts. */ 2279 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2280 2281 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 2282 bge_start(ifp); 2283 2284 return; 2285 } 2286 2287 static void 2288 bge_tick(xsc) 2289 void *xsc; 2290 { 2291 struct bge_softc *sc; 2292 struct mii_data *mii = NULL; 2293 struct ifmedia *ifm = NULL; 2294 struct ifnet *ifp; 2295 int s; 2296 2297 sc = xsc; 2298 ifp = &sc->arpcom.ac_if; 2299 2300 s = splimp(); 2301 2302 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2303 bge_stats_update_regs(sc); 2304 else 2305 bge_stats_update(sc); 2306 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 2307 if (sc->bge_link) { 2308 splx(s); 2309 return; 2310 } 2311 2312 if (sc->bge_tbi) { 2313 ifm = &sc->bge_ifmedia; 2314 if (CSR_READ_4(sc, BGE_MAC_STS) & 2315 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2316 sc->bge_link++; 2317 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2318 printf("bge%d: gigabit link up\n", sc->bge_unit); 2319 if (!ifq_is_empty(&ifp->if_snd)) 2320 bge_start(ifp); 2321 } 2322 splx(s); 2323 return; 2324 } 2325 2326 mii = device_get_softc(sc->bge_miibus); 2327 mii_tick(mii); 2328 2329 if (!sc->bge_link) { 2330 mii_pollstat(mii); 2331 if (mii->mii_media_status & IFM_ACTIVE && 2332 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2333 sc->bge_link++; 2334 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2335 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2336 printf("bge%d: gigabit link up\n", 2337 sc->bge_unit); 2338 if (!ifq_is_empty(&ifp->if_snd)) 2339 bge_start(ifp); 2340 } 2341 } 2342 2343 splx(s); 2344 2345 return; 2346 } 2347 2348 static void 2349 bge_stats_update_regs(sc) 2350 struct bge_softc *sc; 2351 { 2352 struct ifnet *ifp; 2353 struct bge_mac_stats_regs stats; 2354 u_int32_t *s; 2355 int i; 2356 2357 ifp = &sc->arpcom.ac_if; 2358 2359 s = (u_int32_t *)&stats; 2360 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 2361 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 2362 s++; 2363 } 2364 2365 ifp->if_collisions += 2366 (stats.dot3StatsSingleCollisionFrames + 2367 stats.dot3StatsMultipleCollisionFrames + 2368 stats.dot3StatsExcessiveCollisions + 2369 stats.dot3StatsLateCollisions) - 2370 ifp->if_collisions; 2371 2372 return; 2373 } 2374 2375 static void 2376 bge_stats_update(sc) 2377 struct bge_softc *sc; 2378 { 2379 struct ifnet *ifp; 2380 struct bge_stats *stats; 2381 2382 ifp = &sc->arpcom.ac_if; 2383 2384 stats = (struct bge_stats *)(sc->bge_vhandle + 2385 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2386 2387 ifp->if_collisions += 2388 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo + 2389 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo + 2390 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo + 2391 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) - 2392 ifp->if_collisions; 2393 2394 #ifdef notdef 2395 ifp->if_collisions += 2396 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2397 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2398 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2399 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2400 ifp->if_collisions; 2401 #endif 2402 2403 return; 2404 } 2405 2406 /* 2407 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2408 * pointers to descriptors. 2409 */ 2410 static int 2411 bge_encap(sc, m_head, txidx) 2412 struct bge_softc *sc; 2413 struct mbuf *m_head; 2414 u_int32_t *txidx; 2415 { 2416 struct bge_tx_bd *f = NULL; 2417 struct mbuf *m; 2418 u_int32_t frag, cur, cnt = 0; 2419 u_int16_t csum_flags = 0; 2420 struct ifvlan *ifv = NULL; 2421 2422 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2423 m_head->m_pkthdr.rcvif != NULL && 2424 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 2425 ifv = m_head->m_pkthdr.rcvif->if_softc; 2426 2427 m = m_head; 2428 cur = frag = *txidx; 2429 2430 if (m_head->m_pkthdr.csum_flags) { 2431 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2432 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2433 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2434 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2435 if (m_head->m_flags & M_LASTFRAG) 2436 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2437 else if (m_head->m_flags & M_FRAG) 2438 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2439 } 2440 /* 2441 * Start packing the mbufs in this chain into 2442 * the fragment pointers. Stop when we run out 2443 * of fragments or hit the end of the mbuf chain. 2444 */ 2445 for (m = m_head; m != NULL; m = m->m_next) { 2446 if (m->m_len != 0) { 2447 f = &sc->bge_rdata->bge_tx_ring[frag]; 2448 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2449 break; 2450 BGE_HOSTADDR(f->bge_addr, 2451 vtophys(mtod(m, vm_offset_t))); 2452 f->bge_len = m->m_len; 2453 f->bge_flags = csum_flags; 2454 if (ifv != NULL) { 2455 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2456 f->bge_vlan_tag = ifv->ifv_tag; 2457 } else { 2458 f->bge_vlan_tag = 0; 2459 } 2460 /* 2461 * Sanity check: avoid coming within 16 descriptors 2462 * of the end of the ring. 2463 */ 2464 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2465 return(ENOBUFS); 2466 cur = frag; 2467 BGE_INC(frag, BGE_TX_RING_CNT); 2468 cnt++; 2469 } 2470 } 2471 2472 if (m != NULL) 2473 return(ENOBUFS); 2474 2475 if (frag == sc->bge_tx_saved_considx) 2476 return(ENOBUFS); 2477 2478 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2479 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2480 sc->bge_txcnt += cnt; 2481 2482 *txidx = frag; 2483 2484 return(0); 2485 } 2486 2487 /* 2488 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2489 * to the mbuf data regions directly in the transmit descriptors. 2490 */ 2491 static void 2492 bge_start(ifp) 2493 struct ifnet *ifp; 2494 { 2495 struct bge_softc *sc; 2496 struct mbuf *m_head = NULL; 2497 u_int32_t prodidx = 0; 2498 2499 sc = ifp->if_softc; 2500 2501 if (!sc->bge_link) 2502 return; 2503 2504 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2505 2506 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2507 m_head = ifq_poll(&ifp->if_snd); 2508 if (m_head == NULL) 2509 break; 2510 2511 /* 2512 * XXX 2513 * safety overkill. If this is a fragmented packet chain 2514 * with delayed TCP/UDP checksums, then only encapsulate 2515 * it if we have enough descriptors to handle the entire 2516 * chain at once. 2517 * (paranoia -- may not actually be needed) 2518 */ 2519 if (m_head->m_flags & M_FIRSTFRAG && 2520 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2521 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2522 m_head->m_pkthdr.csum_data + 16) { 2523 ifp->if_flags |= IFF_OACTIVE; 2524 break; 2525 } 2526 } 2527 2528 /* 2529 * Pack the data into the transmit ring. If we 2530 * don't have room, set the OACTIVE flag and wait 2531 * for the NIC to drain the ring. 2532 */ 2533 if (bge_encap(sc, m_head, &prodidx)) { 2534 ifp->if_flags |= IFF_OACTIVE; 2535 break; 2536 } 2537 m_head = ifq_dequeue(&ifp->if_snd); 2538 2539 BPF_MTAP(ifp, m_head); 2540 } 2541 2542 /* Transmit */ 2543 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2544 /* 5700 b2 errata */ 2545 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 2546 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2547 2548 /* 2549 * Set a timeout in case the chip goes out to lunch. 2550 */ 2551 ifp->if_timer = 5; 2552 2553 return; 2554 } 2555 2556 static void 2557 bge_init(xsc) 2558 void *xsc; 2559 { 2560 struct bge_softc *sc = xsc; 2561 struct ifnet *ifp; 2562 u_int16_t *m; 2563 int s; 2564 2565 s = splimp(); 2566 2567 ifp = &sc->arpcom.ac_if; 2568 2569 if (ifp->if_flags & IFF_RUNNING) { 2570 splx(s); 2571 return; 2572 } 2573 2574 /* Cancel pending I/O and flush buffers. */ 2575 bge_stop(sc); 2576 bge_reset(sc); 2577 bge_chipinit(sc); 2578 2579 /* 2580 * Init the various state machines, ring 2581 * control blocks and firmware. 2582 */ 2583 if (bge_blockinit(sc)) { 2584 printf("bge%d: initialization failure\n", sc->bge_unit); 2585 splx(s); 2586 return; 2587 } 2588 2589 ifp = &sc->arpcom.ac_if; 2590 2591 /* Specify MTU. */ 2592 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2593 ETHER_HDR_LEN + ETHER_CRC_LEN); 2594 2595 /* Load our MAC address. */ 2596 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2597 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2598 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2599 2600 /* Enable or disable promiscuous mode as needed. */ 2601 if (ifp->if_flags & IFF_PROMISC) { 2602 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2603 } else { 2604 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2605 } 2606 2607 /* Program multicast filter. */ 2608 bge_setmulti(sc); 2609 2610 /* Init RX ring. */ 2611 bge_init_rx_ring_std(sc); 2612 2613 /* 2614 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 2615 * memory to insure that the chip has in fact read the first 2616 * entry of the ring. 2617 */ 2618 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 2619 u_int32_t v, i; 2620 for (i = 0; i < 10; i++) { 2621 DELAY(20); 2622 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 2623 if (v == (MCLBYTES - ETHER_ALIGN)) 2624 break; 2625 } 2626 if (i == 10) 2627 printf ("bge%d: 5705 A0 chip failed to load RX ring\n", 2628 sc->bge_unit); 2629 } 2630 2631 /* Init jumbo RX ring. */ 2632 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2633 bge_init_rx_ring_jumbo(sc); 2634 2635 /* Init our RX return ring index */ 2636 sc->bge_rx_saved_considx = 0; 2637 2638 /* Init TX ring. */ 2639 bge_init_tx_ring(sc); 2640 2641 /* Turn on transmitter */ 2642 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2643 2644 /* Turn on receiver */ 2645 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2646 2647 /* Tell firmware we're alive. */ 2648 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2649 2650 /* Enable host interrupts. */ 2651 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2652 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2653 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2654 2655 bge_ifmedia_upd(ifp); 2656 2657 ifp->if_flags |= IFF_RUNNING; 2658 ifp->if_flags &= ~IFF_OACTIVE; 2659 2660 splx(s); 2661 2662 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc); 2663 } 2664 2665 /* 2666 * Set media options. 2667 */ 2668 static int 2669 bge_ifmedia_upd(ifp) 2670 struct ifnet *ifp; 2671 { 2672 struct bge_softc *sc; 2673 struct mii_data *mii; 2674 struct ifmedia *ifm; 2675 2676 sc = ifp->if_softc; 2677 ifm = &sc->bge_ifmedia; 2678 2679 /* If this is a 1000baseX NIC, enable the TBI port. */ 2680 if (sc->bge_tbi) { 2681 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2682 return(EINVAL); 2683 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2684 case IFM_AUTO: 2685 break; 2686 case IFM_1000_SX: 2687 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2688 BGE_CLRBIT(sc, BGE_MAC_MODE, 2689 BGE_MACMODE_HALF_DUPLEX); 2690 } else { 2691 BGE_SETBIT(sc, BGE_MAC_MODE, 2692 BGE_MACMODE_HALF_DUPLEX); 2693 } 2694 break; 2695 default: 2696 return(EINVAL); 2697 } 2698 return(0); 2699 } 2700 2701 mii = device_get_softc(sc->bge_miibus); 2702 sc->bge_link = 0; 2703 if (mii->mii_instance) { 2704 struct mii_softc *miisc; 2705 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2706 miisc = LIST_NEXT(miisc, mii_list)) 2707 mii_phy_reset(miisc); 2708 } 2709 mii_mediachg(mii); 2710 2711 return(0); 2712 } 2713 2714 /* 2715 * Report current media status. 2716 */ 2717 static void 2718 bge_ifmedia_sts(ifp, ifmr) 2719 struct ifnet *ifp; 2720 struct ifmediareq *ifmr; 2721 { 2722 struct bge_softc *sc; 2723 struct mii_data *mii; 2724 2725 sc = ifp->if_softc; 2726 2727 if (sc->bge_tbi) { 2728 ifmr->ifm_status = IFM_AVALID; 2729 ifmr->ifm_active = IFM_ETHER; 2730 if (CSR_READ_4(sc, BGE_MAC_STS) & 2731 BGE_MACSTAT_TBI_PCS_SYNCHED) 2732 ifmr->ifm_status |= IFM_ACTIVE; 2733 ifmr->ifm_active |= IFM_1000_SX; 2734 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2735 ifmr->ifm_active |= IFM_HDX; 2736 else 2737 ifmr->ifm_active |= IFM_FDX; 2738 return; 2739 } 2740 2741 mii = device_get_softc(sc->bge_miibus); 2742 mii_pollstat(mii); 2743 ifmr->ifm_active = mii->mii_media_active; 2744 ifmr->ifm_status = mii->mii_media_status; 2745 2746 return; 2747 } 2748 2749 static int 2750 bge_ioctl(ifp, command, data, cr) 2751 struct ifnet *ifp; 2752 u_long command; 2753 caddr_t data; 2754 struct ucred *cr; 2755 { 2756 struct bge_softc *sc = ifp->if_softc; 2757 struct ifreq *ifr = (struct ifreq *) data; 2758 int s, mask, error = 0; 2759 struct mii_data *mii; 2760 2761 s = splimp(); 2762 2763 switch(command) { 2764 case SIOCSIFADDR: 2765 case SIOCGIFADDR: 2766 error = ether_ioctl(ifp, command, data); 2767 break; 2768 case SIOCSIFMTU: 2769 /* Disallow jumbo frames on 5705. */ 2770 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2771 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU) 2772 error = EINVAL; 2773 else { 2774 ifp->if_mtu = ifr->ifr_mtu; 2775 ifp->if_flags &= ~IFF_RUNNING; 2776 bge_init(sc); 2777 } 2778 break; 2779 case SIOCSIFFLAGS: 2780 if (ifp->if_flags & IFF_UP) { 2781 /* 2782 * If only the state of the PROMISC flag changed, 2783 * then just use the 'set promisc mode' command 2784 * instead of reinitializing the entire NIC. Doing 2785 * a full re-init means reloading the firmware and 2786 * waiting for it to start up, which may take a 2787 * second or two. 2788 */ 2789 if (ifp->if_flags & IFF_RUNNING && 2790 ifp->if_flags & IFF_PROMISC && 2791 !(sc->bge_if_flags & IFF_PROMISC)) { 2792 BGE_SETBIT(sc, BGE_RX_MODE, 2793 BGE_RXMODE_RX_PROMISC); 2794 } else if (ifp->if_flags & IFF_RUNNING && 2795 !(ifp->if_flags & IFF_PROMISC) && 2796 sc->bge_if_flags & IFF_PROMISC) { 2797 BGE_CLRBIT(sc, BGE_RX_MODE, 2798 BGE_RXMODE_RX_PROMISC); 2799 } else 2800 bge_init(sc); 2801 } else { 2802 if (ifp->if_flags & IFF_RUNNING) { 2803 bge_stop(sc); 2804 } 2805 } 2806 sc->bge_if_flags = ifp->if_flags; 2807 error = 0; 2808 break; 2809 case SIOCADDMULTI: 2810 case SIOCDELMULTI: 2811 if (ifp->if_flags & IFF_RUNNING) { 2812 bge_setmulti(sc); 2813 error = 0; 2814 } 2815 break; 2816 case SIOCSIFMEDIA: 2817 case SIOCGIFMEDIA: 2818 if (sc->bge_tbi) { 2819 error = ifmedia_ioctl(ifp, ifr, 2820 &sc->bge_ifmedia, command); 2821 } else { 2822 mii = device_get_softc(sc->bge_miibus); 2823 error = ifmedia_ioctl(ifp, ifr, 2824 &mii->mii_media, command); 2825 } 2826 break; 2827 case SIOCSIFCAP: 2828 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2829 if (mask & IFCAP_HWCSUM) { 2830 if (IFCAP_HWCSUM & ifp->if_capenable) 2831 ifp->if_capenable &= ~IFCAP_HWCSUM; 2832 else 2833 ifp->if_capenable |= IFCAP_HWCSUM; 2834 } 2835 error = 0; 2836 break; 2837 default: 2838 error = EINVAL; 2839 break; 2840 } 2841 2842 (void)splx(s); 2843 2844 return(error); 2845 } 2846 2847 static void 2848 bge_watchdog(ifp) 2849 struct ifnet *ifp; 2850 { 2851 struct bge_softc *sc; 2852 2853 sc = ifp->if_softc; 2854 2855 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2856 2857 ifp->if_flags &= ~IFF_RUNNING; 2858 bge_init(sc); 2859 2860 ifp->if_oerrors++; 2861 2862 return; 2863 } 2864 2865 /* 2866 * Stop the adapter and free any mbufs allocated to the 2867 * RX and TX lists. 2868 */ 2869 static void 2870 bge_stop(sc) 2871 struct bge_softc *sc; 2872 { 2873 struct ifnet *ifp; 2874 struct ifmedia_entry *ifm; 2875 struct mii_data *mii = NULL; 2876 int mtmp, itmp; 2877 2878 ifp = &sc->arpcom.ac_if; 2879 2880 if (!sc->bge_tbi) 2881 mii = device_get_softc(sc->bge_miibus); 2882 2883 callout_stop(&sc->bge_stat_timer); 2884 2885 /* 2886 * Disable all of the receiver blocks 2887 */ 2888 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2889 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2890 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2891 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2892 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2893 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2894 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2895 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2896 2897 /* 2898 * Disable all of the transmit blocks 2899 */ 2900 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2901 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2902 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2903 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2904 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2905 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2906 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2907 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2908 2909 /* 2910 * Shut down all of the memory managers and related 2911 * state machines. 2912 */ 2913 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2914 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2915 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2916 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2917 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2918 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2919 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2920 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2921 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2922 } 2923 2924 /* Disable host interrupts. */ 2925 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2926 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2927 2928 /* 2929 * Tell firmware we're shutting down. 2930 */ 2931 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2932 2933 /* Free the RX lists. */ 2934 bge_free_rx_ring_std(sc); 2935 2936 /* Free jumbo RX list. */ 2937 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2938 bge_free_rx_ring_jumbo(sc); 2939 2940 /* Free TX buffers. */ 2941 bge_free_tx_ring(sc); 2942 2943 /* 2944 * Isolate/power down the PHY, but leave the media selection 2945 * unchanged so that things will be put back to normal when 2946 * we bring the interface back up. 2947 */ 2948 if (!sc->bge_tbi) { 2949 itmp = ifp->if_flags; 2950 ifp->if_flags |= IFF_UP; 2951 ifm = mii->mii_media.ifm_cur; 2952 mtmp = ifm->ifm_media; 2953 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2954 mii_mediachg(mii); 2955 ifm->ifm_media = mtmp; 2956 ifp->if_flags = itmp; 2957 } 2958 2959 sc->bge_link = 0; 2960 2961 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2962 2963 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2964 2965 return; 2966 } 2967 2968 /* 2969 * Stop all chip I/O so that the kernel's probe routines don't 2970 * get confused by errant DMAs when rebooting. 2971 */ 2972 static void 2973 bge_shutdown(dev) 2974 device_t dev; 2975 { 2976 struct bge_softc *sc; 2977 2978 sc = device_get_softc(dev); 2979 2980 bge_stop(sc); 2981 bge_reset(sc); 2982 2983 return; 2984 } 2985