1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.29 2006/06/24 06:31:30 sephe Exp $ 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/thread2.h> 44 45 #include <net/if.h> 46 #include <net/ifq_var.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <net/bpf.h> 53 54 #include <net/if_types.h> 55 #include <net/vlan/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 61 #include <machine/bus_memio.h> 62 #include <machine/bus.h> 63 #include <machine/resource.h> 64 #include <sys/bus.h> 65 #include <sys/rman.h> 66 67 #include <bus/pci/pcireg.h> 68 #include <bus/pci/pcivar.h> 69 #include <bus/pci/pcidevs.h> 70 71 #include <dev/netif/mii_layer/mii.h> 72 #include <dev/netif/mii_layer/miivar.h> 73 74 #include "if_bfereg.h" 75 76 MODULE_DEPEND(bfe, pci, 1, 1, 1); 77 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 78 79 /* "controller miibus0" required. See GENERIC if you get errors here. */ 80 #include "miibus_if.h" 81 82 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 83 84 static struct bfe_type bfe_devs[] = { 85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 86 "Broadcom BCM4401 Fast Ethernet" }, 87 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0, 88 "Broadcom BCM4401-B0 Fast Ethernet" }, 89 { 0, 0, NULL } 90 }; 91 92 static int bfe_probe(device_t); 93 static int bfe_attach(device_t); 94 static int bfe_detach(device_t); 95 static void bfe_intr(void *); 96 static void bfe_start(struct ifnet *); 97 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 98 static void bfe_init(void *); 99 static void bfe_stop(struct bfe_softc *); 100 static void bfe_watchdog(struct ifnet *); 101 static void bfe_shutdown(device_t); 102 static void bfe_tick(void *); 103 static void bfe_txeof(struct bfe_softc *); 104 static void bfe_rxeof(struct bfe_softc *); 105 static void bfe_set_rx_mode(struct bfe_softc *); 106 static int bfe_list_rx_init(struct bfe_softc *); 107 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*); 108 static void bfe_rx_ring_free(struct bfe_softc *); 109 110 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 111 static int bfe_ifmedia_upd(struct ifnet *); 112 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 113 static int bfe_miibus_readreg(device_t, int, int); 114 static int bfe_miibus_writereg(device_t, int, int, int); 115 static void bfe_miibus_statchg(device_t); 116 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 117 u_long, const int); 118 static void bfe_get_config(struct bfe_softc *sc); 119 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 120 static void bfe_stats_update(struct bfe_softc *); 121 static void bfe_clear_stats (struct bfe_softc *); 122 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 123 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 124 static int bfe_resetphy(struct bfe_softc *); 125 static int bfe_setupphy(struct bfe_softc *); 126 static void bfe_chip_reset(struct bfe_softc *); 127 static void bfe_chip_halt(struct bfe_softc *); 128 static void bfe_core_reset(struct bfe_softc *); 129 static void bfe_core_disable(struct bfe_softc *); 130 static int bfe_dma_alloc(device_t); 131 static void bfe_dma_free(struct bfe_softc *); 132 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int); 133 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int); 134 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 135 136 static device_method_t bfe_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_probe, bfe_probe), 139 DEVMETHOD(device_attach, bfe_attach), 140 DEVMETHOD(device_detach, bfe_detach), 141 DEVMETHOD(device_shutdown, bfe_shutdown), 142 143 /* bus interface */ 144 DEVMETHOD(bus_print_child, bus_generic_print_child), 145 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 146 147 /* MII interface */ 148 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 149 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 150 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 151 152 { 0, 0 } 153 }; 154 155 static driver_t bfe_driver = { 156 "bfe", 157 bfe_methods, 158 sizeof(struct bfe_softc) 159 }; 160 161 static devclass_t bfe_devclass; 162 163 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 164 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 165 166 /* 167 * Probe for a Broadcom 4401 chip. 168 */ 169 static int 170 bfe_probe(device_t dev) 171 { 172 struct bfe_type *t; 173 uint16_t vendor, product; 174 175 vendor = pci_get_vendor(dev); 176 product = pci_get_device(dev); 177 178 for (t = bfe_devs; t->bfe_name != NULL; t++) { 179 if (vendor == t->bfe_vid && product == t->bfe_did) { 180 device_set_desc(dev, t->bfe_name); 181 return(0); 182 } 183 } 184 185 return(ENXIO); 186 } 187 188 static int 189 bfe_dma_alloc(device_t dev) 190 { 191 struct bfe_softc *sc; 192 int error, i, tx_pos, rx_pos; 193 194 sc = device_get_softc(dev); 195 196 /* parent tag */ 197 error = bus_dma_tag_create(NULL, /* parent */ 198 PAGE_SIZE, 0, /* alignment, boundary */ 199 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 200 BUS_SPACE_MAXADDR, /* highaddr */ 201 NULL, NULL, /* filter, filterarg */ 202 MAXBSIZE, /* maxsize */ 203 BUS_SPACE_UNRESTRICTED, /* num of segments */ 204 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 205 BUS_DMA_ALLOCNOW, /* flags */ 206 &sc->bfe_parent_tag); 207 208 if (error) { 209 device_printf(dev, "could not allocate parent dma tag\n"); 210 return(error); 211 } 212 213 /* tag for TX ring */ 214 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE, 215 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 216 NULL, NULL, BFE_TX_LIST_SIZE, 1, 217 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag); 218 219 if (error) { 220 device_printf(dev, "could not allocate dma tag for TX list\n"); 221 return(error); 222 } 223 224 /* tag for RX ring */ 225 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE, 226 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 227 NULL, NULL, BFE_RX_LIST_SIZE, 1, 228 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag); 229 230 if (error) { 231 device_printf(dev, "could not allocate dma tag for RX list\n"); 232 return(error); 233 } 234 235 /* tag for mbufs */ 236 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0, 237 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 238 1, BUS_SPACE_MAXSIZE_32BIT, 0, 239 &sc->bfe_tag); 240 241 if (error) { 242 device_printf(dev, "could not allocate dma tag for mbufs\n"); 243 return(error); 244 } 245 246 rx_pos = tx_pos = 0; 247 248 /* pre allocate dmamaps for RX list */ 249 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 250 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map); 251 if (error) { 252 rx_pos = i; 253 device_printf(dev, "cannot create DMA map for RX\n"); 254 goto ring_fail; 255 } 256 } 257 rx_pos = BFE_RX_LIST_CNT; 258 259 /* pre allocate dmamaps for TX list */ 260 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 261 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map); 262 if (error) { 263 tx_pos = i; 264 device_printf(dev, "cannot create DMA map for TX\n"); 265 goto ring_fail; 266 } 267 } 268 269 /* Alloc dma for rx ring */ 270 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 271 BUS_DMA_WAITOK, &sc->bfe_rx_map); 272 273 if (error) { 274 device_printf(dev, "cannot allocate DMA mem for RX\n"); 275 return(error); 276 } 277 278 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 279 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 280 sc->bfe_rx_list, sizeof(struct bfe_desc), 281 bfe_dma_map, &sc->bfe_rx_dma, 0); 282 283 if (error) { 284 device_printf(dev, "cannot load DMA map for RX\n"); 285 return(error); 286 } 287 288 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 289 290 /* Alloc dma for tx ring */ 291 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 292 BUS_DMA_WAITOK, &sc->bfe_tx_map); 293 if (error) { 294 device_printf(dev, "cannot allocate DMA mem for TX\n"); 295 return(error); 296 } 297 298 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 299 sc->bfe_tx_list, sizeof(struct bfe_desc), 300 bfe_dma_map, &sc->bfe_tx_dma, 0); 301 if (error) { 302 device_printf(dev, "cannot load DMA map for TX\n"); 303 return(error); 304 } 305 306 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 307 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 308 309 return(0); 310 311 ring_fail: 312 for (i = 0; i < rx_pos; ++i) 313 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_rx_ring[i].bfe_map); 314 for (i = 0; i < tx_pos; ++i) 315 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map); 316 317 bus_dma_tag_destroy(sc->bfe_tag); 318 sc->bfe_tag = NULL; 319 return error; 320 } 321 322 static int 323 bfe_attach(device_t dev) 324 { 325 struct ifnet *ifp; 326 struct bfe_softc *sc; 327 int error = 0, rid; 328 329 sc = device_get_softc(dev); 330 331 sc->bfe_dev = dev; 332 callout_init(&sc->bfe_stat_timer); 333 334 /* 335 * Handle power management nonsense. 336 */ 337 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 338 uint32_t membase, irq; 339 340 /* Save important PCI config data. */ 341 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 342 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 343 344 /* Reset the power state. */ 345 device_printf(dev, "chip is in D%d power mode" 346 " -- setting to D0\n", pci_get_powerstate(dev)); 347 348 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 349 350 /* Restore PCI config data. */ 351 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 352 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 353 } 354 355 /* 356 * Map control/status registers. 357 */ 358 pci_enable_busmaster(dev); 359 360 rid = BFE_PCI_MEMLO; 361 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 362 RF_ACTIVE); 363 if (sc->bfe_res == NULL) { 364 device_printf(dev, "couldn't map memory\n"); 365 return ENXIO; 366 } 367 368 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 369 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 370 371 /* Allocate interrupt */ 372 rid = 0; 373 374 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 375 RF_SHAREABLE | RF_ACTIVE); 376 if (sc->bfe_irq == NULL) { 377 device_printf(dev, "couldn't map interrupt\n"); 378 error = ENXIO; 379 goto fail; 380 } 381 382 error = bfe_dma_alloc(dev); 383 if (error != 0) { 384 device_printf(dev, "failed to allocate DMA resources\n"); 385 goto fail; 386 } 387 388 /* Set up ifnet structure */ 389 ifp = &sc->arpcom.ac_if; 390 ifp->if_softc = sc; 391 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 392 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 393 ifp->if_ioctl = bfe_ioctl; 394 ifp->if_start = bfe_start; 395 ifp->if_watchdog = bfe_watchdog; 396 ifp->if_init = bfe_init; 397 ifp->if_mtu = ETHERMTU; 398 ifp->if_baudrate = 100000000; 399 ifp->if_capabilities |= IFCAP_VLAN_MTU; 400 ifp->if_capenable |= IFCAP_VLAN_MTU; 401 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 402 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN); 403 ifq_set_ready(&ifp->if_snd); 404 405 bfe_get_config(sc); 406 407 /* Reset the chip and turn on the PHY */ 408 bfe_chip_reset(sc); 409 410 if (mii_phy_probe(dev, &sc->bfe_miibus, 411 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 412 device_printf(dev, "MII without any PHY!\n"); 413 error = ENXIO; 414 goto fail; 415 } 416 417 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 418 419 /* 420 * Hook interrupt last to avoid having to lock softc 421 */ 422 error = bus_setup_intr(dev, sc->bfe_irq, INTR_NETSAFE, 423 bfe_intr, sc, &sc->bfe_intrhand, 424 sc->arpcom.ac_if.if_serializer); 425 426 if (error) { 427 ether_ifdetach(ifp); 428 device_printf(dev, "couldn't set up irq\n"); 429 goto fail; 430 } 431 return 0; 432 fail: 433 bfe_detach(dev); 434 return(error); 435 } 436 437 static int 438 bfe_detach(device_t dev) 439 { 440 struct bfe_softc *sc = device_get_softc(dev); 441 struct ifnet *ifp = &sc->arpcom.ac_if; 442 443 if (device_is_attached(dev)) { 444 lwkt_serialize_enter(ifp->if_serializer); 445 bfe_stop(sc); 446 bfe_chip_reset(sc); 447 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 448 lwkt_serialize_exit(ifp->if_serializer); 449 450 ether_ifdetach(ifp); 451 } 452 if (sc->bfe_miibus != NULL) 453 device_delete_child(dev, sc->bfe_miibus); 454 bus_generic_detach(dev); 455 456 if (sc->bfe_irq != NULL) 457 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 458 459 if (sc->bfe_res != NULL) { 460 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO, 461 sc->bfe_res); 462 } 463 bfe_dma_free(sc); 464 465 return(0); 466 } 467 468 /* 469 * Stop all chip I/O so that the kernel's probe routines don't 470 * get confused by errant DMAs when rebooting. 471 */ 472 static void 473 bfe_shutdown(device_t dev) 474 { 475 struct bfe_softc *sc = device_get_softc(dev); 476 struct ifnet *ifp = &sc->arpcom.ac_if; 477 478 lwkt_serialize_enter(ifp->if_serializer); 479 bfe_stop(sc); 480 lwkt_serialize_exit(ifp->if_serializer); 481 } 482 483 static int 484 bfe_miibus_readreg(device_t dev, int phy, int reg) 485 { 486 struct bfe_softc *sc; 487 uint32_t ret; 488 489 sc = device_get_softc(dev); 490 if (phy != sc->bfe_phyaddr) 491 return(0); 492 bfe_readphy(sc, reg, &ret); 493 494 return(ret); 495 } 496 497 static int 498 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 499 { 500 struct bfe_softc *sc; 501 502 sc = device_get_softc(dev); 503 if (phy != sc->bfe_phyaddr) 504 return(0); 505 bfe_writephy(sc, reg, val); 506 507 return(0); 508 } 509 510 static void 511 bfe_miibus_statchg(device_t dev) 512 { 513 return; 514 } 515 516 static void 517 bfe_tx_ring_free(struct bfe_softc *sc) 518 { 519 int i; 520 521 for (i = 0; i < BFE_TX_LIST_CNT; i++) 522 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 523 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 524 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 525 bus_dmamap_unload(sc->bfe_tag, 526 sc->bfe_tx_ring[i].bfe_map); 527 } 528 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 529 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 530 } 531 532 static void 533 bfe_rx_ring_free(struct bfe_softc *sc) 534 { 535 int i; 536 537 for (i = 0; i < BFE_RX_LIST_CNT; i++) 538 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 539 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 540 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 541 bus_dmamap_unload(sc->bfe_tag, 542 sc->bfe_rx_ring[i].bfe_map); 543 } 544 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 545 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 546 } 547 548 549 static int 550 bfe_list_rx_init(struct bfe_softc *sc) 551 { 552 int i; 553 554 for (i = 0; i < BFE_RX_LIST_CNT; i++) 555 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 556 return(ENOBUFS); 557 558 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 559 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 560 561 sc->bfe_rx_cons = 0; 562 563 return(0); 564 } 565 566 static int 567 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 568 { 569 struct bfe_rxheader *rx_header; 570 struct bfe_desc *d; 571 struct bfe_data *r; 572 uint32_t ctrl; 573 574 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 575 return(EINVAL); 576 577 if (m == NULL) { 578 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 579 if (m == NULL) 580 return(ENOBUFS); 581 m->m_len = m->m_pkthdr.len = MCLBYTES; 582 } 583 else 584 m->m_data = m->m_ext.ext_buf; 585 586 rx_header = mtod(m, struct bfe_rxheader *); 587 rx_header->len = 0; 588 rx_header->flags = 0; 589 590 /* Map the mbuf into DMA */ 591 sc->bfe_rx_cnt = c; 592 d = &sc->bfe_rx_list[c]; 593 r = &sc->bfe_rx_ring[c]; 594 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 595 MCLBYTES, bfe_dma_map_desc, d, 0); 596 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 597 598 ctrl = ETHER_MAX_LEN + 32; 599 600 if(c == BFE_RX_LIST_CNT - 1) 601 ctrl |= BFE_DESC_EOT; 602 603 d->bfe_ctrl = ctrl; 604 r->bfe_mbuf = m; 605 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 606 return(0); 607 } 608 609 static void 610 bfe_get_config(struct bfe_softc *sc) 611 { 612 uint8_t eeprom[128]; 613 614 bfe_read_eeprom(sc, eeprom); 615 616 sc->arpcom.ac_enaddr[0] = eeprom[79]; 617 sc->arpcom.ac_enaddr[1] = eeprom[78]; 618 sc->arpcom.ac_enaddr[2] = eeprom[81]; 619 sc->arpcom.ac_enaddr[3] = eeprom[80]; 620 sc->arpcom.ac_enaddr[4] = eeprom[83]; 621 sc->arpcom.ac_enaddr[5] = eeprom[82]; 622 623 sc->bfe_phyaddr = eeprom[90] & 0x1f; 624 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 625 626 sc->bfe_core_unit = 0; 627 sc->bfe_dma_offset = BFE_PCI_DMA; 628 } 629 630 static void 631 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 632 { 633 uint32_t bar_orig, pci_rev, val; 634 635 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 636 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 637 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 638 639 val = CSR_READ_4(sc, BFE_SBINTVEC); 640 val |= cores; 641 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 642 643 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 644 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 645 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 646 647 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 648 } 649 650 static void 651 bfe_clear_stats(struct bfe_softc *sc) 652 { 653 u_long reg; 654 655 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 656 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 657 CSR_READ_4(sc, reg); 658 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 659 CSR_READ_4(sc, reg); 660 } 661 662 static int 663 bfe_resetphy(struct bfe_softc *sc) 664 { 665 uint32_t val; 666 667 bfe_writephy(sc, 0, BMCR_RESET); 668 DELAY(100); 669 bfe_readphy(sc, 0, &val); 670 if (val & BMCR_RESET) { 671 if_printf(&sc->arpcom.ac_if, 672 "PHY Reset would not complete.\n"); 673 return(ENXIO); 674 } 675 return(0); 676 } 677 678 static void 679 bfe_chip_halt(struct bfe_softc *sc) 680 { 681 /* disable interrupts - not that it actually does..*/ 682 CSR_WRITE_4(sc, BFE_IMASK, 0); 683 CSR_READ_4(sc, BFE_IMASK); 684 685 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 686 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 687 688 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 689 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 690 DELAY(10); 691 } 692 693 static void 694 bfe_chip_reset(struct bfe_softc *sc) 695 { 696 uint32_t val; 697 698 /* Set the interrupt vector for the enet core */ 699 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 700 701 /* is core up? */ 702 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 703 if (val == BFE_CLOCK) { 704 /* It is, so shut it down */ 705 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 706 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 707 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 708 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 709 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 710 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 711 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 712 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 713 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 714 } 715 716 bfe_core_reset(sc); 717 bfe_clear_stats(sc); 718 719 /* 720 * We want the phy registers to be accessible even when 721 * the driver is "downed" so initialize MDC preamble, frequency, 722 * and whether internal or external phy here. 723 */ 724 725 /* 4402 has 62.5Mhz SB clock and internal phy */ 726 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 727 728 /* Internal or external PHY? */ 729 val = CSR_READ_4(sc, BFE_DEVCTRL); 730 if (!(val & BFE_IPP)) 731 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 732 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 733 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 734 DELAY(100); 735 } 736 737 /* Enable CRC32 generation and set proper LED modes */ 738 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 739 740 /* Reset or clear powerdown control bit */ 741 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 742 743 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 744 BFE_LAZY_FC_MASK)); 745 746 /* 747 * We don't want lazy interrupts, so just send them at the end of a 748 * frame, please 749 */ 750 BFE_OR(sc, BFE_RCV_LAZY, 0); 751 752 /* Set max lengths, accounting for VLAN tags */ 753 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 754 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 755 756 /* Set watermark XXX - magic */ 757 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 758 759 /* 760 * Initialise DMA channels - not forgetting dma addresses need to be 761 * added to BFE_PCI_DMA 762 */ 763 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 764 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 765 766 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 767 BFE_RX_CTRL_ENABLE); 768 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 769 770 bfe_resetphy(sc); 771 bfe_setupphy(sc); 772 } 773 774 static void 775 bfe_core_disable(struct bfe_softc *sc) 776 { 777 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 778 return; 779 780 /* 781 * Set reject, wait for it set, then wait for the core to stop being busy 782 * Then set reset and reject and enable the clocks 783 */ 784 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 785 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 786 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 787 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 788 BFE_RESET)); 789 CSR_READ_4(sc, BFE_SBTMSLOW); 790 DELAY(10); 791 /* Leave reset and reject set */ 792 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 793 DELAY(10); 794 } 795 796 static void 797 bfe_core_reset(struct bfe_softc *sc) 798 { 799 uint32_t val; 800 801 /* Disable the core */ 802 bfe_core_disable(sc); 803 804 /* and bring it back up */ 805 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 806 CSR_READ_4(sc, BFE_SBTMSLOW); 807 DELAY(10); 808 809 /* Chip bug, clear SERR, IB and TO if they are set. */ 810 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 811 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 812 val = CSR_READ_4(sc, BFE_SBIMSTATE); 813 if (val & (BFE_IBE | BFE_TO)) 814 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 815 816 /* Clear reset and allow it to move through the core */ 817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 818 CSR_READ_4(sc, BFE_SBTMSLOW); 819 DELAY(10); 820 821 /* Leave the clock set */ 822 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 823 CSR_READ_4(sc, BFE_SBTMSLOW); 824 DELAY(10); 825 } 826 827 static void 828 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 829 { 830 uint32_t val; 831 832 val = ((uint32_t) data[2]) << 24; 833 val |= ((uint32_t) data[3]) << 16; 834 val |= ((uint32_t) data[4]) << 8; 835 val |= ((uint32_t) data[5]); 836 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 837 val = (BFE_CAM_HI_VALID | 838 (((uint32_t) data[0]) << 8) | 839 (((uint32_t) data[1]))); 840 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 841 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 842 ((uint32_t)index << BFE_CAM_INDEX_SHIFT))); 843 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 844 } 845 846 static void 847 bfe_set_rx_mode(struct bfe_softc *sc) 848 { 849 struct ifnet *ifp = &sc->arpcom.ac_if; 850 struct ifmultiaddr *ifma; 851 uint32_t val; 852 int i = 0; 853 854 val = CSR_READ_4(sc, BFE_RXCONF); 855 856 if (ifp->if_flags & IFF_PROMISC) 857 val |= BFE_RXCONF_PROMISC; 858 else 859 val &= ~BFE_RXCONF_PROMISC; 860 861 if (ifp->if_flags & IFF_BROADCAST) 862 val &= ~BFE_RXCONF_DBCAST; 863 else 864 val |= BFE_RXCONF_DBCAST; 865 866 867 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 868 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 869 870 if (ifp->if_flags & IFF_ALLMULTI) { 871 val |= BFE_RXCONF_ALLMULTI; 872 } else { 873 val &= ~BFE_RXCONF_ALLMULTI; 874 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 875 if (ifma->ifma_addr->sa_family != AF_LINK) 876 continue; 877 bfe_cam_write(sc, 878 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 879 } 880 } 881 882 CSR_WRITE_4(sc, BFE_RXCONF, val); 883 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 884 } 885 886 static void 887 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 888 { 889 uint32_t *ptr; 890 891 ptr = arg; 892 *ptr = segs->ds_addr; 893 } 894 895 static void 896 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 897 { 898 struct bfe_desc *d; 899 900 d = arg; 901 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 902 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 903 } 904 905 static void 906 bfe_dma_free(struct bfe_softc *sc) 907 { 908 if (sc->bfe_tx_tag != NULL) { 909 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 910 if (sc->bfe_tx_list != NULL) { 911 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 912 sc->bfe_tx_map); 913 sc->bfe_tx_list = NULL; 914 } 915 bus_dma_tag_destroy(sc->bfe_tx_tag); 916 sc->bfe_tx_tag = NULL; 917 } 918 919 if (sc->bfe_rx_tag != NULL) { 920 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 921 if (sc->bfe_rx_list != NULL) { 922 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 923 sc->bfe_rx_map); 924 sc->bfe_rx_list = NULL; 925 } 926 bus_dma_tag_destroy(sc->bfe_rx_tag); 927 sc->bfe_rx_tag = NULL; 928 } 929 930 if (sc->bfe_tag != NULL) { 931 int i; 932 933 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 934 bus_dmamap_destroy(sc->bfe_tag, 935 sc->bfe_tx_ring[i].bfe_map); 936 } 937 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 938 bus_dmamap_destroy(sc->bfe_tag, 939 sc->bfe_rx_ring[i].bfe_map); 940 } 941 942 bus_dma_tag_destroy(sc->bfe_tag); 943 sc->bfe_tag = NULL; 944 } 945 946 if (sc->bfe_parent_tag != NULL) { 947 bus_dma_tag_destroy(sc->bfe_parent_tag); 948 sc->bfe_parent_tag = NULL; 949 } 950 } 951 952 static void 953 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 954 { 955 long i; 956 uint16_t *ptr = (uint16_t *)data; 957 958 for (i = 0; i < 128; i += 2) 959 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 960 } 961 962 static int 963 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 964 u_long timeout, const int clear) 965 { 966 u_long i; 967 968 for (i = 0; i < timeout; i++) { 969 uint32_t val = CSR_READ_4(sc, reg); 970 971 if (clear && !(val & bit)) 972 break; 973 if (!clear && (val & bit)) 974 break; 975 DELAY(10); 976 } 977 if (i == timeout) { 978 if_printf(&sc->arpcom.ac_if, 979 "BUG! Timeout waiting for bit %08x of register " 980 "%x to %s.\n", bit, reg, 981 (clear ? "clear" : "set")); 982 return -1; 983 } 984 return 0; 985 } 986 987 static int 988 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 989 { 990 int err; 991 992 /* Clear MII ISR */ 993 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 994 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 995 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 996 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 997 (reg << BFE_MDIO_RA_SHIFT) | 998 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 999 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1000 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1001 return(err); 1002 } 1003 1004 static int 1005 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 1006 { 1007 int status; 1008 1009 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1010 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1011 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1012 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1013 (reg << BFE_MDIO_RA_SHIFT) | 1014 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1015 (val & BFE_MDIO_DATA_DATA))); 1016 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1017 1018 return status; 1019 } 1020 1021 /* 1022 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1023 * twice 1024 */ 1025 static int 1026 bfe_setupphy(struct bfe_softc *sc) 1027 { 1028 uint32_t val; 1029 1030 /* Enable activity LED */ 1031 bfe_readphy(sc, 26, &val); 1032 bfe_writephy(sc, 26, val & 0x7fff); 1033 bfe_readphy(sc, 26, &val); 1034 1035 /* Enable traffic meter LED mode */ 1036 bfe_readphy(sc, 27, &val); 1037 bfe_writephy(sc, 27, val | (1 << 6)); 1038 1039 return(0); 1040 } 1041 1042 static void 1043 bfe_stats_update(struct bfe_softc *sc) 1044 { 1045 u_long reg; 1046 uint32_t *val; 1047 1048 val = &sc->bfe_hwstats.tx_good_octets; 1049 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1050 *val++ += CSR_READ_4(sc, reg); 1051 val = &sc->bfe_hwstats.rx_good_octets; 1052 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1053 *val++ += CSR_READ_4(sc, reg); 1054 } 1055 1056 static void 1057 bfe_txeof(struct bfe_softc *sc) 1058 { 1059 struct ifnet *ifp = &sc->arpcom.ac_if; 1060 uint32_t i, chipidx; 1061 1062 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1063 chipidx /= sizeof(struct bfe_desc); 1064 1065 i = sc->bfe_tx_cons; 1066 /* Go through the mbufs and free those that have been transmitted */ 1067 while (i != chipidx) { 1068 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1069 if (r->bfe_mbuf != NULL) { 1070 ifp->if_opackets++; 1071 m_freem(r->bfe_mbuf); 1072 r->bfe_mbuf = NULL; 1073 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1074 } 1075 sc->bfe_tx_cnt--; 1076 BFE_INC(i, BFE_TX_LIST_CNT); 1077 } 1078 1079 if (i != sc->bfe_tx_cons) { 1080 /* we freed up some mbufs */ 1081 sc->bfe_tx_cons = i; 1082 ifp->if_flags &= ~IFF_OACTIVE; 1083 } 1084 if (sc->bfe_tx_cnt == 0) 1085 ifp->if_timer = 0; 1086 else 1087 ifp->if_timer = 5; 1088 } 1089 1090 /* Pass a received packet up the stack */ 1091 static void 1092 bfe_rxeof(struct bfe_softc *sc) 1093 { 1094 struct ifnet *ifp = &sc->arpcom.ac_if; 1095 struct mbuf *m; 1096 struct bfe_rxheader *rxheader; 1097 struct bfe_data *r; 1098 uint32_t cons, status, current, len, flags; 1099 1100 cons = sc->bfe_rx_cons; 1101 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1102 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1103 1104 while (current != cons) { 1105 r = &sc->bfe_rx_ring[cons]; 1106 m = r->bfe_mbuf; 1107 rxheader = mtod(m, struct bfe_rxheader*); 1108 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1109 len = rxheader->len; 1110 r->bfe_mbuf = NULL; 1111 1112 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1113 flags = rxheader->flags; 1114 1115 len -= ETHER_CRC_LEN; 1116 1117 /* flag an error and try again */ 1118 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1119 ifp->if_ierrors++; 1120 if (flags & BFE_RX_FLAG_SERR) 1121 ifp->if_collisions++; 1122 bfe_list_newbuf(sc, cons, m); 1123 BFE_INC(cons, BFE_RX_LIST_CNT); 1124 continue; 1125 } 1126 1127 /* Go past the rx header */ 1128 if (bfe_list_newbuf(sc, cons, NULL) != 0) { 1129 bfe_list_newbuf(sc, cons, m); 1130 BFE_INC(cons, BFE_RX_LIST_CNT); 1131 ifp->if_ierrors++; 1132 continue; 1133 } 1134 1135 m_adj(m, BFE_RX_OFFSET); 1136 m->m_len = m->m_pkthdr.len = len; 1137 1138 ifp->if_ipackets++; 1139 m->m_pkthdr.rcvif = ifp; 1140 1141 ifp->if_input(ifp, m); 1142 BFE_INC(cons, BFE_RX_LIST_CNT); 1143 } 1144 sc->bfe_rx_cons = cons; 1145 } 1146 1147 static void 1148 bfe_intr(void *xsc) 1149 { 1150 struct bfe_softc *sc = xsc; 1151 struct ifnet *ifp = &sc->arpcom.ac_if; 1152 uint32_t istat, imask, flag; 1153 1154 istat = CSR_READ_4(sc, BFE_ISTAT); 1155 imask = CSR_READ_4(sc, BFE_IMASK); 1156 1157 /* 1158 * Defer unsolicited interrupts - This is necessary because setting the 1159 * chips interrupt mask register to 0 doesn't actually stop the 1160 * interrupts 1161 */ 1162 istat &= imask; 1163 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1164 CSR_READ_4(sc, BFE_ISTAT); 1165 1166 /* not expecting this interrupt, disregard it */ 1167 if (istat == 0) { 1168 return; 1169 } 1170 1171 if (istat & BFE_ISTAT_ERRORS) { 1172 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1173 if (flag & BFE_STAT_EMASK) 1174 ifp->if_oerrors++; 1175 1176 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1177 if (flag & BFE_RX_FLAG_ERRORS) 1178 ifp->if_ierrors++; 1179 1180 ifp->if_flags &= ~IFF_RUNNING; 1181 bfe_init(sc); 1182 } 1183 1184 /* A packet was received */ 1185 if (istat & BFE_ISTAT_RX) 1186 bfe_rxeof(sc); 1187 1188 /* A packet was sent */ 1189 if (istat & BFE_ISTAT_TX) 1190 bfe_txeof(sc); 1191 1192 /* We have packets pending, fire them out */ 1193 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1194 bfe_start(ifp); 1195 } 1196 1197 static int 1198 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1199 { 1200 struct bfe_desc *d = NULL; 1201 struct bfe_data *r = NULL; 1202 struct mbuf *m; 1203 uint32_t frag, cur, cnt = 0; 1204 1205 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1206 return(ENOBUFS); 1207 1208 /* 1209 * Start packing the mbufs in this chain into 1210 * the fragment pointers. Stop when we run out 1211 * of fragments or hit the end of the mbuf chain. 1212 */ 1213 m = m_head; 1214 cur = frag = *txidx; 1215 cnt = 0; 1216 1217 for (m = m_head; m != NULL; m = m->m_next) { 1218 if (m->m_len != 0) { 1219 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1220 return(ENOBUFS); 1221 1222 d = &sc->bfe_tx_list[cur]; 1223 r = &sc->bfe_tx_ring[cur]; 1224 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1225 /* always intterupt on completion */ 1226 d->bfe_ctrl |= BFE_DESC_IOC; 1227 if (cnt == 0) 1228 /* Set start of frame */ 1229 d->bfe_ctrl |= BFE_DESC_SOF; 1230 if (cur == BFE_TX_LIST_CNT - 1) 1231 /* 1232 * Tell the chip to wrap to the start of the 1233 *descriptor list 1234 */ 1235 d->bfe_ctrl |= BFE_DESC_EOT; 1236 1237 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*), 1238 m->m_len, bfe_dma_map_desc, d, 0); 1239 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1240 BUS_DMASYNC_PREREAD); 1241 1242 frag = cur; 1243 BFE_INC(cur, BFE_TX_LIST_CNT); 1244 cnt++; 1245 } 1246 } 1247 1248 if (m != NULL) 1249 return(ENOBUFS); 1250 1251 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1252 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1253 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1254 1255 *txidx = cur; 1256 sc->bfe_tx_cnt += cnt; 1257 return(0); 1258 } 1259 1260 /* 1261 * Set up to transmit a packet 1262 */ 1263 static void 1264 bfe_start(struct ifnet *ifp) 1265 { 1266 struct bfe_softc *sc = ifp->if_softc; 1267 struct mbuf *m_head = NULL; 1268 int idx, need_trans; 1269 1270 /* 1271 * Not much point trying to send if the link is down 1272 * or we have nothing to send. 1273 */ 1274 if (!sc->bfe_link) 1275 return; 1276 1277 if (ifp->if_flags & IFF_OACTIVE) 1278 return; 1279 1280 idx = sc->bfe_tx_prod; 1281 1282 need_trans = 0; 1283 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1284 m_head = ifq_poll(&ifp->if_snd); 1285 if (m_head == NULL) 1286 break; 1287 1288 /* 1289 * Pack the data into the tx ring. If we don't have 1290 * enough room, let the chip drain the ring. 1291 */ 1292 if (bfe_encap(sc, m_head, &idx)) { 1293 ifp->if_flags |= IFF_OACTIVE; 1294 break; 1295 } 1296 ifq_dequeue(&ifp->if_snd, m_head); 1297 need_trans = 1; 1298 1299 /* 1300 * If there's a BPF listener, bounce a copy of this frame 1301 * to him. 1302 */ 1303 BPF_MTAP(ifp, m_head); 1304 } 1305 1306 if (!need_trans) 1307 return; 1308 1309 sc->bfe_tx_prod = idx; 1310 /* Transmit - twice due to apparent hardware bug */ 1311 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1312 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1313 1314 /* 1315 * Set a timeout in case the chip goes out to lunch. 1316 */ 1317 ifp->if_timer = 5; 1318 } 1319 1320 static void 1321 bfe_init(void *xsc) 1322 { 1323 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1324 struct ifnet *ifp = &sc->arpcom.ac_if; 1325 1326 if (ifp->if_flags & IFF_RUNNING) 1327 return; 1328 1329 bfe_stop(sc); 1330 bfe_chip_reset(sc); 1331 1332 if (bfe_list_rx_init(sc) == ENOBUFS) { 1333 if_printf(ifp, "bfe_init failed. " 1334 " Not enough memory for list buffers\n"); 1335 bfe_stop(sc); 1336 return; 1337 } 1338 1339 bfe_set_rx_mode(sc); 1340 1341 /* Enable the chip and core */ 1342 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1343 /* Enable interrupts */ 1344 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1345 1346 bfe_ifmedia_upd(ifp); 1347 ifp->if_flags |= IFF_RUNNING; 1348 ifp->if_flags &= ~IFF_OACTIVE; 1349 1350 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1351 } 1352 1353 /* 1354 * Set media options. 1355 */ 1356 static int 1357 bfe_ifmedia_upd(struct ifnet *ifp) 1358 { 1359 struct bfe_softc *sc = ifp->if_softc; 1360 struct mii_data *mii; 1361 1362 mii = device_get_softc(sc->bfe_miibus); 1363 sc->bfe_link = 0; 1364 if (mii->mii_instance) { 1365 struct mii_softc *miisc; 1366 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1367 miisc = LIST_NEXT(miisc, mii_list)) 1368 mii_phy_reset(miisc); 1369 } 1370 mii_mediachg(mii); 1371 1372 bfe_setupphy(sc); 1373 1374 return(0); 1375 } 1376 1377 /* 1378 * Report current media status. 1379 */ 1380 static void 1381 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1382 { 1383 struct bfe_softc *sc = ifp->if_softc; 1384 struct mii_data *mii; 1385 1386 mii = device_get_softc(sc->bfe_miibus); 1387 mii_pollstat(mii); 1388 ifmr->ifm_active = mii->mii_media_active; 1389 ifmr->ifm_status = mii->mii_media_status; 1390 } 1391 1392 static int 1393 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1394 { 1395 struct bfe_softc *sc = ifp->if_softc; 1396 struct ifreq *ifr = (struct ifreq *) data; 1397 struct mii_data *mii; 1398 int error = 0; 1399 1400 switch (command) { 1401 case SIOCSIFFLAGS: 1402 if (ifp->if_flags & IFF_UP) 1403 if (ifp->if_flags & IFF_RUNNING) 1404 bfe_set_rx_mode(sc); 1405 else 1406 bfe_init(sc); 1407 else if (ifp->if_flags & IFF_RUNNING) 1408 bfe_stop(sc); 1409 break; 1410 case SIOCADDMULTI: 1411 case SIOCDELMULTI: 1412 if (ifp->if_flags & IFF_RUNNING) 1413 bfe_set_rx_mode(sc); 1414 break; 1415 case SIOCGIFMEDIA: 1416 case SIOCSIFMEDIA: 1417 mii = device_get_softc(sc->bfe_miibus); 1418 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1419 command); 1420 break; 1421 default: 1422 error = ether_ioctl(ifp, command, data); 1423 break; 1424 } 1425 return error; 1426 } 1427 1428 static void 1429 bfe_watchdog(struct ifnet *ifp) 1430 { 1431 struct bfe_softc *sc = ifp->if_softc; 1432 1433 if_printf(ifp, "watchdog timeout -- resetting\n"); 1434 1435 ifp->if_flags &= ~IFF_RUNNING; 1436 bfe_init(sc); 1437 1438 ifp->if_oerrors++; 1439 } 1440 1441 static void 1442 bfe_tick(void *xsc) 1443 { 1444 struct bfe_softc *sc = xsc; 1445 struct mii_data *mii; 1446 struct ifnet *ifp = &sc->arpcom.ac_if; 1447 1448 mii = device_get_softc(sc->bfe_miibus); 1449 1450 lwkt_serialize_enter(ifp->if_serializer); 1451 1452 bfe_stats_update(sc); 1453 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1454 1455 if (sc->bfe_link == NULL) { 1456 mii_tick(mii); 1457 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1458 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1459 sc->bfe_link++; 1460 } 1461 if (!sc->bfe_link) 1462 sc->bfe_link++; 1463 } 1464 lwkt_serialize_exit(ifp->if_serializer); 1465 } 1466 1467 /* 1468 * Stop the adapter and free any mbufs allocated to the 1469 * RX and TX lists. 1470 */ 1471 static void 1472 bfe_stop(struct bfe_softc *sc) 1473 { 1474 struct ifnet *ifp = &sc->arpcom.ac_if; 1475 1476 callout_stop(&sc->bfe_stat_timer); 1477 1478 bfe_chip_halt(sc); 1479 bfe_tx_ring_free(sc); 1480 bfe_rx_ring_free(sc); 1481 1482 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1483 } 1484 1485