1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.16 2005/05/27 15:36:09 joerg Exp $ 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 44 #include <net/if.h> 45 #include <net/ifq_var.h> 46 #include <net/if_arp.h> 47 #include <net/ethernet.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <net/bpf.h> 52 53 #include <net/if_types.h> 54 #include <net/vlan/if_vlan_var.h> 55 56 #include <netinet/in_systm.h> 57 #include <netinet/in.h> 58 #include <netinet/ip.h> 59 60 #include <machine/bus_memio.h> 61 #include <machine/bus.h> 62 #include <machine/resource.h> 63 #include <sys/bus.h> 64 #include <sys/rman.h> 65 66 #include <bus/pci/pcireg.h> 67 #include <bus/pci/pcivar.h> 68 #include <bus/pci/pcidevs.h> 69 70 #include <dev/netif/mii_layer/mii.h> 71 #include <dev/netif/mii_layer/miivar.h> 72 73 #include "if_bfereg.h" 74 75 MODULE_DEPEND(bfe, pci, 1, 1, 1); 76 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 77 78 /* "controller miibus0" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 81 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 82 83 static struct bfe_type bfe_devs[] = { 84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 85 "Broadcom BCM4401 Fast Ethernet" }, 86 { 0, 0, NULL } 87 }; 88 89 static int bfe_probe(device_t); 90 static int bfe_attach(device_t); 91 static int bfe_detach(device_t); 92 static void bfe_release_resources(struct bfe_softc *); 93 static void bfe_intr(void *); 94 static void bfe_start(struct ifnet *); 95 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 96 static void bfe_init(void *); 97 static void bfe_stop(struct bfe_softc *); 98 static void bfe_watchdog(struct ifnet *); 99 static void bfe_shutdown(device_t); 100 static void bfe_tick(void *); 101 static void bfe_txeof(struct bfe_softc *); 102 static void bfe_rxeof(struct bfe_softc *); 103 static void bfe_set_rx_mode(struct bfe_softc *); 104 static int bfe_list_rx_init(struct bfe_softc *); 105 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*); 106 static void bfe_rx_ring_free(struct bfe_softc *); 107 108 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 109 static int bfe_ifmedia_upd(struct ifnet *); 110 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 111 static int bfe_miibus_readreg(device_t, int, int); 112 static int bfe_miibus_writereg(device_t, int, int, int); 113 static void bfe_miibus_statchg(device_t); 114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 115 u_long, const int); 116 static void bfe_get_config(struct bfe_softc *sc); 117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 118 static void bfe_stats_update(struct bfe_softc *); 119 static void bfe_clear_stats (struct bfe_softc *); 120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 122 static int bfe_resetphy(struct bfe_softc *); 123 static int bfe_setupphy(struct bfe_softc *); 124 static void bfe_chip_reset(struct bfe_softc *); 125 static void bfe_chip_halt(struct bfe_softc *); 126 static void bfe_core_reset(struct bfe_softc *); 127 static void bfe_core_disable(struct bfe_softc *); 128 static int bfe_dma_alloc(device_t); 129 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int); 130 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int); 131 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 132 133 static device_method_t bfe_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, bfe_probe), 136 DEVMETHOD(device_attach, bfe_attach), 137 DEVMETHOD(device_detach, bfe_detach), 138 DEVMETHOD(device_shutdown, bfe_shutdown), 139 140 /* bus interface */ 141 DEVMETHOD(bus_print_child, bus_generic_print_child), 142 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 143 144 /* MII interface */ 145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 148 149 { 0, 0 } 150 }; 151 152 static driver_t bfe_driver = { 153 "bfe", 154 bfe_methods, 155 sizeof(struct bfe_softc) 156 }; 157 158 static devclass_t bfe_devclass; 159 160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 162 163 /* 164 * Probe for a Broadcom 4401 chip. 165 */ 166 static int 167 bfe_probe(device_t dev) 168 { 169 struct bfe_type *t; 170 uint16_t vendor, product; 171 172 vendor = pci_get_vendor(dev); 173 product = pci_get_device(dev); 174 175 for (t = bfe_devs; t->bfe_name != NULL; t++) { 176 if (vendor == t->bfe_vid && product == t->bfe_did) { 177 device_set_desc_copy(dev, t->bfe_name); 178 return(0); 179 } 180 } 181 182 return(ENXIO); 183 } 184 185 static int 186 bfe_dma_alloc(device_t dev) 187 { 188 struct bfe_softc *sc; 189 int error, i; 190 191 sc = device_get_softc(dev); 192 193 /* parent tag */ 194 error = bus_dma_tag_create(NULL, /* parent */ 195 PAGE_SIZE, 0, /* alignment, boundary */ 196 BUS_SPACE_MAXADDR, /* lowaddr */ 197 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 198 NULL, NULL, /* filter, filterarg */ 199 MAXBSIZE, /* maxsize */ 200 BUS_SPACE_UNRESTRICTED, /* num of segments */ 201 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 202 BUS_DMA_ALLOCNOW, /* flags */ 203 &sc->bfe_parent_tag); 204 205 if (error) { 206 device_printf(dev, "could not allocate dma tag\n"); 207 return(ENOMEM); 208 } 209 210 211 /* tag for TX ring */ 212 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE, 213 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 214 NULL, NULL, BFE_TX_LIST_SIZE, 1, 215 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag); 216 217 if (error) { 218 device_printf(dev, "could not allocate dma tag\n"); 219 return(ENOMEM); 220 } 221 222 /* tag for RX ring */ 223 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE, 224 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 225 NULL, NULL, BFE_RX_LIST_SIZE, 1, 226 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag); 227 228 if (error) { 229 device_printf(dev, "could not allocate dma tag\n"); 230 return(ENOMEM); 231 } 232 233 /* tag for mbufs */ 234 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0, 235 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 236 1, BUS_SPACE_MAXSIZE_32BIT, 0, 237 &sc->bfe_tag); 238 239 if (error) { 240 device_printf(dev, "could not allocate dma tag\n"); 241 return(ENOMEM); 242 } 243 244 /* pre allocate dmamaps for RX list */ 245 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 246 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map); 247 if (error) { 248 device_printf(dev, "cannot create DMA map for RX\n"); 249 return(ENOMEM); 250 } 251 } 252 253 /* pre allocate dmamaps for TX list */ 254 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 255 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map); 256 if (error) { 257 device_printf(dev, "cannot create DMA map for TX\n"); 258 return(ENOMEM); 259 } 260 } 261 262 /* Alloc dma for rx ring */ 263 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 264 BUS_DMA_WAITOK, &sc->bfe_rx_map); 265 266 if (error) 267 return(ENOMEM); 268 269 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 270 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 271 sc->bfe_rx_list, sizeof(struct bfe_desc), 272 bfe_dma_map, &sc->bfe_rx_dma, 0); 273 274 if (error) 275 return(ENOMEM); 276 277 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 278 279 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 280 BUS_DMA_WAITOK, &sc->bfe_tx_map); 281 if (error) 282 return(ENOMEM); 283 284 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 285 sc->bfe_tx_list, sizeof(struct bfe_desc), 286 bfe_dma_map, &sc->bfe_tx_dma, 0); 287 if (error) 288 return(ENOMEM); 289 290 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 291 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 292 293 return(0); 294 } 295 296 static int 297 bfe_attach(device_t dev) 298 { 299 struct ifnet *ifp; 300 struct bfe_softc *sc; 301 int error = 0, rid; 302 303 sc = device_get_softc(dev); 304 305 sc->bfe_dev = dev; 306 callout_init(&sc->bfe_stat_timer); 307 308 /* 309 * Handle power management nonsense. 310 */ 311 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 312 uint32_t membase, irq; 313 314 /* Save important PCI config data. */ 315 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 316 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 317 318 /* Reset the power state. */ 319 device_printf(dev, "chip is in D%d power mode" 320 " -- setting to D0\n", pci_get_powerstate(dev)); 321 322 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 323 324 /* Restore PCI config data. */ 325 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 326 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 327 } 328 329 /* 330 * Map control/status registers. 331 */ 332 pci_enable_busmaster(dev); 333 334 rid = BFE_PCI_MEMLO; 335 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 336 RF_ACTIVE); 337 if (sc->bfe_res == NULL) { 338 device_printf(dev, "couldn't map memory\n"); 339 error = ENXIO; 340 goto fail; 341 } 342 343 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 344 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 345 346 /* Allocate interrupt */ 347 rid = 0; 348 349 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 350 RF_SHAREABLE | RF_ACTIVE); 351 if (sc->bfe_irq == NULL) { 352 device_printf(dev, "couldn't map interrupt\n"); 353 error = ENXIO; 354 goto fail; 355 } 356 357 if (bfe_dma_alloc(dev)) { 358 device_printf(dev, "failed to allocate DMA resources\n"); 359 bfe_release_resources(sc); 360 error = ENXIO; 361 goto fail; 362 } 363 364 /* Set up ifnet structure */ 365 ifp = &sc->arpcom.ac_if; 366 ifp->if_softc = sc; 367 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = bfe_ioctl; 370 ifp->if_start = bfe_start; 371 ifp->if_watchdog = bfe_watchdog; 372 ifp->if_init = bfe_init; 373 ifp->if_mtu = ETHERMTU; 374 ifp->if_baudrate = 10000000; 375 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN); 376 ifq_set_ready(&ifp->if_snd); 377 378 bfe_get_config(sc); 379 380 /* Reset the chip and turn on the PHY */ 381 bfe_chip_reset(sc); 382 383 if (mii_phy_probe(dev, &sc->bfe_miibus, 384 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 385 device_printf(dev, "MII without any PHY!\n"); 386 error = ENXIO; 387 goto fail; 388 } 389 390 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 391 392 /* 393 * Hook interrupt last to avoid having to lock softc 394 */ 395 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 396 bfe_intr, sc, &sc->bfe_intrhand, NULL); 397 398 if (error) { 399 bfe_release_resources(sc); 400 device_printf(dev, "couldn't set up irq\n"); 401 goto fail; 402 } 403 fail: 404 if (error) 405 bfe_release_resources(sc); 406 return(error); 407 } 408 409 static int 410 bfe_detach(device_t dev) 411 { 412 struct bfe_softc *sc; 413 struct ifnet *ifp; 414 int s; 415 416 sc = device_get_softc(dev); 417 418 s = splimp(); 419 420 ifp = &sc->arpcom.ac_if; 421 422 if (device_is_attached(dev)) { 423 bfe_stop(sc); 424 ether_ifdetach(ifp); 425 } 426 427 bfe_chip_reset(sc); 428 429 bus_generic_detach(dev); 430 if (sc->bfe_miibus != NULL) 431 device_delete_child(dev, sc->bfe_miibus); 432 433 bfe_release_resources(sc); 434 splx(s); 435 436 return(0); 437 } 438 439 /* 440 * Stop all chip I/O so that the kernel's probe routines don't 441 * get confused by errant DMAs when rebooting. 442 */ 443 static void 444 bfe_shutdown(device_t dev) 445 { 446 struct bfe_softc *sc; 447 int s; 448 449 sc = device_get_softc(dev); 450 451 s = splimp(); 452 bfe_stop(sc); 453 splx(s); 454 455 return; 456 } 457 458 static int 459 bfe_miibus_readreg(device_t dev, int phy, int reg) 460 { 461 struct bfe_softc *sc; 462 uint32_t ret; 463 464 sc = device_get_softc(dev); 465 if (phy != sc->bfe_phyaddr) 466 return(0); 467 bfe_readphy(sc, reg, &ret); 468 469 return(ret); 470 } 471 472 static int 473 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 474 { 475 struct bfe_softc *sc; 476 477 sc = device_get_softc(dev); 478 if (phy != sc->bfe_phyaddr) 479 return(0); 480 bfe_writephy(sc, reg, val); 481 482 return(0); 483 } 484 485 static void 486 bfe_miibus_statchg(device_t dev) 487 { 488 return; 489 } 490 491 static void 492 bfe_tx_ring_free(struct bfe_softc *sc) 493 { 494 int i; 495 496 for (i = 0; i < BFE_TX_LIST_CNT; i++) 497 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 498 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 499 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 500 bus_dmamap_unload(sc->bfe_tag, 501 sc->bfe_tx_ring[i].bfe_map); 502 bus_dmamap_destroy(sc->bfe_tag, 503 sc->bfe_tx_ring[i].bfe_map); 504 } 505 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 506 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 507 } 508 509 static void 510 bfe_rx_ring_free(struct bfe_softc *sc) 511 { 512 int i; 513 514 for (i = 0; i < BFE_RX_LIST_CNT; i++) 515 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 516 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 517 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 518 bus_dmamap_unload(sc->bfe_tag, 519 sc->bfe_rx_ring[i].bfe_map); 520 bus_dmamap_destroy(sc->bfe_tag, 521 sc->bfe_rx_ring[i].bfe_map); 522 } 523 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 524 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 525 } 526 527 528 static int 529 bfe_list_rx_init(struct bfe_softc *sc) 530 { 531 int i; 532 533 for (i = 0; i < BFE_RX_LIST_CNT; i++) 534 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 535 return(ENOBUFS); 536 537 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 538 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 539 540 sc->bfe_rx_cons = 0; 541 542 return(0); 543 } 544 545 static int 546 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 547 { 548 struct bfe_rxheader *rx_header; 549 struct bfe_desc *d; 550 struct bfe_data *r; 551 uint32_t ctrl; 552 553 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 554 return(EINVAL); 555 556 if (m == NULL) { 557 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 558 if (m == NULL) 559 return(ENOBUFS); 560 m->m_len = m->m_pkthdr.len = MCLBYTES; 561 } 562 else 563 m->m_data = m->m_ext.ext_buf; 564 565 rx_header = mtod(m, struct bfe_rxheader *); 566 rx_header->len = 0; 567 rx_header->flags = 0; 568 569 /* Map the mbuf into DMA */ 570 sc->bfe_rx_cnt = c; 571 d = &sc->bfe_rx_list[c]; 572 r = &sc->bfe_rx_ring[c]; 573 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 574 MCLBYTES, bfe_dma_map_desc, d, 0); 575 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 576 577 ctrl = ETHER_MAX_LEN + 32; 578 579 if(c == BFE_RX_LIST_CNT - 1) 580 ctrl |= BFE_DESC_EOT; 581 582 d->bfe_ctrl = ctrl; 583 r->bfe_mbuf = m; 584 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 585 return(0); 586 } 587 588 static void 589 bfe_get_config(struct bfe_softc *sc) 590 { 591 uint8_t eeprom[128]; 592 593 bfe_read_eeprom(sc, eeprom); 594 595 sc->arpcom.ac_enaddr[0] = eeprom[79]; 596 sc->arpcom.ac_enaddr[1] = eeprom[78]; 597 sc->arpcom.ac_enaddr[2] = eeprom[81]; 598 sc->arpcom.ac_enaddr[3] = eeprom[80]; 599 sc->arpcom.ac_enaddr[4] = eeprom[83]; 600 sc->arpcom.ac_enaddr[5] = eeprom[82]; 601 602 sc->bfe_phyaddr = eeprom[90] & 0x1f; 603 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 604 605 sc->bfe_core_unit = 0; 606 sc->bfe_dma_offset = BFE_PCI_DMA; 607 } 608 609 static void 610 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 611 { 612 uint32_t bar_orig, pci_rev, val; 613 614 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 615 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 616 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 617 618 val = CSR_READ_4(sc, BFE_SBINTVEC); 619 val |= cores; 620 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 621 622 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 623 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 624 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 625 626 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 627 } 628 629 static void 630 bfe_clear_stats(struct bfe_softc *sc) 631 { 632 u_long reg; 633 int s; 634 635 s = splimp(); 636 637 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 638 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 639 CSR_READ_4(sc, reg); 640 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 641 CSR_READ_4(sc, reg); 642 643 splx(s); 644 } 645 646 static int 647 bfe_resetphy(struct bfe_softc *sc) 648 { 649 uint32_t val; 650 int s; 651 652 s = splimp(); 653 bfe_writephy(sc, 0, BMCR_RESET); 654 DELAY(100); 655 bfe_readphy(sc, 0, &val); 656 if (val & BMCR_RESET) { 657 if_printf(&sc->arpcom.ac_if, 658 "PHY Reset would not complete.\n"); 659 splx(s); 660 return(ENXIO); 661 } 662 splx(s); 663 return(0); 664 } 665 666 static void 667 bfe_chip_halt(struct bfe_softc *sc) 668 { 669 int s; 670 671 s = splimp(); 672 /* disable interrupts - not that it actually does..*/ 673 CSR_WRITE_4(sc, BFE_IMASK, 0); 674 CSR_READ_4(sc, BFE_IMASK); 675 676 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 677 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 678 679 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 680 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 681 DELAY(10); 682 683 splx(s); 684 } 685 686 static void 687 bfe_chip_reset(struct bfe_softc *sc) 688 { 689 uint32_t val; 690 int s; 691 692 s = splimp(); 693 694 /* Set the interrupt vector for the enet core */ 695 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 696 697 /* is core up? */ 698 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 699 if (val == BFE_CLOCK) { 700 /* It is, so shut it down */ 701 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 702 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 703 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 704 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 705 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 706 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 707 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 708 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 709 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 710 } 711 712 bfe_core_reset(sc); 713 bfe_clear_stats(sc); 714 715 /* 716 * We want the phy registers to be accessible even when 717 * the driver is "downed" so initialize MDC preamble, frequency, 718 * and whether internal or external phy here. 719 */ 720 721 /* 4402 has 62.5Mhz SB clock and internal phy */ 722 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 723 724 /* Internal or external PHY? */ 725 val = CSR_READ_4(sc, BFE_DEVCTRL); 726 if (!(val & BFE_IPP)) 727 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 728 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 729 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 730 DELAY(100); 731 } 732 733 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB); 734 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 735 BFE_LAZY_FC_MASK)); 736 737 /* 738 * We don't want lazy interrupts, so just send them at the end of a 739 * frame, please 740 */ 741 BFE_OR(sc, BFE_RCV_LAZY, 0); 742 743 /* Set max lengths, accounting for VLAN tags */ 744 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 745 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 746 747 /* Set watermark XXX - magic */ 748 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 749 750 /* 751 * Initialise DMA channels - not forgetting dma addresses need to be 752 * added to BFE_PCI_DMA 753 */ 754 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 755 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 756 757 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 758 BFE_RX_CTRL_ENABLE); 759 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 760 761 bfe_resetphy(sc); 762 bfe_setupphy(sc); 763 764 splx(s); 765 } 766 767 static void 768 bfe_core_disable(struct bfe_softc *sc) 769 { 770 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 771 return; 772 773 /* 774 * Set reject, wait for it set, then wait for the core to stop being busy 775 * Then set reset and reject and enable the clocks 776 */ 777 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 778 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 779 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 780 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 781 BFE_RESET)); 782 CSR_READ_4(sc, BFE_SBTMSLOW); 783 DELAY(10); 784 /* Leave reset and reject set */ 785 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 786 DELAY(10); 787 } 788 789 static void 790 bfe_core_reset(struct bfe_softc *sc) 791 { 792 uint32_t val; 793 794 /* Disable the core */ 795 bfe_core_disable(sc); 796 797 /* and bring it back up */ 798 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 799 CSR_READ_4(sc, BFE_SBTMSLOW); 800 DELAY(10); 801 802 /* Chip bug, clear SERR, IB and TO if they are set. */ 803 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 804 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 805 val = CSR_READ_4(sc, BFE_SBIMSTATE); 806 if (val & (BFE_IBE | BFE_TO)) 807 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 808 809 /* Clear reset and allow it to move through the core */ 810 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 811 CSR_READ_4(sc, BFE_SBTMSLOW); 812 DELAY(10); 813 814 /* Leave the clock set */ 815 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 816 CSR_READ_4(sc, BFE_SBTMSLOW); 817 DELAY(10); 818 } 819 820 static void 821 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 822 { 823 uint32_t val; 824 825 val = ((uint32_t) data[2]) << 24; 826 val |= ((uint32_t) data[3]) << 16; 827 val |= ((uint32_t) data[4]) << 8; 828 val |= ((uint32_t) data[5]); 829 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 830 val = (BFE_CAM_HI_VALID | 831 (((uint32_t) data[0]) << 8) | 832 (((uint32_t) data[1]))); 833 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 834 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 835 (index << BFE_CAM_INDEX_SHIFT))); 836 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 837 } 838 839 static void 840 bfe_set_rx_mode(struct bfe_softc *sc) 841 { 842 struct ifnet *ifp = &sc->arpcom.ac_if; 843 uint32_t val; 844 int i = 0; 845 846 val = CSR_READ_4(sc, BFE_RXCONF); 847 848 if (ifp->if_flags & IFF_PROMISC) 849 val |= BFE_RXCONF_PROMISC; 850 else 851 val &= ~BFE_RXCONF_PROMISC; 852 853 if (ifp->if_flags & IFF_BROADCAST) 854 val &= ~BFE_RXCONF_DBCAST; 855 else 856 val |= BFE_RXCONF_DBCAST; 857 858 859 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 860 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 861 862 CSR_WRITE_4(sc, BFE_RXCONF, val); 863 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 864 } 865 866 static void 867 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 868 { 869 uint32_t *ptr; 870 871 ptr = arg; 872 *ptr = segs->ds_addr; 873 } 874 875 static void 876 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 877 { 878 struct bfe_desc *d; 879 880 d = arg; 881 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 882 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 883 } 884 885 static void 886 bfe_release_resources(struct bfe_softc *sc) 887 { 888 device_t dev; 889 int i; 890 891 dev = sc->bfe_dev; 892 893 if (sc->bfe_intrhand != NULL) 894 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 895 896 if (sc->bfe_irq != NULL) 897 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 898 899 if (sc->bfe_res != NULL) 900 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 901 902 if (sc->bfe_tx_tag != NULL) { 903 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 904 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, sc->bfe_tx_map); 905 bus_dma_tag_destroy(sc->bfe_tx_tag); 906 sc->bfe_tx_tag = NULL; 907 } 908 909 if (sc->bfe_rx_tag != NULL) { 910 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 911 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, sc->bfe_rx_map); 912 bus_dma_tag_destroy(sc->bfe_rx_tag); 913 sc->bfe_rx_tag = NULL; 914 } 915 916 if (sc->bfe_tag != NULL) { 917 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 918 bus_dmamap_destroy(sc->bfe_tag, 919 sc->bfe_tx_ring[i].bfe_map); 920 } 921 bus_dma_tag_destroy(sc->bfe_tag); 922 sc->bfe_tag = NULL; 923 } 924 925 if (sc->bfe_parent_tag != NULL) 926 bus_dma_tag_destroy(sc->bfe_parent_tag); 927 } 928 929 static void 930 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 931 { 932 long i; 933 uint16_t *ptr = (uint16_t *)data; 934 935 for (i = 0; i < 128; i += 2) 936 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 937 } 938 939 static int 940 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 941 u_long timeout, const int clear) 942 { 943 u_long i; 944 945 for (i = 0; i < timeout; i++) { 946 uint32_t val = CSR_READ_4(sc, reg); 947 948 if (clear && !(val & bit)) 949 break; 950 if (!clear && (val & bit)) 951 break; 952 DELAY(10); 953 } 954 if (i == timeout) { 955 if_printf(&sc->arpcom.ac_if, 956 "BUG! Timeout waiting for bit %08x of register " 957 "%x to %s.\n", bit, reg, 958 (clear ? "clear" : "set")); 959 return -1; 960 } 961 return 0; 962 } 963 964 static int 965 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 966 { 967 int err; 968 int s; 969 970 s = splimp(); 971 /* Clear MII ISR */ 972 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 973 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 974 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 975 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 976 (reg << BFE_MDIO_RA_SHIFT) | 977 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 978 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 979 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 980 981 splx(s); 982 return(err); 983 } 984 985 static int 986 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 987 { 988 int status; 989 int s; 990 991 s = splimp(); 992 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 993 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 994 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 995 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 996 (reg << BFE_MDIO_RA_SHIFT) | 997 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 998 (val & BFE_MDIO_DATA_DATA))); 999 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1000 1001 splx(s); 1002 1003 return status; 1004 } 1005 1006 /* 1007 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1008 * twice 1009 */ 1010 static int 1011 bfe_setupphy(struct bfe_softc *sc) 1012 { 1013 uint32_t val; 1014 int s; 1015 1016 s = splimp(); 1017 1018 /* Enable activity LED */ 1019 bfe_readphy(sc, 26, &val); 1020 bfe_writephy(sc, 26, val & 0x7fff); 1021 bfe_readphy(sc, 26, &val); 1022 1023 /* Enable traffic meter LED mode */ 1024 bfe_readphy(sc, 27, &val); 1025 bfe_writephy(sc, 27, val | (1 << 6)); 1026 1027 splx(s); 1028 return(0); 1029 } 1030 1031 static void 1032 bfe_stats_update(struct bfe_softc *sc) 1033 { 1034 u_long reg; 1035 uint32_t *val; 1036 1037 val = &sc->bfe_hwstats.tx_good_octets; 1038 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1039 *val++ += CSR_READ_4(sc, reg); 1040 val = &sc->bfe_hwstats.rx_good_octets; 1041 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1042 *val++ += CSR_READ_4(sc, reg); 1043 } 1044 1045 static void 1046 bfe_txeof(struct bfe_softc *sc) 1047 { 1048 struct ifnet *ifp; 1049 int s; 1050 uint32_t i, chipidx; 1051 1052 s = splimp(); 1053 1054 ifp = &sc->arpcom.ac_if; 1055 1056 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1057 chipidx /= sizeof(struct bfe_desc); 1058 1059 i = sc->bfe_tx_cons; 1060 /* Go through the mbufs and free those that have been transmitted */ 1061 while (i != chipidx) { 1062 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1063 if (r->bfe_mbuf != NULL) { 1064 ifp->if_opackets++; 1065 m_freem(r->bfe_mbuf); 1066 r->bfe_mbuf = NULL; 1067 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1068 } 1069 sc->bfe_tx_cnt--; 1070 BFE_INC(i, BFE_TX_LIST_CNT); 1071 } 1072 1073 if (i != sc->bfe_tx_cons) { 1074 /* we freed up some mbufs */ 1075 sc->bfe_tx_cons = i; 1076 ifp->if_flags &= ~IFF_OACTIVE; 1077 } 1078 if (sc->bfe_tx_cnt == 0) 1079 ifp->if_timer = 0; 1080 else 1081 ifp->if_timer = 5; 1082 1083 splx(s); 1084 } 1085 1086 /* Pass a received packet up the stack */ 1087 static void 1088 bfe_rxeof(struct bfe_softc *sc) 1089 { 1090 struct mbuf *m; 1091 struct ifnet *ifp; 1092 struct bfe_rxheader *rxheader; 1093 struct bfe_data *r; 1094 uint32_t cons, status, current, len, flags; 1095 int s; 1096 1097 s = splimp(); 1098 cons = sc->bfe_rx_cons; 1099 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1100 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1101 1102 ifp = &sc->arpcom.ac_if; 1103 1104 while (current != cons) { 1105 r = &sc->bfe_rx_ring[cons]; 1106 m = r->bfe_mbuf; 1107 rxheader = mtod(m, struct bfe_rxheader*); 1108 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1109 len = rxheader->len; 1110 r->bfe_mbuf = NULL; 1111 1112 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1113 flags = rxheader->flags; 1114 1115 len -= ETHER_CRC_LEN; 1116 1117 /* flag an error and try again */ 1118 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1119 ifp->if_ierrors++; 1120 if (flags & BFE_RX_FLAG_SERR) 1121 ifp->if_collisions++; 1122 bfe_list_newbuf(sc, cons, m); 1123 BFE_INC(cons, BFE_RX_LIST_CNT); 1124 continue; 1125 } 1126 1127 /* Go past the rx header */ 1128 if (bfe_list_newbuf(sc, cons, NULL) != 0) { 1129 bfe_list_newbuf(sc, cons, m); 1130 BFE_INC(cons, BFE_RX_LIST_CNT); 1131 ifp->if_ierrors++; 1132 continue; 1133 } 1134 1135 m_adj(m, BFE_RX_OFFSET); 1136 m->m_len = m->m_pkthdr.len = len; 1137 1138 ifp->if_ipackets++; 1139 m->m_pkthdr.rcvif = ifp; 1140 1141 (*ifp->if_input)(ifp, m); 1142 BFE_INC(cons, BFE_RX_LIST_CNT); 1143 } 1144 sc->bfe_rx_cons = cons; 1145 splx(s); 1146 } 1147 1148 static void 1149 bfe_intr(void *xsc) 1150 { 1151 struct bfe_softc *sc = xsc; 1152 struct ifnet *ifp; 1153 uint32_t istat, imask, flag; 1154 int s; 1155 1156 ifp = &sc->arpcom.ac_if; 1157 1158 s = splimp(); 1159 1160 istat = CSR_READ_4(sc, BFE_ISTAT); 1161 imask = CSR_READ_4(sc, BFE_IMASK); 1162 1163 /* 1164 * Defer unsolicited interrupts - This is necessary because setting the 1165 * chips interrupt mask register to 0 doesn't actually stop the 1166 * interrupts 1167 */ 1168 istat &= imask; 1169 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1170 CSR_READ_4(sc, BFE_ISTAT); 1171 1172 /* not expecting this interrupt, disregard it */ 1173 if (istat == 0) { 1174 splx(s); 1175 return; 1176 } 1177 1178 if (istat & BFE_ISTAT_ERRORS) { 1179 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1180 if (flag & BFE_STAT_EMASK) 1181 ifp->if_oerrors++; 1182 1183 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1184 if (flag & BFE_RX_FLAG_ERRORS) 1185 ifp->if_ierrors++; 1186 1187 ifp->if_flags &= ~IFF_RUNNING; 1188 bfe_init(sc); 1189 } 1190 1191 /* A packet was received */ 1192 if (istat & BFE_ISTAT_RX) 1193 bfe_rxeof(sc); 1194 1195 /* A packet was sent */ 1196 if (istat & BFE_ISTAT_TX) 1197 bfe_txeof(sc); 1198 1199 /* We have packets pending, fire them out */ 1200 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1201 bfe_start(ifp); 1202 1203 splx(s); 1204 } 1205 1206 static int 1207 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1208 { 1209 struct bfe_desc *d = NULL; 1210 struct bfe_data *r = NULL; 1211 struct mbuf *m; 1212 uint32_t frag, cur, cnt = 0; 1213 1214 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1215 return(ENOBUFS); 1216 1217 /* 1218 * Start packing the mbufs in this chain into 1219 * the fragment pointers. Stop when we run out 1220 * of fragments or hit the end of the mbuf chain. 1221 */ 1222 m = m_head; 1223 cur = frag = *txidx; 1224 cnt = 0; 1225 1226 for (m = m_head; m != NULL; m = m->m_next) { 1227 if (m->m_len != 0) { 1228 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1229 return(ENOBUFS); 1230 1231 d = &sc->bfe_tx_list[cur]; 1232 r = &sc->bfe_tx_ring[cur]; 1233 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1234 /* always intterupt on completion */ 1235 d->bfe_ctrl |= BFE_DESC_IOC; 1236 if (cnt == 0) 1237 /* Set start of frame */ 1238 d->bfe_ctrl |= BFE_DESC_SOF; 1239 if (cur == BFE_TX_LIST_CNT - 1) 1240 /* 1241 * Tell the chip to wrap to the start of the 1242 *descriptor list 1243 */ 1244 d->bfe_ctrl |= BFE_DESC_EOT; 1245 1246 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*), 1247 m->m_len, bfe_dma_map_desc, d, 0); 1248 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1249 BUS_DMASYNC_PREREAD); 1250 1251 frag = cur; 1252 BFE_INC(cur, BFE_TX_LIST_CNT); 1253 cnt++; 1254 } 1255 } 1256 1257 if (m != NULL) 1258 return(ENOBUFS); 1259 1260 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1261 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1262 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1263 1264 *txidx = cur; 1265 sc->bfe_tx_cnt += cnt; 1266 return(0); 1267 } 1268 1269 /* 1270 * Set up to transmit a packet 1271 */ 1272 static void 1273 bfe_start(struct ifnet *ifp) 1274 { 1275 struct bfe_softc *sc; 1276 struct mbuf *m_head = NULL; 1277 int idx; 1278 int s; 1279 1280 sc = ifp->if_softc; 1281 idx = sc->bfe_tx_prod; 1282 1283 s = splimp(); 1284 1285 /* 1286 * not much point trying to send if the link is down or we have nothing to 1287 * send 1288 */ 1289 if (!sc->bfe_link) { 1290 splx(s); 1291 return; 1292 } 1293 1294 if (ifp->if_flags & IFF_OACTIVE) { 1295 splx(s); 1296 return; 1297 } 1298 1299 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1300 m_head = ifq_poll(&ifp->if_snd); 1301 if (m_head == NULL) 1302 break; 1303 1304 /* 1305 * Pack the data into the tx ring. If we dont have enough room, let 1306 * the chip drain the ring 1307 */ 1308 if (bfe_encap(sc, m_head, &idx)) { 1309 ifp->if_flags |= IFF_OACTIVE; 1310 break; 1311 } 1312 m_head = ifq_dequeue(&ifp->if_snd); 1313 1314 /* 1315 * If there's a BPF listener, bounce a copy of this frame 1316 * to him. 1317 */ 1318 BPF_MTAP(ifp, m_head); 1319 } 1320 1321 sc->bfe_tx_prod = idx; 1322 /* Transmit - twice due to apparent hardware bug */ 1323 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1324 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1325 1326 /* 1327 * Set a timeout in case the chip goes out to lunch. 1328 */ 1329 ifp->if_timer = 5; 1330 splx(s); 1331 } 1332 1333 static void 1334 bfe_init(void *xsc) 1335 { 1336 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1337 struct ifnet *ifp = &sc->arpcom.ac_if; 1338 int s; 1339 1340 s = splimp(); 1341 1342 if (ifp->if_flags & IFF_RUNNING) { 1343 splx(s); 1344 return; 1345 } 1346 1347 bfe_stop(sc); 1348 bfe_chip_reset(sc); 1349 1350 if (bfe_list_rx_init(sc) == ENOBUFS) { 1351 if_printf(ifp, "bfe_init failed. " 1352 " Not enough memory for list buffers\n"); 1353 bfe_stop(sc); 1354 return; 1355 } 1356 1357 bfe_set_rx_mode(sc); 1358 1359 /* Enable the chip and core */ 1360 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1361 /* Enable interrupts */ 1362 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1363 1364 bfe_ifmedia_upd(ifp); 1365 ifp->if_flags |= IFF_RUNNING; 1366 ifp->if_flags &= ~IFF_OACTIVE; 1367 1368 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1369 splx(s); 1370 } 1371 1372 /* 1373 * Set media options. 1374 */ 1375 static int 1376 bfe_ifmedia_upd(struct ifnet *ifp) 1377 { 1378 struct bfe_softc *sc; 1379 struct mii_data *mii; 1380 int s; 1381 1382 sc = ifp->if_softc; 1383 1384 s = splimp(); 1385 1386 mii = device_get_softc(sc->bfe_miibus); 1387 sc->bfe_link = 0; 1388 if (mii->mii_instance) { 1389 struct mii_softc *miisc; 1390 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1391 miisc = LIST_NEXT(miisc, mii_list)) 1392 mii_phy_reset(miisc); 1393 } 1394 mii_mediachg(mii); 1395 1396 splx(s); 1397 return(0); 1398 } 1399 1400 /* 1401 * Report current media status. 1402 */ 1403 static void 1404 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1405 { 1406 struct bfe_softc *sc = ifp->if_softc; 1407 struct mii_data *mii; 1408 int s; 1409 1410 s = splimp(); 1411 1412 mii = device_get_softc(sc->bfe_miibus); 1413 mii_pollstat(mii); 1414 ifmr->ifm_active = mii->mii_media_active; 1415 ifmr->ifm_status = mii->mii_media_status; 1416 1417 splx(s); 1418 } 1419 1420 static int 1421 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1422 { 1423 struct bfe_softc *sc = ifp->if_softc; 1424 struct ifreq *ifr = (struct ifreq *) data; 1425 struct mii_data *mii; 1426 int error = 0; 1427 int s; 1428 1429 s = splimp(); 1430 1431 switch (command) { 1432 case SIOCSIFFLAGS: 1433 if (ifp->if_flags & IFF_UP) 1434 if (ifp->if_flags & IFF_RUNNING) 1435 bfe_set_rx_mode(sc); 1436 else 1437 bfe_init(sc); 1438 else if (ifp->if_flags & IFF_RUNNING) 1439 bfe_stop(sc); 1440 break; 1441 case SIOCADDMULTI: 1442 case SIOCDELMULTI: 1443 if (ifp->if_flags & IFF_RUNNING) 1444 bfe_set_rx_mode(sc); 1445 break; 1446 case SIOCGIFMEDIA: 1447 case SIOCSIFMEDIA: 1448 mii = device_get_softc(sc->bfe_miibus); 1449 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1450 command); 1451 break; 1452 default: 1453 error = ether_ioctl(ifp, command, data); 1454 break; 1455 } 1456 1457 splx(s); 1458 return error; 1459 } 1460 1461 static void 1462 bfe_watchdog(struct ifnet *ifp) 1463 { 1464 struct bfe_softc *sc; 1465 int s; 1466 1467 sc = ifp->if_softc; 1468 1469 s = splimp(); 1470 1471 if_printf(ifp, "watchdog timeout -- resetting\n"); 1472 1473 ifp->if_flags &= ~IFF_RUNNING; 1474 bfe_init(sc); 1475 1476 ifp->if_oerrors++; 1477 1478 splx(s); 1479 } 1480 1481 static void 1482 bfe_tick(void *xsc) 1483 { 1484 struct bfe_softc *sc = xsc; 1485 struct mii_data *mii; 1486 int s; 1487 1488 if (sc == NULL) 1489 return; 1490 1491 s = splimp(); 1492 1493 mii = device_get_softc(sc->bfe_miibus); 1494 1495 bfe_stats_update(sc); 1496 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1497 1498 if (sc->bfe_link) { 1499 splx(s); 1500 return; 1501 } 1502 1503 mii_tick(mii); 1504 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1505 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1506 sc->bfe_link++; 1507 1508 if (!sc->bfe_link) 1509 sc->bfe_link++; 1510 1511 splx(s); 1512 } 1513 1514 /* 1515 * Stop the adapter and free any mbufs allocated to the 1516 * RX and TX lists. 1517 */ 1518 static void 1519 bfe_stop(struct bfe_softc *sc) 1520 { 1521 struct ifnet *ifp; 1522 int s; 1523 1524 s = splimp(); 1525 1526 callout_stop(&sc->bfe_stat_timer); 1527 1528 ifp = &sc->arpcom.ac_if; 1529 1530 bfe_chip_halt(sc); 1531 bfe_tx_ring_free(sc); 1532 bfe_rx_ring_free(sc); 1533 1534 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1535 1536 splx(s); 1537 } 1538