1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.27 2005/11/28 17:13:41 dillon Exp $ 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/thread2.h> 44 45 #include <net/if.h> 46 #include <net/ifq_var.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <net/bpf.h> 53 54 #include <net/if_types.h> 55 #include <net/vlan/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 61 #include <machine/bus_memio.h> 62 #include <machine/bus.h> 63 #include <machine/resource.h> 64 #include <sys/bus.h> 65 #include <sys/rman.h> 66 67 #include <bus/pci/pcireg.h> 68 #include <bus/pci/pcivar.h> 69 #include <bus/pci/pcidevs.h> 70 71 #include <dev/netif/mii_layer/mii.h> 72 #include <dev/netif/mii_layer/miivar.h> 73 74 #include "if_bfereg.h" 75 76 MODULE_DEPEND(bfe, pci, 1, 1, 1); 77 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 78 79 /* "controller miibus0" required. See GENERIC if you get errors here. */ 80 #include "miibus_if.h" 81 82 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 83 84 static struct bfe_type bfe_devs[] = { 85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 86 "Broadcom BCM4401 Fast Ethernet" }, 87 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0, 88 "Broadcom BCM4401-B0 Fast Ethernet" }, 89 { 0, 0, NULL } 90 }; 91 92 static int bfe_probe(device_t); 93 static int bfe_attach(device_t); 94 static int bfe_detach(device_t); 95 static void bfe_intr(void *); 96 static void bfe_start(struct ifnet *); 97 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 98 static void bfe_init(void *); 99 static void bfe_stop(struct bfe_softc *); 100 static void bfe_watchdog(struct ifnet *); 101 static void bfe_shutdown(device_t); 102 static void bfe_tick(void *); 103 static void bfe_txeof(struct bfe_softc *); 104 static void bfe_rxeof(struct bfe_softc *); 105 static void bfe_set_rx_mode(struct bfe_softc *); 106 static int bfe_list_rx_init(struct bfe_softc *); 107 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*); 108 static void bfe_rx_ring_free(struct bfe_softc *); 109 110 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 111 static int bfe_ifmedia_upd(struct ifnet *); 112 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 113 static int bfe_miibus_readreg(device_t, int, int); 114 static int bfe_miibus_writereg(device_t, int, int, int); 115 static void bfe_miibus_statchg(device_t); 116 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 117 u_long, const int); 118 static void bfe_get_config(struct bfe_softc *sc); 119 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 120 static void bfe_stats_update(struct bfe_softc *); 121 static void bfe_clear_stats (struct bfe_softc *); 122 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 123 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 124 static int bfe_resetphy(struct bfe_softc *); 125 static int bfe_setupphy(struct bfe_softc *); 126 static void bfe_chip_reset(struct bfe_softc *); 127 static void bfe_chip_halt(struct bfe_softc *); 128 static void bfe_core_reset(struct bfe_softc *); 129 static void bfe_core_disable(struct bfe_softc *); 130 static int bfe_dma_alloc(device_t); 131 static void bfe_dma_free(struct bfe_softc *); 132 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int); 133 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int); 134 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 135 136 static device_method_t bfe_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_probe, bfe_probe), 139 DEVMETHOD(device_attach, bfe_attach), 140 DEVMETHOD(device_detach, bfe_detach), 141 DEVMETHOD(device_shutdown, bfe_shutdown), 142 143 /* bus interface */ 144 DEVMETHOD(bus_print_child, bus_generic_print_child), 145 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 146 147 /* MII interface */ 148 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 149 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 150 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 151 152 { 0, 0 } 153 }; 154 155 static driver_t bfe_driver = { 156 "bfe", 157 bfe_methods, 158 sizeof(struct bfe_softc) 159 }; 160 161 static devclass_t bfe_devclass; 162 163 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 164 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 165 166 /* 167 * Probe for a Broadcom 4401 chip. 168 */ 169 static int 170 bfe_probe(device_t dev) 171 { 172 struct bfe_type *t; 173 uint16_t vendor, product; 174 175 vendor = pci_get_vendor(dev); 176 product = pci_get_device(dev); 177 178 for (t = bfe_devs; t->bfe_name != NULL; t++) { 179 if (vendor == t->bfe_vid && product == t->bfe_did) { 180 device_set_desc(dev, t->bfe_name); 181 return(0); 182 } 183 } 184 185 return(ENXIO); 186 } 187 188 static int 189 bfe_dma_alloc(device_t dev) 190 { 191 struct bfe_softc *sc; 192 int error, i, tx_pos, rx_pos; 193 194 sc = device_get_softc(dev); 195 196 /* parent tag */ 197 error = bus_dma_tag_create(NULL, /* parent */ 198 PAGE_SIZE, 0, /* alignment, boundary */ 199 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 200 BUS_SPACE_MAXADDR, /* highaddr */ 201 NULL, NULL, /* filter, filterarg */ 202 MAXBSIZE, /* maxsize */ 203 BUS_SPACE_UNRESTRICTED, /* num of segments */ 204 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 205 BUS_DMA_ALLOCNOW, /* flags */ 206 &sc->bfe_parent_tag); 207 208 if (error) { 209 device_printf(dev, "could not allocate parent dma tag\n"); 210 return(error); 211 } 212 213 /* tag for TX ring */ 214 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE, 215 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 216 NULL, NULL, BFE_TX_LIST_SIZE, 1, 217 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag); 218 219 if (error) { 220 device_printf(dev, "could not allocate dma tag for TX list\n"); 221 return(error); 222 } 223 224 /* tag for RX ring */ 225 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE, 226 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 227 NULL, NULL, BFE_RX_LIST_SIZE, 1, 228 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag); 229 230 if (error) { 231 device_printf(dev, "could not allocate dma tag for RX list\n"); 232 return(error); 233 } 234 235 /* tag for mbufs */ 236 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0, 237 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 238 1, BUS_SPACE_MAXSIZE_32BIT, 0, 239 &sc->bfe_tag); 240 241 if (error) { 242 device_printf(dev, "could not allocate dma tag for mbufs\n"); 243 return(error); 244 } 245 246 rx_pos = tx_pos = 0; 247 248 /* pre allocate dmamaps for RX list */ 249 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 250 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map); 251 if (error) { 252 rx_pos = i; 253 device_printf(dev, "cannot create DMA map for RX\n"); 254 goto ring_fail; 255 } 256 } 257 rx_pos = BFE_RX_LIST_CNT; 258 259 /* pre allocate dmamaps for TX list */ 260 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 261 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map); 262 if (error) { 263 tx_pos = i; 264 device_printf(dev, "cannot create DMA map for TX\n"); 265 goto ring_fail; 266 } 267 } 268 269 /* Alloc dma for rx ring */ 270 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 271 BUS_DMA_WAITOK, &sc->bfe_rx_map); 272 273 if (error) { 274 device_printf(dev, "cannot allocate DMA mem for RX\n"); 275 return(error); 276 } 277 278 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 279 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 280 sc->bfe_rx_list, sizeof(struct bfe_desc), 281 bfe_dma_map, &sc->bfe_rx_dma, 0); 282 283 if (error) { 284 device_printf(dev, "cannot load DMA map for RX\n"); 285 return(error); 286 } 287 288 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 289 290 /* Alloc dma for tx ring */ 291 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 292 BUS_DMA_WAITOK, &sc->bfe_tx_map); 293 if (error) { 294 device_printf(dev, "cannot allocate DMA mem for TX\n"); 295 return(error); 296 } 297 298 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 299 sc->bfe_tx_list, sizeof(struct bfe_desc), 300 bfe_dma_map, &sc->bfe_tx_dma, 0); 301 if (error) { 302 device_printf(dev, "cannot load DMA map for TX\n"); 303 return(error); 304 } 305 306 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 307 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 308 309 return(0); 310 311 ring_fail: 312 for (i = 0; i < rx_pos; ++i) 313 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_rx_ring[i].bfe_map); 314 for (i = 0; i < tx_pos; ++i) 315 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map); 316 317 bus_dma_tag_destroy(sc->bfe_tag); 318 sc->bfe_tag = NULL; 319 return error; 320 } 321 322 static int 323 bfe_attach(device_t dev) 324 { 325 struct ifnet *ifp; 326 struct bfe_softc *sc; 327 int error = 0, rid; 328 329 sc = device_get_softc(dev); 330 331 sc->bfe_dev = dev; 332 callout_init(&sc->bfe_stat_timer); 333 334 /* 335 * Handle power management nonsense. 336 */ 337 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 338 uint32_t membase, irq; 339 340 /* Save important PCI config data. */ 341 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 342 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 343 344 /* Reset the power state. */ 345 device_printf(dev, "chip is in D%d power mode" 346 " -- setting to D0\n", pci_get_powerstate(dev)); 347 348 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 349 350 /* Restore PCI config data. */ 351 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 352 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 353 } 354 355 /* 356 * Map control/status registers. 357 */ 358 pci_enable_busmaster(dev); 359 360 rid = BFE_PCI_MEMLO; 361 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 362 RF_ACTIVE); 363 if (sc->bfe_res == NULL) { 364 device_printf(dev, "couldn't map memory\n"); 365 return ENXIO; 366 } 367 368 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 369 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 370 371 /* Allocate interrupt */ 372 rid = 0; 373 374 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 375 RF_SHAREABLE | RF_ACTIVE); 376 if (sc->bfe_irq == NULL) { 377 device_printf(dev, "couldn't map interrupt\n"); 378 error = ENXIO; 379 goto fail; 380 } 381 382 error = bfe_dma_alloc(dev); 383 if (error != 0) { 384 device_printf(dev, "failed to allocate DMA resources\n"); 385 goto fail; 386 } 387 388 /* Set up ifnet structure */ 389 ifp = &sc->arpcom.ac_if; 390 ifp->if_softc = sc; 391 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 392 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 393 ifp->if_ioctl = bfe_ioctl; 394 ifp->if_start = bfe_start; 395 ifp->if_watchdog = bfe_watchdog; 396 ifp->if_init = bfe_init; 397 ifp->if_mtu = ETHERMTU; 398 ifp->if_baudrate = 100000000; 399 ifp->if_capabilities |= IFCAP_VLAN_MTU; 400 ifp->if_capenable |= IFCAP_VLAN_MTU; 401 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 402 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN); 403 ifq_set_ready(&ifp->if_snd); 404 405 bfe_get_config(sc); 406 407 /* Reset the chip and turn on the PHY */ 408 bfe_chip_reset(sc); 409 410 if (mii_phy_probe(dev, &sc->bfe_miibus, 411 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 412 device_printf(dev, "MII without any PHY!\n"); 413 error = ENXIO; 414 goto fail; 415 } 416 417 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 418 419 /* 420 * Hook interrupt last to avoid having to lock softc 421 */ 422 error = bus_setup_intr(dev, sc->bfe_irq, INTR_NETSAFE, 423 bfe_intr, sc, &sc->bfe_intrhand, 424 sc->arpcom.ac_if.if_serializer); 425 426 if (error) { 427 ether_ifdetach(ifp); 428 device_printf(dev, "couldn't set up irq\n"); 429 goto fail; 430 } 431 return 0; 432 fail: 433 bfe_detach(dev); 434 return(error); 435 } 436 437 static int 438 bfe_detach(device_t dev) 439 { 440 struct bfe_softc *sc = device_get_softc(dev); 441 struct ifnet *ifp = &sc->arpcom.ac_if; 442 443 lwkt_serialize_enter(ifp->if_serializer); 444 445 if (device_is_attached(dev)) { 446 bfe_stop(sc); 447 ether_ifdetach(ifp); 448 bfe_chip_reset(sc); 449 } 450 if (sc->bfe_miibus != NULL) 451 device_delete_child(dev, sc->bfe_miibus); 452 bus_generic_detach(dev); 453 454 if (sc->bfe_intrhand != NULL) 455 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 456 457 if (sc->bfe_irq != NULL) 458 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 459 460 if (sc->bfe_res != NULL) { 461 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO, 462 sc->bfe_res); 463 } 464 bfe_dma_free(sc); 465 lwkt_serialize_exit(ifp->if_serializer); 466 return(0); 467 } 468 469 /* 470 * Stop all chip I/O so that the kernel's probe routines don't 471 * get confused by errant DMAs when rebooting. 472 */ 473 static void 474 bfe_shutdown(device_t dev) 475 { 476 struct bfe_softc *sc = device_get_softc(dev); 477 struct ifnet *ifp = &sc->arpcom.ac_if; 478 479 lwkt_serialize_enter(ifp->if_serializer); 480 bfe_stop(sc); 481 lwkt_serialize_exit(ifp->if_serializer); 482 } 483 484 static int 485 bfe_miibus_readreg(device_t dev, int phy, int reg) 486 { 487 struct bfe_softc *sc; 488 uint32_t ret; 489 490 sc = device_get_softc(dev); 491 if (phy != sc->bfe_phyaddr) 492 return(0); 493 bfe_readphy(sc, reg, &ret); 494 495 return(ret); 496 } 497 498 static int 499 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 500 { 501 struct bfe_softc *sc; 502 503 sc = device_get_softc(dev); 504 if (phy != sc->bfe_phyaddr) 505 return(0); 506 bfe_writephy(sc, reg, val); 507 508 return(0); 509 } 510 511 static void 512 bfe_miibus_statchg(device_t dev) 513 { 514 return; 515 } 516 517 static void 518 bfe_tx_ring_free(struct bfe_softc *sc) 519 { 520 int i; 521 522 for (i = 0; i < BFE_TX_LIST_CNT; i++) 523 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 524 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 525 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 526 bus_dmamap_unload(sc->bfe_tag, 527 sc->bfe_tx_ring[i].bfe_map); 528 } 529 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 530 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 531 } 532 533 static void 534 bfe_rx_ring_free(struct bfe_softc *sc) 535 { 536 int i; 537 538 for (i = 0; i < BFE_RX_LIST_CNT; i++) 539 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 540 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 541 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 542 bus_dmamap_unload(sc->bfe_tag, 543 sc->bfe_rx_ring[i].bfe_map); 544 } 545 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 546 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 547 } 548 549 550 static int 551 bfe_list_rx_init(struct bfe_softc *sc) 552 { 553 int i; 554 555 for (i = 0; i < BFE_RX_LIST_CNT; i++) 556 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 557 return(ENOBUFS); 558 559 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 560 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 561 562 sc->bfe_rx_cons = 0; 563 564 return(0); 565 } 566 567 static int 568 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 569 { 570 struct bfe_rxheader *rx_header; 571 struct bfe_desc *d; 572 struct bfe_data *r; 573 uint32_t ctrl; 574 575 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 576 return(EINVAL); 577 578 if (m == NULL) { 579 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 580 if (m == NULL) 581 return(ENOBUFS); 582 m->m_len = m->m_pkthdr.len = MCLBYTES; 583 } 584 else 585 m->m_data = m->m_ext.ext_buf; 586 587 rx_header = mtod(m, struct bfe_rxheader *); 588 rx_header->len = 0; 589 rx_header->flags = 0; 590 591 /* Map the mbuf into DMA */ 592 sc->bfe_rx_cnt = c; 593 d = &sc->bfe_rx_list[c]; 594 r = &sc->bfe_rx_ring[c]; 595 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 596 MCLBYTES, bfe_dma_map_desc, d, 0); 597 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 598 599 ctrl = ETHER_MAX_LEN + 32; 600 601 if(c == BFE_RX_LIST_CNT - 1) 602 ctrl |= BFE_DESC_EOT; 603 604 d->bfe_ctrl = ctrl; 605 r->bfe_mbuf = m; 606 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 607 return(0); 608 } 609 610 static void 611 bfe_get_config(struct bfe_softc *sc) 612 { 613 uint8_t eeprom[128]; 614 615 bfe_read_eeprom(sc, eeprom); 616 617 sc->arpcom.ac_enaddr[0] = eeprom[79]; 618 sc->arpcom.ac_enaddr[1] = eeprom[78]; 619 sc->arpcom.ac_enaddr[2] = eeprom[81]; 620 sc->arpcom.ac_enaddr[3] = eeprom[80]; 621 sc->arpcom.ac_enaddr[4] = eeprom[83]; 622 sc->arpcom.ac_enaddr[5] = eeprom[82]; 623 624 sc->bfe_phyaddr = eeprom[90] & 0x1f; 625 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 626 627 sc->bfe_core_unit = 0; 628 sc->bfe_dma_offset = BFE_PCI_DMA; 629 } 630 631 static void 632 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 633 { 634 uint32_t bar_orig, pci_rev, val; 635 636 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 637 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 638 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 639 640 val = CSR_READ_4(sc, BFE_SBINTVEC); 641 val |= cores; 642 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 643 644 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 645 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 646 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 647 648 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 649 } 650 651 static void 652 bfe_clear_stats(struct bfe_softc *sc) 653 { 654 u_long reg; 655 656 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 657 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 658 CSR_READ_4(sc, reg); 659 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 660 CSR_READ_4(sc, reg); 661 } 662 663 static int 664 bfe_resetphy(struct bfe_softc *sc) 665 { 666 uint32_t val; 667 668 bfe_writephy(sc, 0, BMCR_RESET); 669 DELAY(100); 670 bfe_readphy(sc, 0, &val); 671 if (val & BMCR_RESET) { 672 if_printf(&sc->arpcom.ac_if, 673 "PHY Reset would not complete.\n"); 674 return(ENXIO); 675 } 676 return(0); 677 } 678 679 static void 680 bfe_chip_halt(struct bfe_softc *sc) 681 { 682 /* disable interrupts - not that it actually does..*/ 683 CSR_WRITE_4(sc, BFE_IMASK, 0); 684 CSR_READ_4(sc, BFE_IMASK); 685 686 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 687 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 688 689 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 690 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 691 DELAY(10); 692 } 693 694 static void 695 bfe_chip_reset(struct bfe_softc *sc) 696 { 697 uint32_t val; 698 699 /* Set the interrupt vector for the enet core */ 700 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 701 702 /* is core up? */ 703 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 704 if (val == BFE_CLOCK) { 705 /* It is, so shut it down */ 706 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 707 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 708 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 709 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 710 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 711 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 712 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 713 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 714 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 715 } 716 717 bfe_core_reset(sc); 718 bfe_clear_stats(sc); 719 720 /* 721 * We want the phy registers to be accessible even when 722 * the driver is "downed" so initialize MDC preamble, frequency, 723 * and whether internal or external phy here. 724 */ 725 726 /* 4402 has 62.5Mhz SB clock and internal phy */ 727 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 728 729 /* Internal or external PHY? */ 730 val = CSR_READ_4(sc, BFE_DEVCTRL); 731 if (!(val & BFE_IPP)) 732 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 733 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 734 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 735 DELAY(100); 736 } 737 738 /* Enable CRC32 generation and set proper LED modes */ 739 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 740 741 /* Reset or clear powerdown control bit */ 742 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 743 744 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 745 BFE_LAZY_FC_MASK)); 746 747 /* 748 * We don't want lazy interrupts, so just send them at the end of a 749 * frame, please 750 */ 751 BFE_OR(sc, BFE_RCV_LAZY, 0); 752 753 /* Set max lengths, accounting for VLAN tags */ 754 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 755 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 756 757 /* Set watermark XXX - magic */ 758 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 759 760 /* 761 * Initialise DMA channels - not forgetting dma addresses need to be 762 * added to BFE_PCI_DMA 763 */ 764 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 765 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 766 767 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 768 BFE_RX_CTRL_ENABLE); 769 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 770 771 bfe_resetphy(sc); 772 bfe_setupphy(sc); 773 } 774 775 static void 776 bfe_core_disable(struct bfe_softc *sc) 777 { 778 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 779 return; 780 781 /* 782 * Set reject, wait for it set, then wait for the core to stop being busy 783 * Then set reset and reject and enable the clocks 784 */ 785 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 786 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 787 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 788 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 789 BFE_RESET)); 790 CSR_READ_4(sc, BFE_SBTMSLOW); 791 DELAY(10); 792 /* Leave reset and reject set */ 793 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 794 DELAY(10); 795 } 796 797 static void 798 bfe_core_reset(struct bfe_softc *sc) 799 { 800 uint32_t val; 801 802 /* Disable the core */ 803 bfe_core_disable(sc); 804 805 /* and bring it back up */ 806 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 807 CSR_READ_4(sc, BFE_SBTMSLOW); 808 DELAY(10); 809 810 /* Chip bug, clear SERR, IB and TO if they are set. */ 811 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 812 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 813 val = CSR_READ_4(sc, BFE_SBIMSTATE); 814 if (val & (BFE_IBE | BFE_TO)) 815 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 816 817 /* Clear reset and allow it to move through the core */ 818 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 819 CSR_READ_4(sc, BFE_SBTMSLOW); 820 DELAY(10); 821 822 /* Leave the clock set */ 823 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 824 CSR_READ_4(sc, BFE_SBTMSLOW); 825 DELAY(10); 826 } 827 828 static void 829 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 830 { 831 uint32_t val; 832 833 val = ((uint32_t) data[2]) << 24; 834 val |= ((uint32_t) data[3]) << 16; 835 val |= ((uint32_t) data[4]) << 8; 836 val |= ((uint32_t) data[5]); 837 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 838 val = (BFE_CAM_HI_VALID | 839 (((uint32_t) data[0]) << 8) | 840 (((uint32_t) data[1]))); 841 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 842 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 843 ((uint32_t)index << BFE_CAM_INDEX_SHIFT))); 844 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 845 } 846 847 static void 848 bfe_set_rx_mode(struct bfe_softc *sc) 849 { 850 struct ifnet *ifp = &sc->arpcom.ac_if; 851 struct ifmultiaddr *ifma; 852 uint32_t val; 853 int i = 0; 854 855 val = CSR_READ_4(sc, BFE_RXCONF); 856 857 if (ifp->if_flags & IFF_PROMISC) 858 val |= BFE_RXCONF_PROMISC; 859 else 860 val &= ~BFE_RXCONF_PROMISC; 861 862 if (ifp->if_flags & IFF_BROADCAST) 863 val &= ~BFE_RXCONF_DBCAST; 864 else 865 val |= BFE_RXCONF_DBCAST; 866 867 868 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 869 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 870 871 if (ifp->if_flags & IFF_ALLMULTI) { 872 val |= BFE_RXCONF_ALLMULTI; 873 } else { 874 val &= ~BFE_RXCONF_ALLMULTI; 875 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 876 if (ifma->ifma_addr->sa_family != AF_LINK) 877 continue; 878 bfe_cam_write(sc, 879 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 880 } 881 } 882 883 CSR_WRITE_4(sc, BFE_RXCONF, val); 884 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 885 } 886 887 static void 888 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 889 { 890 uint32_t *ptr; 891 892 ptr = arg; 893 *ptr = segs->ds_addr; 894 } 895 896 static void 897 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 898 { 899 struct bfe_desc *d; 900 901 d = arg; 902 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 903 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 904 } 905 906 static void 907 bfe_dma_free(struct bfe_softc *sc) 908 { 909 if (sc->bfe_tx_tag != NULL) { 910 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 911 if (sc->bfe_tx_list != NULL) { 912 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 913 sc->bfe_tx_map); 914 sc->bfe_tx_list = NULL; 915 } 916 bus_dma_tag_destroy(sc->bfe_tx_tag); 917 sc->bfe_tx_tag = NULL; 918 } 919 920 if (sc->bfe_rx_tag != NULL) { 921 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 922 if (sc->bfe_rx_list != NULL) { 923 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 924 sc->bfe_rx_map); 925 sc->bfe_rx_list = NULL; 926 } 927 bus_dma_tag_destroy(sc->bfe_rx_tag); 928 sc->bfe_rx_tag = NULL; 929 } 930 931 if (sc->bfe_tag != NULL) { 932 int i; 933 934 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 935 bus_dmamap_destroy(sc->bfe_tag, 936 sc->bfe_tx_ring[i].bfe_map); 937 } 938 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 939 bus_dmamap_destroy(sc->bfe_tag, 940 sc->bfe_rx_ring[i].bfe_map); 941 } 942 943 bus_dma_tag_destroy(sc->bfe_tag); 944 sc->bfe_tag = NULL; 945 } 946 947 if (sc->bfe_parent_tag != NULL) { 948 bus_dma_tag_destroy(sc->bfe_parent_tag); 949 sc->bfe_parent_tag = NULL; 950 } 951 } 952 953 static void 954 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 955 { 956 long i; 957 uint16_t *ptr = (uint16_t *)data; 958 959 for (i = 0; i < 128; i += 2) 960 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 961 } 962 963 static int 964 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 965 u_long timeout, const int clear) 966 { 967 u_long i; 968 969 for (i = 0; i < timeout; i++) { 970 uint32_t val = CSR_READ_4(sc, reg); 971 972 if (clear && !(val & bit)) 973 break; 974 if (!clear && (val & bit)) 975 break; 976 DELAY(10); 977 } 978 if (i == timeout) { 979 if_printf(&sc->arpcom.ac_if, 980 "BUG! Timeout waiting for bit %08x of register " 981 "%x to %s.\n", bit, reg, 982 (clear ? "clear" : "set")); 983 return -1; 984 } 985 return 0; 986 } 987 988 static int 989 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 990 { 991 int err; 992 993 /* Clear MII ISR */ 994 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 995 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 996 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 997 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 998 (reg << BFE_MDIO_RA_SHIFT) | 999 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1000 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1001 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1002 return(err); 1003 } 1004 1005 static int 1006 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 1007 { 1008 int status; 1009 1010 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1011 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1012 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1013 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1014 (reg << BFE_MDIO_RA_SHIFT) | 1015 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1016 (val & BFE_MDIO_DATA_DATA))); 1017 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1018 1019 return status; 1020 } 1021 1022 /* 1023 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1024 * twice 1025 */ 1026 static int 1027 bfe_setupphy(struct bfe_softc *sc) 1028 { 1029 uint32_t val; 1030 1031 /* Enable activity LED */ 1032 bfe_readphy(sc, 26, &val); 1033 bfe_writephy(sc, 26, val & 0x7fff); 1034 bfe_readphy(sc, 26, &val); 1035 1036 /* Enable traffic meter LED mode */ 1037 bfe_readphy(sc, 27, &val); 1038 bfe_writephy(sc, 27, val | (1 << 6)); 1039 1040 return(0); 1041 } 1042 1043 static void 1044 bfe_stats_update(struct bfe_softc *sc) 1045 { 1046 u_long reg; 1047 uint32_t *val; 1048 1049 val = &sc->bfe_hwstats.tx_good_octets; 1050 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1051 *val++ += CSR_READ_4(sc, reg); 1052 val = &sc->bfe_hwstats.rx_good_octets; 1053 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1054 *val++ += CSR_READ_4(sc, reg); 1055 } 1056 1057 static void 1058 bfe_txeof(struct bfe_softc *sc) 1059 { 1060 struct ifnet *ifp = &sc->arpcom.ac_if; 1061 uint32_t i, chipidx; 1062 1063 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1064 chipidx /= sizeof(struct bfe_desc); 1065 1066 i = sc->bfe_tx_cons; 1067 /* Go through the mbufs and free those that have been transmitted */ 1068 while (i != chipidx) { 1069 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1070 if (r->bfe_mbuf != NULL) { 1071 ifp->if_opackets++; 1072 m_freem(r->bfe_mbuf); 1073 r->bfe_mbuf = NULL; 1074 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1075 } 1076 sc->bfe_tx_cnt--; 1077 BFE_INC(i, BFE_TX_LIST_CNT); 1078 } 1079 1080 if (i != sc->bfe_tx_cons) { 1081 /* we freed up some mbufs */ 1082 sc->bfe_tx_cons = i; 1083 ifp->if_flags &= ~IFF_OACTIVE; 1084 } 1085 if (sc->bfe_tx_cnt == 0) 1086 ifp->if_timer = 0; 1087 else 1088 ifp->if_timer = 5; 1089 } 1090 1091 /* Pass a received packet up the stack */ 1092 static void 1093 bfe_rxeof(struct bfe_softc *sc) 1094 { 1095 struct ifnet *ifp = &sc->arpcom.ac_if; 1096 struct mbuf *m; 1097 struct bfe_rxheader *rxheader; 1098 struct bfe_data *r; 1099 uint32_t cons, status, current, len, flags; 1100 1101 cons = sc->bfe_rx_cons; 1102 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1103 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1104 1105 while (current != cons) { 1106 r = &sc->bfe_rx_ring[cons]; 1107 m = r->bfe_mbuf; 1108 rxheader = mtod(m, struct bfe_rxheader*); 1109 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1110 len = rxheader->len; 1111 r->bfe_mbuf = NULL; 1112 1113 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1114 flags = rxheader->flags; 1115 1116 len -= ETHER_CRC_LEN; 1117 1118 /* flag an error and try again */ 1119 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1120 ifp->if_ierrors++; 1121 if (flags & BFE_RX_FLAG_SERR) 1122 ifp->if_collisions++; 1123 bfe_list_newbuf(sc, cons, m); 1124 BFE_INC(cons, BFE_RX_LIST_CNT); 1125 continue; 1126 } 1127 1128 /* Go past the rx header */ 1129 if (bfe_list_newbuf(sc, cons, NULL) != 0) { 1130 bfe_list_newbuf(sc, cons, m); 1131 BFE_INC(cons, BFE_RX_LIST_CNT); 1132 ifp->if_ierrors++; 1133 continue; 1134 } 1135 1136 m_adj(m, BFE_RX_OFFSET); 1137 m->m_len = m->m_pkthdr.len = len; 1138 1139 ifp->if_ipackets++; 1140 m->m_pkthdr.rcvif = ifp; 1141 1142 ifp->if_input(ifp, m); 1143 BFE_INC(cons, BFE_RX_LIST_CNT); 1144 } 1145 sc->bfe_rx_cons = cons; 1146 } 1147 1148 static void 1149 bfe_intr(void *xsc) 1150 { 1151 struct bfe_softc *sc = xsc; 1152 struct ifnet *ifp = &sc->arpcom.ac_if; 1153 uint32_t istat, imask, flag; 1154 1155 istat = CSR_READ_4(sc, BFE_ISTAT); 1156 imask = CSR_READ_4(sc, BFE_IMASK); 1157 1158 /* 1159 * Defer unsolicited interrupts - This is necessary because setting the 1160 * chips interrupt mask register to 0 doesn't actually stop the 1161 * interrupts 1162 */ 1163 istat &= imask; 1164 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1165 CSR_READ_4(sc, BFE_ISTAT); 1166 1167 /* not expecting this interrupt, disregard it */ 1168 if (istat == 0) { 1169 return; 1170 } 1171 1172 if (istat & BFE_ISTAT_ERRORS) { 1173 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1174 if (flag & BFE_STAT_EMASK) 1175 ifp->if_oerrors++; 1176 1177 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1178 if (flag & BFE_RX_FLAG_ERRORS) 1179 ifp->if_ierrors++; 1180 1181 ifp->if_flags &= ~IFF_RUNNING; 1182 bfe_init(sc); 1183 } 1184 1185 /* A packet was received */ 1186 if (istat & BFE_ISTAT_RX) 1187 bfe_rxeof(sc); 1188 1189 /* A packet was sent */ 1190 if (istat & BFE_ISTAT_TX) 1191 bfe_txeof(sc); 1192 1193 /* We have packets pending, fire them out */ 1194 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1195 bfe_start(ifp); 1196 } 1197 1198 static int 1199 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1200 { 1201 struct bfe_desc *d = NULL; 1202 struct bfe_data *r = NULL; 1203 struct mbuf *m; 1204 uint32_t frag, cur, cnt = 0; 1205 1206 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1207 return(ENOBUFS); 1208 1209 /* 1210 * Start packing the mbufs in this chain into 1211 * the fragment pointers. Stop when we run out 1212 * of fragments or hit the end of the mbuf chain. 1213 */ 1214 m = m_head; 1215 cur = frag = *txidx; 1216 cnt = 0; 1217 1218 for (m = m_head; m != NULL; m = m->m_next) { 1219 if (m->m_len != 0) { 1220 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1221 return(ENOBUFS); 1222 1223 d = &sc->bfe_tx_list[cur]; 1224 r = &sc->bfe_tx_ring[cur]; 1225 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1226 /* always intterupt on completion */ 1227 d->bfe_ctrl |= BFE_DESC_IOC; 1228 if (cnt == 0) 1229 /* Set start of frame */ 1230 d->bfe_ctrl |= BFE_DESC_SOF; 1231 if (cur == BFE_TX_LIST_CNT - 1) 1232 /* 1233 * Tell the chip to wrap to the start of the 1234 *descriptor list 1235 */ 1236 d->bfe_ctrl |= BFE_DESC_EOT; 1237 1238 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*), 1239 m->m_len, bfe_dma_map_desc, d, 0); 1240 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1241 BUS_DMASYNC_PREREAD); 1242 1243 frag = cur; 1244 BFE_INC(cur, BFE_TX_LIST_CNT); 1245 cnt++; 1246 } 1247 } 1248 1249 if (m != NULL) 1250 return(ENOBUFS); 1251 1252 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1253 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1254 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1255 1256 *txidx = cur; 1257 sc->bfe_tx_cnt += cnt; 1258 return(0); 1259 } 1260 1261 /* 1262 * Set up to transmit a packet 1263 */ 1264 static void 1265 bfe_start(struct ifnet *ifp) 1266 { 1267 struct bfe_softc *sc = ifp->if_softc; 1268 struct mbuf *m_head = NULL; 1269 int idx, need_trans; 1270 1271 /* 1272 * Not much point trying to send if the link is down 1273 * or we have nothing to send. 1274 */ 1275 if (!sc->bfe_link) 1276 return; 1277 1278 if (ifp->if_flags & IFF_OACTIVE) 1279 return; 1280 1281 idx = sc->bfe_tx_prod; 1282 1283 need_trans = 0; 1284 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1285 m_head = ifq_poll(&ifp->if_snd); 1286 if (m_head == NULL) 1287 break; 1288 1289 /* 1290 * Pack the data into the tx ring. If we don't have 1291 * enough room, let the chip drain the ring. 1292 */ 1293 if (bfe_encap(sc, m_head, &idx)) { 1294 ifp->if_flags |= IFF_OACTIVE; 1295 break; 1296 } 1297 ifq_dequeue(&ifp->if_snd, m_head); 1298 need_trans = 1; 1299 1300 /* 1301 * If there's a BPF listener, bounce a copy of this frame 1302 * to him. 1303 */ 1304 BPF_MTAP(ifp, m_head); 1305 } 1306 1307 if (!need_trans) 1308 return; 1309 1310 sc->bfe_tx_prod = idx; 1311 /* Transmit - twice due to apparent hardware bug */ 1312 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1313 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1314 1315 /* 1316 * Set a timeout in case the chip goes out to lunch. 1317 */ 1318 ifp->if_timer = 5; 1319 } 1320 1321 static void 1322 bfe_init(void *xsc) 1323 { 1324 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1325 struct ifnet *ifp = &sc->arpcom.ac_if; 1326 1327 if (ifp->if_flags & IFF_RUNNING) 1328 return; 1329 1330 bfe_stop(sc); 1331 bfe_chip_reset(sc); 1332 1333 if (bfe_list_rx_init(sc) == ENOBUFS) { 1334 if_printf(ifp, "bfe_init failed. " 1335 " Not enough memory for list buffers\n"); 1336 bfe_stop(sc); 1337 return; 1338 } 1339 1340 bfe_set_rx_mode(sc); 1341 1342 /* Enable the chip and core */ 1343 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1344 /* Enable interrupts */ 1345 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1346 1347 bfe_ifmedia_upd(ifp); 1348 ifp->if_flags |= IFF_RUNNING; 1349 ifp->if_flags &= ~IFF_OACTIVE; 1350 1351 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1352 } 1353 1354 /* 1355 * Set media options. 1356 */ 1357 static int 1358 bfe_ifmedia_upd(struct ifnet *ifp) 1359 { 1360 struct bfe_softc *sc = ifp->if_softc; 1361 struct mii_data *mii; 1362 1363 mii = device_get_softc(sc->bfe_miibus); 1364 sc->bfe_link = 0; 1365 if (mii->mii_instance) { 1366 struct mii_softc *miisc; 1367 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1368 miisc = LIST_NEXT(miisc, mii_list)) 1369 mii_phy_reset(miisc); 1370 } 1371 mii_mediachg(mii); 1372 1373 return(0); 1374 } 1375 1376 /* 1377 * Report current media status. 1378 */ 1379 static void 1380 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1381 { 1382 struct bfe_softc *sc = ifp->if_softc; 1383 struct mii_data *mii; 1384 1385 mii = device_get_softc(sc->bfe_miibus); 1386 mii_pollstat(mii); 1387 ifmr->ifm_active = mii->mii_media_active; 1388 ifmr->ifm_status = mii->mii_media_status; 1389 } 1390 1391 static int 1392 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1393 { 1394 struct bfe_softc *sc = ifp->if_softc; 1395 struct ifreq *ifr = (struct ifreq *) data; 1396 struct mii_data *mii; 1397 int error = 0; 1398 1399 switch (command) { 1400 case SIOCSIFFLAGS: 1401 if (ifp->if_flags & IFF_UP) 1402 if (ifp->if_flags & IFF_RUNNING) 1403 bfe_set_rx_mode(sc); 1404 else 1405 bfe_init(sc); 1406 else if (ifp->if_flags & IFF_RUNNING) 1407 bfe_stop(sc); 1408 break; 1409 case SIOCADDMULTI: 1410 case SIOCDELMULTI: 1411 if (ifp->if_flags & IFF_RUNNING) 1412 bfe_set_rx_mode(sc); 1413 break; 1414 case SIOCGIFMEDIA: 1415 case SIOCSIFMEDIA: 1416 mii = device_get_softc(sc->bfe_miibus); 1417 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1418 command); 1419 break; 1420 default: 1421 error = ether_ioctl(ifp, command, data); 1422 break; 1423 } 1424 return error; 1425 } 1426 1427 static void 1428 bfe_watchdog(struct ifnet *ifp) 1429 { 1430 struct bfe_softc *sc = ifp->if_softc; 1431 1432 if_printf(ifp, "watchdog timeout -- resetting\n"); 1433 1434 ifp->if_flags &= ~IFF_RUNNING; 1435 bfe_init(sc); 1436 1437 ifp->if_oerrors++; 1438 } 1439 1440 static void 1441 bfe_tick(void *xsc) 1442 { 1443 struct bfe_softc *sc = xsc; 1444 struct mii_data *mii; 1445 struct ifnet *ifp = &sc->arpcom.ac_if; 1446 1447 mii = device_get_softc(sc->bfe_miibus); 1448 1449 lwkt_serialize_enter(ifp->if_serializer); 1450 1451 bfe_stats_update(sc); 1452 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1453 1454 if (sc->bfe_link == NULL) { 1455 mii_tick(mii); 1456 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1457 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1458 sc->bfe_link++; 1459 } 1460 if (!sc->bfe_link) 1461 sc->bfe_link++; 1462 } 1463 lwkt_serialize_exit(ifp->if_serializer); 1464 } 1465 1466 /* 1467 * Stop the adapter and free any mbufs allocated to the 1468 * RX and TX lists. 1469 */ 1470 static void 1471 bfe_stop(struct bfe_softc *sc) 1472 { 1473 struct ifnet *ifp = &sc->arpcom.ac_if; 1474 1475 callout_stop(&sc->bfe_stat_timer); 1476 1477 bfe_chip_halt(sc); 1478 bfe_tx_ring_free(sc); 1479 bfe_rx_ring_free(sc); 1480 1481 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1482 } 1483 1484