1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/sockio.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 #include <sys/interrupt.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/queue.h> 43 #include <sys/bus.h> 44 #include <sys/rman.h> 45 #include <sys/thread2.h> 46 47 #include <net/if.h> 48 #include <net/ifq_var.h> 49 #include <net/if_arp.h> 50 #include <net/ethernet.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 54 #include <net/bpf.h> 55 56 #include <net/if_types.h> 57 #include <net/vlan/if_vlan_var.h> 58 59 #include <netinet/in_systm.h> 60 #include <netinet/in.h> 61 #include <netinet/ip.h> 62 63 #include <bus/pci/pcireg.h> 64 #include <bus/pci/pcivar.h> 65 #include <bus/pci/pcidevs.h> 66 67 #include <dev/netif/mii_layer/mii.h> 68 #include <dev/netif/mii_layer/miivar.h> 69 70 #include <dev/netif/bfe/if_bfereg.h> 71 72 MODULE_DEPEND(bfe, pci, 1, 1, 1); 73 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 74 75 /* "controller miibus0" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 79 80 static struct bfe_type bfe_devs[] = { 81 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 82 "Broadcom BCM4401 Fast Ethernet" }, 83 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0, 84 "Broadcom BCM4401-B0 Fast Ethernet" }, 85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402, 86 "Broadcom BCM4402 Fast Ethernet" }, 87 { 0, 0, NULL } 88 }; 89 90 static int bfe_probe(device_t); 91 static int bfe_attach(device_t); 92 static int bfe_detach(device_t); 93 static void bfe_intr(void *); 94 static void bfe_start(struct ifnet *, struct ifaltq_subque *); 95 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 96 static void bfe_init(void *); 97 static void bfe_stop(struct bfe_softc *); 98 static void bfe_watchdog(struct ifnet *); 99 static void bfe_shutdown(device_t); 100 static void bfe_tick(void *); 101 static void bfe_txeof(struct bfe_softc *); 102 static void bfe_rxeof(struct bfe_softc *); 103 static void bfe_set_rx_mode(struct bfe_softc *); 104 static int bfe_list_rx_init(struct bfe_softc *); 105 static int bfe_newbuf(struct bfe_softc *, int, int); 106 static void bfe_setup_rxdesc(struct bfe_softc *, int); 107 static void bfe_rx_ring_free(struct bfe_softc *); 108 109 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 110 static int bfe_ifmedia_upd(struct ifnet *); 111 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 112 static int bfe_miibus_readreg(device_t, int, int); 113 static int bfe_miibus_writereg(device_t, int, int, int); 114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 115 u_long, const int); 116 static void bfe_get_config(struct bfe_softc *sc); 117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 118 static void bfe_stats_update(struct bfe_softc *); 119 static void bfe_clear_stats (struct bfe_softc *); 120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 122 static int bfe_resetphy(struct bfe_softc *); 123 static int bfe_setupphy(struct bfe_softc *); 124 static void bfe_chip_reset(struct bfe_softc *); 125 static void bfe_chip_halt(struct bfe_softc *); 126 static void bfe_core_reset(struct bfe_softc *); 127 static void bfe_core_disable(struct bfe_softc *); 128 static int bfe_dma_alloc(device_t); 129 static void bfe_dma_free(struct bfe_softc *); 130 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 131 132 static device_method_t bfe_methods[] = { 133 /* Device interface */ 134 DEVMETHOD(device_probe, bfe_probe), 135 DEVMETHOD(device_attach, bfe_attach), 136 DEVMETHOD(device_detach, bfe_detach), 137 DEVMETHOD(device_shutdown, bfe_shutdown), 138 139 /* bus interface */ 140 DEVMETHOD(bus_print_child, bus_generic_print_child), 141 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 142 143 /* MII interface */ 144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 146 147 { 0, 0 } 148 }; 149 150 static driver_t bfe_driver = { 151 "bfe", 152 bfe_methods, 153 sizeof(struct bfe_softc) 154 }; 155 156 static devclass_t bfe_devclass; 157 158 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, NULL, NULL); 159 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, NULL, NULL); 160 161 /* 162 * Probe for a Broadcom 4401 chip. 163 */ 164 static int 165 bfe_probe(device_t dev) 166 { 167 struct bfe_type *t; 168 uint16_t vendor, product; 169 170 vendor = pci_get_vendor(dev); 171 product = pci_get_device(dev); 172 173 for (t = bfe_devs; t->bfe_name != NULL; t++) { 174 if (vendor == t->bfe_vid && product == t->bfe_did) { 175 device_set_desc(dev, t->bfe_name); 176 return(0); 177 } 178 } 179 180 return(ENXIO); 181 } 182 183 static int 184 bfe_dma_alloc(device_t dev) 185 { 186 struct bfe_softc *sc = device_get_softc(dev); 187 bus_dmamem_t dmem; 188 int error, i, tx_pos = 0, rx_pos = 0; 189 190 /* 191 * Parent tag. Apparently the chip cannot handle any DMA address 192 * greater than BFE_BUS_SPACE_MAXADDR (1GB). 193 */ 194 error = bus_dma_tag_create(NULL, /* parent */ 195 1, 0, /* alignment, boundary */ 196 BFE_BUS_SPACE_MAXADDR, /* lowaddr */ 197 BUS_SPACE_MAXADDR, /* highaddr */ 198 NULL, NULL, /* filter, filterarg */ 199 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 200 0, /* num of segments */ 201 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 202 0, /* flags */ 203 &sc->bfe_parent_tag); 204 if (error) { 205 device_printf(dev, "could not allocate parent dma tag\n"); 206 return(error); 207 } 208 209 /* Allocate TX ring */ 210 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0, 211 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 212 BFE_TX_LIST_SIZE, 213 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 214 if (error) { 215 device_printf(dev, "could not allocate TX list\n"); 216 return(error); 217 } 218 sc->bfe_tx_tag = dmem.dmem_tag; 219 sc->bfe_tx_map = dmem.dmem_map; 220 sc->bfe_tx_list = dmem.dmem_addr; 221 sc->bfe_tx_dma = dmem.dmem_busaddr; 222 223 /* Allocate RX ring */ 224 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0, 225 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 226 BFE_RX_LIST_SIZE, 227 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 228 if (error) { 229 device_printf(dev, "could not allocate RX list\n"); 230 return(error); 231 } 232 sc->bfe_rx_tag = dmem.dmem_tag; 233 sc->bfe_rx_map = dmem.dmem_map; 234 sc->bfe_rx_list = dmem.dmem_addr; 235 sc->bfe_rx_dma = dmem.dmem_busaddr; 236 237 /* Tag for RX mbufs */ 238 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0, 239 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 240 NULL, NULL, 241 MCLBYTES, 1, MCLBYTES, 242 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 243 &sc->bfe_rxbuf_tag); 244 if (error) { 245 device_printf(dev, "could not allocate dma tag for RX mbufs\n"); 246 return(error); 247 } 248 249 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK, 250 &sc->bfe_rx_tmpmap); 251 if (error) { 252 device_printf(dev, "could not create RX mbuf tmp map\n"); 253 bus_dma_tag_destroy(sc->bfe_rxbuf_tag); 254 sc->bfe_rxbuf_tag = NULL; 255 return error; 256 } 257 258 /* Allocate dma maps for RX list */ 259 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 260 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK, 261 &sc->bfe_rx_ring[i].bfe_map); 262 if (error) { 263 rx_pos = i; 264 device_printf(dev, "cannot create DMA map for RX\n"); 265 goto ring_fail; 266 } 267 } 268 rx_pos = BFE_RX_LIST_CNT; 269 270 /* Tag for TX mbufs */ 271 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0, 272 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 273 NULL, NULL, 274 MCLBYTES, BFE_MAXSEGS, MCLBYTES, 275 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 276 &sc->bfe_txbuf_tag); 277 if (error) { 278 device_printf(dev, "could not allocate dma tag for TX mbufs\n"); 279 return(error); 280 } 281 282 /* Allocate dmamaps for TX list */ 283 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 284 error = bus_dmamap_create(sc->bfe_txbuf_tag, BUS_DMA_WAITOK, 285 &sc->bfe_tx_ring[i].bfe_map); 286 if (error) { 287 tx_pos = i; 288 device_printf(dev, "cannot create DMA map for TX\n"); 289 goto ring_fail; 290 } 291 } 292 293 return(0); 294 295 ring_fail: 296 if (sc->bfe_rxbuf_tag != NULL) { 297 for (i = 0; i < rx_pos; ++i) { 298 bus_dmamap_destroy(sc->bfe_rxbuf_tag, 299 sc->bfe_rx_ring[i].bfe_map); 300 } 301 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap); 302 bus_dma_tag_destroy(sc->bfe_rxbuf_tag); 303 sc->bfe_rxbuf_tag = NULL; 304 } 305 306 if (sc->bfe_txbuf_tag != NULL) { 307 for (i = 0; i < tx_pos; ++i) { 308 bus_dmamap_destroy(sc->bfe_txbuf_tag, 309 sc->bfe_tx_ring[i].bfe_map); 310 } 311 bus_dma_tag_destroy(sc->bfe_txbuf_tag); 312 sc->bfe_txbuf_tag = NULL; 313 } 314 return error; 315 } 316 317 static int 318 bfe_attach(device_t dev) 319 { 320 struct ifnet *ifp; 321 struct bfe_softc *sc; 322 int error = 0, rid; 323 324 sc = device_get_softc(dev); 325 326 sc->bfe_dev = dev; 327 callout_init(&sc->bfe_stat_timer); 328 329 #ifndef BURN_BRIDGES 330 /* 331 * Handle power management nonsense. 332 */ 333 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 334 uint32_t membase, irq; 335 336 /* Save important PCI config data. */ 337 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 338 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 339 340 /* Reset the power state. */ 341 device_printf(dev, "chip is in D%d power mode" 342 " -- setting to D0\n", pci_get_powerstate(dev)); 343 344 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 345 346 /* Restore PCI config data. */ 347 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 348 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 349 } 350 #endif /* !BURN_BRIDGE */ 351 352 /* 353 * Map control/status registers. 354 */ 355 pci_enable_busmaster(dev); 356 357 rid = BFE_PCI_MEMLO; 358 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 359 RF_ACTIVE); 360 if (sc->bfe_res == NULL) { 361 device_printf(dev, "couldn't map memory\n"); 362 return ENXIO; 363 } 364 365 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 366 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 367 368 /* Allocate interrupt */ 369 rid = 0; 370 371 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 372 RF_SHAREABLE | RF_ACTIVE); 373 if (sc->bfe_irq == NULL) { 374 device_printf(dev, "couldn't map interrupt\n"); 375 error = ENXIO; 376 goto fail; 377 } 378 379 error = bfe_dma_alloc(dev); 380 if (error != 0) { 381 device_printf(dev, "failed to allocate DMA resources\n"); 382 goto fail; 383 } 384 385 /* Set up ifnet structure */ 386 ifp = &sc->arpcom.ac_if; 387 ifp->if_softc = sc; 388 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 389 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 390 ifp->if_ioctl = bfe_ioctl; 391 ifp->if_start = bfe_start; 392 ifp->if_watchdog = bfe_watchdog; 393 ifp->if_init = bfe_init; 394 ifp->if_mtu = ETHERMTU; 395 ifp->if_baudrate = 100000000; 396 ifp->if_capabilities |= IFCAP_VLAN_MTU; 397 ifp->if_capenable |= IFCAP_VLAN_MTU; 398 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 399 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN); 400 ifq_set_ready(&ifp->if_snd); 401 402 bfe_get_config(sc); 403 404 /* Reset the chip and turn on the PHY */ 405 bfe_chip_reset(sc); 406 407 if (mii_phy_probe(dev, &sc->bfe_miibus, 408 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 409 device_printf(dev, "MII without any PHY!\n"); 410 error = ENXIO; 411 goto fail; 412 } 413 414 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 415 416 /* 417 * Hook interrupt last to avoid having to lock softc 418 */ 419 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE, 420 bfe_intr, sc, &sc->bfe_intrhand, 421 sc->arpcom.ac_if.if_serializer); 422 423 if (error) { 424 ether_ifdetach(ifp); 425 device_printf(dev, "couldn't set up irq\n"); 426 goto fail; 427 } 428 429 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bfe_irq)); 430 return 0; 431 fail: 432 bfe_detach(dev); 433 return(error); 434 } 435 436 static int 437 bfe_detach(device_t dev) 438 { 439 struct bfe_softc *sc = device_get_softc(dev); 440 struct ifnet *ifp = &sc->arpcom.ac_if; 441 442 if (device_is_attached(dev)) { 443 lwkt_serialize_enter(ifp->if_serializer); 444 bfe_stop(sc); 445 bfe_chip_reset(sc); 446 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 447 lwkt_serialize_exit(ifp->if_serializer); 448 449 ether_ifdetach(ifp); 450 } 451 if (sc->bfe_miibus != NULL) 452 device_delete_child(dev, sc->bfe_miibus); 453 bus_generic_detach(dev); 454 455 if (sc->bfe_irq != NULL) 456 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 457 458 if (sc->bfe_res != NULL) { 459 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO, 460 sc->bfe_res); 461 } 462 bfe_dma_free(sc); 463 464 return(0); 465 } 466 467 /* 468 * Stop all chip I/O so that the kernel's probe routines don't 469 * get confused by errant DMAs when rebooting. 470 */ 471 static void 472 bfe_shutdown(device_t dev) 473 { 474 struct bfe_softc *sc = device_get_softc(dev); 475 struct ifnet *ifp = &sc->arpcom.ac_if; 476 477 lwkt_serialize_enter(ifp->if_serializer); 478 bfe_stop(sc); 479 lwkt_serialize_exit(ifp->if_serializer); 480 } 481 482 static int 483 bfe_miibus_readreg(device_t dev, int phy, int reg) 484 { 485 struct bfe_softc *sc; 486 uint32_t ret; 487 488 sc = device_get_softc(dev); 489 if (phy != sc->bfe_phyaddr) 490 return(0); 491 bfe_readphy(sc, reg, &ret); 492 493 return(ret); 494 } 495 496 static int 497 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 498 { 499 struct bfe_softc *sc; 500 501 sc = device_get_softc(dev); 502 if (phy != sc->bfe_phyaddr) 503 return(0); 504 bfe_writephy(sc, reg, val); 505 506 return(0); 507 } 508 509 static void 510 bfe_tx_ring_free(struct bfe_softc *sc) 511 { 512 int i; 513 514 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 515 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 516 bus_dmamap_unload(sc->bfe_txbuf_tag, 517 sc->bfe_tx_ring[i].bfe_map); 518 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 519 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 520 } 521 } 522 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 523 } 524 525 static void 526 bfe_rx_ring_free(struct bfe_softc *sc) 527 { 528 int i; 529 530 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 531 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 532 bus_dmamap_unload(sc->bfe_rxbuf_tag, 533 sc->bfe_rx_ring[i].bfe_map); 534 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 535 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 536 } 537 } 538 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 539 } 540 541 static int 542 bfe_list_rx_init(struct bfe_softc *sc) 543 { 544 int i, error; 545 546 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 547 error = bfe_newbuf(sc, i, 1); 548 if (error) 549 return(error); 550 } 551 552 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 553 554 sc->bfe_rx_cons = 0; 555 556 return(0); 557 } 558 559 static int 560 bfe_newbuf(struct bfe_softc *sc, int c, int init) 561 { 562 struct bfe_data *r; 563 bus_dmamap_t map; 564 bus_dma_segment_t seg; 565 struct mbuf *m; 566 int error, nsegs; 567 568 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 569 if (m == NULL) 570 return ENOBUFS; 571 m->m_len = m->m_pkthdr.len = MCLBYTES; 572 573 error = bus_dmamap_load_mbuf_segment(sc->bfe_rxbuf_tag, 574 sc->bfe_rx_tmpmap, m, 575 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 576 if (error) { 577 m_freem(m); 578 if (init) 579 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 580 return error; 581 } 582 583 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT); 584 r = &sc->bfe_rx_ring[c]; 585 586 if (r->bfe_mbuf != NULL) 587 bus_dmamap_unload(sc->bfe_rxbuf_tag, r->bfe_map); 588 589 map = r->bfe_map; 590 r->bfe_map = sc->bfe_rx_tmpmap; 591 sc->bfe_rx_tmpmap = map; 592 593 r->bfe_mbuf = m; 594 r->bfe_paddr = seg.ds_addr; 595 596 bfe_setup_rxdesc(sc, c); 597 return 0; 598 } 599 600 static void 601 bfe_setup_rxdesc(struct bfe_softc *sc, int c) 602 { 603 struct bfe_rxheader *rx_header; 604 struct mbuf *m; 605 struct bfe_desc *d; 606 struct bfe_data *r; 607 uint32_t ctrl; 608 609 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT); 610 r = &sc->bfe_rx_ring[c]; 611 d = &sc->bfe_rx_list[c]; 612 613 KKASSERT(r->bfe_mbuf != NULL && r->bfe_paddr != 0); 614 615 m = r->bfe_mbuf; 616 rx_header = mtod(m, struct bfe_rxheader *); 617 rx_header->len = 0; 618 rx_header->flags = 0; 619 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 620 621 ctrl = ETHER_MAX_LEN + 32; 622 if (c == BFE_RX_LIST_CNT - 1) 623 ctrl |= BFE_DESC_EOT; 624 625 d->bfe_addr = r->bfe_paddr + BFE_PCI_DMA; 626 d->bfe_ctrl = ctrl; 627 } 628 629 static void 630 bfe_get_config(struct bfe_softc *sc) 631 { 632 uint8_t eeprom[128]; 633 634 bfe_read_eeprom(sc, eeprom); 635 636 sc->arpcom.ac_enaddr[0] = eeprom[79]; 637 sc->arpcom.ac_enaddr[1] = eeprom[78]; 638 sc->arpcom.ac_enaddr[2] = eeprom[81]; 639 sc->arpcom.ac_enaddr[3] = eeprom[80]; 640 sc->arpcom.ac_enaddr[4] = eeprom[83]; 641 sc->arpcom.ac_enaddr[5] = eeprom[82]; 642 643 sc->bfe_phyaddr = eeprom[90] & 0x1f; 644 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 645 646 sc->bfe_core_unit = 0; 647 sc->bfe_dma_offset = BFE_PCI_DMA; 648 } 649 650 static void 651 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 652 { 653 uint32_t bar_orig, pci_rev, val; 654 655 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 656 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 657 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 658 659 val = CSR_READ_4(sc, BFE_SBINTVEC); 660 val |= cores; 661 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 662 663 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 664 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 665 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 666 667 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 668 } 669 670 static void 671 bfe_clear_stats(struct bfe_softc *sc) 672 { 673 u_long reg; 674 675 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 676 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 677 CSR_READ_4(sc, reg); 678 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 679 CSR_READ_4(sc, reg); 680 } 681 682 static int 683 bfe_resetphy(struct bfe_softc *sc) 684 { 685 uint32_t val; 686 687 bfe_writephy(sc, 0, BMCR_RESET); 688 DELAY(100); 689 bfe_readphy(sc, 0, &val); 690 if (val & BMCR_RESET) { 691 if_printf(&sc->arpcom.ac_if, 692 "PHY Reset would not complete.\n"); 693 return(ENXIO); 694 } 695 return(0); 696 } 697 698 static void 699 bfe_chip_halt(struct bfe_softc *sc) 700 { 701 /* disable interrupts - not that it actually does..*/ 702 CSR_WRITE_4(sc, BFE_IMASK, 0); 703 CSR_READ_4(sc, BFE_IMASK); 704 705 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 706 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 707 708 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 709 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 710 DELAY(10); 711 } 712 713 static void 714 bfe_chip_reset(struct bfe_softc *sc) 715 { 716 uint32_t val; 717 718 /* Set the interrupt vector for the enet core */ 719 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 720 721 /* is core up? */ 722 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 723 if (val == BFE_CLOCK) { 724 /* It is, so shut it down */ 725 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 726 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 727 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 728 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 729 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 730 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 731 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 732 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 733 sc->bfe_rx_cons = 0; 734 } 735 736 bfe_core_reset(sc); 737 bfe_clear_stats(sc); 738 739 /* 740 * We want the phy registers to be accessible even when 741 * the driver is "downed" so initialize MDC preamble, frequency, 742 * and whether internal or external phy here. 743 */ 744 745 /* 4402 has 62.5Mhz SB clock and internal phy */ 746 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 747 748 /* Internal or external PHY? */ 749 val = CSR_READ_4(sc, BFE_DEVCTRL); 750 if (!(val & BFE_IPP)) 751 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 752 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 753 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 754 DELAY(100); 755 } 756 757 /* Enable CRC32 generation and set proper LED modes */ 758 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 759 760 /* Reset or clear powerdown control bit */ 761 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 762 763 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 764 BFE_LAZY_FC_MASK)); 765 766 /* 767 * We don't want lazy interrupts, so just send them at the end of a 768 * frame, please 769 */ 770 BFE_OR(sc, BFE_RCV_LAZY, 0); 771 772 /* Set max lengths, accounting for VLAN tags */ 773 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 774 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 775 776 /* Set watermark XXX - magic */ 777 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 778 779 /* 780 * Initialise DMA channels - not forgetting dma addresses need to be 781 * added to BFE_PCI_DMA 782 */ 783 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 784 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 785 786 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 787 BFE_RX_CTRL_ENABLE); 788 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 789 790 bfe_resetphy(sc); 791 bfe_setupphy(sc); 792 } 793 794 static void 795 bfe_core_disable(struct bfe_softc *sc) 796 { 797 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 798 return; 799 800 /* 801 * Set reject, wait for it set, then wait for the core to stop being busy 802 * Then set reset and reject and enable the clocks 803 */ 804 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 805 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 806 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 807 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 808 BFE_RESET)); 809 CSR_READ_4(sc, BFE_SBTMSLOW); 810 DELAY(10); 811 /* Leave reset and reject set */ 812 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 813 DELAY(10); 814 } 815 816 static void 817 bfe_core_reset(struct bfe_softc *sc) 818 { 819 uint32_t val; 820 821 /* Disable the core */ 822 bfe_core_disable(sc); 823 824 /* and bring it back up */ 825 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 826 CSR_READ_4(sc, BFE_SBTMSLOW); 827 DELAY(10); 828 829 /* Chip bug, clear SERR, IB and TO if they are set. */ 830 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 831 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 832 val = CSR_READ_4(sc, BFE_SBIMSTATE); 833 if (val & (BFE_IBE | BFE_TO)) 834 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 835 836 /* Clear reset and allow it to move through the core */ 837 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 838 CSR_READ_4(sc, BFE_SBTMSLOW); 839 DELAY(10); 840 841 /* Leave the clock set */ 842 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 843 CSR_READ_4(sc, BFE_SBTMSLOW); 844 DELAY(10); 845 } 846 847 static void 848 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 849 { 850 uint32_t val; 851 852 val = ((uint32_t) data[2]) << 24; 853 val |= ((uint32_t) data[3]) << 16; 854 val |= ((uint32_t) data[4]) << 8; 855 val |= ((uint32_t) data[5]); 856 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 857 val = (BFE_CAM_HI_VALID | 858 (((uint32_t) data[0]) << 8) | 859 (((uint32_t) data[1]))); 860 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 861 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 862 ((uint32_t)index << BFE_CAM_INDEX_SHIFT))); 863 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 864 } 865 866 static void 867 bfe_set_rx_mode(struct bfe_softc *sc) 868 { 869 struct ifnet *ifp = &sc->arpcom.ac_if; 870 struct ifmultiaddr *ifma; 871 uint32_t val; 872 int i = 0; 873 874 val = CSR_READ_4(sc, BFE_RXCONF); 875 876 if (ifp->if_flags & IFF_PROMISC) 877 val |= BFE_RXCONF_PROMISC; 878 else 879 val &= ~BFE_RXCONF_PROMISC; 880 881 if (ifp->if_flags & IFF_BROADCAST) 882 val &= ~BFE_RXCONF_DBCAST; 883 else 884 val |= BFE_RXCONF_DBCAST; 885 886 887 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 888 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 889 890 if (ifp->if_flags & IFF_ALLMULTI) { 891 val |= BFE_RXCONF_ALLMULTI; 892 } else { 893 val &= ~BFE_RXCONF_ALLMULTI; 894 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 895 if (ifma->ifma_addr->sa_family != AF_LINK) 896 continue; 897 bfe_cam_write(sc, 898 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 899 } 900 } 901 902 CSR_WRITE_4(sc, BFE_RXCONF, val); 903 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 904 } 905 906 static void 907 bfe_dma_free(struct bfe_softc *sc) 908 { 909 int i; 910 911 if (sc->bfe_tx_tag != NULL) { 912 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 913 if (sc->bfe_tx_list != NULL) { 914 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 915 sc->bfe_tx_map); 916 sc->bfe_tx_list = NULL; 917 } 918 bus_dma_tag_destroy(sc->bfe_tx_tag); 919 sc->bfe_tx_tag = NULL; 920 } 921 922 if (sc->bfe_rx_tag != NULL) { 923 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 924 if (sc->bfe_rx_list != NULL) { 925 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 926 sc->bfe_rx_map); 927 sc->bfe_rx_list = NULL; 928 } 929 bus_dma_tag_destroy(sc->bfe_rx_tag); 930 sc->bfe_rx_tag = NULL; 931 } 932 933 if (sc->bfe_txbuf_tag != NULL) { 934 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 935 bus_dmamap_destroy(sc->bfe_txbuf_tag, 936 sc->bfe_tx_ring[i].bfe_map); 937 } 938 bus_dma_tag_destroy(sc->bfe_txbuf_tag); 939 sc->bfe_txbuf_tag = NULL; 940 } 941 942 if (sc->bfe_rxbuf_tag != NULL) { 943 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 944 bus_dmamap_destroy(sc->bfe_rxbuf_tag, 945 sc->bfe_rx_ring[i].bfe_map); 946 } 947 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap); 948 bus_dma_tag_destroy(sc->bfe_rxbuf_tag); 949 sc->bfe_rxbuf_tag = NULL; 950 } 951 952 if (sc->bfe_parent_tag != NULL) { 953 bus_dma_tag_destroy(sc->bfe_parent_tag); 954 sc->bfe_parent_tag = NULL; 955 } 956 } 957 958 static void 959 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 960 { 961 long i; 962 uint16_t *ptr = (uint16_t *)data; 963 964 for (i = 0; i < 128; i += 2) 965 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 966 } 967 968 static int 969 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 970 u_long timeout, const int clear) 971 { 972 u_long i; 973 974 for (i = 0; i < timeout; i++) { 975 uint32_t val = CSR_READ_4(sc, reg); 976 977 if (clear && !(val & bit)) 978 break; 979 if (!clear && (val & bit)) 980 break; 981 DELAY(10); 982 } 983 if (i == timeout) { 984 if_printf(&sc->arpcom.ac_if, 985 "BUG! Timeout waiting for bit %08x of register " 986 "%x to %s.\n", bit, reg, 987 (clear ? "clear" : "set")); 988 return -1; 989 } 990 return 0; 991 } 992 993 static int 994 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 995 { 996 int err; 997 998 /* Clear MII ISR */ 999 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1000 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1001 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1002 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1003 (reg << BFE_MDIO_RA_SHIFT) | 1004 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1005 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1006 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1007 return(err); 1008 } 1009 1010 static int 1011 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 1012 { 1013 int status; 1014 1015 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1016 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1017 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1018 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1019 (reg << BFE_MDIO_RA_SHIFT) | 1020 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1021 (val & BFE_MDIO_DATA_DATA))); 1022 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1023 1024 return status; 1025 } 1026 1027 /* 1028 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1029 * twice 1030 */ 1031 static int 1032 bfe_setupphy(struct bfe_softc *sc) 1033 { 1034 uint32_t val; 1035 1036 /* Enable activity LED */ 1037 bfe_readphy(sc, 26, &val); 1038 bfe_writephy(sc, 26, val & 0x7fff); 1039 bfe_readphy(sc, 26, &val); 1040 1041 /* Enable traffic meter LED mode */ 1042 bfe_readphy(sc, 27, &val); 1043 bfe_writephy(sc, 27, val | (1 << 6)); 1044 1045 return(0); 1046 } 1047 1048 static void 1049 bfe_stats_update(struct bfe_softc *sc) 1050 { 1051 u_long reg; 1052 uint32_t *val; 1053 1054 val = &sc->bfe_hwstats.tx_good_octets; 1055 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1056 *val++ += CSR_READ_4(sc, reg); 1057 val = &sc->bfe_hwstats.rx_good_octets; 1058 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1059 *val++ += CSR_READ_4(sc, reg); 1060 } 1061 1062 static void 1063 bfe_txeof(struct bfe_softc *sc) 1064 { 1065 struct ifnet *ifp = &sc->arpcom.ac_if; 1066 uint32_t i, chipidx; 1067 1068 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1069 chipidx /= sizeof(struct bfe_desc); 1070 1071 i = sc->bfe_tx_cons; 1072 1073 /* Go through the mbufs and free those that have been transmitted */ 1074 while (i != chipidx) { 1075 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1076 1077 if (r->bfe_mbuf != NULL) { 1078 ifp->if_opackets++; 1079 bus_dmamap_unload(sc->bfe_txbuf_tag, r->bfe_map); 1080 m_freem(r->bfe_mbuf); 1081 r->bfe_mbuf = NULL; 1082 } 1083 1084 KKASSERT(sc->bfe_tx_cnt > 0); 1085 sc->bfe_tx_cnt--; 1086 BFE_INC(i, BFE_TX_LIST_CNT); 1087 } 1088 1089 if (i != sc->bfe_tx_cons) { 1090 sc->bfe_tx_cons = i; 1091 1092 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT) 1093 ifq_clr_oactive(&ifp->if_snd); 1094 } 1095 if (sc->bfe_tx_cnt == 0) 1096 ifp->if_timer = 0; 1097 } 1098 1099 /* Pass a received packet up the stack */ 1100 static void 1101 bfe_rxeof(struct bfe_softc *sc) 1102 { 1103 struct ifnet *ifp = &sc->arpcom.ac_if; 1104 struct mbuf *m; 1105 struct bfe_rxheader *rxheader; 1106 struct bfe_data *r; 1107 uint32_t cons, status, current, len, flags; 1108 1109 cons = sc->bfe_rx_cons; 1110 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1111 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1112 1113 while (current != cons) { 1114 r = &sc->bfe_rx_ring[cons]; 1115 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, 1116 BUS_DMASYNC_POSTREAD); 1117 1118 KKASSERT(r->bfe_mbuf != NULL); 1119 m = r->bfe_mbuf; 1120 rxheader = mtod(m, struct bfe_rxheader*); 1121 len = rxheader->len - ETHER_CRC_LEN; 1122 flags = rxheader->flags; 1123 1124 /* flag an error and try again */ 1125 if (len > ETHER_MAX_LEN + 32 || (flags & BFE_RX_FLAG_ERRORS)) { 1126 ifp->if_ierrors++; 1127 if (flags & BFE_RX_FLAG_SERR) 1128 ifp->if_collisions++; 1129 1130 bfe_setup_rxdesc(sc, cons); 1131 BFE_INC(cons, BFE_RX_LIST_CNT); 1132 continue; 1133 } 1134 1135 /* Go past the rx header */ 1136 if (bfe_newbuf(sc, cons, 0) != 0) { 1137 bfe_setup_rxdesc(sc, cons); 1138 ifp->if_ierrors++; 1139 BFE_INC(cons, BFE_RX_LIST_CNT); 1140 continue; 1141 } 1142 1143 m_adj(m, BFE_RX_OFFSET); 1144 m->m_len = m->m_pkthdr.len = len; 1145 1146 ifp->if_ipackets++; 1147 m->m_pkthdr.rcvif = ifp; 1148 1149 ifp->if_input(ifp, m); 1150 BFE_INC(cons, BFE_RX_LIST_CNT); 1151 } 1152 1153 sc->bfe_rx_cons = cons; 1154 } 1155 1156 static void 1157 bfe_intr(void *xsc) 1158 { 1159 struct bfe_softc *sc = xsc; 1160 struct ifnet *ifp = &sc->arpcom.ac_if; 1161 uint32_t istat, imask, flag; 1162 1163 istat = CSR_READ_4(sc, BFE_ISTAT); 1164 imask = CSR_READ_4(sc, BFE_IMASK); 1165 1166 /* 1167 * Defer unsolicited interrupts - This is necessary because setting the 1168 * chips interrupt mask register to 0 doesn't actually stop the 1169 * interrupts 1170 */ 1171 istat &= imask; 1172 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1173 CSR_READ_4(sc, BFE_ISTAT); 1174 1175 /* not expecting this interrupt, disregard it */ 1176 if (istat == 0) { 1177 return; 1178 } 1179 1180 if (istat & BFE_ISTAT_ERRORS) { 1181 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1182 if (flag & BFE_STAT_EMASK) 1183 ifp->if_oerrors++; 1184 1185 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1186 if (flag & BFE_RX_FLAG_ERRORS) 1187 ifp->if_ierrors++; 1188 1189 ifp->if_flags &= ~IFF_RUNNING; 1190 bfe_init(sc); 1191 } 1192 1193 /* A packet was received */ 1194 if (istat & BFE_ISTAT_RX) 1195 bfe_rxeof(sc); 1196 1197 /* A packet was sent */ 1198 if (istat & BFE_ISTAT_TX) 1199 bfe_txeof(sc); 1200 1201 /* We have packets pending, fire them out */ 1202 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1203 if_devstart(ifp); 1204 } 1205 1206 static int 1207 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1208 { 1209 bus_dma_segment_t segs[BFE_MAXSEGS]; 1210 bus_dmamap_t map; 1211 int i, first_idx, last_idx, cur, error, maxsegs, nsegs; 1212 1213 KKASSERT(sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT); 1214 maxsegs = BFE_TX_LIST_CNT - sc->bfe_tx_cnt - BFE_SPARE_TXDESC; 1215 if (maxsegs > BFE_MAXSEGS) 1216 maxsegs = BFE_MAXSEGS; 1217 1218 first_idx = *txidx; 1219 map = sc->bfe_tx_ring[first_idx].bfe_map; 1220 1221 error = bus_dmamap_load_mbuf_defrag(sc->bfe_txbuf_tag, map, m_head, 1222 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1223 if (error) 1224 goto fail; 1225 bus_dmamap_sync(sc->bfe_txbuf_tag, map, BUS_DMASYNC_PREWRITE); 1226 1227 last_idx = -1; 1228 cur = first_idx; 1229 for (i = 0; i < nsegs; ++i) { 1230 struct bfe_desc *d; 1231 uint32_t ctrl; 1232 1233 ctrl = BFE_DESC_LEN & segs[i].ds_len; 1234 ctrl |= BFE_DESC_IOC; /* always interrupt */ 1235 if (cur == BFE_TX_LIST_CNT - 1) { 1236 /* 1237 * Tell the chip to wrap to the 1238 * start of the descriptor list. 1239 */ 1240 ctrl |= BFE_DESC_EOT; 1241 } 1242 1243 d = &sc->bfe_tx_list[cur]; 1244 d->bfe_addr = segs[i].ds_addr + BFE_PCI_DMA; 1245 d->bfe_ctrl = ctrl; 1246 1247 last_idx = cur; 1248 BFE_INC(cur, BFE_TX_LIST_CNT); 1249 } 1250 KKASSERT(last_idx >= 0); 1251 1252 /* End of the frame */ 1253 sc->bfe_tx_list[last_idx].bfe_ctrl |= BFE_DESC_EOF; 1254 1255 /* 1256 * Set start of the frame on the first fragment, 1257 * _after_ all of the fragments are setup. 1258 */ 1259 sc->bfe_tx_list[first_idx].bfe_ctrl |= BFE_DESC_SOF; 1260 1261 sc->bfe_tx_ring[first_idx].bfe_map = sc->bfe_tx_ring[last_idx].bfe_map; 1262 sc->bfe_tx_ring[last_idx].bfe_map = map; 1263 sc->bfe_tx_ring[last_idx].bfe_mbuf = *m_head; 1264 1265 *txidx = cur; 1266 sc->bfe_tx_cnt += nsegs; 1267 return 0; 1268 fail: 1269 m_freem(*m_head); 1270 *m_head = NULL; 1271 return error; 1272 } 1273 1274 /* 1275 * Set up to transmit a packet 1276 */ 1277 static void 1278 bfe_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1279 { 1280 struct bfe_softc *sc = ifp->if_softc; 1281 struct mbuf *m_head = NULL; 1282 int idx, need_trans; 1283 1284 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1285 ASSERT_SERIALIZED(ifp->if_serializer); 1286 1287 /* 1288 * Not much point trying to send if the link is down 1289 * or we have nothing to send. 1290 */ 1291 if (!sc->bfe_link) { 1292 ifq_purge(&ifp->if_snd); 1293 return; 1294 } 1295 1296 if (ifq_is_oactive(&ifp->if_snd)) 1297 return; 1298 1299 idx = sc->bfe_tx_prod; 1300 1301 need_trans = 0; 1302 while (!ifq_is_empty(&ifp->if_snd)) { 1303 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC >= BFE_TX_LIST_CNT) { 1304 ifq_set_oactive(&ifp->if_snd); 1305 break; 1306 } 1307 1308 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1309 if (m_head == NULL) 1310 break; 1311 1312 /* 1313 * Pack the data into the tx ring. If we don't have 1314 * enough room, let the chip drain the ring. 1315 */ 1316 if (bfe_encap(sc, &m_head, &idx)) { 1317 /* m_head is freed by re_encap(), if we reach here */ 1318 ifp->if_oerrors++; 1319 1320 if (sc->bfe_tx_cnt > 0) { 1321 ifq_set_oactive(&ifp->if_snd); 1322 break; 1323 } else { 1324 /* 1325 * ifq_set_oactive could not be called under 1326 * this situation, since except up/down, 1327 * nothing will call ifq_clr_oactive. 1328 * 1329 * Let's just keep draining the ifq ... 1330 */ 1331 continue; 1332 } 1333 } 1334 need_trans = 1; 1335 1336 /* 1337 * If there's a BPF listener, bounce a copy of this frame 1338 * to him. 1339 */ 1340 BPF_MTAP(ifp, m_head); 1341 } 1342 1343 if (!need_trans) 1344 return; 1345 1346 sc->bfe_tx_prod = idx; 1347 1348 /* Transmit - twice due to apparent hardware bug */ 1349 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1350 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1351 1352 /* 1353 * Set a timeout in case the chip goes out to lunch. 1354 */ 1355 ifp->if_timer = 5; 1356 } 1357 1358 static void 1359 bfe_init(void *xsc) 1360 { 1361 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1362 struct ifnet *ifp = &sc->arpcom.ac_if; 1363 1364 ASSERT_SERIALIZED(ifp->if_serializer); 1365 1366 if (ifp->if_flags & IFF_RUNNING) 1367 return; 1368 1369 bfe_stop(sc); 1370 bfe_chip_reset(sc); 1371 1372 if (bfe_list_rx_init(sc) == ENOBUFS) { 1373 if_printf(ifp, "bfe_init failed. " 1374 " Not enough memory for list buffers\n"); 1375 bfe_stop(sc); 1376 return; 1377 } 1378 1379 bfe_set_rx_mode(sc); 1380 1381 /* Enable the chip and core */ 1382 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1383 /* Enable interrupts */ 1384 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1385 1386 bfe_ifmedia_upd(ifp); 1387 ifp->if_flags |= IFF_RUNNING; 1388 ifq_clr_oactive(&ifp->if_snd); 1389 1390 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1391 } 1392 1393 /* 1394 * Set media options. 1395 */ 1396 static int 1397 bfe_ifmedia_upd(struct ifnet *ifp) 1398 { 1399 struct bfe_softc *sc = ifp->if_softc; 1400 struct mii_data *mii; 1401 1402 ASSERT_SERIALIZED(ifp->if_serializer); 1403 1404 mii = device_get_softc(sc->bfe_miibus); 1405 sc->bfe_link = 0; 1406 if (mii->mii_instance) { 1407 struct mii_softc *miisc; 1408 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1409 miisc = LIST_NEXT(miisc, mii_list)) 1410 mii_phy_reset(miisc); 1411 } 1412 mii_mediachg(mii); 1413 1414 bfe_setupphy(sc); 1415 1416 return(0); 1417 } 1418 1419 /* 1420 * Report current media status. 1421 */ 1422 static void 1423 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1424 { 1425 struct bfe_softc *sc = ifp->if_softc; 1426 struct mii_data *mii; 1427 1428 ASSERT_SERIALIZED(ifp->if_serializer); 1429 1430 mii = device_get_softc(sc->bfe_miibus); 1431 mii_pollstat(mii); 1432 ifmr->ifm_active = mii->mii_media_active; 1433 ifmr->ifm_status = mii->mii_media_status; 1434 } 1435 1436 static int 1437 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1438 { 1439 struct bfe_softc *sc = ifp->if_softc; 1440 struct ifreq *ifr = (struct ifreq *) data; 1441 struct mii_data *mii; 1442 int error = 0; 1443 1444 ASSERT_SERIALIZED(ifp->if_serializer); 1445 1446 switch (command) { 1447 case SIOCSIFFLAGS: 1448 if (ifp->if_flags & IFF_UP) 1449 if (ifp->if_flags & IFF_RUNNING) 1450 bfe_set_rx_mode(sc); 1451 else 1452 bfe_init(sc); 1453 else if (ifp->if_flags & IFF_RUNNING) 1454 bfe_stop(sc); 1455 break; 1456 case SIOCADDMULTI: 1457 case SIOCDELMULTI: 1458 if (ifp->if_flags & IFF_RUNNING) 1459 bfe_set_rx_mode(sc); 1460 break; 1461 case SIOCGIFMEDIA: 1462 case SIOCSIFMEDIA: 1463 mii = device_get_softc(sc->bfe_miibus); 1464 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1465 command); 1466 break; 1467 default: 1468 error = ether_ioctl(ifp, command, data); 1469 break; 1470 } 1471 return error; 1472 } 1473 1474 static void 1475 bfe_watchdog(struct ifnet *ifp) 1476 { 1477 struct bfe_softc *sc = ifp->if_softc; 1478 1479 ASSERT_SERIALIZED(ifp->if_serializer); 1480 1481 if_printf(ifp, "watchdog timeout -- resetting\n"); 1482 1483 ifp->if_flags &= ~IFF_RUNNING; 1484 bfe_init(sc); 1485 1486 ifp->if_oerrors++; 1487 } 1488 1489 static void 1490 bfe_tick(void *xsc) 1491 { 1492 struct bfe_softc *sc = xsc; 1493 struct mii_data *mii; 1494 struct ifnet *ifp = &sc->arpcom.ac_if; 1495 1496 mii = device_get_softc(sc->bfe_miibus); 1497 1498 lwkt_serialize_enter(ifp->if_serializer); 1499 1500 bfe_stats_update(sc); 1501 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1502 1503 if (sc->bfe_link == 0) { 1504 mii_tick(mii); 1505 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1506 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1507 sc->bfe_link++; 1508 } 1509 if (!sc->bfe_link) 1510 sc->bfe_link++; 1511 } 1512 lwkt_serialize_exit(ifp->if_serializer); 1513 } 1514 1515 /* 1516 * Stop the adapter and free any mbufs allocated to the 1517 * RX and TX lists. 1518 */ 1519 static void 1520 bfe_stop(struct bfe_softc *sc) 1521 { 1522 struct ifnet *ifp = &sc->arpcom.ac_if; 1523 1524 ASSERT_SERIALIZED(ifp->if_serializer); 1525 1526 callout_stop(&sc->bfe_stat_timer); 1527 1528 bfe_chip_halt(sc); 1529 bfe_tx_ring_free(sc); 1530 bfe_rx_ring_free(sc); 1531 1532 ifp->if_flags &= ~IFF_RUNNING; 1533 ifq_clr_oactive(&ifp->if_snd); 1534 } 1535