1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v 32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.40 2008/09/17 08:51:29 sephe Exp $ 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/interrupt.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/queue.h> 44 #include <sys/bus.h> 45 #include <sys/rman.h> 46 #include <sys/thread2.h> 47 48 #include <net/if.h> 49 #include <net/ifq_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 55 #include <net/bpf.h> 56 57 #include <net/if_types.h> 58 #include <net/vlan/if_vlan_var.h> 59 60 #include <netinet/in_systm.h> 61 #include <netinet/in.h> 62 #include <netinet/ip.h> 63 64 #include <bus/pci/pcireg.h> 65 #include <bus/pci/pcivar.h> 66 #include <bus/pci/pcidevs.h> 67 68 #include <dev/netif/mii_layer/mii.h> 69 #include <dev/netif/mii_layer/miivar.h> 70 71 #include <dev/netif/bfe/if_bfereg.h> 72 73 MODULE_DEPEND(bfe, pci, 1, 1, 1); 74 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 75 76 /* "controller miibus0" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 80 81 static struct bfe_type bfe_devs[] = { 82 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401, 83 "Broadcom BCM4401 Fast Ethernet" }, 84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0, 85 "Broadcom BCM4401-B0 Fast Ethernet" }, 86 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402, 87 "Broadcom BCM4402 Fast Ethernet" }, 88 { 0, 0, NULL } 89 }; 90 91 static int bfe_probe(device_t); 92 static int bfe_attach(device_t); 93 static int bfe_detach(device_t); 94 static void bfe_intr(void *); 95 static void bfe_start(struct ifnet *); 96 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 97 static void bfe_init(void *); 98 static void bfe_stop(struct bfe_softc *); 99 static void bfe_watchdog(struct ifnet *); 100 static void bfe_shutdown(device_t); 101 static void bfe_tick(void *); 102 static void bfe_txeof(struct bfe_softc *); 103 static void bfe_rxeof(struct bfe_softc *); 104 static void bfe_set_rx_mode(struct bfe_softc *); 105 static int bfe_list_rx_init(struct bfe_softc *); 106 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*); 107 static void bfe_rx_ring_free(struct bfe_softc *); 108 109 static void bfe_pci_setup(struct bfe_softc *, uint32_t); 110 static int bfe_ifmedia_upd(struct ifnet *); 111 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 112 static int bfe_miibus_readreg(device_t, int, int); 113 static int bfe_miibus_writereg(device_t, int, int, int); 114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t, 115 u_long, const int); 116 static void bfe_get_config(struct bfe_softc *sc); 117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *); 118 static void bfe_stats_update(struct bfe_softc *); 119 static void bfe_clear_stats (struct bfe_softc *); 120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*); 121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t); 122 static int bfe_resetphy(struct bfe_softc *); 123 static int bfe_setupphy(struct bfe_softc *); 124 static void bfe_chip_reset(struct bfe_softc *); 125 static void bfe_chip_halt(struct bfe_softc *); 126 static void bfe_core_reset(struct bfe_softc *); 127 static void bfe_core_disable(struct bfe_softc *); 128 static int bfe_dma_alloc(device_t); 129 static void bfe_dma_free(struct bfe_softc *); 130 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int); 131 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int); 132 static void bfe_cam_write(struct bfe_softc *, u_char *, int); 133 134 static device_method_t bfe_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, bfe_probe), 137 DEVMETHOD(device_attach, bfe_attach), 138 DEVMETHOD(device_detach, bfe_detach), 139 DEVMETHOD(device_shutdown, bfe_shutdown), 140 141 /* bus interface */ 142 DEVMETHOD(bus_print_child, bus_generic_print_child), 143 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 144 145 /* MII interface */ 146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 148 149 { 0, 0 } 150 }; 151 152 static driver_t bfe_driver = { 153 "bfe", 154 bfe_methods, 155 sizeof(struct bfe_softc) 156 }; 157 158 static devclass_t bfe_devclass; 159 160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 162 163 /* 164 * Probe for a Broadcom 4401 chip. 165 */ 166 static int 167 bfe_probe(device_t dev) 168 { 169 struct bfe_type *t; 170 uint16_t vendor, product; 171 172 vendor = pci_get_vendor(dev); 173 product = pci_get_device(dev); 174 175 for (t = bfe_devs; t->bfe_name != NULL; t++) { 176 if (vendor == t->bfe_vid && product == t->bfe_did) { 177 device_set_desc(dev, t->bfe_name); 178 return(0); 179 } 180 } 181 182 return(ENXIO); 183 } 184 185 static int 186 bfe_dma_alloc(device_t dev) 187 { 188 struct bfe_softc *sc = device_get_softc(dev); 189 int error, i, tx_pos, rx_pos; 190 191 /* 192 * parent tag. Apparently the chip cannot handle any DMA address 193 * greater than 1GB. 194 */ 195 error = bus_dma_tag_create(NULL, /* parent */ 196 4096, 0, /* alignment, boundary */ 197 0x3FFFFFFF, /* lowaddr */ 198 BUS_SPACE_MAXADDR, /* highaddr */ 199 NULL, NULL, /* filter, filterarg */ 200 MAXBSIZE, /* maxsize */ 201 BUS_SPACE_UNRESTRICTED, /* num of segments */ 202 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 203 0, /* flags */ 204 &sc->bfe_parent_tag); 205 if (error) { 206 device_printf(dev, "could not allocate parent dma tag\n"); 207 return(error); 208 } 209 210 /* tag for TX ring */ 211 error = bus_dma_tag_create(sc->bfe_parent_tag, 4096, 0, 212 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 213 NULL, NULL, 214 BFE_TX_LIST_SIZE, 1, 215 BUS_SPACE_MAXSIZE_32BIT, 216 0, &sc->bfe_tx_tag); 217 if (error) { 218 device_printf(dev, "could not allocate dma tag for TX list\n"); 219 return(error); 220 } 221 222 /* tag for RX ring */ 223 error = bus_dma_tag_create(sc->bfe_parent_tag, 4096, 0, 224 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 225 NULL, NULL, 226 BFE_RX_LIST_SIZE, 1, 227 BUS_SPACE_MAXSIZE_32BIT, 228 0, &sc->bfe_rx_tag); 229 if (error) { 230 device_printf(dev, "could not allocate dma tag for RX list\n"); 231 return(error); 232 } 233 234 /* tag for mbufs */ 235 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0, 236 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 237 NULL, NULL, 238 MCLBYTES, 1, BUS_SPACE_MAXSIZE_32BIT, 239 BUS_DMA_ALLOCNOW, &sc->bfe_tag); 240 if (error) { 241 device_printf(dev, "could not allocate dma tag for mbufs\n"); 242 return(error); 243 } 244 245 rx_pos = tx_pos = 0; 246 247 /* pre allocate dmamaps for RX list */ 248 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 249 error = bus_dmamap_create(sc->bfe_tag, 0, 250 &sc->bfe_rx_ring[i].bfe_map); 251 if (error) { 252 rx_pos = i; 253 device_printf(dev, "cannot create DMA map for RX\n"); 254 goto ring_fail; 255 } 256 } 257 rx_pos = BFE_RX_LIST_CNT; 258 259 /* pre allocate dmamaps for TX list */ 260 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 261 error = bus_dmamap_create(sc->bfe_tag, 0, 262 &sc->bfe_tx_ring[i].bfe_map); 263 if (error) { 264 tx_pos = i; 265 device_printf(dev, "cannot create DMA map for TX\n"); 266 goto ring_fail; 267 } 268 } 269 270 /* Alloc dma for rx ring */ 271 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 272 BUS_DMA_WAITOK | BUS_DMA_ZERO, 273 &sc->bfe_rx_map); 274 if (error) { 275 device_printf(dev, "cannot allocate DMA mem for RX\n"); 276 return(error); 277 } 278 279 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 280 sc->bfe_rx_list, sizeof(struct bfe_desc), 281 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_WAITOK); 282 if (error) { 283 device_printf(dev, "cannot load DMA map for RX\n"); 284 return(error); 285 } 286 287 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 288 289 /* Alloc dma for tx ring */ 290 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 291 BUS_DMA_WAITOK | BUS_DMA_ZERO, 292 &sc->bfe_tx_map); 293 if (error) { 294 device_printf(dev, "cannot allocate DMA mem for TX\n"); 295 return(error); 296 } 297 298 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 299 sc->bfe_tx_list, sizeof(struct bfe_desc), 300 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_WAITOK); 301 if (error) { 302 device_printf(dev, "cannot load DMA map for TX\n"); 303 return(error); 304 } 305 306 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 307 308 return(0); 309 310 ring_fail: 311 for (i = 0; i < rx_pos; ++i) 312 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_rx_ring[i].bfe_map); 313 for (i = 0; i < tx_pos; ++i) 314 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map); 315 316 bus_dma_tag_destroy(sc->bfe_tag); 317 sc->bfe_tag = NULL; 318 return error; 319 } 320 321 static int 322 bfe_attach(device_t dev) 323 { 324 struct ifnet *ifp; 325 struct bfe_softc *sc; 326 int error = 0, rid; 327 328 sc = device_get_softc(dev); 329 330 sc->bfe_dev = dev; 331 callout_init(&sc->bfe_stat_timer); 332 333 #ifndef BURN_BRIDGES 334 /* 335 * Handle power management nonsense. 336 */ 337 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 338 uint32_t membase, irq; 339 340 /* Save important PCI config data. */ 341 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 342 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 343 344 /* Reset the power state. */ 345 device_printf(dev, "chip is in D%d power mode" 346 " -- setting to D0\n", pci_get_powerstate(dev)); 347 348 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 349 350 /* Restore PCI config data. */ 351 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 352 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 353 } 354 #endif /* !BURN_BRIDGE */ 355 356 /* 357 * Map control/status registers. 358 */ 359 pci_enable_busmaster(dev); 360 361 rid = BFE_PCI_MEMLO; 362 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 363 RF_ACTIVE); 364 if (sc->bfe_res == NULL) { 365 device_printf(dev, "couldn't map memory\n"); 366 return ENXIO; 367 } 368 369 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 370 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 371 372 /* Allocate interrupt */ 373 rid = 0; 374 375 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 376 RF_SHAREABLE | RF_ACTIVE); 377 if (sc->bfe_irq == NULL) { 378 device_printf(dev, "couldn't map interrupt\n"); 379 error = ENXIO; 380 goto fail; 381 } 382 383 error = bfe_dma_alloc(dev); 384 if (error != 0) { 385 device_printf(dev, "failed to allocate DMA resources\n"); 386 goto fail; 387 } 388 389 /* Set up ifnet structure */ 390 ifp = &sc->arpcom.ac_if; 391 ifp->if_softc = sc; 392 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 393 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 394 ifp->if_ioctl = bfe_ioctl; 395 ifp->if_start = bfe_start; 396 ifp->if_watchdog = bfe_watchdog; 397 ifp->if_init = bfe_init; 398 ifp->if_mtu = ETHERMTU; 399 ifp->if_baudrate = 100000000; 400 ifp->if_capabilities |= IFCAP_VLAN_MTU; 401 ifp->if_capenable |= IFCAP_VLAN_MTU; 402 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 403 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN); 404 ifq_set_ready(&ifp->if_snd); 405 406 bfe_get_config(sc); 407 408 /* Reset the chip and turn on the PHY */ 409 bfe_chip_reset(sc); 410 411 if (mii_phy_probe(dev, &sc->bfe_miibus, 412 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 413 device_printf(dev, "MII without any PHY!\n"); 414 error = ENXIO; 415 goto fail; 416 } 417 418 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 419 420 /* 421 * Hook interrupt last to avoid having to lock softc 422 */ 423 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE, 424 bfe_intr, sc, &sc->bfe_intrhand, 425 sc->arpcom.ac_if.if_serializer); 426 427 if (error) { 428 ether_ifdetach(ifp); 429 device_printf(dev, "couldn't set up irq\n"); 430 goto fail; 431 } 432 433 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bfe_irq)); 434 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 435 return 0; 436 fail: 437 bfe_detach(dev); 438 return(error); 439 } 440 441 static int 442 bfe_detach(device_t dev) 443 { 444 struct bfe_softc *sc = device_get_softc(dev); 445 struct ifnet *ifp = &sc->arpcom.ac_if; 446 447 if (device_is_attached(dev)) { 448 lwkt_serialize_enter(ifp->if_serializer); 449 bfe_stop(sc); 450 bfe_chip_reset(sc); 451 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 452 lwkt_serialize_exit(ifp->if_serializer); 453 454 ether_ifdetach(ifp); 455 } 456 if (sc->bfe_miibus != NULL) 457 device_delete_child(dev, sc->bfe_miibus); 458 bus_generic_detach(dev); 459 460 if (sc->bfe_irq != NULL) 461 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 462 463 if (sc->bfe_res != NULL) { 464 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO, 465 sc->bfe_res); 466 } 467 bfe_dma_free(sc); 468 469 return(0); 470 } 471 472 /* 473 * Stop all chip I/O so that the kernel's probe routines don't 474 * get confused by errant DMAs when rebooting. 475 */ 476 static void 477 bfe_shutdown(device_t dev) 478 { 479 struct bfe_softc *sc = device_get_softc(dev); 480 struct ifnet *ifp = &sc->arpcom.ac_if; 481 482 lwkt_serialize_enter(ifp->if_serializer); 483 bfe_stop(sc); 484 lwkt_serialize_exit(ifp->if_serializer); 485 } 486 487 static int 488 bfe_miibus_readreg(device_t dev, int phy, int reg) 489 { 490 struct bfe_softc *sc; 491 uint32_t ret; 492 493 sc = device_get_softc(dev); 494 if (phy != sc->bfe_phyaddr) 495 return(0); 496 bfe_readphy(sc, reg, &ret); 497 498 return(ret); 499 } 500 501 static int 502 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 503 { 504 struct bfe_softc *sc; 505 506 sc = device_get_softc(dev); 507 if (phy != sc->bfe_phyaddr) 508 return(0); 509 bfe_writephy(sc, reg, val); 510 511 return(0); 512 } 513 514 static void 515 bfe_tx_ring_free(struct bfe_softc *sc) 516 { 517 int i; 518 519 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 520 bus_dmamap_unload(sc->bfe_tag, 521 sc->bfe_tx_ring[i].bfe_map); 522 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 523 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 524 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 525 } 526 } 527 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 528 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 529 } 530 531 static void 532 bfe_rx_ring_free(struct bfe_softc *sc) 533 { 534 int i; 535 536 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 537 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 538 bus_dmamap_unload(sc->bfe_tag, 539 sc->bfe_rx_ring[i].bfe_map); 540 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 541 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 542 } 543 } 544 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 545 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 546 } 547 548 static int 549 bfe_list_rx_init(struct bfe_softc *sc) 550 { 551 int i; 552 553 for (i = 0; i < BFE_RX_LIST_CNT; i++) 554 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 555 return(ENOBUFS); 556 557 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 558 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 559 560 sc->bfe_rx_cons = 0; 561 562 return(0); 563 } 564 565 static int 566 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 567 { 568 struct bfe_rxheader *rx_header; 569 struct bfe_desc *d; 570 struct bfe_data *r; 571 uint32_t ctrl; 572 573 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 574 return(EINVAL); 575 576 if (m == NULL) { 577 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 578 if (m == NULL) 579 return(ENOBUFS); 580 m->m_len = m->m_pkthdr.len = MCLBYTES; 581 } 582 else 583 m->m_data = m->m_ext.ext_buf; 584 585 rx_header = mtod(m, struct bfe_rxheader *); 586 rx_header->len = 0; 587 rx_header->flags = 0; 588 589 /* Map the mbuf into DMA */ 590 sc->bfe_rx_cnt = c; 591 d = &sc->bfe_rx_list[c]; 592 r = &sc->bfe_rx_ring[c]; 593 /* XXX error? */ 594 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 595 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 596 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 597 598 ctrl = ETHER_MAX_LEN + 32; 599 600 if(c == BFE_RX_LIST_CNT - 1) 601 ctrl |= BFE_DESC_EOT; 602 603 d->bfe_ctrl = ctrl; 604 r->bfe_mbuf = m; 605 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 606 return(0); 607 } 608 609 static void 610 bfe_get_config(struct bfe_softc *sc) 611 { 612 uint8_t eeprom[128]; 613 614 bfe_read_eeprom(sc, eeprom); 615 616 sc->arpcom.ac_enaddr[0] = eeprom[79]; 617 sc->arpcom.ac_enaddr[1] = eeprom[78]; 618 sc->arpcom.ac_enaddr[2] = eeprom[81]; 619 sc->arpcom.ac_enaddr[3] = eeprom[80]; 620 sc->arpcom.ac_enaddr[4] = eeprom[83]; 621 sc->arpcom.ac_enaddr[5] = eeprom[82]; 622 623 sc->bfe_phyaddr = eeprom[90] & 0x1f; 624 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 625 626 sc->bfe_core_unit = 0; 627 sc->bfe_dma_offset = BFE_PCI_DMA; 628 } 629 630 static void 631 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores) 632 { 633 uint32_t bar_orig, pci_rev, val; 634 635 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 636 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 637 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 638 639 val = CSR_READ_4(sc, BFE_SBINTVEC); 640 val |= cores; 641 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 642 643 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 644 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 645 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 646 647 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 648 } 649 650 static void 651 bfe_clear_stats(struct bfe_softc *sc) 652 { 653 u_long reg; 654 655 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 656 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 657 CSR_READ_4(sc, reg); 658 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 659 CSR_READ_4(sc, reg); 660 } 661 662 static int 663 bfe_resetphy(struct bfe_softc *sc) 664 { 665 uint32_t val; 666 667 bfe_writephy(sc, 0, BMCR_RESET); 668 DELAY(100); 669 bfe_readphy(sc, 0, &val); 670 if (val & BMCR_RESET) { 671 if_printf(&sc->arpcom.ac_if, 672 "PHY Reset would not complete.\n"); 673 return(ENXIO); 674 } 675 return(0); 676 } 677 678 static void 679 bfe_chip_halt(struct bfe_softc *sc) 680 { 681 /* disable interrupts - not that it actually does..*/ 682 CSR_WRITE_4(sc, BFE_IMASK, 0); 683 CSR_READ_4(sc, BFE_IMASK); 684 685 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 686 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 687 688 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 689 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 690 DELAY(10); 691 } 692 693 static void 694 bfe_chip_reset(struct bfe_softc *sc) 695 { 696 uint32_t val; 697 698 /* Set the interrupt vector for the enet core */ 699 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 700 701 /* is core up? */ 702 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK); 703 if (val == BFE_CLOCK) { 704 /* It is, so shut it down */ 705 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 706 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 707 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 708 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 709 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 710 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 711 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0); 712 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 713 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 714 } 715 716 bfe_core_reset(sc); 717 bfe_clear_stats(sc); 718 719 /* 720 * We want the phy registers to be accessible even when 721 * the driver is "downed" so initialize MDC preamble, frequency, 722 * and whether internal or external phy here. 723 */ 724 725 /* 4402 has 62.5Mhz SB clock and internal phy */ 726 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 727 728 /* Internal or external PHY? */ 729 val = CSR_READ_4(sc, BFE_DEVCTRL); 730 if (!(val & BFE_IPP)) 731 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 732 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 733 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 734 DELAY(100); 735 } 736 737 /* Enable CRC32 generation and set proper LED modes */ 738 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 739 740 /* Reset or clear powerdown control bit */ 741 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 742 743 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 744 BFE_LAZY_FC_MASK)); 745 746 /* 747 * We don't want lazy interrupts, so just send them at the end of a 748 * frame, please 749 */ 750 BFE_OR(sc, BFE_RCV_LAZY, 0); 751 752 /* Set max lengths, accounting for VLAN tags */ 753 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 754 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 755 756 /* Set watermark XXX - magic */ 757 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 758 759 /* 760 * Initialise DMA channels - not forgetting dma addresses need to be 761 * added to BFE_PCI_DMA 762 */ 763 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 764 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 765 766 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 767 BFE_RX_CTRL_ENABLE); 768 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 769 770 bfe_resetphy(sc); 771 bfe_setupphy(sc); 772 } 773 774 static void 775 bfe_core_disable(struct bfe_softc *sc) 776 { 777 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 778 return; 779 780 /* 781 * Set reject, wait for it set, then wait for the core to stop being busy 782 * Then set reset and reject and enable the clocks 783 */ 784 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 785 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 786 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 787 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 788 BFE_RESET)); 789 CSR_READ_4(sc, BFE_SBTMSLOW); 790 DELAY(10); 791 /* Leave reset and reject set */ 792 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 793 DELAY(10); 794 } 795 796 static void 797 bfe_core_reset(struct bfe_softc *sc) 798 { 799 uint32_t val; 800 801 /* Disable the core */ 802 bfe_core_disable(sc); 803 804 /* and bring it back up */ 805 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 806 CSR_READ_4(sc, BFE_SBTMSLOW); 807 DELAY(10); 808 809 /* Chip bug, clear SERR, IB and TO if they are set. */ 810 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 811 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 812 val = CSR_READ_4(sc, BFE_SBIMSTATE); 813 if (val & (BFE_IBE | BFE_TO)) 814 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 815 816 /* Clear reset and allow it to move through the core */ 817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 818 CSR_READ_4(sc, BFE_SBTMSLOW); 819 DELAY(10); 820 821 /* Leave the clock set */ 822 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 823 CSR_READ_4(sc, BFE_SBTMSLOW); 824 DELAY(10); 825 } 826 827 static void 828 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 829 { 830 uint32_t val; 831 832 val = ((uint32_t) data[2]) << 24; 833 val |= ((uint32_t) data[3]) << 16; 834 val |= ((uint32_t) data[4]) << 8; 835 val |= ((uint32_t) data[5]); 836 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 837 val = (BFE_CAM_HI_VALID | 838 (((uint32_t) data[0]) << 8) | 839 (((uint32_t) data[1]))); 840 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 841 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 842 ((uint32_t)index << BFE_CAM_INDEX_SHIFT))); 843 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 844 } 845 846 static void 847 bfe_set_rx_mode(struct bfe_softc *sc) 848 { 849 struct ifnet *ifp = &sc->arpcom.ac_if; 850 struct ifmultiaddr *ifma; 851 uint32_t val; 852 int i = 0; 853 854 val = CSR_READ_4(sc, BFE_RXCONF); 855 856 if (ifp->if_flags & IFF_PROMISC) 857 val |= BFE_RXCONF_PROMISC; 858 else 859 val &= ~BFE_RXCONF_PROMISC; 860 861 if (ifp->if_flags & IFF_BROADCAST) 862 val &= ~BFE_RXCONF_DBCAST; 863 else 864 val |= BFE_RXCONF_DBCAST; 865 866 867 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 868 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 869 870 if (ifp->if_flags & IFF_ALLMULTI) { 871 val |= BFE_RXCONF_ALLMULTI; 872 } else { 873 val &= ~BFE_RXCONF_ALLMULTI; 874 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 875 if (ifma->ifma_addr->sa_family != AF_LINK) 876 continue; 877 bfe_cam_write(sc, 878 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 879 } 880 } 881 882 CSR_WRITE_4(sc, BFE_RXCONF, val); 883 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 884 } 885 886 static void 887 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 888 { 889 uint32_t *ptr; 890 891 ptr = arg; 892 *ptr = segs->ds_addr; 893 } 894 895 static void 896 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 897 { 898 struct bfe_desc *d; 899 900 d = arg; 901 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 902 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 903 } 904 905 static void 906 bfe_dma_free(struct bfe_softc *sc) 907 { 908 if (sc->bfe_tx_tag != NULL) { 909 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 910 if (sc->bfe_tx_list != NULL) { 911 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 912 sc->bfe_tx_map); 913 sc->bfe_tx_list = NULL; 914 } 915 bus_dma_tag_destroy(sc->bfe_tx_tag); 916 sc->bfe_tx_tag = NULL; 917 } 918 919 if (sc->bfe_rx_tag != NULL) { 920 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 921 if (sc->bfe_rx_list != NULL) { 922 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 923 sc->bfe_rx_map); 924 sc->bfe_rx_list = NULL; 925 } 926 bus_dma_tag_destroy(sc->bfe_rx_tag); 927 sc->bfe_rx_tag = NULL; 928 } 929 930 if (sc->bfe_tag != NULL) { 931 int i; 932 933 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 934 bus_dmamap_destroy(sc->bfe_tag, 935 sc->bfe_tx_ring[i].bfe_map); 936 } 937 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 938 bus_dmamap_destroy(sc->bfe_tag, 939 sc->bfe_rx_ring[i].bfe_map); 940 } 941 942 bus_dma_tag_destroy(sc->bfe_tag); 943 sc->bfe_tag = NULL; 944 } 945 946 if (sc->bfe_parent_tag != NULL) { 947 bus_dma_tag_destroy(sc->bfe_parent_tag); 948 sc->bfe_parent_tag = NULL; 949 } 950 } 951 952 static void 953 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data) 954 { 955 long i; 956 uint16_t *ptr = (uint16_t *)data; 957 958 for (i = 0; i < 128; i += 2) 959 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 960 } 961 962 static int 963 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit, 964 u_long timeout, const int clear) 965 { 966 u_long i; 967 968 for (i = 0; i < timeout; i++) { 969 uint32_t val = CSR_READ_4(sc, reg); 970 971 if (clear && !(val & bit)) 972 break; 973 if (!clear && (val & bit)) 974 break; 975 DELAY(10); 976 } 977 if (i == timeout) { 978 if_printf(&sc->arpcom.ac_if, 979 "BUG! Timeout waiting for bit %08x of register " 980 "%x to %s.\n", bit, reg, 981 (clear ? "clear" : "set")); 982 return -1; 983 } 984 return 0; 985 } 986 987 static int 988 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val) 989 { 990 int err; 991 992 /* Clear MII ISR */ 993 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 994 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 995 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 996 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 997 (reg << BFE_MDIO_RA_SHIFT) | 998 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 999 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1000 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1001 return(err); 1002 } 1003 1004 static int 1005 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val) 1006 { 1007 int status; 1008 1009 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1010 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1011 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1012 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1013 (reg << BFE_MDIO_RA_SHIFT) | 1014 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1015 (val & BFE_MDIO_DATA_DATA))); 1016 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1017 1018 return status; 1019 } 1020 1021 /* 1022 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1023 * twice 1024 */ 1025 static int 1026 bfe_setupphy(struct bfe_softc *sc) 1027 { 1028 uint32_t val; 1029 1030 /* Enable activity LED */ 1031 bfe_readphy(sc, 26, &val); 1032 bfe_writephy(sc, 26, val & 0x7fff); 1033 bfe_readphy(sc, 26, &val); 1034 1035 /* Enable traffic meter LED mode */ 1036 bfe_readphy(sc, 27, &val); 1037 bfe_writephy(sc, 27, val | (1 << 6)); 1038 1039 return(0); 1040 } 1041 1042 static void 1043 bfe_stats_update(struct bfe_softc *sc) 1044 { 1045 u_long reg; 1046 uint32_t *val; 1047 1048 val = &sc->bfe_hwstats.tx_good_octets; 1049 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1050 *val++ += CSR_READ_4(sc, reg); 1051 val = &sc->bfe_hwstats.rx_good_octets; 1052 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1053 *val++ += CSR_READ_4(sc, reg); 1054 } 1055 1056 static void 1057 bfe_txeof(struct bfe_softc *sc) 1058 { 1059 struct ifnet *ifp = &sc->arpcom.ac_if; 1060 uint32_t i, chipidx; 1061 1062 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1063 chipidx /= sizeof(struct bfe_desc); 1064 1065 i = sc->bfe_tx_cons; 1066 /* Go through the mbufs and free those that have been transmitted */ 1067 while (i != chipidx) { 1068 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1069 1070 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1071 if (r->bfe_mbuf != NULL) { 1072 ifp->if_opackets++; 1073 m_freem(r->bfe_mbuf); 1074 r->bfe_mbuf = NULL; 1075 } 1076 sc->bfe_tx_cnt--; 1077 BFE_INC(i, BFE_TX_LIST_CNT); 1078 } 1079 1080 if (i != sc->bfe_tx_cons) { 1081 /* we freed up some mbufs */ 1082 sc->bfe_tx_cons = i; 1083 ifp->if_flags &= ~IFF_OACTIVE; 1084 } 1085 if (sc->bfe_tx_cnt == 0) 1086 ifp->if_timer = 0; 1087 else 1088 ifp->if_timer = 5; 1089 } 1090 1091 /* Pass a received packet up the stack */ 1092 static void 1093 bfe_rxeof(struct bfe_softc *sc) 1094 { 1095 struct ifnet *ifp = &sc->arpcom.ac_if; 1096 struct mbuf *m; 1097 struct bfe_rxheader *rxheader; 1098 struct bfe_data *r; 1099 uint32_t cons, status, current, len, flags; 1100 struct mbuf_chain chain[MAXCPU]; 1101 1102 cons = sc->bfe_rx_cons; 1103 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1104 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1105 1106 ether_input_chain_init(chain); 1107 1108 while (current != cons) { 1109 r = &sc->bfe_rx_ring[cons]; 1110 m = r->bfe_mbuf; 1111 rxheader = mtod(m, struct bfe_rxheader*); 1112 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD); 1113 len = rxheader->len; 1114 r->bfe_mbuf = NULL; 1115 1116 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1117 flags = rxheader->flags; 1118 1119 len -= ETHER_CRC_LEN; 1120 1121 /* flag an error and try again */ 1122 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1123 ifp->if_ierrors++; 1124 if (flags & BFE_RX_FLAG_SERR) 1125 ifp->if_collisions++; 1126 bfe_list_newbuf(sc, cons, m); 1127 BFE_INC(cons, BFE_RX_LIST_CNT); 1128 continue; 1129 } 1130 1131 /* Go past the rx header */ 1132 if (bfe_list_newbuf(sc, cons, NULL) != 0) { 1133 bfe_list_newbuf(sc, cons, m); 1134 BFE_INC(cons, BFE_RX_LIST_CNT); 1135 ifp->if_ierrors++; 1136 continue; 1137 } 1138 1139 m_adj(m, BFE_RX_OFFSET); 1140 m->m_len = m->m_pkthdr.len = len; 1141 1142 ifp->if_ipackets++; 1143 m->m_pkthdr.rcvif = ifp; 1144 1145 ether_input_chain(ifp, m, chain); 1146 BFE_INC(cons, BFE_RX_LIST_CNT); 1147 } 1148 1149 ether_input_dispatch(chain); 1150 1151 sc->bfe_rx_cons = cons; 1152 } 1153 1154 static void 1155 bfe_intr(void *xsc) 1156 { 1157 struct bfe_softc *sc = xsc; 1158 struct ifnet *ifp = &sc->arpcom.ac_if; 1159 uint32_t istat, imask, flag; 1160 1161 istat = CSR_READ_4(sc, BFE_ISTAT); 1162 imask = CSR_READ_4(sc, BFE_IMASK); 1163 1164 /* 1165 * Defer unsolicited interrupts - This is necessary because setting the 1166 * chips interrupt mask register to 0 doesn't actually stop the 1167 * interrupts 1168 */ 1169 istat &= imask; 1170 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1171 CSR_READ_4(sc, BFE_ISTAT); 1172 1173 /* not expecting this interrupt, disregard it */ 1174 if (istat == 0) { 1175 return; 1176 } 1177 1178 if (istat & BFE_ISTAT_ERRORS) { 1179 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1180 if (flag & BFE_STAT_EMASK) 1181 ifp->if_oerrors++; 1182 1183 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1184 if (flag & BFE_RX_FLAG_ERRORS) 1185 ifp->if_ierrors++; 1186 1187 ifp->if_flags &= ~IFF_RUNNING; 1188 bfe_init(sc); 1189 } 1190 1191 /* A packet was received */ 1192 if (istat & BFE_ISTAT_RX) 1193 bfe_rxeof(sc); 1194 1195 /* A packet was sent */ 1196 if (istat & BFE_ISTAT_TX) 1197 bfe_txeof(sc); 1198 1199 /* We have packets pending, fire them out */ 1200 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1201 if_devstart(ifp); 1202 } 1203 1204 static int 1205 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1206 { 1207 struct bfe_desc *d = NULL; 1208 struct bfe_data *r = NULL; 1209 struct mbuf *m; 1210 uint32_t frag, cur, cnt = 0; 1211 int error, chainlen = 0; 1212 1213 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt)); 1214 1215 /* 1216 * Count the number of frags in this chain to see if 1217 * we need to m_defrag. Since the descriptor list is shared 1218 * by all packets, we'll m_defrag long chains so that they 1219 * do not use up the entire list, even if they would fit. 1220 */ 1221 for (m = *m_head; m != NULL; m = m->m_next) 1222 chainlen++; 1223 1224 if (chainlen > (BFE_TX_LIST_CNT / 4) || 1225 BFE_TX_LIST_CNT < (2 + chainlen + sc->bfe_tx_cnt)) { 1226 m = m_defrag(*m_head, MB_DONTWAIT); 1227 if (m == NULL) { 1228 m_freem(*m_head); 1229 return (ENOBUFS); 1230 } 1231 *m_head = m; 1232 } 1233 1234 /* 1235 * Start packing the mbufs in this chain into 1236 * the fragment pointers. Stop when we run out 1237 * of fragments or hit the end of the mbuf chain. 1238 */ 1239 cur = frag = *txidx; 1240 cnt = 0; 1241 1242 for (m = *m_head; m != NULL; m = m->m_next) { 1243 if (m->m_len != 0) { 1244 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt + cnt)); 1245 1246 d = &sc->bfe_tx_list[cur]; 1247 r = &sc->bfe_tx_ring[cur]; 1248 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1249 /* always intterupt on completion */ 1250 d->bfe_ctrl |= BFE_DESC_IOC; 1251 if (cnt == 0) { 1252 /* Set start of frame */ 1253 d->bfe_ctrl |= BFE_DESC_SOF; 1254 } 1255 if (cur == BFE_TX_LIST_CNT - 1) { 1256 /* 1257 * Tell the chip to wrap to the start of the 1258 * descriptor list 1259 */ 1260 d->bfe_ctrl |= BFE_DESC_EOT; 1261 } 1262 1263 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, 1264 mtod(m, void *), m->m_len, 1265 bfe_dma_map_desc, d, 1266 BUS_DMA_NOWAIT); 1267 if (error) { 1268 /* XXX This should be a fatal error. */ 1269 if_printf(&sc->arpcom.ac_if, 1270 "%s bus_dmamap_load failed: %d", 1271 __func__, error); 1272 m_freem(*m_head); 1273 return (ENOBUFS); 1274 } 1275 1276 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1277 BUS_DMASYNC_PREWRITE); 1278 1279 frag = cur; 1280 BFE_INC(cur, BFE_TX_LIST_CNT); 1281 cnt++; 1282 } 1283 } 1284 1285 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1286 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head; 1287 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 1288 1289 *txidx = cur; 1290 sc->bfe_tx_cnt += cnt; 1291 return(0); 1292 } 1293 1294 /* 1295 * Set up to transmit a packet 1296 */ 1297 static void 1298 bfe_start(struct ifnet *ifp) 1299 { 1300 struct bfe_softc *sc = ifp->if_softc; 1301 struct mbuf *m_head = NULL; 1302 int idx, need_trans; 1303 1304 ASSERT_SERIALIZED(ifp->if_serializer); 1305 1306 /* 1307 * Not much point trying to send if the link is down 1308 * or we have nothing to send. 1309 */ 1310 if (!sc->bfe_link) { 1311 ifq_purge(&ifp->if_snd); 1312 return; 1313 } 1314 1315 if (ifp->if_flags & IFF_OACTIVE) 1316 return; 1317 1318 idx = sc->bfe_tx_prod; 1319 1320 need_trans = 0; 1321 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1322 if (BFE_TX_LIST_CNT < (2 + sc->bfe_tx_cnt)) { 1323 ifp->if_flags |= IFF_OACTIVE; 1324 break; 1325 } 1326 1327 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1328 if (m_head == NULL) 1329 break; 1330 1331 /* 1332 * Pack the data into the tx ring. If we don't have 1333 * enough room, let the chip drain the ring. 1334 */ 1335 if (bfe_encap(sc, &m_head, &idx)) { 1336 ifp->if_flags |= IFF_OACTIVE; 1337 break; 1338 } 1339 need_trans = 1; 1340 1341 /* 1342 * If there's a BPF listener, bounce a copy of this frame 1343 * to him. 1344 */ 1345 BPF_MTAP(ifp, m_head); 1346 } 1347 1348 if (!need_trans) 1349 return; 1350 1351 sc->bfe_tx_prod = idx; 1352 /* Transmit - twice due to apparent hardware bug */ 1353 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1354 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1355 1356 /* 1357 * Set a timeout in case the chip goes out to lunch. 1358 */ 1359 ifp->if_timer = 5; 1360 } 1361 1362 static void 1363 bfe_init(void *xsc) 1364 { 1365 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1366 struct ifnet *ifp = &sc->arpcom.ac_if; 1367 1368 ASSERT_SERIALIZED(ifp->if_serializer); 1369 1370 if (ifp->if_flags & IFF_RUNNING) 1371 return; 1372 1373 bfe_stop(sc); 1374 bfe_chip_reset(sc); 1375 1376 if (bfe_list_rx_init(sc) == ENOBUFS) { 1377 if_printf(ifp, "bfe_init failed. " 1378 " Not enough memory for list buffers\n"); 1379 bfe_stop(sc); 1380 return; 1381 } 1382 1383 bfe_set_rx_mode(sc); 1384 1385 /* Enable the chip and core */ 1386 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1387 /* Enable interrupts */ 1388 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1389 1390 bfe_ifmedia_upd(ifp); 1391 ifp->if_flags |= IFF_RUNNING; 1392 ifp->if_flags &= ~IFF_OACTIVE; 1393 1394 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1395 } 1396 1397 /* 1398 * Set media options. 1399 */ 1400 static int 1401 bfe_ifmedia_upd(struct ifnet *ifp) 1402 { 1403 struct bfe_softc *sc = ifp->if_softc; 1404 struct mii_data *mii; 1405 1406 ASSERT_SERIALIZED(ifp->if_serializer); 1407 1408 mii = device_get_softc(sc->bfe_miibus); 1409 sc->bfe_link = 0; 1410 if (mii->mii_instance) { 1411 struct mii_softc *miisc; 1412 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1413 miisc = LIST_NEXT(miisc, mii_list)) 1414 mii_phy_reset(miisc); 1415 } 1416 mii_mediachg(mii); 1417 1418 bfe_setupphy(sc); 1419 1420 return(0); 1421 } 1422 1423 /* 1424 * Report current media status. 1425 */ 1426 static void 1427 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1428 { 1429 struct bfe_softc *sc = ifp->if_softc; 1430 struct mii_data *mii; 1431 1432 ASSERT_SERIALIZED(ifp->if_serializer); 1433 1434 mii = device_get_softc(sc->bfe_miibus); 1435 mii_pollstat(mii); 1436 ifmr->ifm_active = mii->mii_media_active; 1437 ifmr->ifm_status = mii->mii_media_status; 1438 } 1439 1440 static int 1441 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1442 { 1443 struct bfe_softc *sc = ifp->if_softc; 1444 struct ifreq *ifr = (struct ifreq *) data; 1445 struct mii_data *mii; 1446 int error = 0; 1447 1448 ASSERT_SERIALIZED(ifp->if_serializer); 1449 1450 switch (command) { 1451 case SIOCSIFFLAGS: 1452 if (ifp->if_flags & IFF_UP) 1453 if (ifp->if_flags & IFF_RUNNING) 1454 bfe_set_rx_mode(sc); 1455 else 1456 bfe_init(sc); 1457 else if (ifp->if_flags & IFF_RUNNING) 1458 bfe_stop(sc); 1459 break; 1460 case SIOCADDMULTI: 1461 case SIOCDELMULTI: 1462 if (ifp->if_flags & IFF_RUNNING) 1463 bfe_set_rx_mode(sc); 1464 break; 1465 case SIOCGIFMEDIA: 1466 case SIOCSIFMEDIA: 1467 mii = device_get_softc(sc->bfe_miibus); 1468 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1469 command); 1470 break; 1471 default: 1472 error = ether_ioctl(ifp, command, data); 1473 break; 1474 } 1475 return error; 1476 } 1477 1478 static void 1479 bfe_watchdog(struct ifnet *ifp) 1480 { 1481 struct bfe_softc *sc = ifp->if_softc; 1482 1483 ASSERT_SERIALIZED(ifp->if_serializer); 1484 1485 if_printf(ifp, "watchdog timeout -- resetting\n"); 1486 1487 ifp->if_flags &= ~IFF_RUNNING; 1488 bfe_init(sc); 1489 1490 ifp->if_oerrors++; 1491 } 1492 1493 static void 1494 bfe_tick(void *xsc) 1495 { 1496 struct bfe_softc *sc = xsc; 1497 struct mii_data *mii; 1498 struct ifnet *ifp = &sc->arpcom.ac_if; 1499 1500 mii = device_get_softc(sc->bfe_miibus); 1501 1502 lwkt_serialize_enter(ifp->if_serializer); 1503 1504 bfe_stats_update(sc); 1505 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc); 1506 1507 if (sc->bfe_link == 0) { 1508 mii_tick(mii); 1509 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1510 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1511 sc->bfe_link++; 1512 } 1513 if (!sc->bfe_link) 1514 sc->bfe_link++; 1515 } 1516 lwkt_serialize_exit(ifp->if_serializer); 1517 } 1518 1519 /* 1520 * Stop the adapter and free any mbufs allocated to the 1521 * RX and TX lists. 1522 */ 1523 static void 1524 bfe_stop(struct bfe_softc *sc) 1525 { 1526 struct ifnet *ifp = &sc->arpcom.ac_if; 1527 1528 ASSERT_SERIALIZED(ifp->if_serializer); 1529 1530 callout_stop(&sc->bfe_stat_timer); 1531 1532 bfe_chip_halt(sc); 1533 bfe_tx_ring_free(sc); 1534 bfe_rx_ring_free(sc); 1535 1536 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1537 } 1538