1572ff6f6SMatthew Dillon /*- 2572ff6f6SMatthew Dillon * Copyright (c) 2004 INRIA 3572ff6f6SMatthew Dillon * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 4572ff6f6SMatthew Dillon * All rights reserved. 5572ff6f6SMatthew Dillon * 6572ff6f6SMatthew Dillon * Redistribution and use in source and binary forms, with or without 7572ff6f6SMatthew Dillon * modification, are permitted provided that the following conditions 8572ff6f6SMatthew Dillon * are met: 9572ff6f6SMatthew Dillon * 1. Redistributions of source code must retain the above copyright 10572ff6f6SMatthew Dillon * notice, this list of conditions and the following disclaimer, 11572ff6f6SMatthew Dillon without modification. 12572ff6f6SMatthew Dillon * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13572ff6f6SMatthew Dillon * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14572ff6f6SMatthew Dillon * redistribution must be conditioned upon including a substantially 15572ff6f6SMatthew Dillon * similar Disclaimer requirement for further binary redistribution. 16572ff6f6SMatthew Dillon * 3. Neither the names of the above-listed copyright holders nor the names 17572ff6f6SMatthew Dillon * of any contributors may be used to endorse or promote products derived 18572ff6f6SMatthew Dillon * from this software without specific prior written permission. 19572ff6f6SMatthew Dillon * 20572ff6f6SMatthew Dillon * Alternatively, this software may be distributed under the terms of the 21572ff6f6SMatthew Dillon * GNU General Public License ("GPL") version 2 as published by the Free 22572ff6f6SMatthew Dillon * Software Foundation. 23572ff6f6SMatthew Dillon * 24572ff6f6SMatthew Dillon * NO WARRANTY 25572ff6f6SMatthew Dillon * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26572ff6f6SMatthew Dillon * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27*df052c2aSSascha Wildner * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY 28572ff6f6SMatthew Dillon * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 29572ff6f6SMatthew Dillon * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 30572ff6f6SMatthew Dillon * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31572ff6f6SMatthew Dillon * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32572ff6f6SMatthew Dillon * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 33572ff6f6SMatthew Dillon * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34572ff6f6SMatthew Dillon * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35572ff6f6SMatthew Dillon * THE POSSIBILITY OF SUCH DAMAGES. 36572ff6f6SMatthew Dillon * 37572ff6f6SMatthew Dillon * $FreeBSD$ 38572ff6f6SMatthew Dillon */ 39572ff6f6SMatthew Dillon 40572ff6f6SMatthew Dillon #ifndef _DEV_ATH_RATE_AMRR_H 41572ff6f6SMatthew Dillon #define _DEV_ATH_RATE_AMRR_H 42572ff6f6SMatthew Dillon 43572ff6f6SMatthew Dillon /* per-device state */ 44572ff6f6SMatthew Dillon struct amrr_softc { 45572ff6f6SMatthew Dillon struct ath_ratectrl arc; /* base state */ 46572ff6f6SMatthew Dillon }; 47572ff6f6SMatthew Dillon 48572ff6f6SMatthew Dillon /* per-node state */ 49572ff6f6SMatthew Dillon struct amrr_node { 50572ff6f6SMatthew Dillon int amn_rix; /* current rate index */ 51572ff6f6SMatthew Dillon int amn_ticks; /* time of last update */ 52572ff6f6SMatthew Dillon int amn_interval; /* update interval (ticks) */ 53572ff6f6SMatthew Dillon /* AMRR statistics for this node */ 54572ff6f6SMatthew Dillon u_int amn_tx_try0_cnt; 55572ff6f6SMatthew Dillon u_int amn_tx_try1_cnt; 56572ff6f6SMatthew Dillon u_int amn_tx_try2_cnt; 57572ff6f6SMatthew Dillon u_int amn_tx_try3_cnt; 58572ff6f6SMatthew Dillon u_int amn_tx_failure_cnt; 59572ff6f6SMatthew Dillon /* AMRR algorithm state for this node */ 60572ff6f6SMatthew Dillon u_int amn_success_threshold; 61572ff6f6SMatthew Dillon u_int amn_success; 62572ff6f6SMatthew Dillon u_int amn_recovery; 63572ff6f6SMatthew Dillon /* rate index et al. */ 64572ff6f6SMatthew Dillon u_int8_t amn_tx_rix0; /* series 0 rate index */ 65572ff6f6SMatthew Dillon u_int8_t amn_tx_rate0; /* series 0 h/w rate */ 66572ff6f6SMatthew Dillon u_int8_t amn_tx_rate1; /* series 1 h/w rate */ 67572ff6f6SMatthew Dillon u_int8_t amn_tx_rate2; /* series 2 h/w rate */ 68572ff6f6SMatthew Dillon u_int8_t amn_tx_rate3; /* series 3 h/w rate */ 69572ff6f6SMatthew Dillon u_int8_t amn_tx_rate0sp; /* series 0 short preamble h/w rate */ 70572ff6f6SMatthew Dillon u_int8_t amn_tx_rate1sp; /* series 1 short preamble h/w rate */ 71572ff6f6SMatthew Dillon u_int8_t amn_tx_rate2sp; /* series 2 short preamble h/w rate */ 72572ff6f6SMatthew Dillon u_int8_t amn_tx_rate3sp; /* series 3 short preamble h/w rate */ 73572ff6f6SMatthew Dillon u_int8_t amn_tx_try0; /* series 0 try count */ 74572ff6f6SMatthew Dillon u_int amn_tx_try1; /* series 1 try count */ 75572ff6f6SMatthew Dillon u_int amn_tx_try2; /* series 2 try count */ 76572ff6f6SMatthew Dillon u_int amn_tx_try3; /* series 3 try count */ 77572ff6f6SMatthew Dillon }; 78572ff6f6SMatthew Dillon #define ATH_NODE_AMRR(an) ((struct amrr_node *)&an[1]) 79572ff6f6SMatthew Dillon #endif /* _DEV_ATH_RATE_AMRR_H */ 80