1*572ff6f6SMatthew Dillon /*
2*572ff6f6SMatthew Dillon * Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd
3*572ff6f6SMatthew Dillon * Copyright (c) 2010 Atheros Communications, Inc.
4*572ff6f6SMatthew Dillon *
5*572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6*572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7*572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8*572ff6f6SMatthew Dillon *
9*572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10*572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11*572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12*572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13*572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14*572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15*572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16*572ff6f6SMatthew Dillon *
17*572ff6f6SMatthew Dillon * $FreeBSD$
18*572ff6f6SMatthew Dillon */
19*572ff6f6SMatthew Dillon #include "opt_ah.h"
20*572ff6f6SMatthew Dillon
21*572ff6f6SMatthew Dillon #include "ah.h"
22*572ff6f6SMatthew Dillon #include "ah_internal.h"
23*572ff6f6SMatthew Dillon #include "ah_devid.h"
24*572ff6f6SMatthew Dillon
25*572ff6f6SMatthew Dillon #include "ar5416/ar5416.h"
26*572ff6f6SMatthew Dillon #include "ar5416/ar5416reg.h"
27*572ff6f6SMatthew Dillon #include "ar5416/ar5416phy.h"
28*572ff6f6SMatthew Dillon #include "ar9001/ar9130_phy.h"
29*572ff6f6SMatthew Dillon
30*572ff6f6SMatthew Dillon void
ar9130InitPLL(struct ath_hal * ah,const struct ieee80211_channel * chan)31*572ff6f6SMatthew Dillon ar9130InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
32*572ff6f6SMatthew Dillon {
33*572ff6f6SMatthew Dillon
34*572ff6f6SMatthew Dillon uint32_t pll;
35*572ff6f6SMatthew Dillon
36*572ff6f6SMatthew Dillon /*
37*572ff6f6SMatthew Dillon * XXX TODO: support half/quarter rates
38*572ff6f6SMatthew Dillon */
39*572ff6f6SMatthew Dillon if (chan && IEEE80211_IS_CHAN_5GHZ(chan))
40*572ff6f6SMatthew Dillon pll = 0x1450;
41*572ff6f6SMatthew Dillon else
42*572ff6f6SMatthew Dillon pll = 0x1458;
43*572ff6f6SMatthew Dillon
44*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
45*572ff6f6SMatthew Dillon OS_DELAY(RTC_PLL_SETTLE_DELAY);
46*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK);
47*572ff6f6SMatthew Dillon }
48