xref: /dflybsd-src/sys/dev/netif/ath/ath_hal/ar5312/ar5312phy.h (revision 572ff6f6e8b95055988f178b6ba12ce77bb5b3c2)
1*572ff6f6SMatthew Dillon /*
2*572ff6f6SMatthew Dillon  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3*572ff6f6SMatthew Dillon  * Copyright (c) 2002-2008 Atheros Communications, Inc.
4*572ff6f6SMatthew Dillon  *
5*572ff6f6SMatthew Dillon  * Permission to use, copy, modify, and/or distribute this software for any
6*572ff6f6SMatthew Dillon  * purpose with or without fee is hereby granted, provided that the above
7*572ff6f6SMatthew Dillon  * copyright notice and this permission notice appear in all copies.
8*572ff6f6SMatthew Dillon  *
9*572ff6f6SMatthew Dillon  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10*572ff6f6SMatthew Dillon  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11*572ff6f6SMatthew Dillon  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12*572ff6f6SMatthew Dillon  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13*572ff6f6SMatthew Dillon  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14*572ff6f6SMatthew Dillon  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15*572ff6f6SMatthew Dillon  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16*572ff6f6SMatthew Dillon  *
17*572ff6f6SMatthew Dillon  * $FreeBSD$
18*572ff6f6SMatthew Dillon  */
19*572ff6f6SMatthew Dillon #ifndef _DEV_ATH_AR5312PHY_H_
20*572ff6f6SMatthew Dillon #define _DEV_ATH_AR5312PHY_H_
21*572ff6f6SMatthew Dillon 
22*572ff6f6SMatthew Dillon #include "ar5212/ar5212phy.h"
23*572ff6f6SMatthew Dillon 
24*572ff6f6SMatthew Dillon /* PHY registers */
25*572ff6f6SMatthew Dillon 
26*572ff6f6SMatthew Dillon #define AR_PHY_PLL_CTL_44_5312  0x14d6          /* 44 MHz for 11b, 11g */
27*572ff6f6SMatthew Dillon #define AR_PHY_PLL_CTL_40_5312  0x14d4          /* 40 MHz for 11a, turbos */
28*572ff6f6SMatthew Dillon #define AR_PHY_PLL_CTL_40_5312_HALF  0x15d4	/* 40 MHz for 11a, turbos (Half)*/
29*572ff6f6SMatthew Dillon #define AR_PHY_PLL_CTL_40_5312_QUARTER  0x16d4	/* 40 MHz for 11a, turbos (Quarter)*/
30*572ff6f6SMatthew Dillon 
31*572ff6f6SMatthew Dillon #endif	/* _DEV_ATH_AR5312PHY_H_ */
32