1*572ff6f6SMatthew Dillon /*
2*572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3*572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc.
4*572ff6f6SMatthew Dillon *
5*572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6*572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7*572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8*572ff6f6SMatthew Dillon *
9*572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10*572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11*572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12*572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13*572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14*572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15*572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16*572ff6f6SMatthew Dillon *
17*572ff6f6SMatthew Dillon * $FreeBSD$
18*572ff6f6SMatthew Dillon */
19*572ff6f6SMatthew Dillon #include "opt_ah.h"
20*572ff6f6SMatthew Dillon
21*572ff6f6SMatthew Dillon #ifdef AH_SUPPORT_AR5312
22*572ff6f6SMatthew Dillon
23*572ff6f6SMatthew Dillon #include "ah.h"
24*572ff6f6SMatthew Dillon #include "ah_internal.h"
25*572ff6f6SMatthew Dillon #include "ah_devid.h"
26*572ff6f6SMatthew Dillon
27*572ff6f6SMatthew Dillon #include "ar5312/ar5312.h"
28*572ff6f6SMatthew Dillon #include "ar5312/ar5312reg.h"
29*572ff6f6SMatthew Dillon #include "ar5312/ar5312phy.h"
30*572ff6f6SMatthew Dillon
31*572ff6f6SMatthew Dillon #define AR_NUM_GPIO 6 /* 6 GPIO pins */
32*572ff6f6SMatthew Dillon #define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */
33*572ff6f6SMatthew Dillon
34*572ff6f6SMatthew Dillon /*
35*572ff6f6SMatthew Dillon * Change the LED blinking pattern to correspond to the connectivity
36*572ff6f6SMatthew Dillon */
37*572ff6f6SMatthew Dillon void
ar5312SetLedState(struct ath_hal * ah,HAL_LED_STATE state)38*572ff6f6SMatthew Dillon ar5312SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
39*572ff6f6SMatthew Dillon {
40*572ff6f6SMatthew Dillon uint32_t val;
41*572ff6f6SMatthew Dillon uint32_t resOffset = (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh));
42*572ff6f6SMatthew Dillon if(IS_2316(ah)) return; /* not yet */
43*572ff6f6SMatthew Dillon val = SM(AR5312_PCICFG_LEDSEL0, AR5312_PCICFG_LEDSEL) |
44*572ff6f6SMatthew Dillon SM(AR5312_PCICFG_LEDMOD0, AR5312_PCICFG_LEDMODE) |
45*572ff6f6SMatthew Dillon 2;
46*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, resOffset+AR5312_PCICFG,
47*572ff6f6SMatthew Dillon (OS_REG_READ(ah, AR5312_PCICFG) &~
48*572ff6f6SMatthew Dillon (AR5312_PCICFG_LEDSEL | AR5312_PCICFG_LEDMODE |
49*572ff6f6SMatthew Dillon AR5312_PCICFG_LEDSBR))
50*572ff6f6SMatthew Dillon | val);
51*572ff6f6SMatthew Dillon }
52*572ff6f6SMatthew Dillon
53*572ff6f6SMatthew Dillon /*
54*572ff6f6SMatthew Dillon * Detect if our wireless mac is present.
55*572ff6f6SMatthew Dillon */
56*572ff6f6SMatthew Dillon HAL_BOOL
ar5312DetectCardPresent(struct ath_hal * ah)57*572ff6f6SMatthew Dillon ar5312DetectCardPresent(struct ath_hal *ah)
58*572ff6f6SMatthew Dillon {
59*572ff6f6SMatthew Dillon uint16_t macVersion, macRev;
60*572ff6f6SMatthew Dillon uint32_t v;
61*572ff6f6SMatthew Dillon
62*572ff6f6SMatthew Dillon /*
63*572ff6f6SMatthew Dillon * Read the Silicon Revision register and compare that
64*572ff6f6SMatthew Dillon * to what we read at attach time. If the same, we say
65*572ff6f6SMatthew Dillon * a card/device is present.
66*572ff6f6SMatthew Dillon */
67*572ff6f6SMatthew Dillon #if (AH_SUPPORT_2316 || AH_SUPPORT_2317)
68*572ff6f6SMatthew Dillon if(IS_5315(ah))
69*572ff6f6SMatthew Dillon {
70*572ff6f6SMatthew Dillon v = (OS_REG_READ(ah,
71*572ff6f6SMatthew Dillon (AR5315_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5315_WREV))
72*572ff6f6SMatthew Dillon & AR_SREV_ID;
73*572ff6f6SMatthew Dillon macVersion = v >> AR_SREV_ID_S;
74*572ff6f6SMatthew Dillon macRev = v & AR_SREV_REVISION;
75*572ff6f6SMatthew Dillon return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
76*572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macRev == macRev);
77*572ff6f6SMatthew Dillon }
78*572ff6f6SMatthew Dillon else
79*572ff6f6SMatthew Dillon #endif
80*572ff6f6SMatthew Dillon {
81*572ff6f6SMatthew Dillon v = (OS_REG_READ(ah,
82*572ff6f6SMatthew Dillon (AR5312_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5312_WREV))
83*572ff6f6SMatthew Dillon & AR_SREV_ID;
84*572ff6f6SMatthew Dillon macVersion = v >> AR_SREV_ID_S;
85*572ff6f6SMatthew Dillon macRev = v & AR_SREV_REVISION;
86*572ff6f6SMatthew Dillon return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
87*572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_macRev == macRev);
88*572ff6f6SMatthew Dillon }
89*572ff6f6SMatthew Dillon }
90*572ff6f6SMatthew Dillon
91*572ff6f6SMatthew Dillon /*
92*572ff6f6SMatthew Dillon * If 32KHz clock exists, use it to lower power consumption during sleep
93*572ff6f6SMatthew Dillon *
94*572ff6f6SMatthew Dillon * Note: If clock is set to 32 KHz, delays on accessing certain
95*572ff6f6SMatthew Dillon * baseband registers (27-31, 124-127) are required.
96*572ff6f6SMatthew Dillon */
97*572ff6f6SMatthew Dillon void
ar5312SetupClock(struct ath_hal * ah,HAL_OPMODE opmode)98*572ff6f6SMatthew Dillon ar5312SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
99*572ff6f6SMatthew Dillon {
100*572ff6f6SMatthew Dillon if (ar5212Use32KHzclock(ah, opmode)) {
101*572ff6f6SMatthew Dillon /*
102*572ff6f6SMatthew Dillon * Enable clocks to be turned OFF in BB during sleep
103*572ff6f6SMatthew Dillon * and also enable turning OFF 32MHz/40MHz Refclk
104*572ff6f6SMatthew Dillon * from A2.
105*572ff6f6SMatthew Dillon */
106*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
107*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0d);
108*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c);
109*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03);
110*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x05);
111*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
112*572ff6f6SMatthew Dillon IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
113*572ff6f6SMatthew Dillon
114*572ff6f6SMatthew Dillon OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
115*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */
116*572ff6f6SMatthew Dillon
117*572ff6f6SMatthew Dillon } else {
118*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */
119*572ff6f6SMatthew Dillon OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
120*572ff6f6SMatthew Dillon IS_RAD5112_ANY(ah) ? 39 : 31);
121*572ff6f6SMatthew Dillon
122*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
123*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
124*572ff6f6SMatthew Dillon
125*572ff6f6SMatthew Dillon if (IS_5312_2_X(ah)) {
126*572ff6f6SMatthew Dillon /* Set ADC/DAC select values */
127*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);
128*572ff6f6SMatthew Dillon } else {
129*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
130*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
131*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
132*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
133*572ff6f6SMatthew Dillon IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
134*572ff6f6SMatthew Dillon }
135*572ff6f6SMatthew Dillon }
136*572ff6f6SMatthew Dillon }
137*572ff6f6SMatthew Dillon
138*572ff6f6SMatthew Dillon /*
139*572ff6f6SMatthew Dillon * If 32KHz clock exists, turn it off and turn back on the 32Mhz
140*572ff6f6SMatthew Dillon */
141*572ff6f6SMatthew Dillon void
ar5312RestoreClock(struct ath_hal * ah,HAL_OPMODE opmode)142*572ff6f6SMatthew Dillon ar5312RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
143*572ff6f6SMatthew Dillon {
144*572ff6f6SMatthew Dillon if (ar5212Use32KHzclock(ah, opmode)) {
145*572ff6f6SMatthew Dillon /* # Set sleep clock rate back to 32 MHz. */
146*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */
147*572ff6f6SMatthew Dillon OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
148*572ff6f6SMatthew Dillon IS_RAD5112_ANY(ah) ? 39 : 31);
149*572ff6f6SMatthew Dillon
150*572ff6f6SMatthew Dillon /*
151*572ff6f6SMatthew Dillon * Restore BB registers to power-on defaults
152*572ff6f6SMatthew Dillon */
153*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
154*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
155*572ff6f6SMatthew Dillon if (IS_5312_2_X(ah)) {
156*572ff6f6SMatthew Dillon /* Set ADC/DAC select values */
157*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);
158*572ff6f6SMatthew Dillon } else {
159*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
160*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
161*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
162*572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
163*572ff6f6SMatthew Dillon IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
164*572ff6f6SMatthew Dillon }
165*572ff6f6SMatthew Dillon }
166*572ff6f6SMatthew Dillon }
167*572ff6f6SMatthew Dillon
168*572ff6f6SMatthew Dillon #endif /* AH_SUPPORT_AR5312 */
169