1*572ff6f6SMatthew Dillon /* 2*572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3*572ff6f6SMatthew Dillon * Copyright (c) 2002-2004 Atheros Communications, Inc. 4*572ff6f6SMatthew Dillon * 5*572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any 6*572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above 7*572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies. 8*572ff6f6SMatthew Dillon * 9*572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10*572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11*572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12*572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13*572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14*572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15*572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16*572ff6f6SMatthew Dillon * 17*572ff6f6SMatthew Dillon * $FreeBSD$ 18*572ff6f6SMatthew Dillon */ 19*572ff6f6SMatthew Dillon #ifndef _DEV_ATH_AR5210PHY_H 20*572ff6f6SMatthew Dillon #define _DEV_ATH_AR5210PHY_H 21*572ff6f6SMatthew Dillon 22*572ff6f6SMatthew Dillon /* 23*572ff6f6SMatthew Dillon * Definitions for the PHY on the Atheros AR5210 parts. 24*572ff6f6SMatthew Dillon */ 25*572ff6f6SMatthew Dillon 26*572ff6f6SMatthew Dillon /* PHY Registers */ 27*572ff6f6SMatthew Dillon #define AR_PHY_BASE 0x9800 /* PHY register base */ 28*572ff6f6SMatthew Dillon #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 29*572ff6f6SMatthew Dillon 30*572ff6f6SMatthew Dillon #define AR_PHY_FRCTL 0x9804 /* PHY frame control */ 31*572ff6f6SMatthew Dillon #define AR_PHY_TURBO_MODE 0x00000001 /* PHY turbo mode */ 32*572ff6f6SMatthew Dillon #define AR_PHY_TURBO_SHORT 0x00000002 /* PHY turbo short symbol */ 33*572ff6f6SMatthew Dillon #define AR_PHY_TIMING_ERR 0x01000000 /* Detect PHY timing error */ 34*572ff6f6SMatthew Dillon #define AR_PHY_PARITY_ERR 0x02000000 /* Detect signal parity err */ 35*572ff6f6SMatthew Dillon #define AR_PHY_ILLRATE_ERR 0x04000000 /* Detect PHY illegal rate */ 36*572ff6f6SMatthew Dillon #define AR_PHY_ILLLEN_ERR 0x08000000 /* Detect PHY illegal length */ 37*572ff6f6SMatthew Dillon #define AR_PHY_SERVICE_ERR 0x20000000 /* Detect PHY nonzero service */ 38*572ff6f6SMatthew Dillon #define AR_PHY_TXURN_ERR 0x40000000 /* DetectPHY TX underrun */ 39*572ff6f6SMatthew Dillon #define AR_PHY_FRCTL_BITS \ 40*572ff6f6SMatthew Dillon "\20\1TURBO_MODE\2TURBO_SHORT\30TIMING_ERR\31PARITY_ERR\32ILLRATE_ERR"\ 41*572ff6f6SMatthew Dillon "\33ILLEN_ERR\35SERVICE_ERR\36TXURN_ERR" 42*572ff6f6SMatthew Dillon 43*572ff6f6SMatthew Dillon #define AR_PHY_AGC 0x9808 /* PHY AGC command */ 44*572ff6f6SMatthew Dillon #define AR_PHY_AGC_DISABLE 0x08000000 /* Disable PHY AGC */ 45*572ff6f6SMatthew Dillon #define AR_PHY_AGC_BITS "\20\33DISABLE" 46*572ff6f6SMatthew Dillon 47*572ff6f6SMatthew Dillon #define AR_PHY_CHIPID 0x9818 /* PHY chip revision */ 48*572ff6f6SMatthew Dillon 49*572ff6f6SMatthew Dillon #define AR_PHY_ACTIVE 0x981c /* PHY activation */ 50*572ff6f6SMatthew Dillon #define AR_PHY_ENABLE 0x00000001 /* activate PHY */ 51*572ff6f6SMatthew Dillon #define AR_PHY_DISABLE 0x00000002 /* deactivate PHY */ 52*572ff6f6SMatthew Dillon #define AR_PHY_ACTIVE_BITS "\20\1ENABLE\2DISABLE" 53*572ff6f6SMatthew Dillon 54*572ff6f6SMatthew Dillon #define AR_PHY_AGCCTL 0x9860 /* PHY calibration and noise floor */ 55*572ff6f6SMatthew Dillon #define AR_PHY_AGC_CAL 0x00000001 /* PHY internal calibration */ 56*572ff6f6SMatthew Dillon #define AR_PHY_AGC_NF 0x00000002 /* calc PHY noise-floor */ 57*572ff6f6SMatthew Dillon #define AR_PHY_AGCCTL_BITS "\20\1CAL\2NF" 58*572ff6f6SMatthew Dillon 59*572ff6f6SMatthew Dillon #endif /* _DEV_ATH_AR5210PHY_H */ 60