1572ff6f6SMatthew Dillon /* 2572ff6f6SMatthew Dillon * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3572ff6f6SMatthew Dillon * Copyright (c) 2002-2004 Atheros Communications, Inc. 4572ff6f6SMatthew Dillon * 5572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any 6572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above 7572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies. 8572ff6f6SMatthew Dillon * 9572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16572ff6f6SMatthew Dillon * 17572ff6f6SMatthew Dillon * $FreeBSD$ 18572ff6f6SMatthew Dillon */ 19572ff6f6SMatthew Dillon #ifndef _ATH_AR5210_H_ 20572ff6f6SMatthew Dillon #define _ATH_AR5210_H_ 21572ff6f6SMatthew Dillon 22572ff6f6SMatthew Dillon #define AR5210_MAGIC 0x19980124 23572ff6f6SMatthew Dillon 24572ff6f6SMatthew Dillon #if 0 25572ff6f6SMatthew Dillon /* 26572ff6f6SMatthew Dillon * RTS_ENABLE includes LONG_PKT because they essentially 27572ff6f6SMatthew Dillon * imply the same thing, and are set or not set together 28572ff6f6SMatthew Dillon * for this chip 29572ff6f6SMatthew Dillon */ 30572ff6f6SMatthew Dillon #define AR5210_TXD_CTRL_A_HDR_LEN(_val) (((_val) ) & 0x0003f) 31572ff6f6SMatthew Dillon #define AR5210_TXD_CTRL_A_TX_RATE(_val) (((_val) << 6) & 0x003c0) 32572ff6f6SMatthew Dillon #define AR5210_TXD_CTRL_A_RTS_ENABLE ( 0x00c00) 33572ff6f6SMatthew Dillon #define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000) 34572ff6f6SMatthew Dillon #define AR5210_TXD_CTRL_A_ANT_MODE(_val) (((_val) << 13) & 0x02000) 35572ff6f6SMatthew Dillon #define AR5210_TXD_CTRL_A_PKT_TYPE(_val) (((_val) << 14) & 0x1c000) 36572ff6f6SMatthew Dillon #define AR5210_TXD_CTRL_A_INT_REQ ( 0x20000) 37572ff6f6SMatthew Dillon #define AR5210_TXD_CTRL_A_KEY_VALID ( 0x40000) 38572ff6f6SMatthew Dillon #define AR5210_TXD_CTRL_B_KEY_ID(_val) (((_val) ) & 0x0003f) 39572ff6f6SMatthew Dillon #define AR5210_TXD_CTRL_B_RTS_DURATION(_val) (((_val) << 6) & 0x7ffc0) 40572ff6f6SMatthew Dillon #endif 41572ff6f6SMatthew Dillon 42572ff6f6SMatthew Dillon #define INIT_CONFIG_STATUS 0x00000000 43572ff6f6SMatthew Dillon #define INIT_ACKTOPS 0x00000008 44572ff6f6SMatthew Dillon #define INIT_BCON_CNTRL_REG 0x00000000 45572ff6f6SMatthew Dillon #define INIT_SLOT_TIME 0x00000168 46572ff6f6SMatthew Dillon #define INIT_SLOT_TIME_TURBO 0x000001e0 /* More aggressive turbo slot timing = 6 us */ 47572ff6f6SMatthew Dillon #define INIT_ACK_CTS_TIMEOUT 0x04000400 48572ff6f6SMatthew Dillon #define INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 49572ff6f6SMatthew Dillon 50572ff6f6SMatthew Dillon #define INIT_USEC 0x27 51572ff6f6SMatthew Dillon #define INIT_USEC_TURBO 0x4f 52572ff6f6SMatthew Dillon #define INIT_USEC_32 0x1f 53572ff6f6SMatthew Dillon #define INIT_TX_LATENCY 0x36 54572ff6f6SMatthew Dillon #define INIT_RX_LATENCY 0x1D 55572ff6f6SMatthew Dillon #define INIT_TRANSMIT_LATENCY \ 56572ff6f6SMatthew Dillon ((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \ 57572ff6f6SMatthew Dillon (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \ 58572ff6f6SMatthew Dillon (INIT_USEC_32 << 7) | INIT_USEC ) 59572ff6f6SMatthew Dillon #define INIT_TRANSMIT_LATENCY_TURBO \ 60572ff6f6SMatthew Dillon ((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \ 61572ff6f6SMatthew Dillon (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \ 62572ff6f6SMatthew Dillon (INIT_USEC_32 << 7) | INIT_USEC_TURBO) 63572ff6f6SMatthew Dillon 64572ff6f6SMatthew Dillon #define INIT_SIFS 0x230 /* = 16 us - 2 us */ 65572ff6f6SMatthew Dillon #define INIT_SIFS_TURBO 0x1E0 /* More aggressive turbo SIFS timing - 8 us - 2 us */ 66572ff6f6SMatthew Dillon 67572ff6f6SMatthew Dillon /* 68572ff6f6SMatthew Dillon * Various fifo fill before Tx start, in 64-byte units 69572ff6f6SMatthew Dillon * i.e. put the frame in the air while still DMAing 70572ff6f6SMatthew Dillon */ 71572ff6f6SMatthew Dillon #define MIN_TX_FIFO_THRESHOLD 0x1 72572ff6f6SMatthew Dillon #define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1) 73572ff6f6SMatthew Dillon 74572ff6f6SMatthew Dillon #define INIT_NEXT_CFP_START 0xffffffff 75572ff6f6SMatthew Dillon 76572ff6f6SMatthew Dillon #define INIT_BEACON_PERIOD 0xffff 77572ff6f6SMatthew Dillon #define INIT_BEACON_EN 0 /* this should be set by AP only when it's ready */ 78572ff6f6SMatthew Dillon #define INIT_BEACON_CONTROL \ 79572ff6f6SMatthew Dillon ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \ 80572ff6f6SMatthew Dillon (INIT_TIM_OFFSET<<16) | INIT_BEACON_PERIOD) 81572ff6f6SMatthew Dillon 82572ff6f6SMatthew Dillon #define INIT_RSSI_THR 0x00000700 /* Missed beacon counter initialized to max value of 7 */ 83572ff6f6SMatthew Dillon #define INIT_ProgIFS 0x398 /* PIFS - 2us */ 84572ff6f6SMatthew Dillon #define INIT_ProgIFS_TURBO 0x3C0 85572ff6f6SMatthew Dillon #define INIT_EIFS 0xd70 86572ff6f6SMatthew Dillon #define INIT_EIFS_TURBO 0x1ae0 87572ff6f6SMatthew Dillon #define INIT_CARR_SENSE_EN 1 88572ff6f6SMatthew Dillon #define INIT_PROTO_TIME_CNTRL ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS << 12) | \ 89572ff6f6SMatthew Dillon (INIT_ProgIFS) ) 90572ff6f6SMatthew Dillon #define INIT_PROTO_TIME_CNTRL_TURBO ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS_TURBO << 12) | \ 91572ff6f6SMatthew Dillon (INIT_ProgIFS_TURBO) ) 92572ff6f6SMatthew Dillon 93572ff6f6SMatthew Dillon #define AR5210_MAX_RATE_POWER 60 94572ff6f6SMatthew Dillon 95572ff6f6SMatthew Dillon #undef HAL_NUM_TX_QUEUES /* from ah.h */ 96572ff6f6SMatthew Dillon #define HAL_NUM_TX_QUEUES 3 97572ff6f6SMatthew Dillon 98572ff6f6SMatthew Dillon struct ath_hal_5210 { 99572ff6f6SMatthew Dillon struct ath_hal_private ah_priv; /* base definitions */ 100572ff6f6SMatthew Dillon 101572ff6f6SMatthew Dillon uint8_t ah_macaddr[IEEE80211_ADDR_LEN]; 102572ff6f6SMatthew Dillon /* 103572ff6f6SMatthew Dillon * Runtime state. 104572ff6f6SMatthew Dillon */ 105572ff6f6SMatthew Dillon uint32_t ah_maskReg; /* shadow of IMR+IER regs */ 106572ff6f6SMatthew Dillon uint32_t ah_txOkInterruptMask; 107572ff6f6SMatthew Dillon uint32_t ah_txErrInterruptMask; 108572ff6f6SMatthew Dillon uint32_t ah_txDescInterruptMask; 109572ff6f6SMatthew Dillon uint32_t ah_txEolInterruptMask; 110572ff6f6SMatthew Dillon uint32_t ah_txUrnInterruptMask; 111572ff6f6SMatthew Dillon uint8_t ah_bssid[IEEE80211_ADDR_LEN]; 112572ff6f6SMatthew Dillon HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */ 113572ff6f6SMatthew Dillon /* 114572ff6f6SMatthew Dillon * Station mode support. 115572ff6f6SMatthew Dillon */ 116572ff6f6SMatthew Dillon uint32_t ah_staId1Defaults; /* STA_ID1 default settings */ 117572ff6f6SMatthew Dillon uint32_t ah_rssiThr; /* RSSI_THR settings */ 118572ff6f6SMatthew Dillon 119572ff6f6SMatthew Dillon u_int ah_sifstime; /* user-specified sifs time */ 120572ff6f6SMatthew Dillon u_int ah_slottime; /* user-specified slot time */ 121572ff6f6SMatthew Dillon u_int ah_acktimeout; /* user-specified ack timeout */ 122572ff6f6SMatthew Dillon u_int ah_ctstimeout; /* user-specified cts timeout */ 123d98a0bcfSMatthew Dillon 124d98a0bcfSMatthew Dillon uint16_t ah_associd; /* association id */ 125572ff6f6SMatthew Dillon }; 126572ff6f6SMatthew Dillon #define AH5210(ah) ((struct ath_hal_5210 *)(ah)) 127572ff6f6SMatthew Dillon 128572ff6f6SMatthew Dillon struct ath_hal; 129572ff6f6SMatthew Dillon 130572ff6f6SMatthew Dillon extern void ar5210Detach(struct ath_hal *ah); 131572ff6f6SMatthew Dillon extern HAL_BOOL ar5210Reset(struct ath_hal *, HAL_OPMODE, 132*b14ca477SMatthew Dillon struct ieee80211_channel *, HAL_BOOL bChannelChange, 133*b14ca477SMatthew Dillon HAL_RESET_TYPE, HAL_STATUS *); 134572ff6f6SMatthew Dillon extern void ar5210SetPCUConfig(struct ath_hal *); 135572ff6f6SMatthew Dillon extern HAL_BOOL ar5210PhyDisable(struct ath_hal *); 136572ff6f6SMatthew Dillon extern HAL_BOOL ar5210Disable(struct ath_hal *); 137572ff6f6SMatthew Dillon extern HAL_BOOL ar5210ChipReset(struct ath_hal *, struct ieee80211_channel *); 138572ff6f6SMatthew Dillon extern HAL_BOOL ar5210PerCalibration(struct ath_hal *, struct ieee80211_channel *, HAL_BOOL *); 139572ff6f6SMatthew Dillon extern HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan, 140572ff6f6SMatthew Dillon u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone); 141572ff6f6SMatthew Dillon extern HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *); 142572ff6f6SMatthew Dillon extern int16_t ar5210GetNoiseFloor(struct ath_hal *); 143572ff6f6SMatthew Dillon extern int16_t ar5210GetNfAdjust(struct ath_hal *, 144572ff6f6SMatthew Dillon const HAL_CHANNEL_INTERNAL *); 145572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetTxPowerLimit(struct ath_hal *, uint32_t limit); 146572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetTransmitPower(struct ath_hal *, 147572ff6f6SMatthew Dillon const struct ieee80211_channel *); 148572ff6f6SMatthew Dillon extern HAL_BOOL ar5210CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 149572ff6f6SMatthew Dillon extern HAL_BOOL ar5210ResetDma(struct ath_hal *, HAL_OPMODE); 150572ff6f6SMatthew Dillon 151572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetTxQueueProps(struct ath_hal *ah, int q, 152572ff6f6SMatthew Dillon const HAL_TXQ_INFO *qInfo); 153572ff6f6SMatthew Dillon extern HAL_BOOL ar5210GetTxQueueProps(struct ath_hal *ah, int q, 154572ff6f6SMatthew Dillon HAL_TXQ_INFO *qInfo); 155572ff6f6SMatthew Dillon extern int ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, 156572ff6f6SMatthew Dillon const HAL_TXQ_INFO *qInfo); 157572ff6f6SMatthew Dillon extern HAL_BOOL ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q); 158572ff6f6SMatthew Dillon extern HAL_BOOL ar5210ResetTxQueue(struct ath_hal *ah, u_int q); 159572ff6f6SMatthew Dillon extern uint32_t ar5210GetTxDP(struct ath_hal *, u_int); 160572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetTxDP(struct ath_hal *, u_int, uint32_t txdp); 161572ff6f6SMatthew Dillon extern HAL_BOOL ar5210UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL); 162572ff6f6SMatthew Dillon extern uint32_t ar5210NumTxPending(struct ath_hal *, u_int); 163572ff6f6SMatthew Dillon extern HAL_BOOL ar5210StartTxDma(struct ath_hal *, u_int); 164572ff6f6SMatthew Dillon extern HAL_BOOL ar5210StopTxDma(struct ath_hal *, u_int); 165572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetupTxDesc(struct ath_hal *, struct ath_desc *, 166572ff6f6SMatthew Dillon u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, 167572ff6f6SMatthew Dillon u_int txRate0, u_int txRetries0, 168572ff6f6SMatthew Dillon u_int keyIx, u_int antMode, u_int flags, 169572ff6f6SMatthew Dillon u_int rtsctsRate, u_int rtsctsDuration, 170572ff6f6SMatthew Dillon u_int compicvLen, u_int compivLen, u_int comp); 171572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetupXTxDesc(struct ath_hal *, struct ath_desc *, 172572ff6f6SMatthew Dillon u_int txRate1, u_int txRetries1, 173572ff6f6SMatthew Dillon u_int txRate2, u_int txRetries2, 174572ff6f6SMatthew Dillon u_int txRate3, u_int txRetries3); 175572ff6f6SMatthew Dillon extern HAL_BOOL ar5210FillTxDesc(struct ath_hal *, struct ath_desc *, 176572ff6f6SMatthew Dillon HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 177572ff6f6SMatthew Dillon u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 178572ff6f6SMatthew Dillon const struct ath_desc *ds0); 179572ff6f6SMatthew Dillon extern HAL_STATUS ar5210ProcTxDesc(struct ath_hal *, 180572ff6f6SMatthew Dillon struct ath_desc *, struct ath_tx_status *); 181572ff6f6SMatthew Dillon extern void ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *); 182572ff6f6SMatthew Dillon extern void ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *); 183572ff6f6SMatthew Dillon extern HAL_BOOL ar5210GetTxCompletionRates(struct ath_hal *ah, 184572ff6f6SMatthew Dillon const struct ath_desc *, int *rates, int *tries); 185572ff6f6SMatthew Dillon extern void ar5210SetTxDescLink(struct ath_hal *ah, void *ds, 186572ff6f6SMatthew Dillon uint32_t link); 187572ff6f6SMatthew Dillon extern void ar5210GetTxDescLink(struct ath_hal *ah, void *ds, 188572ff6f6SMatthew Dillon uint32_t *link); 189572ff6f6SMatthew Dillon extern void ar5210GetTxDescLinkPtr(struct ath_hal *ah, void *ds, 190572ff6f6SMatthew Dillon uint32_t **linkptr); 191572ff6f6SMatthew Dillon 192572ff6f6SMatthew Dillon extern uint32_t ar5210GetRxDP(struct ath_hal *, HAL_RX_QUEUE); 193572ff6f6SMatthew Dillon extern void ar5210SetRxDP(struct ath_hal *, uint32_t rxdp, HAL_RX_QUEUE); 194572ff6f6SMatthew Dillon extern void ar5210EnableReceive(struct ath_hal *); 195572ff6f6SMatthew Dillon extern HAL_BOOL ar5210StopDmaReceive(struct ath_hal *); 196572ff6f6SMatthew Dillon extern void ar5210StartPcuReceive(struct ath_hal *); 197572ff6f6SMatthew Dillon extern void ar5210StopPcuReceive(struct ath_hal *); 198572ff6f6SMatthew Dillon extern void ar5210SetMulticastFilter(struct ath_hal *, 199572ff6f6SMatthew Dillon uint32_t filter0, uint32_t filter1); 200572ff6f6SMatthew Dillon extern HAL_BOOL ar5210ClrMulticastFilterIndex(struct ath_hal *, uint32_t); 201572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetMulticastFilterIndex(struct ath_hal *, uint32_t); 202572ff6f6SMatthew Dillon extern uint32_t ar5210GetRxFilter(struct ath_hal *); 203572ff6f6SMatthew Dillon extern void ar5210SetRxFilter(struct ath_hal *, uint32_t); 204572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetupRxDesc(struct ath_hal *, struct ath_desc *, 205572ff6f6SMatthew Dillon uint32_t, u_int flags); 206572ff6f6SMatthew Dillon extern HAL_STATUS ar5210ProcRxDesc(struct ath_hal *, struct ath_desc *, 207572ff6f6SMatthew Dillon uint32_t, struct ath_desc *, uint64_t, 208572ff6f6SMatthew Dillon struct ath_rx_status *); 209572ff6f6SMatthew Dillon 210572ff6f6SMatthew Dillon extern void ar5210GetMacAddress(struct ath_hal *, uint8_t *); 211572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *); 212572ff6f6SMatthew Dillon extern void ar5210GetBssIdMask(struct ath_hal *, uint8_t *); 213572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetBssIdMask(struct ath_hal *, const uint8_t *); 214572ff6f6SMatthew Dillon extern HAL_BOOL ar5210EepromRead(struct ath_hal *, u_int off, uint16_t *data); 215572ff6f6SMatthew Dillon extern HAL_BOOL ar5210EepromWrite(struct ath_hal *, u_int off, uint16_t data); 216572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetRegulatoryDomain(struct ath_hal *, 217572ff6f6SMatthew Dillon uint16_t, HAL_STATUS *); 218572ff6f6SMatthew Dillon extern u_int ar5210GetWirelessModes(struct ath_hal *ah); 219572ff6f6SMatthew Dillon extern void ar5210EnableRfKill(struct ath_hal *); 220572ff6f6SMatthew Dillon extern HAL_BOOL ar5210GpioCfgInput(struct ath_hal *, uint32_t gpio); 221572ff6f6SMatthew Dillon extern HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio, 222572ff6f6SMatthew Dillon HAL_GPIO_MUX_TYPE); 223572ff6f6SMatthew Dillon extern uint32_t ar5210GpioGet(struct ath_hal *, uint32_t gpio); 224572ff6f6SMatthew Dillon extern HAL_BOOL ar5210GpioSet(struct ath_hal *, uint32_t gpio, uint32_t); 225572ff6f6SMatthew Dillon extern void ar5210Gpio0SetIntr(struct ath_hal *, u_int, uint32_t ilevel); 226572ff6f6SMatthew Dillon extern void ar5210SetLedState(struct ath_hal *, HAL_LED_STATE); 227572ff6f6SMatthew Dillon extern u_int ar5210GetDefAntenna(struct ath_hal *); 228572ff6f6SMatthew Dillon extern void ar5210SetDefAntenna(struct ath_hal *, u_int); 229572ff6f6SMatthew Dillon extern HAL_ANT_SETTING ar5210GetAntennaSwitch(struct ath_hal *); 230572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); 231572ff6f6SMatthew Dillon extern void ar5210WriteAssocid(struct ath_hal *, 232572ff6f6SMatthew Dillon const uint8_t *bssid, uint16_t assocId); 233572ff6f6SMatthew Dillon extern uint32_t ar5210GetTsf32(struct ath_hal *); 234572ff6f6SMatthew Dillon extern uint64_t ar5210GetTsf64(struct ath_hal *); 235572ff6f6SMatthew Dillon extern void ar5210ResetTsf(struct ath_hal *); 236572ff6f6SMatthew Dillon extern uint32_t ar5210GetRandomSeed(struct ath_hal *); 237572ff6f6SMatthew Dillon extern HAL_BOOL ar5210DetectCardPresent(struct ath_hal *); 238572ff6f6SMatthew Dillon extern void ar5210UpdateMibCounters(struct ath_hal *, HAL_MIB_STATS *); 239572ff6f6SMatthew Dillon extern void ar5210EnableHwEncryption(struct ath_hal *); 240572ff6f6SMatthew Dillon extern void ar5210DisableHwEncryption(struct ath_hal *); 241572ff6f6SMatthew Dillon extern HAL_RFGAIN ar5210GetRfgain(struct ath_hal *); 242572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetSifsTime(struct ath_hal *, u_int); 243572ff6f6SMatthew Dillon extern u_int ar5210GetSifsTime(struct ath_hal *); 244572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetSlotTime(struct ath_hal *, u_int); 245572ff6f6SMatthew Dillon extern u_int ar5210GetSlotTime(struct ath_hal *); 246572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetAckTimeout(struct ath_hal *, u_int); 247572ff6f6SMatthew Dillon extern u_int ar5210GetAckTimeout(struct ath_hal *); 248572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetAckCTSRate(struct ath_hal *, u_int); 249572ff6f6SMatthew Dillon extern u_int ar5210GetAckCTSRate(struct ath_hal *); 250572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetCTSTimeout(struct ath_hal *, u_int); 251572ff6f6SMatthew Dillon extern u_int ar5210GetCTSTimeout(struct ath_hal *); 252572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetDecompMask(struct ath_hal *, uint16_t, int); 253572ff6f6SMatthew Dillon void ar5210SetCoverageClass(struct ath_hal *, uint8_t, int); 254572ff6f6SMatthew Dillon extern HAL_STATUS ar5210GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 255572ff6f6SMatthew Dillon uint32_t, uint32_t *); 256572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 257572ff6f6SMatthew Dillon uint32_t, uint32_t, HAL_STATUS *); 258572ff6f6SMatthew Dillon extern HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request, 259572ff6f6SMatthew Dillon const void *args, uint32_t argsize, 260572ff6f6SMatthew Dillon void **result, uint32_t *resultsize); 261572ff6f6SMatthew Dillon extern uint32_t ar5210Get11nExtBusy(struct ath_hal *); 262572ff6f6SMatthew Dillon extern HAL_BOOL ar5210GetMibCycleCounts(struct ath_hal *, 263572ff6f6SMatthew Dillon HAL_SURVEY_SAMPLE *); 264572ff6f6SMatthew Dillon extern void ar5210SetChainMasks(struct ath_hal *, uint32_t, uint32_t); 265572ff6f6SMatthew Dillon extern void ar5210EnableDfs(struct ath_hal *, HAL_PHYERR_PARAM *); 266572ff6f6SMatthew Dillon extern void ar5210GetDfsThresh(struct ath_hal *, HAL_PHYERR_PARAM *); 267572ff6f6SMatthew Dillon extern void ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val); 268572ff6f6SMatthew Dillon 269572ff6f6SMatthew Dillon extern u_int ar5210GetKeyCacheSize(struct ath_hal *); 270572ff6f6SMatthew Dillon extern HAL_BOOL ar5210IsKeyCacheEntryValid(struct ath_hal *, uint16_t); 271572ff6f6SMatthew Dillon extern HAL_BOOL ar5210ResetKeyCacheEntry(struct ath_hal *, uint16_t entry); 272572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetKeyCacheEntry(struct ath_hal *, uint16_t entry, 273572ff6f6SMatthew Dillon const HAL_KEYVAL *, const uint8_t *mac, int xorKey); 274572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetKeyCacheEntryMac(struct ath_hal *, 275572ff6f6SMatthew Dillon uint16_t, const uint8_t *); 276572ff6f6SMatthew Dillon 277572ff6f6SMatthew Dillon extern HAL_BOOL ar5210SetPowerMode(struct ath_hal *, uint32_t powerRequest, 278572ff6f6SMatthew Dillon int setChip); 279572ff6f6SMatthew Dillon extern HAL_POWER_MODE ar5210GetPowerMode(struct ath_hal *); 280572ff6f6SMatthew Dillon 281572ff6f6SMatthew Dillon extern void ar5210SetBeaconTimers(struct ath_hal *, 282572ff6f6SMatthew Dillon const HAL_BEACON_TIMERS *); 283572ff6f6SMatthew Dillon extern void ar5210BeaconInit(struct ath_hal *, uint32_t, uint32_t); 284572ff6f6SMatthew Dillon extern void ar5210SetStaBeaconTimers(struct ath_hal *, 285572ff6f6SMatthew Dillon const HAL_BEACON_STATE *); 286572ff6f6SMatthew Dillon extern void ar5210ResetStaBeaconTimers(struct ath_hal *); 287572ff6f6SMatthew Dillon extern uint64_t ar5210GetNextTBTT(struct ath_hal *); 288572ff6f6SMatthew Dillon 289572ff6f6SMatthew Dillon extern HAL_BOOL ar5210IsInterruptPending(struct ath_hal *); 290572ff6f6SMatthew Dillon extern HAL_BOOL ar5210GetPendingInterrupts(struct ath_hal *, HAL_INT *); 291572ff6f6SMatthew Dillon extern HAL_INT ar5210GetInterrupts(struct ath_hal *); 292572ff6f6SMatthew Dillon extern HAL_INT ar5210SetInterrupts(struct ath_hal *, HAL_INT ints); 293572ff6f6SMatthew Dillon 294572ff6f6SMatthew Dillon extern const HAL_RATE_TABLE *ar5210GetRateTable(struct ath_hal *, u_int mode); 295572ff6f6SMatthew Dillon 296572ff6f6SMatthew Dillon extern HAL_BOOL ar5210AniControl(struct ath_hal *, HAL_ANI_CMD, int ); 297572ff6f6SMatthew Dillon extern void ar5210AniPoll(struct ath_hal *, const struct ieee80211_channel *); 298572ff6f6SMatthew Dillon extern void ar5210RxMonitor(struct ath_hal *, const HAL_NODE_STATS *, 299572ff6f6SMatthew Dillon const struct ieee80211_channel *); 300572ff6f6SMatthew Dillon extern void ar5210MibEvent(struct ath_hal *, const HAL_NODE_STATS *); 301572ff6f6SMatthew Dillon #endif /* _ATH_AR5210_H_ */ 302