xref: /dflybsd-src/sys/dev/netif/ath/ath_hal/ah_eeprom_v1.h (revision 572ff6f6e8b95055988f178b6ba12ce77bb5b3c2)
1*572ff6f6SMatthew Dillon /*
2*572ff6f6SMatthew Dillon  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3*572ff6f6SMatthew Dillon  * Copyright (c) 2002-2008 Atheros Communications, Inc.
4*572ff6f6SMatthew Dillon  *
5*572ff6f6SMatthew Dillon  * Permission to use, copy, modify, and/or distribute this software for any
6*572ff6f6SMatthew Dillon  * purpose with or without fee is hereby granted, provided that the above
7*572ff6f6SMatthew Dillon  * copyright notice and this permission notice appear in all copies.
8*572ff6f6SMatthew Dillon  *
9*572ff6f6SMatthew Dillon  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10*572ff6f6SMatthew Dillon  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11*572ff6f6SMatthew Dillon  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12*572ff6f6SMatthew Dillon  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13*572ff6f6SMatthew Dillon  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14*572ff6f6SMatthew Dillon  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15*572ff6f6SMatthew Dillon  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16*572ff6f6SMatthew Dillon  *
17*572ff6f6SMatthew Dillon  * $FreeBSD$
18*572ff6f6SMatthew Dillon  */
19*572ff6f6SMatthew Dillon #ifndef _ATH_AH_EEPROM_V1_H_
20*572ff6f6SMatthew Dillon #define _ATH_AH_EEPROM_V1_H_
21*572ff6f6SMatthew Dillon 
22*572ff6f6SMatthew Dillon #include "ah_eeprom.h"
23*572ff6f6SMatthew Dillon 
24*572ff6f6SMatthew Dillon /*
25*572ff6f6SMatthew Dillon  * EEPROM defines for Version 1 Crete EEPROM.
26*572ff6f6SMatthew Dillon  *
27*572ff6f6SMatthew Dillon  * The EEPROM is segmented into three sections:
28*572ff6f6SMatthew Dillon  *
29*572ff6f6SMatthew Dillon  *    PCI/Cardbus default configuration settings
30*572ff6f6SMatthew Dillon  *    Cardbus CIS tuples and vendor-specific data
31*572ff6f6SMatthew Dillon  *    Atheros-specific data
32*572ff6f6SMatthew Dillon  *
33*572ff6f6SMatthew Dillon  * EEPROM entries are read 32-bits at a time through the PCI bus
34*572ff6f6SMatthew Dillon  * interface but are all 16-bit values.
35*572ff6f6SMatthew Dillon  *
36*572ff6f6SMatthew Dillon  * Access to the Atheros-specific data is controlled by protection
37*572ff6f6SMatthew Dillon  * bits and the data is checksum'd.  The driver reads the Atheros
38*572ff6f6SMatthew Dillon  * data from the EEPROM at attach and caches it in its private state.
39*572ff6f6SMatthew Dillon  * This data includes the local regulatory domain, channel calibration
40*572ff6f6SMatthew Dillon  * settings, and phy-related configuration settings.
41*572ff6f6SMatthew Dillon  */
42*572ff6f6SMatthew Dillon #define	AR_EEPROM_MAC(i)	(0x1f-(i))/* MAC address word */
43*572ff6f6SMatthew Dillon #define	AR_EEPROM_MAGIC		0x3d	/* magic number */
44*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT	0x3f	/* Atheros segment protect register */
45*572ff6f6SMatthew Dillon #define	AR_EEPROM_PROTOTECT_WP_128_191	0x80
46*572ff6f6SMatthew Dillon #define AR_EEPROM_REG_DOMAIN	0xbf	/* Current regulatory domain register */
47*572ff6f6SMatthew Dillon #define AR_EEPROM_ATHEROS_BASE	0xc0	/* Base of Atheros-specific data */
48*572ff6f6SMatthew Dillon #define AR_EEPROM_ATHEROS_MAX	64	/* 64x2=128 bytes of EEPROM settings */
49*572ff6f6SMatthew Dillon #define	AR_EEPROM_ATHEROS(n)	(AR_EEPROM_ATHEROS_BASE+(n))
50*572ff6f6SMatthew Dillon #define	AR_EEPROM_VERSION	AR_EEPROM_ATHEROS(1)
51*572ff6f6SMatthew Dillon #define AR_EEPROM_ATHEROS_TP_SETTINGS	0x09	/* Transmit power settings */
52*572ff6f6SMatthew Dillon #define AR_REG_DOMAINS_MAX	4	/* # of Regulatory Domains */
53*572ff6f6SMatthew Dillon #define AR_CHANNELS_MAX		5	/* # of Channel calibration groups */
54*572ff6f6SMatthew Dillon #define AR_TP_SETTINGS_SIZE	11	/* # locations/Channel group */
55*572ff6f6SMatthew Dillon #define AR_TP_SCALING_ENTRIES	11	/* # entries in transmit power dBm->pcdac */
56*572ff6f6SMatthew Dillon 
57*572ff6f6SMatthew Dillon /*
58*572ff6f6SMatthew Dillon  * NB: we store the rfsilent select+polarity data packed
59*572ff6f6SMatthew Dillon  *     with the encoding used in later parts so values
60*572ff6f6SMatthew Dillon  *     returned to applications are consistent.
61*572ff6f6SMatthew Dillon  */
62*572ff6f6SMatthew Dillon #define AR_EEPROM_RFSILENT_GPIO_SEL	0x001c
63*572ff6f6SMatthew Dillon #define AR_EEPROM_RFSILENT_GPIO_SEL_S	2
64*572ff6f6SMatthew Dillon #define AR_EEPROM_RFSILENT_POLARITY	0x0002
65*572ff6f6SMatthew Dillon #define AR_EEPROM_RFSILENT_POLARITY_S	1
66*572ff6f6SMatthew Dillon 
67*572ff6f6SMatthew Dillon #define AR_I2DBM(x)	((uint8_t)((x * 2) + 3))
68*572ff6f6SMatthew Dillon 
69*572ff6f6SMatthew Dillon /*
70*572ff6f6SMatthew Dillon  * Transmit power and channel calibration settings.
71*572ff6f6SMatthew Dillon  */
72*572ff6f6SMatthew Dillon struct tpcMap {
73*572ff6f6SMatthew Dillon 	uint8_t		pcdac[AR_TP_SCALING_ENTRIES];
74*572ff6f6SMatthew Dillon 	uint8_t		gainF[AR_TP_SCALING_ENTRIES];
75*572ff6f6SMatthew Dillon 	uint8_t		rate36;
76*572ff6f6SMatthew Dillon 	uint8_t		rate48;
77*572ff6f6SMatthew Dillon 	uint8_t		rate54;
78*572ff6f6SMatthew Dillon 	uint8_t		regdmn[AR_REG_DOMAINS_MAX];
79*572ff6f6SMatthew Dillon };
80*572ff6f6SMatthew Dillon 
81*572ff6f6SMatthew Dillon /*
82*572ff6f6SMatthew Dillon  * Information retrieved from EEPROM.
83*572ff6f6SMatthew Dillon  */
84*572ff6f6SMatthew Dillon typedef struct {
85*572ff6f6SMatthew Dillon 	uint16_t	ee_version;		/* Version field */
86*572ff6f6SMatthew Dillon 	uint16_t	ee_protect;		/* EEPROM protect field */
87*572ff6f6SMatthew Dillon 	uint16_t	ee_antenna;		/* Antenna Settings */
88*572ff6f6SMatthew Dillon 	uint16_t	ee_biasCurrents;	/* OB, DB */
89*572ff6f6SMatthew Dillon 	uint8_t		ee_thresh62;		/* thresh62 */
90*572ff6f6SMatthew Dillon 	uint8_t		ee_xlnaOn;		/* External LNA timing */
91*572ff6f6SMatthew Dillon 	uint8_t		ee_xpaOff;		/* Extern output stage timing */
92*572ff6f6SMatthew Dillon 	uint8_t		ee_xpaOn;		/* Extern output stage timing */
93*572ff6f6SMatthew Dillon 	uint8_t		ee_rfKill;		/* Single low bit signalling if RF Kill is implemented */
94*572ff6f6SMatthew Dillon 	uint8_t		ee_devType;		/* Type: PCI, miniPCI, CB */
95*572ff6f6SMatthew Dillon 	uint8_t		ee_regDomain[AR_REG_DOMAINS_MAX];
96*572ff6f6SMatthew Dillon 						/* calibrated reg domains */
97*572ff6f6SMatthew Dillon 	struct tpcMap	ee_tpc[AR_CHANNELS_MAX];
98*572ff6f6SMatthew Dillon } HAL_EEPROM_v1;
99*572ff6f6SMatthew Dillon #endif /* _ATH_AH_EEPROM_V1_H_ */
100