xref: /dflybsd-src/sys/dev/netif/ath/ath_hal/ah_eeprom_9287.h (revision 572ff6f6e8b95055988f178b6ba12ce77bb5b3c2)
1*572ff6f6SMatthew Dillon /*
2*572ff6f6SMatthew Dillon  * Copyright (c) 2008-2009 Atheros Communications Inc.
3*572ff6f6SMatthew Dillon  *
4*572ff6f6SMatthew Dillon  * Permission to use, copy, modify, and/or distribute this software for any
5*572ff6f6SMatthew Dillon  * purpose with or without fee is hereby granted, provided that the above
6*572ff6f6SMatthew Dillon  * copyright notice and this permission notice appear in all copies.
7*572ff6f6SMatthew Dillon  *
8*572ff6f6SMatthew Dillon  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*572ff6f6SMatthew Dillon  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*572ff6f6SMatthew Dillon  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11*572ff6f6SMatthew Dillon  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*572ff6f6SMatthew Dillon  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13*572ff6f6SMatthew Dillon  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14*572ff6f6SMatthew Dillon  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*572ff6f6SMatthew Dillon  *
16*572ff6f6SMatthew Dillon  * $FreeBSD$
17*572ff6f6SMatthew Dillon  */
18*572ff6f6SMatthew Dillon 
19*572ff6f6SMatthew Dillon #ifndef	__AH_EEPROM_9287_H__
20*572ff6f6SMatthew Dillon #define	__AH_EEPROM_9287_H__
21*572ff6f6SMatthew Dillon 
22*572ff6f6SMatthew Dillon #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
23*572ff6f6SMatthew Dillon 				 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
24*572ff6f6SMatthew Dillon 
25*572ff6f6SMatthew Dillon #define AR9287_EEP_VER               0xE
26*572ff6f6SMatthew Dillon #define AR9287_EEP_VER_MINOR_MASK    0xFFF
27*572ff6f6SMatthew Dillon #define AR9287_EEP_MINOR_VER_1       0x1
28*572ff6f6SMatthew Dillon #define AR9287_EEP_MINOR_VER_2       0x2
29*572ff6f6SMatthew Dillon #define AR9287_EEP_MINOR_VER_3       0x3
30*572ff6f6SMatthew Dillon #define AR9287_EEP_MINOR_VER         AR9287_EEP_MINOR_VER_3
31*572ff6f6SMatthew Dillon #define AR9287_EEP_MINOR_VER_b       AR9287_EEP_MINOR_VER
32*572ff6f6SMatthew Dillon #define AR9287_EEP_NO_BACK_VER       AR9287_EEP_MINOR_VER_1
33*572ff6f6SMatthew Dillon 
34*572ff6f6SMatthew Dillon #define	AR9287_RDEXT_DEFAULT		0x1F
35*572ff6f6SMatthew Dillon 
36*572ff6f6SMatthew Dillon #define AR9287_EEP_START_LOC            128
37*572ff6f6SMatthew Dillon #define AR9287_HTC_EEP_START_LOC        256
38*572ff6f6SMatthew Dillon #define AR9287_NUM_2G_CAL_PIERS         3
39*572ff6f6SMatthew Dillon #define AR9287_NUM_2G_CCK_TARGET_POWERS 3
40*572ff6f6SMatthew Dillon #define AR9287_NUM_2G_20_TARGET_POWERS  3
41*572ff6f6SMatthew Dillon #define AR9287_NUM_2G_40_TARGET_POWERS  3
42*572ff6f6SMatthew Dillon #define AR9287_NUM_CTLS              	12
43*572ff6f6SMatthew Dillon #define AR9287_NUM_BAND_EDGES        	4
44*572ff6f6SMatthew Dillon #define AR9287_PD_GAIN_ICEPTS           1
45*572ff6f6SMatthew Dillon #define AR9287_EEPMISC_BIG_ENDIAN       0x01
46*572ff6f6SMatthew Dillon #define AR9287_EEPMISC_WOW              0x02
47*572ff6f6SMatthew Dillon #define AR9287_MAX_CHAINS               2
48*572ff6f6SMatthew Dillon #define AR9287_ANT_16S                  32
49*572ff6f6SMatthew Dillon 
50*572ff6f6SMatthew Dillon #define AR9287_DATA_SZ                  32
51*572ff6f6SMatthew Dillon 
52*572ff6f6SMatthew Dillon #define AR9287_PWR_TABLE_OFFSET_DB  -5
53*572ff6f6SMatthew Dillon 
54*572ff6f6SMatthew Dillon #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
55*572ff6f6SMatthew Dillon 
56*572ff6f6SMatthew Dillon struct base_eep_ar9287_header {
57*572ff6f6SMatthew Dillon 	uint16_t version;		/* Swapped w/ length; check ah_eeprom_v14.h */
58*572ff6f6SMatthew Dillon 	uint16_t checksum;
59*572ff6f6SMatthew Dillon 	uint16_t length;
60*572ff6f6SMatthew Dillon 	uint8_t opCapFlags;
61*572ff6f6SMatthew Dillon 	uint8_t eepMisc;
62*572ff6f6SMatthew Dillon 	uint16_t regDmn[2];
63*572ff6f6SMatthew Dillon 	uint8_t macAddr[6];
64*572ff6f6SMatthew Dillon 	uint8_t rxMask;
65*572ff6f6SMatthew Dillon 	uint8_t txMask;
66*572ff6f6SMatthew Dillon 	uint16_t rfSilent;
67*572ff6f6SMatthew Dillon 	uint16_t blueToothOptions;
68*572ff6f6SMatthew Dillon 	uint16_t deviceCap;
69*572ff6f6SMatthew Dillon 	uint32_t binBuildNumber;
70*572ff6f6SMatthew Dillon 	uint8_t deviceType;
71*572ff6f6SMatthew Dillon 	uint8_t openLoopPwrCntl;
72*572ff6f6SMatthew Dillon 	int8_t pwrTableOffset;
73*572ff6f6SMatthew Dillon 	int8_t tempSensSlope;
74*572ff6f6SMatthew Dillon 	int8_t tempSensSlopePalOn;
75*572ff6f6SMatthew Dillon 	uint8_t futureBase[29];
76*572ff6f6SMatthew Dillon } __packed;
77*572ff6f6SMatthew Dillon 
78*572ff6f6SMatthew Dillon struct modal_eep_ar9287_header {
79*572ff6f6SMatthew Dillon 	uint32_t antCtrlChain[AR9287_MAX_CHAINS];
80*572ff6f6SMatthew Dillon 	uint32_t antCtrlCommon;
81*572ff6f6SMatthew Dillon 	int8_t antennaGainCh[AR9287_MAX_CHAINS];
82*572ff6f6SMatthew Dillon 	uint8_t switchSettling;
83*572ff6f6SMatthew Dillon 	uint8_t txRxAttenCh[AR9287_MAX_CHAINS];
84*572ff6f6SMatthew Dillon 	uint8_t rxTxMarginCh[AR9287_MAX_CHAINS];
85*572ff6f6SMatthew Dillon 	int8_t adcDesiredSize;
86*572ff6f6SMatthew Dillon 	uint8_t txEndToXpaOff;
87*572ff6f6SMatthew Dillon 	uint8_t txEndToRxOn;
88*572ff6f6SMatthew Dillon 	uint8_t txFrameToXpaOn;
89*572ff6f6SMatthew Dillon 	uint8_t thresh62;
90*572ff6f6SMatthew Dillon 	int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
91*572ff6f6SMatthew Dillon 	uint8_t xpdGain;
92*572ff6f6SMatthew Dillon 	uint8_t xpd;
93*572ff6f6SMatthew Dillon 	int8_t iqCalICh[AR9287_MAX_CHAINS];
94*572ff6f6SMatthew Dillon 	int8_t iqCalQCh[AR9287_MAX_CHAINS];
95*572ff6f6SMatthew Dillon 	uint8_t pdGainOverlap;
96*572ff6f6SMatthew Dillon 	uint8_t xpaBiasLvl;
97*572ff6f6SMatthew Dillon 	uint8_t txFrameToDataStart;
98*572ff6f6SMatthew Dillon 	uint8_t txFrameToPaOn;
99*572ff6f6SMatthew Dillon 	uint8_t ht40PowerIncForPdadc;
100*572ff6f6SMatthew Dillon 	uint8_t bswAtten[AR9287_MAX_CHAINS];
101*572ff6f6SMatthew Dillon 	uint8_t bswMargin[AR9287_MAX_CHAINS];
102*572ff6f6SMatthew Dillon 	uint8_t swSettleHt40;
103*572ff6f6SMatthew Dillon 	uint8_t version;
104*572ff6f6SMatthew Dillon 	uint8_t db1;
105*572ff6f6SMatthew Dillon 	uint8_t db2;
106*572ff6f6SMatthew Dillon 	uint8_t ob_cck;
107*572ff6f6SMatthew Dillon 	uint8_t ob_psk;
108*572ff6f6SMatthew Dillon 	uint8_t ob_qam;
109*572ff6f6SMatthew Dillon 	uint8_t ob_pal_off;
110*572ff6f6SMatthew Dillon 	uint8_t futureModal[30];
111*572ff6f6SMatthew Dillon 	SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS];
112*572ff6f6SMatthew Dillon } __packed;
113*572ff6f6SMatthew Dillon 
114*572ff6f6SMatthew Dillon struct cal_data_op_loop_ar9287 {
115*572ff6f6SMatthew Dillon 	uint8_t pwrPdg[2][5];
116*572ff6f6SMatthew Dillon 	uint8_t vpdPdg[2][5];
117*572ff6f6SMatthew Dillon 	uint8_t pcdac[2][5];
118*572ff6f6SMatthew Dillon 	uint8_t empty[2][5];
119*572ff6f6SMatthew Dillon } __packed;
120*572ff6f6SMatthew Dillon 
121*572ff6f6SMatthew Dillon struct cal_data_per_freq_ar9287 {
122*572ff6f6SMatthew Dillon 	uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
123*572ff6f6SMatthew Dillon 	uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
124*572ff6f6SMatthew Dillon } __packed;
125*572ff6f6SMatthew Dillon 
126*572ff6f6SMatthew Dillon union cal_data_per_freq_ar9287_u {
127*572ff6f6SMatthew Dillon 	struct cal_data_op_loop_ar9287 calDataOpen;
128*572ff6f6SMatthew Dillon 	struct cal_data_per_freq_ar9287 calDataClose;
129*572ff6f6SMatthew Dillon } __packed;
130*572ff6f6SMatthew Dillon 
131*572ff6f6SMatthew Dillon struct cal_ctl_data_ar9287 {
132*572ff6f6SMatthew Dillon 	CAL_CTL_EDGES ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
133*572ff6f6SMatthew Dillon } __packed;
134*572ff6f6SMatthew Dillon 
135*572ff6f6SMatthew Dillon struct ar9287_eeprom {
136*572ff6f6SMatthew Dillon 	struct base_eep_ar9287_header baseEepHeader;
137*572ff6f6SMatthew Dillon 	uint8_t custData[AR9287_DATA_SZ];
138*572ff6f6SMatthew Dillon 	struct modal_eep_ar9287_header modalHeader;
139*572ff6f6SMatthew Dillon 	uint8_t calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
140*572ff6f6SMatthew Dillon 	union cal_data_per_freq_ar9287_u
141*572ff6f6SMatthew Dillon 	    calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
142*572ff6f6SMatthew Dillon 	CAL_TARGET_POWER_LEG
143*572ff6f6SMatthew Dillon 	    calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
144*572ff6f6SMatthew Dillon 	CAL_TARGET_POWER_LEG
145*572ff6f6SMatthew Dillon 	    calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
146*572ff6f6SMatthew Dillon 	CAL_TARGET_POWER_HT
147*572ff6f6SMatthew Dillon 	    calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
148*572ff6f6SMatthew Dillon 	CAL_TARGET_POWER_HT
149*572ff6f6SMatthew Dillon 	    calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
150*572ff6f6SMatthew Dillon 	uint8_t ctlIndex[AR9287_NUM_CTLS];
151*572ff6f6SMatthew Dillon 	struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
152*572ff6f6SMatthew Dillon 	uint8_t padding;
153*572ff6f6SMatthew Dillon } __packed;
154*572ff6f6SMatthew Dillon 
155*572ff6f6SMatthew Dillon typedef struct {
156*572ff6f6SMatthew Dillon         struct ar9287_eeprom ee_base;
157*572ff6f6SMatthew Dillon #define NUM_EDGES        8
158*572ff6f6SMatthew Dillon         uint16_t        ee_numCtls;
159*572ff6f6SMatthew Dillon         RD_EDGES_POWER  ee_rdEdgesPower[NUM_EDGES*AR9287_NUM_CTLS];
160*572ff6f6SMatthew Dillon         /* XXX these are dynamically calculated for use by shared code */
161*572ff6f6SMatthew Dillon         int8_t          ee_antennaGainMax[2];
162*572ff6f6SMatthew Dillon } HAL_EEPROM_9287;
163*572ff6f6SMatthew Dillon 
164*572ff6f6SMatthew Dillon typedef struct modal_eep_ar9287_header MODAL_EEP_9287_HEADER;
165*572ff6f6SMatthew Dillon typedef struct base_eep_ar9287_header BASE_EEP_9287_HEADER;
166*572ff6f6SMatthew Dillon 
167*572ff6f6SMatthew Dillon 
168*572ff6f6SMatthew Dillon #endif /* __AH_EEPROM_9287_H__ */
169