1572ff6f6SMatthew Dillon /* 2572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc. 4572ff6f6SMatthew Dillon * 5572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any 6572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above 7572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies. 8572ff6f6SMatthew Dillon * 9572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16572ff6f6SMatthew Dillon * 17572ff6f6SMatthew Dillon * $FreeBSD$ 18572ff6f6SMatthew Dillon */ 19572ff6f6SMatthew Dillon #ifndef _ATH_AH_DECODE_H_ 20572ff6f6SMatthew Dillon #define _ATH_AH_DECODE_H_ 21572ff6f6SMatthew Dillon /* 22572ff6f6SMatthew Dillon * Register tracing support. 23572ff6f6SMatthew Dillon * 24572ff6f6SMatthew Dillon * Setting hw.ath.hal.alq=1 enables tracing of all register reads and 25572ff6f6SMatthew Dillon * writes to the file /tmp/ath_hal.log. The file format is a simple 26572ff6f6SMatthew Dillon * fixed-size array of records. When done logging set hw.ath.hal.alq=0 27572ff6f6SMatthew Dillon * and then decode the file with the arcode program (that is part of the 28572ff6f6SMatthew Dillon * HAL). If you start+stop tracing the data will be appended to an 29572ff6f6SMatthew Dillon * existing file. 30572ff6f6SMatthew Dillon */ 31572ff6f6SMatthew Dillon struct athregrec { 32572ff6f6SMatthew Dillon uint32_t threadid; 33572ff6f6SMatthew Dillon uint32_t op : 8, 34572ff6f6SMatthew Dillon reg : 24; 35572ff6f6SMatthew Dillon uint32_t val; 36572ff6f6SMatthew Dillon }; 37572ff6f6SMatthew Dillon 38572ff6f6SMatthew Dillon enum { 39572ff6f6SMatthew Dillon OP_READ = 0, /* register read */ 40572ff6f6SMatthew Dillon OP_WRITE = 1, /* register write */ 41572ff6f6SMatthew Dillon OP_DEVICE = 2, /* device identification */ 42572ff6f6SMatthew Dillon OP_MARK = 3, /* application marker */ 43572ff6f6SMatthew Dillon }; 44572ff6f6SMatthew Dillon 45572ff6f6SMatthew Dillon enum { 46572ff6f6SMatthew Dillon AH_MARK_RESET, /* ar*Reset entry, bChannelChange */ 47572ff6f6SMatthew Dillon AH_MARK_RESET_LINE, /* ar*_reset.c, line %d */ 48572ff6f6SMatthew Dillon AH_MARK_RESET_DONE, /* ar*Reset exit, error code */ 49572ff6f6SMatthew Dillon AH_MARK_CHIPRESET, /* ar*ChipReset, channel num */ 50572ff6f6SMatthew Dillon AH_MARK_PERCAL, /* ar*PerCalibration, channel num */ 51572ff6f6SMatthew Dillon AH_MARK_SETCHANNEL, /* ar*SetChannel, channel num */ 52572ff6f6SMatthew Dillon AH_MARK_ANI_RESET, /* ar*AniReset, opmode */ 53572ff6f6SMatthew Dillon AH_MARK_ANI_POLL, /* ar*AniReset, listen time */ 54572ff6f6SMatthew Dillon AH_MARK_ANI_CONTROL, /* ar*AniReset, cmd */ 55572ff6f6SMatthew Dillon AH_MARK_RX_CTL, /* RX DMA control */ 56*848b370cSMatthew Dillon AH_MARK_CHIP_POWER, /* chip power control, mode */ 57*848b370cSMatthew Dillon AH_MARK_CHIP_POWER_DONE, /* chip power control done, status */ 58572ff6f6SMatthew Dillon }; 59572ff6f6SMatthew Dillon 60572ff6f6SMatthew Dillon enum { 61572ff6f6SMatthew Dillon AH_MARK_RX_CTL_PCU_START, 62572ff6f6SMatthew Dillon AH_MARK_RX_CTL_PCU_STOP, 63572ff6f6SMatthew Dillon AH_MARK_RX_CTL_DMA_START, 64572ff6f6SMatthew Dillon AH_MARK_RX_CTL_DMA_STOP, 65572ff6f6SMatthew Dillon AH_MARK_RX_CTL_DMA_STOP_ERR, 66*848b370cSMatthew Dillon AH_MARK_RX_CTL_DMA_STOP_OK, 67572ff6f6SMatthew Dillon }; 68572ff6f6SMatthew Dillon 69572ff6f6SMatthew Dillon #endif /* _ATH_AH_DECODE_H_ */ 70