1bbf76eecSMatthew Dillon /*- 2bbf76eecSMatthew Dillon * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3bbf76eecSMatthew Dillon * All rights reserved. 4bbf76eecSMatthew Dillon * 5bbf76eecSMatthew Dillon * Redistribution and use in source and binary forms, with or without 6bbf76eecSMatthew Dillon * modification, are permitted provided that the following conditions 7bbf76eecSMatthew Dillon * are met: 8bbf76eecSMatthew Dillon * 1. Redistributions of source code must retain the above copyright 9bbf76eecSMatthew Dillon * notice unmodified, this list of conditions, and the following 10bbf76eecSMatthew Dillon * disclaimer. 11bbf76eecSMatthew Dillon * 2. Redistributions in binary form must reproduce the above copyright 12bbf76eecSMatthew Dillon * notice, this list of conditions and the following disclaimer in the 13bbf76eecSMatthew Dillon * documentation and/or other materials provided with the distribution. 14bbf76eecSMatthew Dillon * 15bbf76eecSMatthew Dillon * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16bbf76eecSMatthew Dillon * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17bbf76eecSMatthew Dillon * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18bbf76eecSMatthew Dillon * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19bbf76eecSMatthew Dillon * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20bbf76eecSMatthew Dillon * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21bbf76eecSMatthew Dillon * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22bbf76eecSMatthew Dillon * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23bbf76eecSMatthew Dillon * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24bbf76eecSMatthew Dillon * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25bbf76eecSMatthew Dillon * SUCH DAMAGE. 26bbf76eecSMatthew Dillon * 27bbf76eecSMatthew Dillon * $FreeBSD: src/sys/dev/alc/if_alcvar.h,v 1.1 2009/06/10 02:07:58 yongari Exp $ 28bbf76eecSMatthew Dillon */ 29bbf76eecSMatthew Dillon 30bbf76eecSMatthew Dillon #ifndef _IF_ALCVAR_H 31bbf76eecSMatthew Dillon #define _IF_ALCVAR_H 32bbf76eecSMatthew Dillon 33bbf76eecSMatthew Dillon #define ALC_TX_RING_CNT 256 34bbf76eecSMatthew Dillon #define ALC_TX_RING_ALIGN sizeof(struct tx_desc) 35bbf76eecSMatthew Dillon #define ALC_RX_RING_CNT 256 36bbf76eecSMatthew Dillon #define ALC_RX_RING_ALIGN sizeof(struct rx_desc) 37bbf76eecSMatthew Dillon #define ALC_RX_BUF_ALIGN 4 38bbf76eecSMatthew Dillon #define ALC_RR_RING_CNT ALC_RX_RING_CNT 39bbf76eecSMatthew Dillon #define ALC_RR_RING_ALIGN sizeof(struct rx_rdesc) 40bbf76eecSMatthew Dillon #define ALC_CMB_ALIGN 8 41bbf76eecSMatthew Dillon #define ALC_SMB_ALIGN 8 42bbf76eecSMatthew Dillon 43bbf76eecSMatthew Dillon #define ALC_TSO_MAXSEGSIZE 4096 44bbf76eecSMatthew Dillon #define ALC_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 45bbf76eecSMatthew Dillon #define ALC_MAXTXSEGS 32 46bbf76eecSMatthew Dillon 47bbf76eecSMatthew Dillon #define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 48bbf76eecSMatthew Dillon #define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32) 49bbf76eecSMatthew Dillon 50bbf76eecSMatthew Dillon #define ALC_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 51bbf76eecSMatthew Dillon 52bbf76eecSMatthew Dillon /* Water mark to kick reclaiming Tx buffers. */ 53bbf76eecSMatthew Dillon #define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10) 54bbf76eecSMatthew Dillon 556421ab1dSMatthew Dillon /* 566421ab1dSMatthew Dillon * AR816x controllers support up to 16 messages but this driver 576421ab1dSMatthew Dillon * uses single message. 586421ab1dSMatthew Dillon */ 596421ab1dSMatthew Dillon #define ALC_MSI_MESSAGES 1 606421ab1dSMatthew Dillon #define ALC_MSIX_MESSAGES 1 616421ab1dSMatthew Dillon 62bbf76eecSMatthew Dillon #define ALC_TX_RING_SZ \ 63bbf76eecSMatthew Dillon (sizeof(struct tx_desc) * ALC_TX_RING_CNT) 64bbf76eecSMatthew Dillon #define ALC_RX_RING_SZ \ 65bbf76eecSMatthew Dillon (sizeof(struct rx_desc) * ALC_RX_RING_CNT) 66bbf76eecSMatthew Dillon #define ALC_RR_RING_SZ \ 67bbf76eecSMatthew Dillon (sizeof(struct rx_rdesc) * ALC_RR_RING_CNT) 68bbf76eecSMatthew Dillon #define ALC_CMB_SZ (sizeof(struct cmb)) 69bbf76eecSMatthew Dillon #define ALC_SMB_SZ (sizeof(struct smb)) 70bbf76eecSMatthew Dillon 71bbf76eecSMatthew Dillon #define ALC_PROC_MIN 16 72bbf76eecSMatthew Dillon #define ALC_PROC_MAX (ALC_RX_RING_CNT - 1) 73bbf76eecSMatthew Dillon #define ALC_PROC_DEFAULT (ALC_RX_RING_CNT / 4) 74bbf76eecSMatthew Dillon 75bbf76eecSMatthew Dillon /* 76cffbd125SMatthew Dillon * The number of bits reserved for MSS in AR813x/AR815x controllers 77bbf76eecSMatthew Dillon * are 13 bits. This limits the maximum interface MTU size in TSO 78bbf76eecSMatthew Dillon * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper 79bbf76eecSMatthew Dillon * stack should not generate TCP segments with MSS greater than the 80bbf76eecSMatthew Dillon * limit. Also Atheros says that maximum MTU for TSO is 6KB. 81bbf76eecSMatthew Dillon */ 82bbf76eecSMatthew Dillon #define ALC_TSO_MTU (6 * 1024) 83bbf76eecSMatthew Dillon 84bbf76eecSMatthew Dillon 85bbf76eecSMatthew Dillon struct alc_rxdesc { 86bbf76eecSMatthew Dillon struct mbuf *rx_m; 87bbf76eecSMatthew Dillon bus_dmamap_t rx_dmamap; 88bbf76eecSMatthew Dillon struct rx_desc *rx_desc; 89bbf76eecSMatthew Dillon }; 90bbf76eecSMatthew Dillon 91bbf76eecSMatthew Dillon struct alc_txdesc { 92bbf76eecSMatthew Dillon struct mbuf *tx_m; 93bbf76eecSMatthew Dillon bus_dmamap_t tx_dmamap; 94bbf76eecSMatthew Dillon }; 95bbf76eecSMatthew Dillon 96bbf76eecSMatthew Dillon struct alc_ring_data { 97bbf76eecSMatthew Dillon struct tx_desc *alc_tx_ring; 98bbf76eecSMatthew Dillon bus_addr_t alc_tx_ring_paddr; 99bbf76eecSMatthew Dillon struct rx_desc *alc_rx_ring; 100bbf76eecSMatthew Dillon bus_addr_t alc_rx_ring_paddr; 101bbf76eecSMatthew Dillon struct rx_rdesc *alc_rr_ring; 102bbf76eecSMatthew Dillon bus_addr_t alc_rr_ring_paddr; 103bbf76eecSMatthew Dillon struct cmb *alc_cmb; 104bbf76eecSMatthew Dillon bus_addr_t alc_cmb_paddr; 105bbf76eecSMatthew Dillon struct smb *alc_smb; 106bbf76eecSMatthew Dillon bus_addr_t alc_smb_paddr; 107bbf76eecSMatthew Dillon }; 108bbf76eecSMatthew Dillon 109bbf76eecSMatthew Dillon struct alc_chain_data { 110bbf76eecSMatthew Dillon bus_dma_tag_t alc_parent_tag; 111bbf76eecSMatthew Dillon bus_dma_tag_t alc_buffer_tag; 112bbf76eecSMatthew Dillon bus_dma_tag_t alc_tx_tag; 113bbf76eecSMatthew Dillon struct alc_txdesc alc_txdesc[ALC_TX_RING_CNT]; 114bbf76eecSMatthew Dillon bus_dma_tag_t alc_rx_tag; 115bbf76eecSMatthew Dillon struct alc_rxdesc alc_rxdesc[ALC_RX_RING_CNT]; 116bbf76eecSMatthew Dillon bus_dma_tag_t alc_tx_ring_tag; 117bbf76eecSMatthew Dillon bus_dmamap_t alc_tx_ring_map; 118bbf76eecSMatthew Dillon bus_dma_tag_t alc_rx_ring_tag; 119bbf76eecSMatthew Dillon bus_dmamap_t alc_rx_ring_map; 120bbf76eecSMatthew Dillon bus_dma_tag_t alc_rr_ring_tag; 121bbf76eecSMatthew Dillon bus_dmamap_t alc_rr_ring_map; 122bbf76eecSMatthew Dillon bus_dmamap_t alc_rx_sparemap; 123bbf76eecSMatthew Dillon bus_dma_tag_t alc_cmb_tag; 124bbf76eecSMatthew Dillon bus_dmamap_t alc_cmb_map; 125bbf76eecSMatthew Dillon bus_dma_tag_t alc_smb_tag; 126bbf76eecSMatthew Dillon bus_dmamap_t alc_smb_map; 127bbf76eecSMatthew Dillon 128bbf76eecSMatthew Dillon int alc_tx_prod; 129bbf76eecSMatthew Dillon int alc_tx_cons; 130bbf76eecSMatthew Dillon int alc_tx_cnt; 131bbf76eecSMatthew Dillon int alc_rx_cons; 132bbf76eecSMatthew Dillon int alc_rr_cons; 133bbf76eecSMatthew Dillon int alc_rxlen; 134bbf76eecSMatthew Dillon 135bbf76eecSMatthew Dillon struct mbuf *alc_rxhead; 136bbf76eecSMatthew Dillon struct mbuf *alc_rxtail; 137bbf76eecSMatthew Dillon struct mbuf *alc_rxprev_tail; 138bbf76eecSMatthew Dillon }; 139bbf76eecSMatthew Dillon 140bbf76eecSMatthew Dillon struct alc_hw_stats { 141bbf76eecSMatthew Dillon /* Rx stats. */ 142bbf76eecSMatthew Dillon uint32_t rx_frames; 143bbf76eecSMatthew Dillon uint32_t rx_bcast_frames; 144bbf76eecSMatthew Dillon uint32_t rx_mcast_frames; 145bbf76eecSMatthew Dillon uint32_t rx_pause_frames; 146bbf76eecSMatthew Dillon uint32_t rx_control_frames; 147bbf76eecSMatthew Dillon uint32_t rx_crcerrs; 148bbf76eecSMatthew Dillon uint32_t rx_lenerrs; 149bbf76eecSMatthew Dillon uint64_t rx_bytes; 150bbf76eecSMatthew Dillon uint32_t rx_runts; 151bbf76eecSMatthew Dillon uint32_t rx_fragments; 152bbf76eecSMatthew Dillon uint32_t rx_pkts_64; 153bbf76eecSMatthew Dillon uint32_t rx_pkts_65_127; 154bbf76eecSMatthew Dillon uint32_t rx_pkts_128_255; 155bbf76eecSMatthew Dillon uint32_t rx_pkts_256_511; 156bbf76eecSMatthew Dillon uint32_t rx_pkts_512_1023; 157bbf76eecSMatthew Dillon uint32_t rx_pkts_1024_1518; 158bbf76eecSMatthew Dillon uint32_t rx_pkts_1519_max; 159bbf76eecSMatthew Dillon uint32_t rx_pkts_truncated; 160bbf76eecSMatthew Dillon uint32_t rx_fifo_oflows; 161bbf76eecSMatthew Dillon uint32_t rx_rrs_errs; 162bbf76eecSMatthew Dillon uint32_t rx_alignerrs; 163bbf76eecSMatthew Dillon uint64_t rx_bcast_bytes; 164bbf76eecSMatthew Dillon uint64_t rx_mcast_bytes; 165bbf76eecSMatthew Dillon uint32_t rx_pkts_filtered; 166bbf76eecSMatthew Dillon /* Tx stats. */ 167bbf76eecSMatthew Dillon uint32_t tx_frames; 168bbf76eecSMatthew Dillon uint32_t tx_bcast_frames; 169bbf76eecSMatthew Dillon uint32_t tx_mcast_frames; 170bbf76eecSMatthew Dillon uint32_t tx_pause_frames; 171bbf76eecSMatthew Dillon uint32_t tx_excess_defer; 172bbf76eecSMatthew Dillon uint32_t tx_control_frames; 173bbf76eecSMatthew Dillon uint32_t tx_deferred; 174bbf76eecSMatthew Dillon uint64_t tx_bytes; 175bbf76eecSMatthew Dillon uint32_t tx_pkts_64; 176bbf76eecSMatthew Dillon uint32_t tx_pkts_65_127; 177bbf76eecSMatthew Dillon uint32_t tx_pkts_128_255; 178bbf76eecSMatthew Dillon uint32_t tx_pkts_256_511; 179bbf76eecSMatthew Dillon uint32_t tx_pkts_512_1023; 180bbf76eecSMatthew Dillon uint32_t tx_pkts_1024_1518; 181bbf76eecSMatthew Dillon uint32_t tx_pkts_1519_max; 182bbf76eecSMatthew Dillon uint32_t tx_single_colls; 183bbf76eecSMatthew Dillon uint32_t tx_multi_colls; 184bbf76eecSMatthew Dillon uint32_t tx_late_colls; 185bbf76eecSMatthew Dillon uint32_t tx_excess_colls; 186bbf76eecSMatthew Dillon uint32_t tx_abort; 187bbf76eecSMatthew Dillon uint32_t tx_underrun; 188bbf76eecSMatthew Dillon uint32_t tx_desc_underrun; 189bbf76eecSMatthew Dillon uint32_t tx_lenerrs; 190bbf76eecSMatthew Dillon uint32_t tx_pkts_truncated; 191bbf76eecSMatthew Dillon uint64_t tx_bcast_bytes; 192bbf76eecSMatthew Dillon uint64_t tx_mcast_bytes; 193bbf76eecSMatthew Dillon }; 194bbf76eecSMatthew Dillon 195cffbd125SMatthew Dillon struct alc_ident { 196cffbd125SMatthew Dillon uint16_t vendorid; 197cffbd125SMatthew Dillon uint16_t deviceid; 198cffbd125SMatthew Dillon uint32_t max_framelen; 199cffbd125SMatthew Dillon const char *name; 200cffbd125SMatthew Dillon }; 201cffbd125SMatthew Dillon 202bbf76eecSMatthew Dillon /* 203bbf76eecSMatthew Dillon * Software state per device. 204bbf76eecSMatthew Dillon */ 205bbf76eecSMatthew Dillon struct alc_softc { 206bbf76eecSMatthew Dillon struct arpcom arpcom; 207bbf76eecSMatthew Dillon struct ifnet *alc_ifp; /* points to arpcom.ac_if */ 208bbf76eecSMatthew Dillon device_t alc_dev; 209bbf76eecSMatthew Dillon device_t alc_miibus; 210a0e18bfdSSepherosa Ziehau int alc_res_rid; 211a0e18bfdSSepherosa Ziehau struct resource *alc_res; 212a0e18bfdSSepherosa Ziehau bus_space_handle_t alc_res_bhand; 213a0e18bfdSSepherosa Ziehau bus_space_tag_t alc_res_btag; 214a0e18bfdSSepherosa Ziehau int alc_irq_type; 215a0e18bfdSSepherosa Ziehau int alc_irq_rid; 216a0e18bfdSSepherosa Ziehau struct resource *alc_irq; 217a0e18bfdSSepherosa Ziehau void *alc_intrhand; 218cffbd125SMatthew Dillon struct alc_ident *alc_ident; 219bbf76eecSMatthew Dillon int alc_rev; 220bbf76eecSMatthew Dillon int alc_chip_rev; 221bbf76eecSMatthew Dillon int alc_phyaddr; 222bbf76eecSMatthew Dillon uint8_t alc_eaddr[ETHER_ADDR_LEN]; 223bbf76eecSMatthew Dillon uint32_t alc_dma_rd_burst; 224bbf76eecSMatthew Dillon uint32_t alc_dma_wr_burst; 225bbf76eecSMatthew Dillon uint32_t alc_rcb; 226cffbd125SMatthew Dillon int alc_expcap; 227cffbd125SMatthew Dillon int alc_pmcap; 228bbf76eecSMatthew Dillon int alc_flags; 229bbf76eecSMatthew Dillon #define ALC_FLAG_PCIE 0x0001 2306421ab1dSMatthew Dillon #define ALC_FLAG_PCIX 0x0002 231cffbd125SMatthew Dillon #define ALC_FLAG_PM 0x0010 232bbf76eecSMatthew Dillon #define ALC_FLAG_FASTETHER 0x0020 233bbf76eecSMatthew Dillon #define ALC_FLAG_JUMBO 0x0040 234bbf76eecSMatthew Dillon #define ALC_FLAG_CMB_BUG 0x0100 235bbf76eecSMatthew Dillon #define ALC_FLAG_SMB_BUG 0x0200 236cffbd125SMatthew Dillon #define ALC_FLAG_L0S 0x0400 237cffbd125SMatthew Dillon #define ALC_FLAG_L1S 0x0800 238cffbd125SMatthew Dillon #define ALC_FLAG_APS 0x1000 2396421ab1dSMatthew Dillon #define ALC_FLAG_AR816X_FAMILY 0x2000 2406421ab1dSMatthew Dillon #define ALC_FLAG_LINK_WAR 0x4000 241bbf76eecSMatthew Dillon #define ALC_FLAG_LINK 0x8000 2426421ab1dSMatthew Dillon #define ALC_FLAG_DETACH 0x10000 243*76375588SSepherosa Ziehau #define ALC_FLAG_E2X00 0x20000 244bbf76eecSMatthew Dillon 245bbf76eecSMatthew Dillon struct callout alc_tick_ch; 246bbf76eecSMatthew Dillon struct alc_hw_stats alc_stats; 247bbf76eecSMatthew Dillon struct alc_chain_data alc_cdata; 248bbf76eecSMatthew Dillon struct alc_ring_data alc_rdata; 249bbf76eecSMatthew Dillon int alc_if_flags; 250bbf76eecSMatthew Dillon int alc_watchdog_timer; 251bbf76eecSMatthew Dillon int alc_process_limit; 252bbf76eecSMatthew Dillon int alc_int_rx_mod; 253bbf76eecSMatthew Dillon int alc_int_tx_mod; 254bbf76eecSMatthew Dillon int alc_buf_size; 255bbf76eecSMatthew Dillon }; 256bbf76eecSMatthew Dillon 257bbf76eecSMatthew Dillon /* Register access macros. */ 258a0e18bfdSSepherosa Ziehau #define CSR_WRITE_4(sc, reg, val) \ 259a0e18bfdSSepherosa Ziehau bus_space_write_4(sc->alc_res_btag, sc->alc_res_bhand, (reg), (val)) 260a0e18bfdSSepherosa Ziehau #define CSR_READ_4(sc, reg) \ 261a0e18bfdSSepherosa Ziehau bus_space_read_4(sc->alc_res_btag, sc->alc_res_bhand, (reg)) 262a0e18bfdSSepherosa Ziehau #define CSR_WRITE_2(sc, reg, val) \ 263a0e18bfdSSepherosa Ziehau bus_space_write_2(sc->alc_res_btag, sc->alc_res_bhand, (reg), (val)) 264a0e18bfdSSepherosa Ziehau #define CSR_READ_2(sc, reg) \ 265a0e18bfdSSepherosa Ziehau bus_space_read_2(sc->alc_res_btag, sc->alc_res_bhand, (reg)) 266bbf76eecSMatthew Dillon 267bbf76eecSMatthew Dillon #define ALC_RXCHAIN_RESET(_sc) \ 268bbf76eecSMatthew Dillon do { \ 269bbf76eecSMatthew Dillon (_sc)->alc_cdata.alc_rxhead = NULL; \ 270bbf76eecSMatthew Dillon (_sc)->alc_cdata.alc_rxtail = NULL; \ 271bbf76eecSMatthew Dillon (_sc)->alc_cdata.alc_rxprev_tail = NULL; \ 272bbf76eecSMatthew Dillon (_sc)->alc_cdata.alc_rxlen = 0; \ 273bbf76eecSMatthew Dillon } while (0) 274bbf76eecSMatthew Dillon 275bbf76eecSMatthew Dillon #define ALC_TX_TIMEOUT 5 276bbf76eecSMatthew Dillon #define ALC_RESET_TIMEOUT 100 277bbf76eecSMatthew Dillon #define ALC_TIMEOUT 1000 278bbf76eecSMatthew Dillon #define ALC_PHY_TIMEOUT 1000 279bbf76eecSMatthew Dillon 280bbf76eecSMatthew Dillon #endif /* _IF_ALCVAR_H */ 281