1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/alc/if_alc.c,v 1.6 2009/09/29 23:03:16 yongari Exp $ 28 * $DragonFly$ 29 */ 30 31 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 32 33 #include <sys/cdefs.h> 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/mbuf.h> 43 #include <sys/module.h> 44 #include <sys/spinlock.h> 45 #include <sys/rman.h> 46 #include <sys/queue.h> 47 #include <sys/socket.h> 48 #include <sys/sockio.h> 49 #include <sys/sysctl.h> 50 #include <sys/taskqueue.h> 51 52 #include <net/bpf.h> 53 #include <net/if.h> 54 #include <net/if_arp.h> 55 #include <net/ethernet.h> 56 #include <net/if_dl.h> 57 #include <net/if_llc.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 #include <net/ifq_var.h> 61 #include <net/vlan/if_vlan_var.h> 62 #include <net/vlan/if_vlan_ether.h> 63 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/ip.h> 67 #include <netinet/tcp.h> 68 69 #include <dev/netif/mii_layer/mii.h> 70 #include <dev/netif/mii_layer/miivar.h> 71 72 #include <bus/pci/pcireg.h> 73 #include <bus/pci/pcivar.h> 74 75 #include <machine/atomic.h> 76 /* 77 XXX 78 #include <machine/bus.h> 79 #include <machine/in_cksum.h> 80 */ 81 82 #include "if_alcreg.h" 83 #include "if_alcvar.h" 84 85 /* "device miibus" required. See GENERIC if you get errors here. */ 86 #include "miibus_if.h" 87 #undef ALC_USE_CUSTOM_CSUM 88 89 #ifdef ALC_USE_CUSTOM_CSUM 90 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 91 #else 92 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 93 #endif 94 #ifndef IFCAP_VLAN_HWTSO 95 #define IFCAP_VLAN_HWTSO 0 96 #endif 97 98 MODULE_DEPEND(alc, pci, 1, 1, 1); 99 MODULE_DEPEND(alc, ether, 1, 1, 1); 100 MODULE_DEPEND(alc, miibus, 1, 1, 1); 101 102 /* Tunables. */ 103 static int msi_disable = 0; 104 static int msix_disable = 0; 105 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 106 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 107 108 /* 109 * Devices supported by this driver. 110 */ 111 112 static struct alc_ident alc_ident_table[] = { 113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 114 "Atheros AR8131 PCIe Gigabit Ethernet" }, 115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 116 "Atheros AR8132 PCIe Fast Ethernet" }, 117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 118 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 120 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 122 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 123 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 124 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 125 { 0, 0, 0, NULL} 126 }; 127 128 static void alc_aspm(struct alc_softc *, int); 129 static int alc_attach(device_t); 130 static int alc_check_boundary(struct alc_softc *); 131 static int alc_detach(device_t); 132 static void alc_disable_l0s_l1(struct alc_softc *); 133 static int alc_dma_alloc(struct alc_softc *); 134 static void alc_dma_free(struct alc_softc *); 135 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 136 static int alc_encap(struct alc_softc *, struct mbuf **); 137 static struct alc_ident *alc_find_ident(device_t); 138 #ifndef __NO_STRICT_ALIGNMENT 139 static struct mbuf * 140 alc_fixup_rx(struct ifnet *, struct mbuf *); 141 #endif 142 static void alc_get_macaddr(struct alc_softc *); 143 static void alc_init(void *); 144 static void alc_init_cmb(struct alc_softc *); 145 static void alc_init_locked(struct alc_softc *); 146 static void alc_init_rr_ring(struct alc_softc *); 147 static int alc_init_rx_ring(struct alc_softc *); 148 static void alc_init_smb(struct alc_softc *); 149 static void alc_init_tx_ring(struct alc_softc *); 150 static void alc_int_task(void *, int); 151 static void alc_intr(void *); 152 static int alc_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 153 static void alc_mac_config(struct alc_softc *); 154 static int alc_miibus_readreg(device_t, int, int); 155 static void alc_miibus_statchg(device_t); 156 static int alc_miibus_writereg(device_t, int, int, int); 157 static int alc_mediachange(struct ifnet *); 158 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 159 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 160 static void alc_phy_down(struct alc_softc *); 161 static void alc_phy_reset(struct alc_softc *); 162 static int alc_probe(device_t); 163 static void alc_reset(struct alc_softc *); 164 static int alc_resume(device_t); 165 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 166 static int alc_rxintr(struct alc_softc *, int); 167 static void alc_rxfilter(struct alc_softc *); 168 static void alc_rxvlan(struct alc_softc *); 169 #if 0 170 static void alc_setlinkspeed(struct alc_softc *); 171 /* XXX: WOL */ 172 static void alc_setwol(struct alc_softc *); 173 #endif 174 static int alc_shutdown(device_t); 175 static void alc_start(struct ifnet *); 176 static void alc_start_queue(struct alc_softc *); 177 static void alc_stats_clear(struct alc_softc *); 178 static void alc_stats_update(struct alc_softc *); 179 static void alc_stop(struct alc_softc *); 180 static void alc_stop_mac(struct alc_softc *); 181 static void alc_stop_queue(struct alc_softc *); 182 static int alc_suspend(device_t); 183 static void alc_sysctl_node(struct alc_softc *); 184 static void alc_tick(void *); 185 static void alc_tx_task(void *, int); 186 static void alc_txeof(struct alc_softc *); 187 static void alc_watchdog(struct alc_softc *); 188 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 189 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 190 191 static device_method_t alc_methods[] = { 192 /* Device interface. */ 193 DEVMETHOD(device_probe, alc_probe), 194 DEVMETHOD(device_attach, alc_attach), 195 DEVMETHOD(device_detach, alc_detach), 196 DEVMETHOD(device_shutdown, alc_shutdown), 197 DEVMETHOD(device_suspend, alc_suspend), 198 DEVMETHOD(device_resume, alc_resume), 199 200 /* MII interface. */ 201 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 202 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 203 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 204 205 { NULL, NULL } 206 }; 207 208 static driver_t alc_driver = { 209 "alc", 210 alc_methods, 211 sizeof(struct alc_softc) 212 }; 213 214 static devclass_t alc_devclass; 215 216 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 217 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 218 219 static struct resource_spec alc_res_spec_mem[] = { 220 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 221 { -1, 0, 0 } 222 }; 223 224 static struct resource_spec alc_irq_spec_legacy[] = { 225 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 226 { -1, 0, 0 } 227 }; 228 229 static struct resource_spec alc_irq_spec_msi[] = { 230 { SYS_RES_IRQ, 1, RF_ACTIVE }, 231 { -1, 0, 0 } 232 }; 233 234 static struct resource_spec alc_irq_spec_msix[] = { 235 { SYS_RES_IRQ, 1, RF_ACTIVE }, 236 { -1, 0, 0 } 237 }; 238 239 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 240 241 static int 242 alc_miibus_readreg(device_t dev, int phy, int reg) 243 { 244 struct alc_softc *sc; 245 uint32_t v; 246 int i; 247 248 sc = device_get_softc(dev); 249 250 if (phy != sc->alc_phyaddr) 251 return (0); 252 253 /* 254 * For AR8132 fast ethernet controller, do not report 1000baseT 255 * capability to mii(4). Even though AR8132 uses the same 256 * model/revision number of F1 gigabit PHY, the PHY has no 257 * ability to establish 1000baseT link. 258 */ 259 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 260 reg == MII_EXTSR) 261 return (0); 262 263 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 264 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 265 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 266 DELAY(5); 267 v = CSR_READ_4(sc, ALC_MDIO); 268 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 269 break; 270 } 271 272 if (i == 0) { 273 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 274 return (0); 275 } 276 277 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 278 } 279 280 static int 281 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 282 { 283 struct alc_softc *sc; 284 uint32_t v; 285 int i; 286 287 sc = device_get_softc(dev); 288 289 if (phy != sc->alc_phyaddr) 290 return (0); 291 292 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 293 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 294 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 295 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 296 DELAY(5); 297 v = CSR_READ_4(sc, ALC_MDIO); 298 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 299 break; 300 } 301 302 if (i == 0) 303 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 304 305 return (0); 306 } 307 308 static void 309 alc_miibus_statchg(device_t dev) 310 { 311 struct alc_softc *sc; 312 struct mii_data *mii; 313 struct ifnet *ifp; 314 uint32_t reg; 315 316 sc = device_get_softc(dev); 317 318 mii = device_get_softc(sc->alc_miibus); 319 ifp = sc->alc_ifp; 320 if (mii == NULL || ifp == NULL || 321 (ifp->if_flags & IFF_RUNNING) == 0) 322 return; 323 324 sc->alc_flags &= ~ALC_FLAG_LINK; 325 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 326 (IFM_ACTIVE | IFM_AVALID)) { 327 switch (IFM_SUBTYPE(mii->mii_media_active)) { 328 case IFM_10_T: 329 case IFM_100_TX: 330 sc->alc_flags |= ALC_FLAG_LINK; 331 break; 332 case IFM_1000_T: 333 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 334 sc->alc_flags |= ALC_FLAG_LINK; 335 break; 336 default: 337 break; 338 } 339 } 340 alc_stop_queue(sc); 341 /* Stop Rx/Tx MACs. */ 342 alc_stop_mac(sc); 343 344 /* Program MACs with resolved speed/duplex/flow-control. */ 345 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 346 alc_start_queue(sc); 347 alc_mac_config(sc); 348 /* Re-enable Tx/Rx MACs. */ 349 reg = CSR_READ_4(sc, ALC_MAC_CFG); 350 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 351 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 352 } 353 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 354 } 355 356 static void 357 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 358 { 359 struct alc_softc *sc; 360 struct mii_data *mii; 361 362 sc = ifp->if_softc; 363 ALC_LOCK(sc); 364 if ((ifp->if_flags & IFF_UP) == 0) { 365 ALC_UNLOCK(sc); 366 return; 367 } 368 mii = device_get_softc(sc->alc_miibus); 369 370 mii_pollstat(mii); 371 ALC_UNLOCK(sc); 372 ifmr->ifm_status = mii->mii_media_status; 373 ifmr->ifm_active = mii->mii_media_active; 374 } 375 376 static int 377 alc_mediachange(struct ifnet *ifp) 378 { 379 struct alc_softc *sc; 380 struct mii_data *mii; 381 struct mii_softc *miisc; 382 int error; 383 384 sc = ifp->if_softc; 385 ALC_LOCK(sc); 386 mii = device_get_softc(sc->alc_miibus); 387 if (mii->mii_instance != 0) { 388 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 389 mii_phy_reset(miisc); 390 } 391 error = mii_mediachg(mii); 392 ALC_UNLOCK(sc); 393 394 return (error); 395 } 396 397 static struct alc_ident * 398 alc_find_ident(device_t dev) 399 { 400 struct alc_ident *ident; 401 uint16_t vendor, devid; 402 403 vendor = pci_get_vendor(dev); 404 devid = pci_get_device(dev); 405 for (ident = alc_ident_table; ident->name != NULL; ident++) { 406 if (vendor == ident->vendorid && devid == ident->deviceid) 407 return (ident); 408 } 409 return (NULL); 410 } 411 412 static int 413 alc_probe(device_t dev) 414 { 415 struct alc_ident *ident; 416 417 ident = alc_find_ident(dev); 418 if (ident != NULL) { 419 device_set_desc(dev, ident->name); 420 return (BUS_PROBE_DEFAULT); 421 } 422 return (ENXIO); 423 } 424 425 static void 426 alc_get_macaddr(struct alc_softc *sc) 427 { 428 uint32_t ea[2], opt; 429 uint16_t val; 430 int eeprom, i; 431 432 eeprom = 0; 433 opt = CSR_READ_4(sc, ALC_OPT_CFG); 434 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 435 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 436 /* 437 * EEPROM found, let TWSI reload EEPROM configuration. 438 * This will set ethernet address of controller. 439 */ 440 eeprom++; 441 switch (sc->alc_ident->deviceid) { 442 case DEVICEID_ATHEROS_AR8131: 443 case DEVICEID_ATHEROS_AR8132: 444 if ((opt & OPT_CFG_CLK_ENB) == 0) { 445 opt |= OPT_CFG_CLK_ENB; 446 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 447 CSR_READ_4(sc, ALC_OPT_CFG); 448 DELAY(1000); 449 } 450 break; 451 case DEVICEID_ATHEROS_AR8151: 452 case DEVICEID_ATHEROS_AR8151_V2: 453 case DEVICEID_ATHEROS_AR8152_B: 454 case DEVICEID_ATHEROS_AR8152_B2: 455 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 456 ALC_MII_DBG_ADDR, 0x00); 457 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 458 ALC_MII_DBG_DATA); 459 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 460 ALC_MII_DBG_DATA, val & 0xFF7F); 461 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 462 ALC_MII_DBG_ADDR, 0x3B); 463 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 464 ALC_MII_DBG_DATA); 465 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 466 ALC_MII_DBG_DATA, val | 0x0008); 467 DELAY(20); 468 break; 469 } 470 471 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 472 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 473 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 474 CSR_READ_4(sc, ALC_WOL_CFG); 475 476 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 477 TWSI_CFG_SW_LD_START); 478 479 for (i = 100; i > 0; i--) { 480 DELAY(1000); 481 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 482 TWSI_CFG_SW_LD_START) == 0) 483 break; 484 } 485 if (i == 0) 486 device_printf(sc->alc_dev, 487 "reloading EEPROM timeout!\n"); 488 } else { 489 if (bootverbose) 490 device_printf(sc->alc_dev, "EEPROM not found!\n"); 491 } 492 493 if (eeprom != 0) { 494 switch (sc->alc_ident->deviceid) { 495 case DEVICEID_ATHEROS_AR8131: 496 case DEVICEID_ATHEROS_AR8132: 497 if ((opt & OPT_CFG_CLK_ENB) != 0) { 498 opt &= ~OPT_CFG_CLK_ENB; 499 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 500 CSR_READ_4(sc, ALC_OPT_CFG); 501 DELAY(1000); 502 } 503 break; 504 case DEVICEID_ATHEROS_AR8151: 505 case DEVICEID_ATHEROS_AR8151_V2: 506 case DEVICEID_ATHEROS_AR8152_B: 507 case DEVICEID_ATHEROS_AR8152_B2: 508 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 509 ALC_MII_DBG_ADDR, 0x00); 510 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 511 ALC_MII_DBG_DATA); 512 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 513 ALC_MII_DBG_DATA, val | 0x0080); 514 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 515 ALC_MII_DBG_ADDR, 0x3B); 516 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 517 ALC_MII_DBG_DATA); 518 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 519 ALC_MII_DBG_DATA, val & 0xFFF7); 520 DELAY(20); 521 break; 522 } 523 } 524 525 ea[0] = CSR_READ_4(sc, ALC_PAR0); 526 ea[1] = CSR_READ_4(sc, ALC_PAR1); 527 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 528 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 529 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 530 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 531 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 532 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 533 } 534 535 static void 536 alc_disable_l0s_l1(struct alc_softc *sc) 537 { 538 uint32_t pmcfg; 539 540 /* Another magic from vendor. */ 541 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 542 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 543 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 544 PM_CFG_SERDES_PD_EX_L1); 545 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 546 PM_CFG_SERDES_L1_ENB; 547 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 548 } 549 550 static void 551 alc_phy_reset(struct alc_softc *sc) 552 { 553 uint16_t data; 554 555 /* Reset magic from Linux. */ 556 CSR_WRITE_2(sc, ALC_GPHY_CFG, 557 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 558 CSR_READ_2(sc, ALC_GPHY_CFG); 559 DELAY(10 * 1000); 560 561 CSR_WRITE_2(sc, ALC_GPHY_CFG, 562 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 563 GPHY_CFG_SEL_ANA_RESET); 564 CSR_READ_2(sc, ALC_GPHY_CFG); 565 DELAY(10 * 1000); 566 567 /* DSP fixup, Vendor magic. */ 568 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 569 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 570 ALC_MII_DBG_ADDR, 0x000A); 571 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 572 ALC_MII_DBG_DATA); 573 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 574 ALC_MII_DBG_DATA, data & 0xDFFF); 575 } 576 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 577 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 578 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 579 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 580 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 581 ALC_MII_DBG_ADDR, 0x003B); 582 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 583 ALC_MII_DBG_DATA); 584 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 585 ALC_MII_DBG_DATA, data & 0xFFF7); 586 DELAY(20 * 1000); 587 } 588 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 589 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 590 ALC_MII_DBG_ADDR, 0x0029); 591 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 592 ALC_MII_DBG_DATA, 0x929D); 593 } 594 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 595 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 596 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 597 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 598 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 599 ALC_MII_DBG_ADDR, 0x0029); 600 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 601 ALC_MII_DBG_DATA, 0xB6DD); 602 } 603 604 /* Load DSP codes, vendor magic. */ 605 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 606 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 607 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 608 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 609 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 610 ALC_MII_DBG_DATA, data); 611 612 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 613 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 614 ANA_SERDES_EN_LCKDT; 615 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 616 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 617 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 618 ALC_MII_DBG_DATA, data); 619 620 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 621 ANA_LONG_CABLE_TH_100_MASK) | 622 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 623 ANA_SHORT_CABLE_TH_100_SHIFT) | 624 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 625 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 626 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 627 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 628 ALC_MII_DBG_DATA, data); 629 630 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 631 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 632 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 633 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 634 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 635 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 636 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 637 ALC_MII_DBG_DATA, data); 638 639 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 640 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 641 ANA_OEN_125M; 642 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 643 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 644 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 645 ALC_MII_DBG_DATA, data); 646 DELAY(1000); 647 } 648 649 static void 650 alc_phy_down(struct alc_softc *sc) 651 { 652 switch (sc->alc_ident->deviceid) { 653 case DEVICEID_ATHEROS_AR8151: 654 case DEVICEID_ATHEROS_AR8151_V2: 655 /* 656 * GPHY power down caused more problems on AR8151 v2.0. 657 * When driver is reloaded after GPHY power down, 658 * accesses to PHY/MAC registers hung the system. Only 659 * cold boot recovered from it. I'm not sure whether 660 * AR8151 v1.0 also requires this one though. I don't 661 * have AR8151 v1.0 controller in hand. 662 * The only option left is to isolate the PHY and 663 * initiates power down the PHY which in turn saves 664 * more power when driver is unloaded. 665 */ 666 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 667 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 668 break; 669 default: 670 /* Force PHY down. */ 671 CSR_WRITE_2(sc, ALC_GPHY_CFG, 672 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 673 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 674 GPHY_CFG_PWDOWN_HW); 675 DELAY(1000); 676 break; 677 } 678 679 } 680 681 static void 682 alc_aspm(struct alc_softc *sc, int media) 683 { 684 uint32_t pmcfg; 685 uint16_t linkcfg; 686 687 ALC_LOCK_ASSERT(sc); 688 689 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 690 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 691 (ALC_FLAG_APS | ALC_FLAG_PCIE)) { 692 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 693 PCIR_EXPRESS_LINK_CTL); 694 } else { 695 linkcfg = 0; 696 } 697 698 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 699 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 700 pmcfg |= PM_CFG_MAC_ASPM_CHK; 701 pmcfg |= PM_CFG_SERDES_ENB | PM_CFG_RBER_ENB; 702 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 703 704 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 705 /* Disable extended sync except AR8152 B v1.0 */ 706 linkcfg &= ~0x80; 707 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 708 sc->alc_rev == ATHEROS_AR8152_B_V10) 709 linkcfg |= 0x80; 710 CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, 711 linkcfg); 712 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 713 PM_CFG_HOTRST); 714 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 715 PM_CFG_L1_ENTRY_TIMER_SHIFT); 716 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 717 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 718 PM_CFG_PM_REQ_TIMER_SHIFT); 719 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 720 } 721 722 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 723 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 724 pmcfg |= PM_CFG_ASPM_L0S_ENB; 725 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 726 pmcfg |= PM_CFG_ASPM_L1_ENB; 727 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 728 if (sc->alc_ident->deviceid == 729 DEVICEID_ATHEROS_AR8152_B) { 730 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 731 } 732 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 733 PM_CFG_SERDES_PLL_L1_ENB | 734 PM_CFG_SERDES_BUDS_RX_L1_ENB); 735 pmcfg |= PM_CFG_CLK_SWH_L1; 736 if (media == IFM_100_TX || media == IFM_1000_T) { 737 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 738 switch (sc->alc_ident->deviceid) { 739 case DEVICEID_ATHEROS_AR8152_B: 740 pmcfg |= (7 << 741 PM_CFG_L1_ENTRY_TIMER_SHIFT); 742 break; 743 case DEVICEID_ATHEROS_AR8152_B2: 744 case DEVICEID_ATHEROS_AR8151_V2: 745 pmcfg |= (4 << 746 PM_CFG_L1_ENTRY_TIMER_SHIFT); 747 break; 748 default: 749 pmcfg |= (15 << 750 PM_CFG_L1_ENTRY_TIMER_SHIFT); 751 break; 752 } 753 } 754 } else { 755 pmcfg |= PM_CFG_SERDES_L1_ENB | 756 PM_CFG_SERDES_PLL_L1_ENB | 757 PM_CFG_SERDES_BUDS_RX_L1_ENB; 758 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 759 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 760 } 761 } else { 762 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 763 PM_CFG_SERDES_PLL_L1_ENB); 764 pmcfg |= PM_CFG_CLK_SWH_L1; 765 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 766 pmcfg |= PM_CFG_ASPM_L1_ENB; 767 } 768 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 769 } 770 771 static int 772 alc_attach(device_t dev) 773 { 774 struct alc_softc *sc; 775 struct ifnet *ifp; 776 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 777 uint16_t burst; 778 int base, error, i, msic, msixc, state; 779 uint32_t cap, ctl, val; 780 781 error = 0; 782 sc = device_get_softc(dev); 783 sc->alc_dev = dev; 784 785 lockinit(&sc->alc_lock, "alc_lock", 0, LK_CANRECURSE); 786 callout_init_mp(&sc->alc_tick_ch); 787 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 788 sc->alc_ident = alc_find_ident(dev); 789 790 /* Map the device. */ 791 pci_enable_busmaster(dev); 792 sc->alc_res_spec = alc_res_spec_mem; 793 sc->alc_irq_spec = alc_irq_spec_legacy; 794 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 795 if (error != 0) { 796 device_printf(dev, "cannot allocate memory resources.\n"); 797 goto fail; 798 } 799 800 /* Set PHY address. */ 801 sc->alc_phyaddr = ALC_PHY_ADDR; 802 803 /* Initialize DMA parameters. */ 804 sc->alc_dma_rd_burst = 0; 805 sc->alc_dma_wr_burst = 0; 806 sc->alc_rcb = DMA_CFG_RCB_64; 807 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { 808 sc->alc_flags |= ALC_FLAG_PCIE; 809 sc->alc_expcap = base; 810 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); 811 sc->alc_dma_rd_burst = 812 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; 813 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; 814 if (bootverbose) { 815 device_printf(dev, "Read request size : %u bytes.\n", 816 alc_dma_burst[sc->alc_dma_rd_burst]); 817 device_printf(dev, "TLP payload size : %u bytes.\n", 818 alc_dma_burst[sc->alc_dma_wr_burst]); 819 } 820 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 821 sc->alc_dma_rd_burst = 3; 822 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 823 sc->alc_dma_wr_burst = 3; 824 /* Clear data link and flow-control protocol error. */ 825 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 826 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 827 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 828 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 829 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 830 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 831 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 832 PCIE_PHYMISC_FORCE_RCV_DET); 833 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 834 sc->alc_rev == ATHEROS_AR8152_B_V10) { 835 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 836 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 837 PCIE_PHYMISC2_SERDES_TH_MASK); 838 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 839 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 840 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 841 } 842 843 /* Disable ASPM L0S and L1. */ 844 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 845 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 846 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 847 if ((ctl & 0x08) != 0) 848 sc->alc_rcb = DMA_CFG_RCB_128; 849 if (bootverbose) 850 device_printf(dev, "RCB %u bytes\n", 851 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 852 state = ctl & 0x03; 853 if (state & 0x01) 854 sc->alc_flags |= ALC_FLAG_L0S; 855 if (state & 0x02) 856 sc->alc_flags |= ALC_FLAG_L1S; 857 if (bootverbose) 858 device_printf(sc->alc_dev, "ASPM %s %s\n", 859 aspm_state[state], 860 state == 0 ? "disabled" : "enabled"); 861 alc_disable_l0s_l1(sc); 862 } else { 863 if (bootverbose) 864 device_printf(sc->alc_dev, "no ASPM support\n"); 865 } 866 } 867 868 /* Reset PHY. */ 869 alc_phy_reset(sc); 870 871 /* Reset the ethernet controller. */ 872 alc_reset(sc); 873 874 /* 875 * One odd thing is AR8132 uses the same PHY hardware(F1 876 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 877 * the PHY supports 1000Mbps but that's not true. The PHY 878 * used in AR8132 can't establish gigabit link even if it 879 * shows the same PHY model/revision number of AR8131. 880 */ 881 switch (sc->alc_ident->deviceid) { 882 case DEVICEID_ATHEROS_AR8152_B: 883 case DEVICEID_ATHEROS_AR8152_B2: 884 sc->alc_flags |= ALC_FLAG_APS; 885 /* FALLTHROUGH */ 886 case DEVICEID_ATHEROS_AR8132: 887 sc->alc_flags |= ALC_FLAG_FASTETHER; 888 break; 889 case DEVICEID_ATHEROS_AR8151: 890 case DEVICEID_ATHEROS_AR8151_V2: 891 sc->alc_flags |= ALC_FLAG_APS; 892 /* FALLTHROUGH */ 893 default: 894 break; 895 } 896 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 897 898 /* 899 * It seems that AR813x/AR815x has silicon bug for SMB. In 900 * addition, Atheros said that enabling SMB wouldn't improve 901 * performance. However I think it's bad to access lots of 902 * registers to extract MAC statistics. 903 */ 904 sc->alc_flags |= ALC_FLAG_SMB_BUG; 905 906 /* 907 * Don't use Tx CMB. It is known to have silicon bug. 908 */ 909 sc->alc_flags |= ALC_FLAG_CMB_BUG; 910 sc->alc_rev = pci_get_revid(dev); 911 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 912 MASTER_CHIP_REV_SHIFT; 913 if (bootverbose) { 914 device_printf(dev, "PCI device revision : 0x%04x\n", 915 sc->alc_rev); 916 device_printf(dev, "Chip id/revision : 0x%04x\n", 917 sc->alc_chip_rev); 918 } 919 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 920 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 921 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 922 923 /* Allocate IRQ resources. */ 924 msixc = pci_msix_count(dev); 925 msic = pci_msi_count(dev); 926 if (bootverbose) { 927 device_printf(dev, "MSIX count : %d\n", msixc); 928 device_printf(dev, "MSI count : %d\n", msic); 929 } 930 /* Prefer MSIX over MSI. */ 931 if (msix_disable == 0 || msi_disable == 0) { 932 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 933 pci_alloc_msix(dev, &msixc) == 0) { 934 if (msic == ALC_MSIX_MESSAGES) { 935 device_printf(dev, 936 "Using %d MSIX message(s).\n", msixc); 937 sc->alc_flags |= ALC_FLAG_MSIX; 938 sc->alc_irq_spec = alc_irq_spec_msix; 939 } else 940 pci_release_msi(dev); 941 } 942 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 943 msic == ALC_MSI_MESSAGES && 944 pci_alloc_msi(dev, &msic) == 0) { 945 if (msic == ALC_MSI_MESSAGES) { 946 device_printf(dev, 947 "Using %d MSI message(s).\n", msic); 948 sc->alc_flags |= ALC_FLAG_MSI; 949 sc->alc_irq_spec = alc_irq_spec_msi; 950 } else 951 pci_release_msi(dev); 952 } 953 } 954 955 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 956 if (error != 0) { 957 device_printf(dev, "cannot allocate IRQ resources.\n"); 958 goto fail; 959 } 960 961 /* Create device sysctl node. */ 962 alc_sysctl_node(sc); 963 964 if ((error = alc_dma_alloc(sc) != 0)) 965 goto fail; 966 967 /* Load station address. */ 968 alc_get_macaddr(sc); 969 970 ifp = sc->alc_ifp = &sc->arpcom.ac_if; 971 ifp->if_softc = sc; 972 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 973 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 974 ifp->if_ioctl = alc_ioctl; 975 ifp->if_start = alc_start; 976 ifp->if_init = alc_init; 977 ifp->if_snd.ifq_maxlen = ALC_TX_RING_CNT - 1; 978 ifq_set_maxlen(&ifp->if_snd, ifp->if_snd.ifq_maxlen); 979 ifq_set_ready(&ifp->if_snd); 980 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 981 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 982 #if 0 983 /* XXX: WOL */ 984 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 985 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 986 sc->alc_flags |= ALC_FLAG_PM; 987 sc->alc_pmcap = base; 988 } 989 #endif 990 ifp->if_capenable = ifp->if_capabilities; 991 992 /* Set up MII bus. */ 993 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange, 994 alc_mediastatus)) != 0) { 995 device_printf(dev, "no PHY found!\n"); 996 goto fail; 997 } 998 999 ether_ifattach(ifp, sc->alc_eaddr, NULL); 1000 1001 /* VLAN capability setup. */ 1002 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1003 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 1004 ifp->if_capenable = ifp->if_capabilities; 1005 /* 1006 * XXX 1007 * It seems enabling Tx checksum offloading makes more trouble. 1008 * Sometimes the controller does not receive any frames when 1009 * Tx checksum offloading is enabled. I'm not sure whether this 1010 * is a bug in Tx checksum offloading logic or I got broken 1011 * sample boards. To safety, don't enable Tx checksum offloading 1012 * by default but give chance to users to toggle it if they know 1013 * their controllers work without problems. 1014 */ 1015 ifp->if_capenable &= ~IFCAP_TXCSUM; 1016 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1017 1018 /* Tell the upper layer(s) we support long frames. */ 1019 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1020 1021 /* Create local taskq. */ 1022 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp); 1023 sc->alc_tq = taskqueue_create("alc_taskq", M_WAITOK, 1024 taskqueue_thread_enqueue, &sc->alc_tq); 1025 if (sc->alc_tq == NULL) { 1026 device_printf(dev, "could not create taskqueue.\n"); 1027 ether_ifdetach(ifp); 1028 error = ENXIO; 1029 goto fail; 1030 } 1031 taskqueue_start_threads(&sc->alc_tq, 1, TDPRI_KERN_DAEMON, -1, "%s taskq", 1032 device_get_nameunit(sc->alc_dev)); 1033 1034 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1035 msic = ALC_MSIX_MESSAGES; 1036 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1037 msic = ALC_MSI_MESSAGES; 1038 else 1039 msic = 1; 1040 for (i = 0; i < msic; i++) { 1041 error = bus_setup_intr(dev, sc->alc_irq[i], INTR_MPSAFE, 1042 alc_intr, sc, 1043 &sc->alc_intrhand[i], NULL); 1044 if (error != 0) 1045 break; 1046 } 1047 if (error != 0) { 1048 device_printf(dev, "could not set up interrupt handler.\n"); 1049 taskqueue_free(sc->alc_tq); 1050 sc->alc_tq = NULL; 1051 ether_ifdetach(ifp); 1052 goto fail; 1053 } 1054 1055 fail: 1056 if (error != 0) 1057 alc_detach(dev); 1058 1059 return (error); 1060 } 1061 1062 static int 1063 alc_detach(device_t dev) 1064 { 1065 struct alc_softc *sc; 1066 struct ifnet *ifp; 1067 int i, msic; 1068 1069 sc = device_get_softc(dev); 1070 1071 ifp = sc->alc_ifp; 1072 if (device_is_attached(dev)) { 1073 ALC_LOCK(sc); 1074 sc->alc_flags |= ALC_FLAG_DETACH; 1075 alc_stop(sc); 1076 ALC_UNLOCK(sc); 1077 #if 0 1078 /* XXX */ 1079 callout_drain(&sc->alc_tick_ch); 1080 #endif 1081 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1082 taskqueue_drain(sc->alc_tq, &sc->alc_tx_task); 1083 ether_ifdetach(ifp); 1084 } 1085 1086 if (sc->alc_tq != NULL) { 1087 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1088 taskqueue_free(sc->alc_tq); 1089 sc->alc_tq = NULL; 1090 } 1091 1092 if (sc->alc_miibus != NULL) { 1093 device_delete_child(dev, sc->alc_miibus); 1094 sc->alc_miibus = NULL; 1095 } 1096 bus_generic_detach(dev); 1097 alc_dma_free(sc); 1098 1099 if (ifp != NULL) { 1100 // XXX? if_free(ifp); 1101 sc->alc_ifp = NULL; 1102 } 1103 1104 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1105 msic = ALC_MSIX_MESSAGES; 1106 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1107 msic = ALC_MSI_MESSAGES; 1108 else 1109 msic = 1; 1110 for (i = 0; i < msic; i++) { 1111 if (sc->alc_intrhand[i] != NULL) { 1112 bus_teardown_intr(dev, sc->alc_irq[i], 1113 sc->alc_intrhand[i]); 1114 sc->alc_intrhand[i] = NULL; 1115 } 1116 } 1117 if (sc->alc_res[0] != NULL) 1118 alc_phy_down(sc); 1119 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1120 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1121 pci_release_msi(dev); 1122 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1123 lockuninit(&sc->alc_lock); 1124 1125 return (0); 1126 } 1127 1128 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1129 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1130 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1131 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1132 1133 static void 1134 alc_sysctl_node(struct alc_softc *sc) 1135 { 1136 struct sysctl_ctx_list *ctx; 1137 struct sysctl_oid *tree; 1138 struct sysctl_oid_list *child, *parent; 1139 struct alc_hw_stats *stats; 1140 int error; 1141 1142 stats = &sc->alc_stats; 1143 ctx = &sc->alc_sysctl_ctx; 1144 sysctl_ctx_init(ctx); 1145 1146 tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw), 1147 OID_AUTO, 1148 device_get_nameunit(sc->alc_dev), 1149 CTLFLAG_RD, 0, ""); 1150 if (tree == NULL) { 1151 device_printf(sc->alc_dev, "can't add sysctl node\n"); 1152 return; 1153 } 1154 child = SYSCTL_CHILDREN(tree); 1155 1156 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1157 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1158 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1159 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1160 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1161 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1162 /* Pull in device tunables. */ 1163 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1164 error = resource_int_value(device_get_name(sc->alc_dev), 1165 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1166 if (error == 0) { 1167 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1168 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1169 device_printf(sc->alc_dev, "int_rx_mod value out of " 1170 "range; using default: %d\n", 1171 ALC_IM_RX_TIMER_DEFAULT); 1172 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1173 } 1174 } 1175 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1176 error = resource_int_value(device_get_name(sc->alc_dev), 1177 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1178 if (error == 0) { 1179 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1180 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1181 device_printf(sc->alc_dev, "int_tx_mod value out of " 1182 "range; using default: %d\n", 1183 ALC_IM_TX_TIMER_DEFAULT); 1184 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1185 } 1186 } 1187 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1188 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1189 sysctl_hw_alc_proc_limit, "I", 1190 "max number of Rx events to process"); 1191 /* Pull in device tunables. */ 1192 sc->alc_process_limit = ALC_PROC_DEFAULT; 1193 error = resource_int_value(device_get_name(sc->alc_dev), 1194 device_get_unit(sc->alc_dev), "process_limit", 1195 &sc->alc_process_limit); 1196 if (error == 0) { 1197 if (sc->alc_process_limit < ALC_PROC_MIN || 1198 sc->alc_process_limit > ALC_PROC_MAX) { 1199 device_printf(sc->alc_dev, 1200 "process_limit value out of range; " 1201 "using default: %d\n", ALC_PROC_DEFAULT); 1202 sc->alc_process_limit = ALC_PROC_DEFAULT; 1203 } 1204 } 1205 1206 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1207 NULL, "ALC statistics"); 1208 parent = SYSCTL_CHILDREN(tree); 1209 1210 /* Rx statistics. */ 1211 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1212 NULL, "Rx MAC statistics"); 1213 child = SYSCTL_CHILDREN(tree); 1214 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1215 &stats->rx_frames, "Good frames"); 1216 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1217 &stats->rx_bcast_frames, "Good broadcast frames"); 1218 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1219 &stats->rx_mcast_frames, "Good multicast frames"); 1220 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1221 &stats->rx_pause_frames, "Pause control frames"); 1222 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1223 &stats->rx_control_frames, "Control frames"); 1224 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1225 &stats->rx_crcerrs, "CRC errors"); 1226 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1227 &stats->rx_lenerrs, "Frames with length mismatched"); 1228 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1229 &stats->rx_bytes, "Good octets"); 1230 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1231 &stats->rx_bcast_bytes, "Good broadcast octets"); 1232 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1233 &stats->rx_mcast_bytes, "Good multicast octets"); 1234 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1235 &stats->rx_runts, "Too short frames"); 1236 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1237 &stats->rx_fragments, "Fragmented frames"); 1238 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1239 &stats->rx_pkts_64, "64 bytes frames"); 1240 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1241 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1242 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1243 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1244 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1245 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1246 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1247 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1248 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1249 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1250 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1251 &stats->rx_pkts_1519_max, "1519 to max frames"); 1252 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1253 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1254 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1255 &stats->rx_fifo_oflows, "FIFO overflows"); 1256 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1257 &stats->rx_rrs_errs, "Return status write-back errors"); 1258 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1259 &stats->rx_alignerrs, "Alignment errors"); 1260 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1261 &stats->rx_pkts_filtered, 1262 "Frames dropped due to address filtering"); 1263 1264 /* Tx statistics. */ 1265 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1266 NULL, "Tx MAC statistics"); 1267 child = SYSCTL_CHILDREN(tree); 1268 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1269 &stats->tx_frames, "Good frames"); 1270 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1271 &stats->tx_bcast_frames, "Good broadcast frames"); 1272 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1273 &stats->tx_mcast_frames, "Good multicast frames"); 1274 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1275 &stats->tx_pause_frames, "Pause control frames"); 1276 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1277 &stats->tx_control_frames, "Control frames"); 1278 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1279 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1280 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1281 &stats->tx_excess_defer, "Frames with derferrals"); 1282 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1283 &stats->tx_bytes, "Good octets"); 1284 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1285 &stats->tx_bcast_bytes, "Good broadcast octets"); 1286 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1287 &stats->tx_mcast_bytes, "Good multicast octets"); 1288 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1289 &stats->tx_pkts_64, "64 bytes frames"); 1290 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1291 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1292 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1293 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1294 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1295 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1296 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1297 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1298 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1299 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1300 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1301 &stats->tx_pkts_1519_max, "1519 to max frames"); 1302 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1303 &stats->tx_single_colls, "Single collisions"); 1304 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1305 &stats->tx_multi_colls, "Multiple collisions"); 1306 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1307 &stats->tx_late_colls, "Late collisions"); 1308 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1309 &stats->tx_excess_colls, "Excessive collisions"); 1310 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1311 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1312 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1313 &stats->tx_underrun, "FIFO underruns"); 1314 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1315 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1316 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1317 &stats->tx_lenerrs, "Frames with length mismatched"); 1318 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1319 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1320 } 1321 1322 #undef ALC_SYSCTL_STAT_ADD32 1323 #undef ALC_SYSCTL_STAT_ADD64 1324 1325 struct alc_dmamap_arg { 1326 bus_addr_t alc_busaddr; 1327 }; 1328 1329 static void 1330 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1331 { 1332 struct alc_dmamap_arg *ctx; 1333 1334 if (error != 0) 1335 return; 1336 1337 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1338 1339 ctx = (struct alc_dmamap_arg *)arg; 1340 ctx->alc_busaddr = segs[0].ds_addr; 1341 } 1342 1343 /* 1344 * Normal and high Tx descriptors shares single Tx high address. 1345 * Four Rx descriptor/return rings and CMB shares the same Rx 1346 * high address. 1347 */ 1348 static int 1349 alc_check_boundary(struct alc_softc *sc) 1350 { 1351 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1352 1353 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1354 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1355 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1356 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1357 1358 /* 4GB boundary crossing is not allowed. */ 1359 if ((ALC_ADDR_HI(rx_ring_end) != 1360 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1361 (ALC_ADDR_HI(rr_ring_end) != 1362 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1363 (ALC_ADDR_HI(cmb_end) != 1364 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1365 (ALC_ADDR_HI(tx_ring_end) != 1366 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1367 return (EFBIG); 1368 /* 1369 * Make sure Rx return descriptor/Rx descriptor/CMB use 1370 * the same high address. 1371 */ 1372 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1373 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1374 return (EFBIG); 1375 1376 return (0); 1377 } 1378 1379 static int 1380 alc_dma_alloc(struct alc_softc *sc) 1381 { 1382 struct alc_txdesc *txd; 1383 struct alc_rxdesc *rxd; 1384 bus_addr_t lowaddr; 1385 struct alc_dmamap_arg ctx; 1386 int error, i; 1387 1388 lowaddr = BUS_SPACE_MAXADDR; 1389 again: 1390 /* Create parent DMA tag. */ 1391 error = bus_dma_tag_create( 1392 sc->alc_cdata.alc_parent_tag, /* parent */ 1393 1, 0, /* alignment, boundary */ 1394 lowaddr, /* lowaddr */ 1395 BUS_SPACE_MAXADDR, /* highaddr */ 1396 NULL, NULL, /* filter, filterarg */ 1397 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1398 0, /* nsegments */ 1399 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1400 0, /* flags */ 1401 &sc->alc_cdata.alc_parent_tag); 1402 if (error != 0) { 1403 device_printf(sc->alc_dev, 1404 "could not create parent DMA tag.\n"); 1405 goto fail; 1406 } 1407 1408 /* Create DMA tag for Tx descriptor ring. */ 1409 error = bus_dma_tag_create( 1410 sc->alc_cdata.alc_parent_tag, /* parent */ 1411 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1412 BUS_SPACE_MAXADDR, /* lowaddr */ 1413 BUS_SPACE_MAXADDR, /* highaddr */ 1414 NULL, NULL, /* filter, filterarg */ 1415 ALC_TX_RING_SZ, /* maxsize */ 1416 1, /* nsegments */ 1417 ALC_TX_RING_SZ, /* maxsegsize */ 1418 0, /* flags */ 1419 &sc->alc_cdata.alc_tx_ring_tag); 1420 if (error != 0) { 1421 device_printf(sc->alc_dev, 1422 "could not create Tx ring DMA tag.\n"); 1423 goto fail; 1424 } 1425 1426 /* Create DMA tag for Rx free descriptor ring. */ 1427 error = bus_dma_tag_create( 1428 sc->alc_cdata.alc_parent_tag, /* parent */ 1429 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1430 BUS_SPACE_MAXADDR, /* lowaddr */ 1431 BUS_SPACE_MAXADDR, /* highaddr */ 1432 NULL, NULL, /* filter, filterarg */ 1433 ALC_RX_RING_SZ, /* maxsize */ 1434 1, /* nsegments */ 1435 ALC_RX_RING_SZ, /* maxsegsize */ 1436 0, /* flags */ 1437 &sc->alc_cdata.alc_rx_ring_tag); 1438 if (error != 0) { 1439 device_printf(sc->alc_dev, 1440 "could not create Rx ring DMA tag.\n"); 1441 goto fail; 1442 } 1443 /* Create DMA tag for Rx return descriptor ring. */ 1444 error = bus_dma_tag_create( 1445 sc->alc_cdata.alc_parent_tag, /* parent */ 1446 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1447 BUS_SPACE_MAXADDR, /* lowaddr */ 1448 BUS_SPACE_MAXADDR, /* highaddr */ 1449 NULL, NULL, /* filter, filterarg */ 1450 ALC_RR_RING_SZ, /* maxsize */ 1451 1, /* nsegments */ 1452 ALC_RR_RING_SZ, /* maxsegsize */ 1453 0, /* flags */ 1454 &sc->alc_cdata.alc_rr_ring_tag); 1455 if (error != 0) { 1456 device_printf(sc->alc_dev, 1457 "could not create Rx return ring DMA tag.\n"); 1458 goto fail; 1459 } 1460 1461 /* Create DMA tag for coalescing message block. */ 1462 error = bus_dma_tag_create( 1463 sc->alc_cdata.alc_parent_tag, /* parent */ 1464 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1465 BUS_SPACE_MAXADDR, /* lowaddr */ 1466 BUS_SPACE_MAXADDR, /* highaddr */ 1467 NULL, NULL, /* filter, filterarg */ 1468 ALC_CMB_SZ, /* maxsize */ 1469 1, /* nsegments */ 1470 ALC_CMB_SZ, /* maxsegsize */ 1471 0, /* flags */ 1472 &sc->alc_cdata.alc_cmb_tag); 1473 if (error != 0) { 1474 device_printf(sc->alc_dev, 1475 "could not create CMB DMA tag.\n"); 1476 goto fail; 1477 } 1478 /* Create DMA tag for status message block. */ 1479 error = bus_dma_tag_create( 1480 sc->alc_cdata.alc_parent_tag, /* parent */ 1481 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1482 BUS_SPACE_MAXADDR, /* lowaddr */ 1483 BUS_SPACE_MAXADDR, /* highaddr */ 1484 NULL, NULL, /* filter, filterarg */ 1485 ALC_SMB_SZ, /* maxsize */ 1486 1, /* nsegments */ 1487 ALC_SMB_SZ, /* maxsegsize */ 1488 0, /* flags */ 1489 &sc->alc_cdata.alc_smb_tag); 1490 if (error != 0) { 1491 device_printf(sc->alc_dev, 1492 "could not create SMB DMA tag.\n"); 1493 goto fail; 1494 } 1495 1496 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1497 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1498 (void **)&sc->alc_rdata.alc_tx_ring, 1499 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1500 &sc->alc_cdata.alc_tx_ring_map); 1501 if (error != 0) { 1502 device_printf(sc->alc_dev, 1503 "could not allocate DMA'able memory for Tx ring.\n"); 1504 goto fail; 1505 } 1506 ctx.alc_busaddr = 0; 1507 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1508 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1509 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1510 if (error != 0 || ctx.alc_busaddr == 0) { 1511 device_printf(sc->alc_dev, 1512 "could not load DMA'able memory for Tx ring.\n"); 1513 goto fail; 1514 } 1515 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1516 1517 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1518 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1519 (void **)&sc->alc_rdata.alc_rx_ring, 1520 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1521 &sc->alc_cdata.alc_rx_ring_map); 1522 if (error != 0) { 1523 device_printf(sc->alc_dev, 1524 "could not allocate DMA'able memory for Rx ring.\n"); 1525 goto fail; 1526 } 1527 ctx.alc_busaddr = 0; 1528 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1529 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1530 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1531 if (error != 0 || ctx.alc_busaddr == 0) { 1532 device_printf(sc->alc_dev, 1533 "could not load DMA'able memory for Rx ring.\n"); 1534 goto fail; 1535 } 1536 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1537 1538 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1539 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1540 (void **)&sc->alc_rdata.alc_rr_ring, 1541 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1542 &sc->alc_cdata.alc_rr_ring_map); 1543 if (error != 0) { 1544 device_printf(sc->alc_dev, 1545 "could not allocate DMA'able memory for Rx return ring.\n"); 1546 goto fail; 1547 } 1548 ctx.alc_busaddr = 0; 1549 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1550 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1551 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1552 if (error != 0 || ctx.alc_busaddr == 0) { 1553 device_printf(sc->alc_dev, 1554 "could not load DMA'able memory for Tx ring.\n"); 1555 goto fail; 1556 } 1557 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1558 1559 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1560 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1561 (void **)&sc->alc_rdata.alc_cmb, 1562 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1563 &sc->alc_cdata.alc_cmb_map); 1564 if (error != 0) { 1565 device_printf(sc->alc_dev, 1566 "could not allocate DMA'able memory for CMB.\n"); 1567 goto fail; 1568 } 1569 ctx.alc_busaddr = 0; 1570 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1571 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1572 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1573 if (error != 0 || ctx.alc_busaddr == 0) { 1574 device_printf(sc->alc_dev, 1575 "could not load DMA'able memory for CMB.\n"); 1576 goto fail; 1577 } 1578 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1579 1580 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1581 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1582 (void **)&sc->alc_rdata.alc_smb, 1583 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1584 &sc->alc_cdata.alc_smb_map); 1585 if (error != 0) { 1586 device_printf(sc->alc_dev, 1587 "could not allocate DMA'able memory for SMB.\n"); 1588 goto fail; 1589 } 1590 ctx.alc_busaddr = 0; 1591 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1592 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1593 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1594 if (error != 0 || ctx.alc_busaddr == 0) { 1595 device_printf(sc->alc_dev, 1596 "could not load DMA'able memory for CMB.\n"); 1597 goto fail; 1598 } 1599 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1600 1601 /* Make sure we've not crossed 4GB boundary. */ 1602 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1603 (error = alc_check_boundary(sc)) != 0) { 1604 device_printf(sc->alc_dev, "4GB boundary crossed, " 1605 "switching to 32bit DMA addressing mode.\n"); 1606 alc_dma_free(sc); 1607 /* 1608 * Limit max allowable DMA address space to 32bit 1609 * and try again. 1610 */ 1611 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1612 goto again; 1613 } 1614 1615 /* 1616 * Create Tx buffer parent tag. 1617 * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers 1618 * so it needs separate parent DMA tag as parent DMA address 1619 * space could be restricted to be within 32bit address space 1620 * by 4GB boundary crossing. 1621 */ 1622 error = bus_dma_tag_create( 1623 sc->alc_cdata.alc_parent_tag, /* parent */ 1624 1, 0, /* alignment, boundary */ 1625 BUS_SPACE_MAXADDR, /* lowaddr */ 1626 BUS_SPACE_MAXADDR, /* highaddr */ 1627 NULL, NULL, /* filter, filterarg */ 1628 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1629 0, /* nsegments */ 1630 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1631 0, /* flags */ 1632 &sc->alc_cdata.alc_buffer_tag); 1633 if (error != 0) { 1634 device_printf(sc->alc_dev, 1635 "could not create parent buffer DMA tag.\n"); 1636 goto fail; 1637 } 1638 1639 /* Create DMA tag for Tx buffers. */ 1640 error = bus_dma_tag_create( 1641 sc->alc_cdata.alc_buffer_tag, /* parent */ 1642 1, 0, /* alignment, boundary */ 1643 BUS_SPACE_MAXADDR, /* lowaddr */ 1644 BUS_SPACE_MAXADDR, /* highaddr */ 1645 NULL, NULL, /* filter, filterarg */ 1646 ALC_TSO_MAXSIZE, /* maxsize */ 1647 ALC_MAXTXSEGS, /* nsegments */ 1648 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1649 0, /* flags */ 1650 &sc->alc_cdata.alc_tx_tag); 1651 if (error != 0) { 1652 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1653 goto fail; 1654 } 1655 1656 /* Create DMA tag for Rx buffers. */ 1657 error = bus_dma_tag_create( 1658 sc->alc_cdata.alc_buffer_tag, /* parent */ 1659 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1660 BUS_SPACE_MAXADDR, /* lowaddr */ 1661 BUS_SPACE_MAXADDR, /* highaddr */ 1662 NULL, NULL, /* filter, filterarg */ 1663 MCLBYTES, /* maxsize */ 1664 1, /* nsegments */ 1665 MCLBYTES, /* maxsegsize */ 1666 0, /* flags */ 1667 &sc->alc_cdata.alc_rx_tag); 1668 if (error != 0) { 1669 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1670 goto fail; 1671 } 1672 /* Create DMA maps for Tx buffers. */ 1673 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1674 txd = &sc->alc_cdata.alc_txdesc[i]; 1675 txd->tx_m = NULL; 1676 txd->tx_dmamap = NULL; 1677 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 1678 BUS_DMA_WAITOK, &txd->tx_dmamap); 1679 if (error != 0) { 1680 device_printf(sc->alc_dev, 1681 "could not create Tx dmamap.\n"); 1682 goto fail; 1683 } 1684 } 1685 /* Create DMA maps for Rx buffers. */ 1686 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 1687 BUS_DMA_WAITOK, 1688 &sc->alc_cdata.alc_rx_sparemap); 1689 if (error) { 1690 device_printf(sc->alc_dev, 1691 "could not create spare Rx dmamap.\n"); 1692 goto fail; 1693 } 1694 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1695 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1696 rxd->rx_m = NULL; 1697 rxd->rx_dmamap = NULL; 1698 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 1699 BUS_DMA_WAITOK, 1700 &rxd->rx_dmamap); 1701 if (error != 0) { 1702 device_printf(sc->alc_dev, 1703 "could not create Rx dmamap.\n"); 1704 goto fail; 1705 } 1706 } 1707 1708 fail: 1709 return (error); 1710 } 1711 1712 static void 1713 alc_dma_free(struct alc_softc *sc) 1714 { 1715 struct alc_txdesc *txd; 1716 struct alc_rxdesc *rxd; 1717 int i; 1718 1719 /* Tx buffers. */ 1720 if (sc->alc_cdata.alc_tx_tag != NULL) { 1721 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1722 txd = &sc->alc_cdata.alc_txdesc[i]; 1723 if (txd->tx_dmamap != NULL) { 1724 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1725 txd->tx_dmamap); 1726 txd->tx_dmamap = NULL; 1727 } 1728 } 1729 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1730 sc->alc_cdata.alc_tx_tag = NULL; 1731 } 1732 /* Rx buffers */ 1733 if (sc->alc_cdata.alc_rx_tag != NULL) { 1734 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1735 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1736 if (rxd->rx_dmamap != NULL) { 1737 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1738 rxd->rx_dmamap); 1739 rxd->rx_dmamap = NULL; 1740 } 1741 } 1742 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1743 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1744 sc->alc_cdata.alc_rx_sparemap); 1745 sc->alc_cdata.alc_rx_sparemap = NULL; 1746 } 1747 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1748 sc->alc_cdata.alc_rx_tag = NULL; 1749 } 1750 /* Tx descriptor ring. */ 1751 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1752 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1753 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1754 sc->alc_cdata.alc_tx_ring_map); 1755 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1756 sc->alc_rdata.alc_tx_ring != NULL) 1757 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1758 sc->alc_rdata.alc_tx_ring, 1759 sc->alc_cdata.alc_tx_ring_map); 1760 sc->alc_rdata.alc_tx_ring = NULL; 1761 sc->alc_cdata.alc_tx_ring_map = NULL; 1762 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1763 sc->alc_cdata.alc_tx_ring_tag = NULL; 1764 } 1765 /* Rx ring. */ 1766 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1767 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1768 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1769 sc->alc_cdata.alc_rx_ring_map); 1770 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1771 sc->alc_rdata.alc_rx_ring != NULL) 1772 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1773 sc->alc_rdata.alc_rx_ring, 1774 sc->alc_cdata.alc_rx_ring_map); 1775 sc->alc_rdata.alc_rx_ring = NULL; 1776 sc->alc_cdata.alc_rx_ring_map = NULL; 1777 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1778 sc->alc_cdata.alc_rx_ring_tag = NULL; 1779 } 1780 /* Rx return ring. */ 1781 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1782 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1783 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1784 sc->alc_cdata.alc_rr_ring_map); 1785 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1786 sc->alc_rdata.alc_rr_ring != NULL) 1787 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1788 sc->alc_rdata.alc_rr_ring, 1789 sc->alc_cdata.alc_rr_ring_map); 1790 sc->alc_rdata.alc_rr_ring = NULL; 1791 sc->alc_cdata.alc_rr_ring_map = NULL; 1792 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1793 sc->alc_cdata.alc_rr_ring_tag = NULL; 1794 } 1795 /* CMB block */ 1796 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1797 if (sc->alc_cdata.alc_cmb_map != NULL) 1798 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1799 sc->alc_cdata.alc_cmb_map); 1800 if (sc->alc_cdata.alc_cmb_map != NULL && 1801 sc->alc_rdata.alc_cmb != NULL) 1802 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1803 sc->alc_rdata.alc_cmb, 1804 sc->alc_cdata.alc_cmb_map); 1805 sc->alc_rdata.alc_cmb = NULL; 1806 sc->alc_cdata.alc_cmb_map = NULL; 1807 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1808 sc->alc_cdata.alc_cmb_tag = NULL; 1809 } 1810 /* SMB block */ 1811 if (sc->alc_cdata.alc_smb_tag != NULL) { 1812 if (sc->alc_cdata.alc_smb_map != NULL) 1813 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1814 sc->alc_cdata.alc_smb_map); 1815 if (sc->alc_cdata.alc_smb_map != NULL && 1816 sc->alc_rdata.alc_smb != NULL) 1817 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1818 sc->alc_rdata.alc_smb, 1819 sc->alc_cdata.alc_smb_map); 1820 sc->alc_rdata.alc_smb = NULL; 1821 sc->alc_cdata.alc_smb_map = NULL; 1822 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1823 sc->alc_cdata.alc_smb_tag = NULL; 1824 } 1825 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1826 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1827 sc->alc_cdata.alc_buffer_tag = NULL; 1828 } 1829 if (sc->alc_cdata.alc_parent_tag != NULL) { 1830 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1831 sc->alc_cdata.alc_parent_tag = NULL; 1832 } 1833 } 1834 1835 static int 1836 alc_shutdown(device_t dev) 1837 { 1838 1839 return (alc_suspend(dev)); 1840 } 1841 1842 #if 0 1843 /* XXX: LINK SPEED */ 1844 /* 1845 * Note, this driver resets the link speed to 10/100Mbps by 1846 * restarting auto-negotiation in suspend/shutdown phase but we 1847 * don't know whether that auto-negotiation would succeed or not 1848 * as driver has no control after powering off/suspend operation. 1849 * If the renegotiation fail WOL may not work. Running at 1Gbps 1850 * will draw more power than 375mA at 3.3V which is specified in 1851 * PCI specification and that would result in complete 1852 * shutdowning power to ethernet controller. 1853 * 1854 * TODO 1855 * Save current negotiated media speed/duplex/flow-control to 1856 * softc and restore the same link again after resuming. PHY 1857 * handling such as power down/resetting to 100Mbps may be better 1858 * handled in suspend method in phy driver. 1859 */ 1860 static void 1861 alc_setlinkspeed(struct alc_softc *sc) 1862 { 1863 struct mii_data *mii; 1864 int aneg, i; 1865 1866 mii = device_get_softc(sc->alc_miibus); 1867 mii_pollstat(mii); 1868 aneg = 0; 1869 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1870 (IFM_ACTIVE | IFM_AVALID)) { 1871 switch IFM_SUBTYPE(mii->mii_media_active) { 1872 case IFM_10_T: 1873 case IFM_100_TX: 1874 return; 1875 case IFM_1000_T: 1876 aneg++; 1877 break; 1878 default: 1879 break; 1880 } 1881 } 1882 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1883 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1884 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1885 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1886 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1887 DELAY(1000); 1888 if (aneg != 0) { 1889 /* 1890 * Poll link state until alc(4) get a 10/100Mbps link. 1891 */ 1892 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1893 mii_pollstat(mii); 1894 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1895 == (IFM_ACTIVE | IFM_AVALID)) { 1896 switch (IFM_SUBTYPE( 1897 mii->mii_media_active)) { 1898 case IFM_10_T: 1899 case IFM_100_TX: 1900 alc_mac_config(sc); 1901 return; 1902 default: 1903 break; 1904 } 1905 } 1906 ALC_UNLOCK(sc); 1907 pause("alclnk", hz); 1908 ALC_LOCK(sc); 1909 } 1910 if (i == MII_ANEGTICKS_GIGE) 1911 device_printf(sc->alc_dev, 1912 "establishing a link failed, WOL may not work!"); 1913 } 1914 /* 1915 * No link, force MAC to have 100Mbps, full-duplex link. 1916 * This is the last resort and may/may not work. 1917 */ 1918 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1919 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1920 alc_mac_config(sc); 1921 } 1922 #endif 1923 1924 #if 0 1925 /* XXX: WOL */ 1926 static void 1927 alc_setwol(struct alc_softc *sc) 1928 { 1929 struct ifnet *ifp; 1930 uint32_t reg, pmcs; 1931 uint16_t pmstat; 1932 1933 ALC_LOCK_ASSERT(sc); 1934 1935 alc_disable_l0s_l1(sc); 1936 ifp = sc->alc_ifp; 1937 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 1938 /* Disable WOL. */ 1939 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1940 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1941 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1942 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1943 /* Force PHY power down. */ 1944 alc_phy_down(sc); 1945 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1946 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1947 return; 1948 } 1949 1950 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1951 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1952 alc_setlinkspeed(sc); 1953 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1954 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 1955 } 1956 1957 pmcs = 0; 1958 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1959 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1960 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1961 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1962 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1963 MAC_CFG_BCAST); 1964 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1965 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1966 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1967 reg |= MAC_CFG_RX_ENB; 1968 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1969 1970 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1971 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1972 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1973 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1974 /* WOL disabled, PHY power down. */ 1975 alc_phy_down(sc); 1976 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1977 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1978 1979 } 1980 /* Request PME. */ 1981 pmstat = pci_read_config(sc->alc_dev, 1982 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1983 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1984 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1985 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1986 pci_write_config(sc->alc_dev, 1987 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1988 } 1989 #endif 1990 1991 static int 1992 alc_suspend(device_t dev) 1993 { 1994 struct alc_softc *sc; 1995 1996 sc = device_get_softc(dev); 1997 1998 ALC_LOCK(sc); 1999 alc_stop(sc); 2000 #if 0 2001 /* XXX: WOL */ 2002 alc_setwol(sc); 2003 #endif 2004 ALC_UNLOCK(sc); 2005 2006 return (0); 2007 } 2008 2009 static int 2010 alc_resume(device_t dev) 2011 { 2012 struct alc_softc *sc; 2013 struct ifnet *ifp; 2014 uint16_t pmstat; 2015 2016 sc = device_get_softc(dev); 2017 2018 ALC_LOCK(sc); 2019 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2020 /* Disable PME and clear PME status. */ 2021 pmstat = pci_read_config(sc->alc_dev, 2022 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2023 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2024 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2025 pci_write_config(sc->alc_dev, 2026 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2027 } 2028 } 2029 /* Reset PHY. */ 2030 alc_phy_reset(sc); 2031 ifp = sc->alc_ifp; 2032 if ((ifp->if_flags & IFF_UP) != 0) { 2033 ifp->if_flags &= ~IFF_RUNNING; 2034 alc_init_locked(sc); 2035 } 2036 ALC_UNLOCK(sc); 2037 2038 return (0); 2039 } 2040 2041 static int 2042 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2043 { 2044 struct alc_txdesc *txd, *txd_last; 2045 struct tx_desc *desc; 2046 struct mbuf *m; 2047 struct ip *ip; 2048 struct tcphdr *tcp; 2049 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2050 bus_dmamap_t map; 2051 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2052 int error, idx, nsegs, prod; 2053 2054 ALC_LOCK_ASSERT(sc); 2055 2056 M_ASSERTPKTHDR((*m_head)); 2057 2058 m = *m_head; 2059 ip = NULL; 2060 tcp = NULL; 2061 ip_off = poff = 0; 2062 #if 0 2063 /* XXX: TSO */ 2064 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2065 /* 2066 * AR813x/AR815x requires offset of TCP/UDP header in its 2067 * Tx descriptor to perform Tx checksum offloading. TSO 2068 * also requires TCP header offset and modification of 2069 * IP/TCP header. This kind of operation takes many CPU 2070 * cycles on FreeBSD so fast host CPU is required to get 2071 * smooth TSO performance. 2072 */ 2073 struct ether_header *eh; 2074 2075 if (M_WRITABLE(m) == 0) { 2076 /* Get a writable copy. */ 2077 m = m_dup(*m_head, MB_DONTWAIT); 2078 /* Release original mbufs. */ 2079 m_freem(*m_head); 2080 if (m == NULL) { 2081 *m_head = NULL; 2082 return (ENOBUFS); 2083 } 2084 *m_head = m; 2085 } 2086 2087 ip_off = sizeof(struct ether_header); 2088 m = m_pullup(m, ip_off + sizeof(struct ip)); 2089 if (m == NULL) { 2090 *m_head = NULL; 2091 return (ENOBUFS); 2092 } 2093 eh = mtod(m, struct ether_header *); 2094 /* 2095 * Check if hardware VLAN insertion is off. 2096 * Additional check for LLC/SNAP frame? 2097 */ 2098 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2099 ip_off = sizeof(struct ether_vlan_header); 2100 m = m_pullup(m, ip_off); 2101 if (m == NULL) { 2102 *m_head = NULL; 2103 return (ENOBUFS); 2104 } 2105 } 2106 m = m_pullup(m, ip_off + sizeof(struct ip)); 2107 if (m == NULL) { 2108 *m_head = NULL; 2109 return (ENOBUFS); 2110 } 2111 ip = (struct ip *)(mtod(m, char *) + ip_off); 2112 poff = ip_off + (ip->ip_hl << 2); 2113 2114 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2115 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2116 if (m == NULL) { 2117 *m_head = NULL; 2118 return (ENOBUFS); 2119 } 2120 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2121 m = m_pullup(m, poff + (tcp->th_off << 2)); 2122 if (m == NULL) { 2123 *m_head = NULL; 2124 return (ENOBUFS); 2125 } 2126 /* 2127 * Due to strict adherence of Microsoft NDIS 2128 * Large Send specification, hardware expects 2129 * a pseudo TCP checksum inserted by upper 2130 * stack. Unfortunately the pseudo TCP 2131 * checksum that NDIS refers to does not include 2132 * TCP payload length so driver should recompute 2133 * the pseudo checksum here. Hopefully this 2134 * wouldn't be much burden on modern CPUs. 2135 * 2136 * Reset IP checksum and recompute TCP pseudo 2137 * checksum as NDIS specification said. 2138 */ 2139 ip->ip_sum = 0; 2140 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2141 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2142 } 2143 *m_head = m; 2144 } 2145 #endif /* TSO */ 2146 2147 prod = sc->alc_cdata.alc_tx_prod; 2148 txd = &sc->alc_cdata.alc_txdesc[prod]; 2149 txd_last = txd; 2150 map = txd->tx_dmamap; 2151 2152 error = bus_dmamap_load_mbuf_defrag( 2153 sc->alc_cdata.alc_tx_tag, map, m_head, 2154 txsegs, ALC_MAXTXSEGS, &nsegs, BUS_DMA_NOWAIT); 2155 if (error) { 2156 m_freem(*m_head); 2157 *m_head = NULL; 2158 return (error); 2159 } 2160 if (nsegs == 0) { 2161 m_freem(*m_head); 2162 *m_head = NULL; 2163 return (EIO); 2164 } 2165 2166 /* Check descriptor overrun. */ 2167 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2168 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2169 return (ENOBUFS); 2170 } 2171 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2172 2173 m = *m_head; 2174 cflags = TD_ETHERNET; 2175 vtag = 0; 2176 desc = NULL; 2177 idx = 0; 2178 /* Configure VLAN hardware tag insertion. */ 2179 if ((m->m_flags & M_VLANTAG) != 0) { 2180 vtag = htons(m->m_pkthdr.ether_vlantag); 2181 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2182 cflags |= TD_INS_VLAN_TAG; 2183 } 2184 /* Configure Tx checksum offload. */ 2185 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2186 #ifdef ALC_USE_CUSTOM_CSUM 2187 cflags |= TD_CUSTOM_CSUM; 2188 /* Set checksum start offset. */ 2189 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2190 TD_PLOAD_OFFSET_MASK; 2191 /* Set checksum insertion position of TCP/UDP. */ 2192 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2193 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2194 #else 2195 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2196 cflags |= TD_IPCSUM; 2197 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2198 cflags |= TD_TCPCSUM; 2199 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2200 cflags |= TD_UDPCSUM; 2201 /* Set TCP/UDP header offset. */ 2202 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2203 TD_L4HDR_OFFSET_MASK; 2204 #endif 2205 } else if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2206 /* Request TSO and set MSS. */ 2207 cflags |= TD_TSO | TD_TSO_DESCV1; 2208 #if 0 2209 /* XXX: TSO */ 2210 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2211 TD_MSS_MASK; 2212 /* Set TCP header offset. */ 2213 #endif 2214 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2215 TD_TCPHDR_OFFSET_MASK; 2216 /* 2217 * AR813x/AR815x requires the first buffer should 2218 * only hold IP/TCP header data. Payload should 2219 * be handled in other descriptors. 2220 */ 2221 hdrlen = poff + (tcp->th_off << 2); 2222 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2223 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2224 desc->flags = htole32(cflags); 2225 desc->addr = htole64(txsegs[0].ds_addr); 2226 sc->alc_cdata.alc_tx_cnt++; 2227 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2228 if (m->m_len - hdrlen > 0) { 2229 /* Handle remaining payload of the first fragment. */ 2230 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2231 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2232 vtag)); 2233 desc->flags = htole32(cflags); 2234 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2235 sc->alc_cdata.alc_tx_cnt++; 2236 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2237 } 2238 /* Handle remaining fragments. */ 2239 idx = 1; 2240 } 2241 for (; idx < nsegs; idx++) { 2242 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2243 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2244 desc->flags = htole32(cflags); 2245 desc->addr = htole64(txsegs[idx].ds_addr); 2246 sc->alc_cdata.alc_tx_cnt++; 2247 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2248 } 2249 /* Update producer index. */ 2250 sc->alc_cdata.alc_tx_prod = prod; 2251 2252 /* Finally set EOP on the last descriptor. */ 2253 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2254 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2255 desc->flags |= htole32(TD_EOP); 2256 2257 /* Swap dmamap of the first and the last. */ 2258 txd = &sc->alc_cdata.alc_txdesc[prod]; 2259 map = txd_last->tx_dmamap; 2260 txd_last->tx_dmamap = txd->tx_dmamap; 2261 txd->tx_dmamap = map; 2262 txd->tx_m = m; 2263 2264 return (0); 2265 } 2266 2267 static void 2268 alc_tx_task(void *arg, int pending) 2269 { 2270 struct ifnet *ifp; 2271 2272 ifp = (struct ifnet *)arg; 2273 alc_start(ifp); 2274 } 2275 2276 static void 2277 alc_start(struct ifnet *ifp) 2278 { 2279 struct alc_softc *sc; 2280 struct mbuf *m_head; 2281 int enq; 2282 2283 sc = ifp->if_softc; 2284 2285 ALC_LOCK(sc); 2286 2287 /* Reclaim transmitted frames. */ 2288 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2289 alc_txeof(sc); 2290 2291 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 2292 ALC_UNLOCK(sc); 2293 return; 2294 } 2295 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2296 ifq_purge(&ifp->if_snd); 2297 ALC_UNLOCK(sc); 2298 return; 2299 } 2300 2301 for (enq = 0; !ifq_is_empty(&ifp->if_snd); ) { 2302 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2303 if (m_head == NULL) 2304 break; 2305 /* 2306 * Pack the data into the transmit ring. If we 2307 * don't have room, set the OACTIVE flag and wait 2308 * for the NIC to drain the ring. 2309 */ 2310 if (alc_encap(sc, &m_head)) { 2311 if (m_head == NULL) 2312 break; 2313 ifq_prepend(&ifp->if_snd, m_head); 2314 ifp->if_flags |= IFF_OACTIVE; 2315 break; 2316 } 2317 2318 enq++; 2319 /* 2320 * If there's a BPF listener, bounce a copy of this frame 2321 * to him. 2322 */ 2323 ETHER_BPF_MTAP(ifp, m_head); 2324 } 2325 2326 if (enq > 0) { 2327 /* Sync descriptors. */ 2328 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2329 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2330 /* Kick. Assume we're using normal Tx priority queue. */ 2331 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2332 (sc->alc_cdata.alc_tx_prod << 2333 MBOX_TD_PROD_LO_IDX_SHIFT) & 2334 MBOX_TD_PROD_LO_IDX_MASK); 2335 /* Set a timeout in case the chip goes out to lunch. */ 2336 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2337 } 2338 2339 ALC_UNLOCK(sc); 2340 } 2341 2342 static void 2343 alc_watchdog(struct alc_softc *sc) 2344 { 2345 struct ifnet *ifp; 2346 2347 ALC_LOCK_ASSERT(sc); 2348 2349 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2350 return; 2351 2352 ifp = sc->alc_ifp; 2353 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2354 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2355 ifp->if_oerrors++; 2356 ifp->if_flags &= ~IFF_RUNNING; 2357 alc_init_locked(sc); 2358 return; 2359 } 2360 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2361 ifp->if_oerrors++; 2362 ifp->if_flags &= ~IFF_RUNNING; 2363 alc_init_locked(sc); 2364 if (!ifq_is_empty(&ifp->if_snd)) 2365 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2366 } 2367 2368 static int 2369 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 2370 { 2371 struct alc_softc *sc; 2372 struct ifreq *ifr; 2373 struct mii_data *mii; 2374 int error, mask; 2375 2376 (void)cr; 2377 sc = ifp->if_softc; 2378 ifr = (struct ifreq *)data; 2379 error = 0; 2380 switch (cmd) { 2381 case SIOCSIFMTU: 2382 if (ifr->ifr_mtu < ETHERMIN || 2383 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 2384 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 2385 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2386 ifr->ifr_mtu > ETHERMTU)) { 2387 error = EINVAL; 2388 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2389 ALC_LOCK(sc); 2390 ifp->if_mtu = ifr->ifr_mtu; 2391 /* AR813x/AR815x has 13 bits MSS field. */ 2392 if (ifp->if_mtu > ALC_TSO_MTU && 2393 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2394 ifp->if_capenable &= ~IFCAP_TSO4; 2395 ifp->if_hwassist &= ~CSUM_TSO; 2396 } 2397 ALC_UNLOCK(sc); 2398 } 2399 break; 2400 case SIOCSIFFLAGS: 2401 ALC_LOCK(sc); 2402 if ((ifp->if_flags & IFF_UP) != 0) { 2403 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2404 ((ifp->if_flags ^ sc->alc_if_flags) & 2405 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2406 alc_rxfilter(sc); 2407 else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0) 2408 alc_init_locked(sc); 2409 } else if ((ifp->if_flags & IFF_RUNNING) != 0) 2410 alc_stop(sc); 2411 sc->alc_if_flags = ifp->if_flags; 2412 ALC_UNLOCK(sc); 2413 break; 2414 case SIOCADDMULTI: 2415 case SIOCDELMULTI: 2416 ALC_LOCK(sc); 2417 if ((ifp->if_flags & IFF_RUNNING) != 0) 2418 alc_rxfilter(sc); 2419 ALC_UNLOCK(sc); 2420 break; 2421 case SIOCSIFMEDIA: 2422 case SIOCGIFMEDIA: 2423 mii = device_get_softc(sc->alc_miibus); 2424 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2425 break; 2426 case SIOCSIFCAP: 2427 ALC_LOCK(sc); 2428 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2429 if ((mask & IFCAP_TXCSUM) != 0 && 2430 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2431 ifp->if_capenable ^= IFCAP_TXCSUM; 2432 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2433 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2434 else 2435 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2436 } 2437 if ((mask & IFCAP_TSO4) != 0 && 2438 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2439 ifp->if_capenable ^= IFCAP_TSO4; 2440 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2441 /* AR813x/AR815x has 13 bits MSS field. */ 2442 if (ifp->if_mtu > ALC_TSO_MTU) { 2443 ifp->if_capenable &= ~IFCAP_TSO4; 2444 ifp->if_hwassist &= ~CSUM_TSO; 2445 } else 2446 ifp->if_hwassist |= CSUM_TSO; 2447 } else 2448 ifp->if_hwassist &= ~CSUM_TSO; 2449 } 2450 #if 0 2451 /* XXX: WOL */ 2452 if ((mask & IFCAP_WOL_MCAST) != 0 && 2453 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2454 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2455 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2456 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2457 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2458 #endif 2459 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2460 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2461 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2462 alc_rxvlan(sc); 2463 } 2464 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2465 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2466 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2467 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2468 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2469 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2470 /* 2471 * VLAN hardware tagging is required to do checksum 2472 * offload or TSO on VLAN interface. Checksum offload 2473 * on VLAN interface also requires hardware checksum 2474 * offload of parent interface. 2475 */ 2476 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 2477 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2478 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2479 ifp->if_capenable &= 2480 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2481 ALC_UNLOCK(sc); 2482 // XXX VLAN_CAPABILITIES(ifp); 2483 break; 2484 default: 2485 error = ether_ioctl(ifp, cmd, data); 2486 break; 2487 } 2488 2489 return (error); 2490 } 2491 2492 static void 2493 alc_mac_config(struct alc_softc *sc) 2494 { 2495 struct mii_data *mii; 2496 uint32_t reg; 2497 2498 ALC_LOCK_ASSERT(sc); 2499 2500 mii = device_get_softc(sc->alc_miibus); 2501 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2502 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2503 MAC_CFG_SPEED_MASK); 2504 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 2505 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 2506 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 2507 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2508 } 2509 /* Reprogram MAC with resolved speed/duplex. */ 2510 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2511 case IFM_10_T: 2512 case IFM_100_TX: 2513 reg |= MAC_CFG_SPEED_10_100; 2514 break; 2515 case IFM_1000_T: 2516 reg |= MAC_CFG_SPEED_1000; 2517 break; 2518 } 2519 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2520 reg |= MAC_CFG_FULL_DUPLEX; 2521 #ifdef notyet 2522 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2523 reg |= MAC_CFG_TX_FC; 2524 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2525 reg |= MAC_CFG_RX_FC; 2526 #endif 2527 } 2528 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2529 } 2530 2531 static void 2532 alc_stats_clear(struct alc_softc *sc) 2533 { 2534 struct smb sb, *smb; 2535 uint32_t *reg; 2536 int i; 2537 2538 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2539 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2540 sc->alc_cdata.alc_smb_map, 2541 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2542 smb = sc->alc_rdata.alc_smb; 2543 /* Update done, clear. */ 2544 smb->updated = 0; 2545 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2546 sc->alc_cdata.alc_smb_map, 2547 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2548 } else { 2549 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2550 reg++) { 2551 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2552 i += sizeof(uint32_t); 2553 } 2554 /* Read Tx statistics. */ 2555 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2556 reg++) { 2557 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2558 i += sizeof(uint32_t); 2559 } 2560 } 2561 } 2562 2563 static void 2564 alc_stats_update(struct alc_softc *sc) 2565 { 2566 struct alc_hw_stats *stat; 2567 struct smb sb, *smb; 2568 struct ifnet *ifp; 2569 uint32_t *reg; 2570 int i; 2571 2572 ALC_LOCK_ASSERT(sc); 2573 2574 ifp = sc->alc_ifp; 2575 stat = &sc->alc_stats; 2576 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2577 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2578 sc->alc_cdata.alc_smb_map, 2579 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2580 smb = sc->alc_rdata.alc_smb; 2581 if (smb->updated == 0) 2582 return; 2583 } else { 2584 smb = &sb; 2585 /* Read Rx statistics. */ 2586 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2587 reg++) { 2588 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2589 i += sizeof(uint32_t); 2590 } 2591 /* Read Tx statistics. */ 2592 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2593 reg++) { 2594 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2595 i += sizeof(uint32_t); 2596 } 2597 } 2598 2599 /* Rx stats. */ 2600 stat->rx_frames += smb->rx_frames; 2601 stat->rx_bcast_frames += smb->rx_bcast_frames; 2602 stat->rx_mcast_frames += smb->rx_mcast_frames; 2603 stat->rx_pause_frames += smb->rx_pause_frames; 2604 stat->rx_control_frames += smb->rx_control_frames; 2605 stat->rx_crcerrs += smb->rx_crcerrs; 2606 stat->rx_lenerrs += smb->rx_lenerrs; 2607 stat->rx_bytes += smb->rx_bytes; 2608 stat->rx_runts += smb->rx_runts; 2609 stat->rx_fragments += smb->rx_fragments; 2610 stat->rx_pkts_64 += smb->rx_pkts_64; 2611 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2612 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2613 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2614 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2615 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2616 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2617 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2618 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2619 stat->rx_rrs_errs += smb->rx_rrs_errs; 2620 stat->rx_alignerrs += smb->rx_alignerrs; 2621 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2622 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2623 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2624 2625 /* Tx stats. */ 2626 stat->tx_frames += smb->tx_frames; 2627 stat->tx_bcast_frames += smb->tx_bcast_frames; 2628 stat->tx_mcast_frames += smb->tx_mcast_frames; 2629 stat->tx_pause_frames += smb->tx_pause_frames; 2630 stat->tx_excess_defer += smb->tx_excess_defer; 2631 stat->tx_control_frames += smb->tx_control_frames; 2632 stat->tx_deferred += smb->tx_deferred; 2633 stat->tx_bytes += smb->tx_bytes; 2634 stat->tx_pkts_64 += smb->tx_pkts_64; 2635 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2636 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2637 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2638 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2639 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2640 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2641 stat->tx_single_colls += smb->tx_single_colls; 2642 stat->tx_multi_colls += smb->tx_multi_colls; 2643 stat->tx_late_colls += smb->tx_late_colls; 2644 stat->tx_excess_colls += smb->tx_excess_colls; 2645 stat->tx_abort += smb->tx_abort; 2646 stat->tx_underrun += smb->tx_underrun; 2647 stat->tx_desc_underrun += smb->tx_desc_underrun; 2648 stat->tx_lenerrs += smb->tx_lenerrs; 2649 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2650 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2651 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2652 2653 /* Update counters in ifnet. */ 2654 ifp->if_opackets += smb->tx_frames; 2655 2656 ifp->if_collisions += smb->tx_single_colls + 2657 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2658 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2659 2660 /* 2661 * XXX 2662 * tx_pkts_truncated counter looks suspicious. It constantly 2663 * increments with no sign of Tx errors. This may indicate 2664 * the counter name is not correct one so I've removed the 2665 * counter in output errors. 2666 */ 2667 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2668 smb->tx_underrun; 2669 2670 ifp->if_ipackets += smb->rx_frames; 2671 2672 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2673 smb->rx_runts + smb->rx_pkts_truncated + 2674 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2675 smb->rx_alignerrs; 2676 2677 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2678 /* Update done, clear. */ 2679 smb->updated = 0; 2680 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2681 sc->alc_cdata.alc_smb_map, 2682 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2683 } 2684 } 2685 2686 static void 2687 alc_intr(void *arg) 2688 { 2689 struct alc_softc *sc; 2690 uint32_t status; 2691 2692 sc = (struct alc_softc *)arg; 2693 2694 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2695 if ((status & ALC_INTRS) == 0) { 2696 return; 2697 } 2698 /* Disable interrupts. */ 2699 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2700 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2701 2702 return; 2703 } 2704 2705 static void 2706 alc_int_task(void *arg, int pending) 2707 { 2708 struct alc_softc *sc; 2709 struct ifnet *ifp; 2710 uint32_t status; 2711 int more; 2712 2713 sc = (struct alc_softc *)arg; 2714 ifp = sc->alc_ifp; 2715 2716 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2717 more = atomic_readandclear_32(&sc->alc_morework); 2718 if (more != 0) 2719 status |= INTR_RX_PKT; 2720 if ((status & ALC_INTRS) == 0) 2721 goto done; 2722 2723 /* Acknowledge interrupts but still disable interrupts. */ 2724 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2725 2726 more = 0; 2727 if ((ifp->if_flags & IFF_RUNNING) != 0) { 2728 if ((status & INTR_RX_PKT) != 0) { 2729 more = alc_rxintr(sc, sc->alc_process_limit); 2730 if (more == EAGAIN) 2731 atomic_set_int(&sc->alc_morework, 1); 2732 else if (more == EIO) { 2733 ALC_LOCK(sc); 2734 ifp->if_flags &= ~IFF_RUNNING; 2735 alc_init_locked(sc); 2736 ALC_UNLOCK(sc); 2737 return; 2738 } 2739 } 2740 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2741 INTR_TXQ_TO_RST)) != 0) { 2742 if ((status & INTR_DMA_RD_TO_RST) != 0) 2743 device_printf(sc->alc_dev, 2744 "DMA read error! -- resetting\n"); 2745 if ((status & INTR_DMA_WR_TO_RST) != 0) 2746 device_printf(sc->alc_dev, 2747 "DMA write error! -- resetting\n"); 2748 if ((status & INTR_TXQ_TO_RST) != 0) 2749 device_printf(sc->alc_dev, 2750 "TxQ reset! -- resetting\n"); 2751 ALC_LOCK(sc); 2752 ifp->if_flags &= ~IFF_RUNNING; 2753 alc_init_locked(sc); 2754 ALC_UNLOCK(sc); 2755 return; 2756 } 2757 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2758 !ifq_is_empty(&ifp->if_snd)) 2759 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2760 } 2761 2762 if (more == EAGAIN || 2763 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2764 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2765 return; 2766 } 2767 2768 done: 2769 if ((ifp->if_flags & IFF_RUNNING) != 0) { 2770 /* Re-enable interrupts if we're running. */ 2771 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2772 } 2773 } 2774 2775 static void 2776 alc_txeof(struct alc_softc *sc) 2777 { 2778 struct ifnet *ifp; 2779 struct alc_txdesc *txd; 2780 uint32_t cons, prod; 2781 int prog; 2782 2783 ALC_LOCK_ASSERT(sc); 2784 2785 ifp = sc->alc_ifp; 2786 2787 if (sc->alc_cdata.alc_tx_cnt == 0) 2788 return; 2789 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2790 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2791 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2792 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2793 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2794 prod = sc->alc_rdata.alc_cmb->cons; 2795 } else 2796 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2797 /* Assume we're using normal Tx priority queue. */ 2798 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2799 MBOX_TD_CONS_LO_IDX_SHIFT; 2800 cons = sc->alc_cdata.alc_tx_cons; 2801 /* 2802 * Go through our Tx list and free mbufs for those 2803 * frames which have been transmitted. 2804 */ 2805 for (prog = 0; cons != prod; prog++, 2806 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2807 if (sc->alc_cdata.alc_tx_cnt <= 0) 2808 break; 2809 prog++; 2810 ifp->if_flags &= ~IFF_OACTIVE; 2811 sc->alc_cdata.alc_tx_cnt--; 2812 txd = &sc->alc_cdata.alc_txdesc[cons]; 2813 if (txd->tx_m != NULL) { 2814 /* Reclaim transmitted mbufs. */ 2815 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2816 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2817 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2818 txd->tx_dmamap); 2819 m_freem(txd->tx_m); 2820 txd->tx_m = NULL; 2821 } 2822 } 2823 2824 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2825 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2826 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2827 sc->alc_cdata.alc_tx_cons = cons; 2828 /* 2829 * Unarm watchdog timer only when there is no pending 2830 * frames in Tx queue. 2831 */ 2832 if (sc->alc_cdata.alc_tx_cnt == 0) 2833 sc->alc_watchdog_timer = 0; 2834 } 2835 2836 static int 2837 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2838 { 2839 struct mbuf *m; 2840 bus_dma_segment_t segs[1]; 2841 bus_dmamap_t map; 2842 int nsegs; 2843 int error; 2844 2845 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2846 if (m == NULL) 2847 return (ENOBUFS); 2848 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2849 #ifndef __NO_STRICT_ALIGNMENT 2850 m_adj(m, sizeof(uint64_t)); 2851 #endif 2852 2853 error = bus_dmamap_load_mbuf_segment( 2854 sc->alc_cdata.alc_rx_tag, 2855 sc->alc_cdata.alc_rx_sparemap, 2856 m, segs, 1, &nsegs, BUS_DMA_NOWAIT); 2857 if (error) { 2858 m_freem(m); 2859 return (ENOBUFS); 2860 } 2861 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2862 2863 if (rxd->rx_m != NULL) { 2864 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2865 BUS_DMASYNC_POSTREAD); 2866 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2867 } 2868 map = rxd->rx_dmamap; 2869 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2870 sc->alc_cdata.alc_rx_sparemap = map; 2871 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2872 BUS_DMASYNC_PREREAD); 2873 rxd->rx_m = m; 2874 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2875 return (0); 2876 } 2877 2878 static int 2879 alc_rxintr(struct alc_softc *sc, int count) 2880 { 2881 struct ifnet *ifp; 2882 struct rx_rdesc *rrd; 2883 uint32_t nsegs, status; 2884 int rr_cons, prog; 2885 2886 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2887 sc->alc_cdata.alc_rr_ring_map, 2888 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2889 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2890 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2891 rr_cons = sc->alc_cdata.alc_rr_cons; 2892 ifp = sc->alc_ifp; 2893 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2894 if (count-- <= 0) 2895 break; 2896 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2897 status = le32toh(rrd->status); 2898 if ((status & RRD_VALID) == 0) 2899 break; 2900 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2901 if (nsegs == 0) { 2902 /* This should not happen! */ 2903 device_printf(sc->alc_dev, 2904 "unexpected segment count -- resetting\n"); 2905 return (EIO); 2906 } 2907 alc_rxeof(sc, rrd); 2908 /* Clear Rx return status. */ 2909 rrd->status = 0; 2910 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2911 sc->alc_cdata.alc_rx_cons += nsegs; 2912 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2913 prog += nsegs; 2914 } 2915 2916 if (prog > 0) { 2917 /* Update the consumer index. */ 2918 sc->alc_cdata.alc_rr_cons = rr_cons; 2919 /* Sync Rx return descriptors. */ 2920 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2921 sc->alc_cdata.alc_rr_ring_map, 2922 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2923 /* 2924 * Sync updated Rx descriptors such that controller see 2925 * modified buffer addresses. 2926 */ 2927 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2928 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2929 /* 2930 * Let controller know availability of new Rx buffers. 2931 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2932 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2933 * only when Rx buffer pre-fetching is required. In 2934 * addition we already set ALC_RX_RD_FREE_THRESH to 2935 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2936 * it still seems that pre-fetching needs more 2937 * experimentation. 2938 */ 2939 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2940 sc->alc_cdata.alc_rx_cons); 2941 } 2942 2943 return (count > 0 ? 0 : EAGAIN); 2944 } 2945 2946 #ifndef __NO_STRICT_ALIGNMENT 2947 static struct mbuf * 2948 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2949 { 2950 struct mbuf *n; 2951 int i; 2952 uint16_t *src, *dst; 2953 2954 src = mtod(m, uint16_t *); 2955 dst = src - 3; 2956 2957 if (m->m_next == NULL) { 2958 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2959 *dst++ = *src++; 2960 m->m_data -= 6; 2961 return (m); 2962 } 2963 /* 2964 * Append a new mbuf to received mbuf chain and copy ethernet 2965 * header from the mbuf chain. This can save lots of CPU 2966 * cycles for jumbo frame. 2967 */ 2968 MGETHDR(n, MB_DONTWAIT, MT_DATA); 2969 if (n == NULL) { 2970 ifp->if_iqdrops++; 2971 m_freem(m); 2972 return (NULL); 2973 } 2974 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2975 m->m_data += ETHER_HDR_LEN; 2976 m->m_len -= ETHER_HDR_LEN; 2977 n->m_len = ETHER_HDR_LEN; 2978 M_MOVE_PKTHDR(n, m); 2979 n->m_next = m; 2980 return (n); 2981 } 2982 #endif 2983 2984 /* Receive a frame. */ 2985 static void 2986 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2987 { 2988 struct alc_rxdesc *rxd; 2989 struct ifnet *ifp; 2990 struct mbuf *mp, *m; 2991 uint32_t rdinfo, status, vtag; 2992 int count, nsegs, rx_cons; 2993 2994 ifp = sc->alc_ifp; 2995 status = le32toh(rrd->status); 2996 rdinfo = le32toh(rrd->rdinfo); 2997 rx_cons = RRD_RD_IDX(rdinfo); 2998 nsegs = RRD_RD_CNT(rdinfo); 2999 3000 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3001 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3002 /* 3003 * We want to pass the following frames to upper 3004 * layer regardless of error status of Rx return 3005 * ring. 3006 * 3007 * o IP/TCP/UDP checksum is bad. 3008 * o frame length and protocol specific length 3009 * does not match. 3010 * 3011 * Force network stack compute checksum for 3012 * errored frames. 3013 */ 3014 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3015 if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC | 3016 RRD_ERR_RUNT) != 0) 3017 return; 3018 } 3019 3020 for (count = 0; count < nsegs; count++, 3021 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3022 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3023 mp = rxd->rx_m; 3024 /* Add a new receive buffer to the ring. */ 3025 if (alc_newbuf(sc, rxd) != 0) { 3026 ifp->if_iqdrops++; 3027 /* Reuse Rx buffers. */ 3028 if (sc->alc_cdata.alc_rxhead != NULL) 3029 m_freem(sc->alc_cdata.alc_rxhead); 3030 break; 3031 } 3032 3033 /* 3034 * Assume we've received a full sized frame. 3035 * Actual size is fixed when we encounter the end of 3036 * multi-segmented frame. 3037 */ 3038 mp->m_len = sc->alc_buf_size; 3039 3040 /* Chain received mbufs. */ 3041 if (sc->alc_cdata.alc_rxhead == NULL) { 3042 sc->alc_cdata.alc_rxhead = mp; 3043 sc->alc_cdata.alc_rxtail = mp; 3044 } else { 3045 mp->m_flags &= ~M_PKTHDR; 3046 sc->alc_cdata.alc_rxprev_tail = 3047 sc->alc_cdata.alc_rxtail; 3048 sc->alc_cdata.alc_rxtail->m_next = mp; 3049 sc->alc_cdata.alc_rxtail = mp; 3050 } 3051 3052 if (count == nsegs - 1) { 3053 /* Last desc. for this frame. */ 3054 m = sc->alc_cdata.alc_rxhead; 3055 m->m_flags |= M_PKTHDR; 3056 /* 3057 * It seems that L1C/L2C controller has no way 3058 * to tell hardware to strip CRC bytes. 3059 */ 3060 m->m_pkthdr.len = 3061 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3062 if (nsegs > 1) { 3063 /* Set last mbuf size. */ 3064 mp->m_len = sc->alc_cdata.alc_rxlen - 3065 (nsegs - 1) * sc->alc_buf_size; 3066 /* Remove the CRC bytes in chained mbufs. */ 3067 if (mp->m_len <= ETHER_CRC_LEN) { 3068 sc->alc_cdata.alc_rxtail = 3069 sc->alc_cdata.alc_rxprev_tail; 3070 sc->alc_cdata.alc_rxtail->m_len -= 3071 (ETHER_CRC_LEN - mp->m_len); 3072 sc->alc_cdata.alc_rxtail->m_next = NULL; 3073 m_freem(mp); 3074 } else { 3075 mp->m_len -= ETHER_CRC_LEN; 3076 } 3077 } else 3078 m->m_len = m->m_pkthdr.len; 3079 m->m_pkthdr.rcvif = ifp; 3080 /* 3081 * Due to hardware bugs, Rx checksum offloading 3082 * was intentionally disabled. 3083 */ 3084 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3085 (status & RRD_VLAN_TAG) != 0) { 3086 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3087 m->m_pkthdr.ether_vlantag = ntohs(vtag); 3088 m->m_flags |= M_VLANTAG; 3089 } 3090 #ifndef __NO_STRICT_ALIGNMENT 3091 m = alc_fixup_rx(ifp, m); 3092 if (m != NULL) 3093 #endif 3094 { 3095 /* Pass it on. */ 3096 (*ifp->if_input)(ifp, m); 3097 } 3098 } 3099 } 3100 /* Reset mbuf chains. */ 3101 ALC_RXCHAIN_RESET(sc); 3102 } 3103 3104 static void 3105 alc_tick(void *arg) 3106 { 3107 struct alc_softc *sc; 3108 struct mii_data *mii; 3109 3110 sc = (struct alc_softc *)arg; 3111 3112 ALC_LOCK(sc); 3113 3114 mii = device_get_softc(sc->alc_miibus); 3115 mii_tick(mii); 3116 alc_stats_update(sc); 3117 /* 3118 * alc(4) does not rely on Tx completion interrupts to reclaim 3119 * transferred buffers. Instead Tx completion interrupts are 3120 * used to hint for scheduling Tx task. So it's necessary to 3121 * release transmitted buffers by kicking Tx completion 3122 * handler. This limits the maximum reclamation delay to a hz. 3123 */ 3124 alc_txeof(sc); 3125 alc_watchdog(sc); 3126 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3127 ALC_UNLOCK(sc); 3128 } 3129 3130 static void 3131 alc_reset(struct alc_softc *sc) 3132 { 3133 uint32_t reg; 3134 int i; 3135 3136 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 3137 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3138 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3139 3140 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3141 DELAY(10); 3142 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3143 break; 3144 } 3145 if (i == 0) 3146 device_printf(sc->alc_dev, "master reset timeout!\n"); 3147 3148 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3149 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 3150 break; 3151 DELAY(10); 3152 } 3153 3154 if (i == 0) 3155 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3156 } 3157 3158 static void 3159 alc_init(void *xsc) 3160 { 3161 struct alc_softc *sc; 3162 3163 sc = (struct alc_softc *)xsc; 3164 ALC_LOCK(sc); 3165 alc_init_locked(sc); 3166 ALC_UNLOCK(sc); 3167 } 3168 3169 static void 3170 alc_init_locked(struct alc_softc *sc) 3171 { 3172 struct ifnet *ifp; 3173 struct mii_data *mii; 3174 uint8_t eaddr[ETHER_ADDR_LEN]; 3175 bus_addr_t paddr; 3176 uint32_t reg, rxf_hi, rxf_lo; 3177 3178 ALC_LOCK_ASSERT(sc); 3179 3180 ifp = sc->alc_ifp; 3181 mii = device_get_softc(sc->alc_miibus); 3182 3183 if ((ifp->if_flags & IFF_RUNNING) != 0) 3184 return; 3185 /* 3186 * Cancel any pending I/O. 3187 */ 3188 alc_stop(sc); 3189 /* 3190 * Reset the chip to a known state. 3191 */ 3192 alc_reset(sc); 3193 3194 /* Initialize Rx descriptors. */ 3195 if (alc_init_rx_ring(sc) != 0) { 3196 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3197 alc_stop(sc); 3198 return; 3199 } 3200 alc_init_rr_ring(sc); 3201 alc_init_tx_ring(sc); 3202 alc_init_cmb(sc); 3203 alc_init_smb(sc); 3204 3205 /* Reprogram the station address. */ 3206 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3207 CSR_WRITE_4(sc, ALC_PAR0, 3208 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3209 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3210 /* 3211 * Clear WOL status and disable all WOL feature as WOL 3212 * would interfere Rx operation under normal environments. 3213 */ 3214 CSR_READ_4(sc, ALC_WOL_CFG); 3215 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3216 /* Set Tx descriptor base addresses. */ 3217 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3218 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3219 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3220 /* We don't use high priority ring. */ 3221 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3222 /* Set Tx descriptor counter. */ 3223 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3224 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3225 /* Set Rx descriptor base addresses. */ 3226 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3227 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3228 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3229 /* We use one Rx ring. */ 3230 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3231 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3232 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3233 /* Set Rx descriptor counter. */ 3234 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3235 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3236 3237 /* 3238 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3239 * if it do not fit the buffer size. Rx return descriptor holds 3240 * a counter that indicates how many fragments were made by the 3241 * hardware. The buffer size should be multiple of 8 bytes. 3242 * Since hardware has limit on the size of buffer size, always 3243 * use the maximum value. 3244 * For strict-alignment architectures make sure to reduce buffer 3245 * size by 8 bytes to make room for alignment fixup. 3246 */ 3247 #ifndef __NO_STRICT_ALIGNMENT 3248 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3249 #else 3250 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3251 #endif 3252 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3253 3254 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3255 /* Set Rx return descriptor base addresses. */ 3256 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3257 /* We use one Rx return ring. */ 3258 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3259 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3260 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3261 /* Set Rx return descriptor counter. */ 3262 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3263 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3264 paddr = sc->alc_rdata.alc_cmb_paddr; 3265 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3266 paddr = sc->alc_rdata.alc_smb_paddr; 3267 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3268 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3269 3270 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 3271 /* Reconfigure SRAM - Vendor magic. */ 3272 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 3273 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 3274 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 3275 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 3276 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 3277 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 3278 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 3279 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 3280 } 3281 3282 /* Tell hardware that we're ready to load DMA blocks. */ 3283 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 3284 3285 /* Configure interrupt moderation timer. */ 3286 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 3287 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 3288 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3289 /* 3290 * We don't want to automatic interrupt clear as task queue 3291 * for the interrupt should know interrupt status. 3292 */ 3293 reg = MASTER_SA_TIMER_ENB; 3294 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3295 reg |= MASTER_IM_RX_TIMER_ENB; 3296 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3297 reg |= MASTER_IM_TX_TIMER_ENB; 3298 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3299 /* 3300 * Disable interrupt re-trigger timer. We don't want automatic 3301 * re-triggering of un-ACKed interrupts. 3302 */ 3303 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3304 /* Configure CMB. */ 3305 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3306 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3307 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3308 } else { 3309 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3310 } 3311 /* 3312 * Hardware can be configured to issue SMB interrupt based 3313 * on programmed interval. Since there is a callout that is 3314 * invoked for every hz in driver we use that instead of 3315 * relying on periodic SMB interrupt. 3316 */ 3317 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3318 /* Clear MAC statistics. */ 3319 alc_stats_clear(sc); 3320 3321 /* 3322 * Always use maximum frame size that controller can support. 3323 * Otherwise received frames that has larger frame length 3324 * than alc(4) MTU would be silently dropped in hardware. This 3325 * would make path-MTU discovery hard as sender wouldn't get 3326 * any responses from receiver. alc(4) supports 3327 * multi-fragmented frames on Rx path so it has no issue on 3328 * assembling fragmented frames. Using maximum frame size also 3329 * removes the need to reinitialize hardware when interface 3330 * MTU configuration was changed. 3331 * 3332 * Be conservative in what you do, be liberal in what you 3333 * accept from others - RFC 793. 3334 */ 3335 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 3336 3337 /* Disable header split(?) */ 3338 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3339 3340 /* Configure IPG/IFG parameters. */ 3341 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3342 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3343 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3344 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3345 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3346 /* Set parameters for half-duplex media. */ 3347 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3348 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3349 HDPX_CFG_LCOL_MASK) | 3350 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3351 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3352 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3353 HDPX_CFG_ABEBT_MASK) | 3354 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3355 HDPX_CFG_JAMIPG_MASK)); 3356 /* 3357 * Set TSO/checksum offload threshold. For frames that is 3358 * larger than this threshold, hardware wouldn't do 3359 * TSO/checksum offloading. 3360 */ 3361 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3362 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3363 TSO_OFFLOAD_THRESH_MASK); 3364 /* Configure TxQ. */ 3365 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3366 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3367 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3368 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 3369 reg >>= 1; 3370 } 3371 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3372 TXQ_CFG_TD_BURST_MASK; 3373 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3374 3375 /* Configure Rx free descriptor pre-fetching. */ 3376 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3377 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3378 RX_RD_FREE_THRESH_HI_MASK) | 3379 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3380 RX_RD_FREE_THRESH_LO_MASK)); 3381 3382 /* 3383 * Configure flow control parameters. 3384 * XON : 80% of Rx FIFO 3385 * XOFF : 30% of Rx FIFO 3386 */ 3387 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 3388 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 3389 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3390 rxf_hi = (reg * 8) / 10; 3391 rxf_lo = (reg * 3) / 10; 3392 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3393 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3394 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3395 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3396 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3397 } 3398 3399 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3400 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) { 3401 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3402 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3403 SERDES_PHY_CLK_SLOWDOWN); 3404 } 3405 3406 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3407 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3408 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3409 3410 /* Configure RxQ. */ 3411 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3412 RXQ_CFG_RD_BURST_MASK; 3413 reg |= RXQ_CFG_RSS_MODE_DIS; 3414 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3415 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3416 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3417 3418 /* Configure DMA parameters. */ 3419 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3420 reg |= sc->alc_rcb; 3421 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3422 reg |= DMA_CFG_CMB_ENB; 3423 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3424 reg |= DMA_CFG_SMB_ENB; 3425 else 3426 reg |= DMA_CFG_SMB_DIS; 3427 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3428 DMA_CFG_RD_BURST_SHIFT; 3429 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3430 DMA_CFG_WR_BURST_SHIFT; 3431 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3432 DMA_CFG_RD_DELAY_CNT_MASK; 3433 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3434 DMA_CFG_WR_DELAY_CNT_MASK; 3435 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3436 3437 /* 3438 * Configure Tx/Rx MACs. 3439 * - Auto-padding for short frames. 3440 * - Enable CRC generation. 3441 * Actual reconfiguration of MAC for resolved speed/duplex 3442 * is followed after detection of link establishment. 3443 * AR813x/AR815x always does checksum computation regardless 3444 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3445 * have bug in protocol field in Rx return structure so 3446 * these controllers can't handle fragmented frames. Disable 3447 * Rx checksum offloading until there is a newer controller 3448 * that has sane implementation. 3449 */ 3450 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3451 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3452 MAC_CFG_PREAMBLE_MASK); 3453 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3454 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3455 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 3456 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3457 } 3458 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3459 reg |= MAC_CFG_SPEED_10_100; 3460 else 3461 reg |= MAC_CFG_SPEED_1000; 3462 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3463 3464 /* Set up the receive filter. */ 3465 alc_rxfilter(sc); 3466 alc_rxvlan(sc); 3467 3468 /* Acknowledge all pending interrupts and clear it. */ 3469 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3470 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3471 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3472 3473 sc->alc_flags &= ~ALC_FLAG_LINK; 3474 /* Switch to the current media. */ 3475 mii_mediachg(mii); 3476 3477 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3478 3479 ifp->if_flags |= IFF_RUNNING; 3480 ifp->if_flags &= ~IFF_OACTIVE; 3481 } 3482 3483 static void 3484 alc_stop(struct alc_softc *sc) 3485 { 3486 struct ifnet *ifp; 3487 struct alc_txdesc *txd; 3488 struct alc_rxdesc *rxd; 3489 uint32_t reg; 3490 int i; 3491 3492 ALC_LOCK_ASSERT(sc); 3493 /* 3494 * Mark the interface down and cancel the watchdog timer. 3495 */ 3496 ifp = sc->alc_ifp; 3497 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3498 sc->alc_flags &= ~ALC_FLAG_LINK; 3499 callout_stop(&sc->alc_tick_ch); 3500 sc->alc_watchdog_timer = 0; 3501 alc_stats_update(sc); 3502 /* Disable interrupts. */ 3503 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3504 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3505 alc_stop_queue(sc); 3506 /* Disable DMA. */ 3507 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3508 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3509 reg |= DMA_CFG_SMB_DIS; 3510 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3511 DELAY(1000); 3512 /* Stop Rx/Tx MACs. */ 3513 alc_stop_mac(sc); 3514 /* Disable interrupts which might be touched in taskq handler. */ 3515 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3516 3517 /* Reclaim Rx buffers that have been processed. */ 3518 if (sc->alc_cdata.alc_rxhead != NULL) 3519 m_freem(sc->alc_cdata.alc_rxhead); 3520 ALC_RXCHAIN_RESET(sc); 3521 /* 3522 * Free Tx/Rx mbufs still in the queues. 3523 */ 3524 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3525 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3526 if (rxd->rx_m != NULL) { 3527 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3528 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3529 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3530 rxd->rx_dmamap); 3531 m_freem(rxd->rx_m); 3532 rxd->rx_m = NULL; 3533 } 3534 } 3535 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3536 txd = &sc->alc_cdata.alc_txdesc[i]; 3537 if (txd->tx_m != NULL) { 3538 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3539 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3540 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3541 txd->tx_dmamap); 3542 m_freem(txd->tx_m); 3543 txd->tx_m = NULL; 3544 } 3545 } 3546 } 3547 3548 static void 3549 alc_stop_mac(struct alc_softc *sc) 3550 { 3551 uint32_t reg; 3552 int i; 3553 3554 ALC_LOCK_ASSERT(sc); 3555 3556 /* Disable Rx/Tx MAC. */ 3557 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3558 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3559 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 3560 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3561 } 3562 for (i = ALC_TIMEOUT; i > 0; i--) { 3563 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3564 if (reg == 0) 3565 break; 3566 DELAY(10); 3567 } 3568 if (i == 0) 3569 device_printf(sc->alc_dev, 3570 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3571 } 3572 3573 static void 3574 alc_start_queue(struct alc_softc *sc) 3575 { 3576 uint32_t qcfg[] = { 3577 0, 3578 RXQ_CFG_QUEUE0_ENB, 3579 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3580 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3581 RXQ_CFG_ENB 3582 }; 3583 uint32_t cfg; 3584 3585 ALC_LOCK_ASSERT(sc); 3586 3587 /* Enable RxQ. */ 3588 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3589 cfg &= ~RXQ_CFG_ENB; 3590 cfg |= qcfg[1]; 3591 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3592 /* Enable TxQ. */ 3593 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3594 cfg |= TXQ_CFG_ENB; 3595 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3596 } 3597 3598 static void 3599 alc_stop_queue(struct alc_softc *sc) 3600 { 3601 uint32_t reg; 3602 int i; 3603 3604 ALC_LOCK_ASSERT(sc); 3605 3606 /* Disable RxQ. */ 3607 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3608 if ((reg & RXQ_CFG_ENB) != 0) { 3609 reg &= ~RXQ_CFG_ENB; 3610 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3611 } 3612 /* Disable TxQ. */ 3613 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3614 if ((reg & TXQ_CFG_ENB) == 0) { 3615 reg &= ~TXQ_CFG_ENB; 3616 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3617 } 3618 for (i = ALC_TIMEOUT; i > 0; i--) { 3619 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3620 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3621 break; 3622 DELAY(10); 3623 } 3624 if (i == 0) 3625 device_printf(sc->alc_dev, 3626 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3627 } 3628 3629 static void 3630 alc_init_tx_ring(struct alc_softc *sc) 3631 { 3632 struct alc_ring_data *rd; 3633 struct alc_txdesc *txd; 3634 int i; 3635 3636 ALC_LOCK_ASSERT(sc); 3637 3638 sc->alc_cdata.alc_tx_prod = 0; 3639 sc->alc_cdata.alc_tx_cons = 0; 3640 sc->alc_cdata.alc_tx_cnt = 0; 3641 3642 rd = &sc->alc_rdata; 3643 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3644 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3645 txd = &sc->alc_cdata.alc_txdesc[i]; 3646 txd->tx_m = NULL; 3647 } 3648 3649 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3650 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3651 } 3652 3653 static int 3654 alc_init_rx_ring(struct alc_softc *sc) 3655 { 3656 struct alc_ring_data *rd; 3657 struct alc_rxdesc *rxd; 3658 int i; 3659 3660 ALC_LOCK_ASSERT(sc); 3661 3662 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3663 sc->alc_morework = 0; 3664 rd = &sc->alc_rdata; 3665 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3666 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3667 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3668 rxd->rx_m = NULL; 3669 rxd->rx_desc = &rd->alc_rx_ring[i]; 3670 if (alc_newbuf(sc, rxd) != 0) 3671 return (ENOBUFS); 3672 } 3673 3674 /* 3675 * Since controller does not update Rx descriptors, driver 3676 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3677 * is enough to ensure coherence. 3678 */ 3679 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3680 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3681 /* Let controller know availability of new Rx buffers. */ 3682 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3683 3684 return (0); 3685 } 3686 3687 static void 3688 alc_init_rr_ring(struct alc_softc *sc) 3689 { 3690 struct alc_ring_data *rd; 3691 3692 ALC_LOCK_ASSERT(sc); 3693 3694 sc->alc_cdata.alc_rr_cons = 0; 3695 ALC_RXCHAIN_RESET(sc); 3696 3697 rd = &sc->alc_rdata; 3698 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3699 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3700 sc->alc_cdata.alc_rr_ring_map, 3701 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3702 } 3703 3704 static void 3705 alc_init_cmb(struct alc_softc *sc) 3706 { 3707 struct alc_ring_data *rd; 3708 3709 ALC_LOCK_ASSERT(sc); 3710 3711 rd = &sc->alc_rdata; 3712 bzero(rd->alc_cmb, ALC_CMB_SZ); 3713 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3714 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3715 } 3716 3717 static void 3718 alc_init_smb(struct alc_softc *sc) 3719 { 3720 struct alc_ring_data *rd; 3721 3722 ALC_LOCK_ASSERT(sc); 3723 3724 rd = &sc->alc_rdata; 3725 bzero(rd->alc_smb, ALC_SMB_SZ); 3726 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3727 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3728 } 3729 3730 static void 3731 alc_rxvlan(struct alc_softc *sc) 3732 { 3733 struct ifnet *ifp; 3734 uint32_t reg; 3735 3736 ALC_LOCK_ASSERT(sc); 3737 3738 ifp = sc->alc_ifp; 3739 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3740 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3741 reg |= MAC_CFG_VLAN_TAG_STRIP; 3742 else 3743 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3744 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3745 } 3746 3747 static void 3748 alc_rxfilter(struct alc_softc *sc) 3749 { 3750 struct ifnet *ifp; 3751 struct ifmultiaddr *ifma; 3752 uint32_t crc; 3753 uint32_t mchash[2]; 3754 uint32_t rxcfg; 3755 3756 ALC_LOCK_ASSERT(sc); 3757 3758 ifp = sc->alc_ifp; 3759 3760 bzero(mchash, sizeof(mchash)); 3761 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3762 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3763 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3764 rxcfg |= MAC_CFG_BCAST; 3765 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3766 if ((ifp->if_flags & IFF_PROMISC) != 0) 3767 rxcfg |= MAC_CFG_PROMISC; 3768 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3769 rxcfg |= MAC_CFG_ALLMULTI; 3770 mchash[0] = 0xFFFFFFFF; 3771 mchash[1] = 0xFFFFFFFF; 3772 goto chipit; 3773 } 3774 3775 #if 0 3776 /* XXX */ 3777 if_maddr_rlock(ifp); 3778 #endif 3779 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3780 if (ifma->ifma_addr->sa_family != AF_LINK) 3781 continue; 3782 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3783 ifma->ifma_addr), ETHER_ADDR_LEN); 3784 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3785 } 3786 #if 0 3787 /* XXX */ 3788 if_maddr_runlock(ifp); 3789 #endif 3790 3791 chipit: 3792 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3793 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3794 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3795 } 3796 3797 static int 3798 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3799 { 3800 return (sysctl_int_range(oidp, arg1, arg2, req, 3801 ALC_PROC_MIN, ALC_PROC_MAX)); 3802 } 3803 3804 static int 3805 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3806 { 3807 3808 return (sysctl_int_range(oidp, arg1, arg2, req, 3809 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3810 } 3811