1*57e252bfSMichael Neumann /* 2*57e252bfSMichael Neumann * Copyright 2012 Advanced Micro Devices, Inc. 3*57e252bfSMichael Neumann * 4*57e252bfSMichael Neumann * Permission is hereby granted, free of charge, to any person obtaining a 5*57e252bfSMichael Neumann * copy of this software and associated documentation files (the "Software"), 6*57e252bfSMichael Neumann * to deal in the Software without restriction, including without limitation 7*57e252bfSMichael Neumann * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*57e252bfSMichael Neumann * and/or sell copies of the Software, and to permit persons to whom the 9*57e252bfSMichael Neumann * Software is furnished to do so, subject to the following conditions: 10*57e252bfSMichael Neumann * 11*57e252bfSMichael Neumann * The above copyright notice and this permission notice shall be included in 12*57e252bfSMichael Neumann * all copies or substantial portions of the Software. 13*57e252bfSMichael Neumann * 14*57e252bfSMichael Neumann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*57e252bfSMichael Neumann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*57e252bfSMichael Neumann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*57e252bfSMichael Neumann * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*57e252bfSMichael Neumann * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*57e252bfSMichael Neumann * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*57e252bfSMichael Neumann * OTHER DEALINGS IN THE SOFTWARE. 21*57e252bfSMichael Neumann * 22*57e252bfSMichael Neumann * Authors: Alex Deucher 23*57e252bfSMichael Neumann */ 24*57e252bfSMichael Neumann #ifndef _SUMOD_H_ 25*57e252bfSMichael Neumann #define _SUMOD_H_ 26*57e252bfSMichael Neumann 27*57e252bfSMichael Neumann /* pm registers */ 28*57e252bfSMichael Neumann 29*57e252bfSMichael Neumann /* rcu */ 30*57e252bfSMichael Neumann #define RCU_FW_VERSION 0x30c 31*57e252bfSMichael Neumann 32*57e252bfSMichael Neumann #define RCU_PWR_GATING_SEQ0 0x408 33*57e252bfSMichael Neumann #define RCU_PWR_GATING_SEQ1 0x40c 34*57e252bfSMichael Neumann #define RCU_PWR_GATING_CNTL 0x410 35*57e252bfSMichael Neumann # define PWR_GATING_EN (1 << 0) 36*57e252bfSMichael Neumann # define RSVD_MASK (0x3 << 1) 37*57e252bfSMichael Neumann # define PCV(x) ((x) << 3) 38*57e252bfSMichael Neumann # define PCV_MASK (0x1f << 3) 39*57e252bfSMichael Neumann # define PCV_SHIFT 3 40*57e252bfSMichael Neumann # define PCP(x) ((x) << 8) 41*57e252bfSMichael Neumann # define PCP_MASK (0xf << 8) 42*57e252bfSMichael Neumann # define PCP_SHIFT 8 43*57e252bfSMichael Neumann # define RPW(x) ((x) << 16) 44*57e252bfSMichael Neumann # define RPW_MASK (0xf << 16) 45*57e252bfSMichael Neumann # define RPW_SHIFT 16 46*57e252bfSMichael Neumann # define ID(x) ((x) << 24) 47*57e252bfSMichael Neumann # define ID_MASK (0xf << 24) 48*57e252bfSMichael Neumann # define ID_SHIFT 24 49*57e252bfSMichael Neumann # define PGS(x) ((x) << 28) 50*57e252bfSMichael Neumann # define PGS_MASK (0xf << 28) 51*57e252bfSMichael Neumann # define PGS_SHIFT 28 52*57e252bfSMichael Neumann 53*57e252bfSMichael Neumann #define RCU_ALTVDDNB_NOTIFY 0x430 54*57e252bfSMichael Neumann #define RCU_LCLK_SCALING_CNTL 0x434 55*57e252bfSMichael Neumann # define LCLK_SCALING_EN (1 << 0) 56*57e252bfSMichael Neumann # define LCLK_SCALING_TYPE (1 << 1) 57*57e252bfSMichael Neumann # define LCLK_SCALING_TIMER_PRESCALER(x) ((x) << 4) 58*57e252bfSMichael Neumann # define LCLK_SCALING_TIMER_PRESCALER_MASK (0xf << 4) 59*57e252bfSMichael Neumann # define LCLK_SCALING_TIMER_PRESCALER_SHIFT 4 60*57e252bfSMichael Neumann # define LCLK_SCALING_TIMER_PERIOD(x) ((x) << 16) 61*57e252bfSMichael Neumann # define LCLK_SCALING_TIMER_PERIOD_MASK (0xf << 16) 62*57e252bfSMichael Neumann # define LCLK_SCALING_TIMER_PERIOD_SHIFT 16 63*57e252bfSMichael Neumann 64*57e252bfSMichael Neumann #define RCU_PWR_GATING_CNTL_2 0x4a0 65*57e252bfSMichael Neumann # define MPPU(x) ((x) << 0) 66*57e252bfSMichael Neumann # define MPPU_MASK (0xffff << 0) 67*57e252bfSMichael Neumann # define MPPU_SHIFT 0 68*57e252bfSMichael Neumann # define MPPD(x) ((x) << 16) 69*57e252bfSMichael Neumann # define MPPD_MASK (0xffff << 16) 70*57e252bfSMichael Neumann # define MPPD_SHIFT 16 71*57e252bfSMichael Neumann #define RCU_PWR_GATING_CNTL_3 0x4a4 72*57e252bfSMichael Neumann # define DPPU(x) ((x) << 0) 73*57e252bfSMichael Neumann # define DPPU_MASK (0xffff << 0) 74*57e252bfSMichael Neumann # define DPPU_SHIFT 0 75*57e252bfSMichael Neumann # define DPPD(x) ((x) << 16) 76*57e252bfSMichael Neumann # define DPPD_MASK (0xffff << 16) 77*57e252bfSMichael Neumann # define DPPD_SHIFT 16 78*57e252bfSMichael Neumann #define RCU_PWR_GATING_CNTL_4 0x4a8 79*57e252bfSMichael Neumann # define RT(x) ((x) << 0) 80*57e252bfSMichael Neumann # define RT_MASK (0xffff << 0) 81*57e252bfSMichael Neumann # define RT_SHIFT 0 82*57e252bfSMichael Neumann # define IT(x) ((x) << 16) 83*57e252bfSMichael Neumann # define IT_MASK (0xffff << 16) 84*57e252bfSMichael Neumann # define IT_SHIFT 16 85*57e252bfSMichael Neumann 86*57e252bfSMichael Neumann /* yes these two have the same address */ 87*57e252bfSMichael Neumann #define RCU_PWR_GATING_CNTL_5 0x504 88*57e252bfSMichael Neumann #define RCU_GPU_BOOST_DISABLE 0x508 89*57e252bfSMichael Neumann 90*57e252bfSMichael Neumann #define MCU_M3ARB_INDEX 0x504 91*57e252bfSMichael Neumann #define MCU_M3ARB_PARAMS 0x508 92*57e252bfSMichael Neumann 93*57e252bfSMichael Neumann #define RCU_GNB_PWR_REP_TIMER_CNTL 0x50C 94*57e252bfSMichael Neumann 95*57e252bfSMichael Neumann #define RCU_SclkDpmTdpLimit01 0x514 96*57e252bfSMichael Neumann #define RCU_SclkDpmTdpLimit23 0x518 97*57e252bfSMichael Neumann #define RCU_SclkDpmTdpLimit47 0x51C 98*57e252bfSMichael Neumann #define RCU_SclkDpmTdpLimitPG 0x520 99*57e252bfSMichael Neumann 100*57e252bfSMichael Neumann #define GNB_TDP_LIMIT 0x540 101*57e252bfSMichael Neumann #define RCU_BOOST_MARGIN 0x544 102*57e252bfSMichael Neumann #define RCU_THROTTLE_MARGIN 0x548 103*57e252bfSMichael Neumann 104*57e252bfSMichael Neumann #define SMU_PCIE_PG_ARGS 0x58C 105*57e252bfSMichael Neumann #define SMU_PCIE_PG_ARGS_2 0x598 106*57e252bfSMichael Neumann #define SMU_PCIE_PG_ARGS_3 0x59C 107*57e252bfSMichael Neumann 108*57e252bfSMichael Neumann /* mmio */ 109*57e252bfSMichael Neumann #define RCU_STATUS 0x11c 110*57e252bfSMichael Neumann # define GMC_PWR_GATER_BUSY (1 << 8) 111*57e252bfSMichael Neumann # define GFX_PWR_GATER_BUSY (1 << 9) 112*57e252bfSMichael Neumann # define UVD_PWR_GATER_BUSY (1 << 10) 113*57e252bfSMichael Neumann # define PCIE_PWR_GATER_BUSY (1 << 11) 114*57e252bfSMichael Neumann # define GMC_PWR_GATER_STATE (1 << 12) 115*57e252bfSMichael Neumann # define GFX_PWR_GATER_STATE (1 << 13) 116*57e252bfSMichael Neumann # define UVD_PWR_GATER_STATE (1 << 14) 117*57e252bfSMichael Neumann # define PCIE_PWR_GATER_STATE (1 << 15) 118*57e252bfSMichael Neumann # define GFX1_PWR_GATER_BUSY (1 << 16) 119*57e252bfSMichael Neumann # define GFX2_PWR_GATER_BUSY (1 << 17) 120*57e252bfSMichael Neumann # define GFX1_PWR_GATER_STATE (1 << 18) 121*57e252bfSMichael Neumann # define GFX2_PWR_GATER_STATE (1 << 19) 122*57e252bfSMichael Neumann 123*57e252bfSMichael Neumann #define GFX_INT_REQ 0x120 124*57e252bfSMichael Neumann # define INT_REQ (1 << 0) 125*57e252bfSMichael Neumann # define SERV_INDEX(x) ((x) << 1) 126*57e252bfSMichael Neumann # define SERV_INDEX_MASK (0xff << 1) 127*57e252bfSMichael Neumann # define SERV_INDEX_SHIFT 1 128*57e252bfSMichael Neumann #define GFX_INT_STATUS 0x124 129*57e252bfSMichael Neumann # define INT_ACK (1 << 0) 130*57e252bfSMichael Neumann # define INT_DONE (1 << 1) 131*57e252bfSMichael Neumann 132*57e252bfSMichael Neumann #define CG_SCLK_CNTL 0x600 133*57e252bfSMichael Neumann # define SCLK_DIVIDER(x) ((x) << 0) 134*57e252bfSMichael Neumann # define SCLK_DIVIDER_MASK (0x7f << 0) 135*57e252bfSMichael Neumann # define SCLK_DIVIDER_SHIFT 0 136*57e252bfSMichael Neumann #define CG_SCLK_STATUS 0x604 137*57e252bfSMichael Neumann # define SCLK_OVERCLK_DETECT (1 << 2) 138*57e252bfSMichael Neumann 139*57e252bfSMichael Neumann #define CG_DCLK_CNTL 0x610 140*57e252bfSMichael Neumann # define DCLK_DIVIDER_MASK 0x7f 141*57e252bfSMichael Neumann # define DCLK_DIR_CNTL_EN (1 << 8) 142*57e252bfSMichael Neumann #define CG_DCLK_STATUS 0x614 143*57e252bfSMichael Neumann # define DCLK_STATUS (1 << 0) 144*57e252bfSMichael Neumann #define CG_VCLK_CNTL 0x618 145*57e252bfSMichael Neumann # define VCLK_DIVIDER_MASK 0x7f 146*57e252bfSMichael Neumann # define VCLK_DIR_CNTL_EN (1 << 8) 147*57e252bfSMichael Neumann #define CG_VCLK_STATUS 0x61c 148*57e252bfSMichael Neumann 149*57e252bfSMichael Neumann #define GENERAL_PWRMGT 0x63c 150*57e252bfSMichael Neumann # define STATIC_PM_EN (1 << 1) 151*57e252bfSMichael Neumann 152*57e252bfSMichael Neumann #define SCLK_PWRMGT_CNTL 0x644 153*57e252bfSMichael Neumann # define SCLK_PWRMGT_OFF (1 << 0) 154*57e252bfSMichael Neumann # define SCLK_LOW_D1 (1 << 1) 155*57e252bfSMichael Neumann # define FIR_RESET (1 << 4) 156*57e252bfSMichael Neumann # define FIR_FORCE_TREND_SEL (1 << 5) 157*57e252bfSMichael Neumann # define FIR_TREND_MODE (1 << 6) 158*57e252bfSMichael Neumann # define DYN_GFX_CLK_OFF_EN (1 << 7) 159*57e252bfSMichael Neumann # define GFX_CLK_FORCE_ON (1 << 8) 160*57e252bfSMichael Neumann # define GFX_CLK_REQUEST_OFF (1 << 9) 161*57e252bfSMichael Neumann # define GFX_CLK_FORCE_OFF (1 << 10) 162*57e252bfSMichael Neumann # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 163*57e252bfSMichael Neumann # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 164*57e252bfSMichael Neumann # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 165*57e252bfSMichael Neumann # define GFX_VOLTAGE_CHANGE_EN (1 << 16) 166*57e252bfSMichael Neumann # define GFX_VOLTAGE_CHANGE_MODE (1 << 17) 167*57e252bfSMichael Neumann 168*57e252bfSMichael Neumann #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 169*57e252bfSMichael Neumann # define TARG_SCLK_INDEX(x) ((x) << 6) 170*57e252bfSMichael Neumann # define TARG_SCLK_INDEX_MASK (0x7 << 6) 171*57e252bfSMichael Neumann # define TARG_SCLK_INDEX_SHIFT 6 172*57e252bfSMichael Neumann # define CURR_SCLK_INDEX(x) ((x) << 9) 173*57e252bfSMichael Neumann # define CURR_SCLK_INDEX_MASK (0x7 << 9) 174*57e252bfSMichael Neumann # define CURR_SCLK_INDEX_SHIFT 9 175*57e252bfSMichael Neumann # define TARG_INDEX(x) ((x) << 12) 176*57e252bfSMichael Neumann # define TARG_INDEX_MASK (0x7 << 12) 177*57e252bfSMichael Neumann # define TARG_INDEX_SHIFT 12 178*57e252bfSMichael Neumann # define CURR_INDEX(x) ((x) << 15) 179*57e252bfSMichael Neumann # define CURR_INDEX_MASK (0x7 << 15) 180*57e252bfSMichael Neumann # define CURR_INDEX_SHIFT 15 181*57e252bfSMichael Neumann 182*57e252bfSMichael Neumann #define CG_SCLK_DPM_CTRL 0x684 183*57e252bfSMichael Neumann # define SCLK_FSTATE_0_DIV(x) ((x) << 0) 184*57e252bfSMichael Neumann # define SCLK_FSTATE_0_DIV_MASK (0x7f << 0) 185*57e252bfSMichael Neumann # define SCLK_FSTATE_0_DIV_SHIFT 0 186*57e252bfSMichael Neumann # define SCLK_FSTATE_0_VLD (1 << 7) 187*57e252bfSMichael Neumann # define SCLK_FSTATE_1_DIV(x) ((x) << 8) 188*57e252bfSMichael Neumann # define SCLK_FSTATE_1_DIV_MASK (0x7f << 8) 189*57e252bfSMichael Neumann # define SCLK_FSTATE_1_DIV_SHIFT 8 190*57e252bfSMichael Neumann # define SCLK_FSTATE_1_VLD (1 << 15) 191*57e252bfSMichael Neumann # define SCLK_FSTATE_2_DIV(x) ((x) << 16) 192*57e252bfSMichael Neumann # define SCLK_FSTATE_2_DIV_MASK (0x7f << 16) 193*57e252bfSMichael Neumann # define SCLK_FSTATE_2_DIV_SHIFT 16 194*57e252bfSMichael Neumann # define SCLK_FSTATE_2_VLD (1 << 23) 195*57e252bfSMichael Neumann # define SCLK_FSTATE_3_DIV(x) ((x) << 24) 196*57e252bfSMichael Neumann # define SCLK_FSTATE_3_DIV_MASK (0x7f << 24) 197*57e252bfSMichael Neumann # define SCLK_FSTATE_3_DIV_SHIFT 24 198*57e252bfSMichael Neumann # define SCLK_FSTATE_3_VLD (1 << 31) 199*57e252bfSMichael Neumann #define CG_SCLK_DPM_CTRL_2 0x688 200*57e252bfSMichael Neumann #define CG_GCOOR 0x68c 201*57e252bfSMichael Neumann # define PHC(x) ((x) << 0) 202*57e252bfSMichael Neumann # define PHC_MASK (0x1f << 0) 203*57e252bfSMichael Neumann # define PHC_SHIFT 0 204*57e252bfSMichael Neumann # define SDC(x) ((x) << 9) 205*57e252bfSMichael Neumann # define SDC_MASK (0x3ff << 9) 206*57e252bfSMichael Neumann # define SDC_SHIFT 9 207*57e252bfSMichael Neumann # define SU(x) ((x) << 23) 208*57e252bfSMichael Neumann # define SU_MASK (0xf << 23) 209*57e252bfSMichael Neumann # define SU_SHIFT 23 210*57e252bfSMichael Neumann # define DIV_ID(x) ((x) << 28) 211*57e252bfSMichael Neumann # define DIV_ID_MASK (0x7 << 28) 212*57e252bfSMichael Neumann # define DIV_ID_SHIFT 28 213*57e252bfSMichael Neumann 214*57e252bfSMichael Neumann #define CG_FTV 0x690 215*57e252bfSMichael Neumann #define CG_FFCT_0 0x694 216*57e252bfSMichael Neumann # define UTC_0(x) ((x) << 0) 217*57e252bfSMichael Neumann # define UTC_0_MASK (0x3ff << 0) 218*57e252bfSMichael Neumann # define UTC_0_SHIFT 0 219*57e252bfSMichael Neumann # define DTC_0(x) ((x) << 10) 220*57e252bfSMichael Neumann # define DTC_0_MASK (0x3ff << 10) 221*57e252bfSMichael Neumann # define DTC_0_SHIFT 10 222*57e252bfSMichael Neumann 223*57e252bfSMichael Neumann #define CG_GIT 0x6d8 224*57e252bfSMichael Neumann # define CG_GICST(x) ((x) << 0) 225*57e252bfSMichael Neumann # define CG_GICST_MASK (0xffff << 0) 226*57e252bfSMichael Neumann # define CG_GICST_SHIFT 0 227*57e252bfSMichael Neumann # define CG_GIPOT(x) ((x) << 16) 228*57e252bfSMichael Neumann # define CG_GIPOT_MASK (0xffff << 16) 229*57e252bfSMichael Neumann # define CG_GIPOT_SHIFT 16 230*57e252bfSMichael Neumann 231*57e252bfSMichael Neumann #define CG_SCLK_DPM_CTRL_3 0x6e0 232*57e252bfSMichael Neumann # define FORCE_SCLK_STATE(x) ((x) << 0) 233*57e252bfSMichael Neumann # define FORCE_SCLK_STATE_MASK (0x7 << 0) 234*57e252bfSMichael Neumann # define FORCE_SCLK_STATE_SHIFT 0 235*57e252bfSMichael Neumann # define FORCE_SCLK_STATE_EN (1 << 3) 236*57e252bfSMichael Neumann # define GNB_TT(x) ((x) << 8) 237*57e252bfSMichael Neumann # define GNB_TT_MASK (0xff << 8) 238*57e252bfSMichael Neumann # define GNB_TT_SHIFT 8 239*57e252bfSMichael Neumann # define GNB_THERMTHRO_MASK (1 << 16) 240*57e252bfSMichael Neumann # define CNB_THERMTHRO_MASK_SCLK (1 << 17) 241*57e252bfSMichael Neumann # define DPM_SCLK_ENABLE (1 << 18) 242*57e252bfSMichael Neumann # define GNB_SLOW_FSTATE_0_MASK (1 << 23) 243*57e252bfSMichael Neumann # define GNB_SLOW_FSTATE_0_SHIFT 23 244*57e252bfSMichael Neumann # define FORCE_NB_PSTATE_1 (1 << 31) 245*57e252bfSMichael Neumann 246*57e252bfSMichael Neumann #define CG_SSP 0x6e8 247*57e252bfSMichael Neumann # define SST(x) ((x) << 0) 248*57e252bfSMichael Neumann # define SST_MASK (0xffff << 0) 249*57e252bfSMichael Neumann # define SST_SHIFT 0 250*57e252bfSMichael Neumann # define SSTU(x) ((x) << 16) 251*57e252bfSMichael Neumann # define SSTU_MASK (0xffff << 16) 252*57e252bfSMichael Neumann # define SSTU_SHIFT 16 253*57e252bfSMichael Neumann 254*57e252bfSMichael Neumann #define CG_ACPI_CNTL 0x70c 255*57e252bfSMichael Neumann # define SCLK_ACPI_DIV(x) ((x) << 0) 256*57e252bfSMichael Neumann # define SCLK_ACPI_DIV_MASK (0x7f << 0) 257*57e252bfSMichael Neumann # define SCLK_ACPI_DIV_SHIFT 0 258*57e252bfSMichael Neumann 259*57e252bfSMichael Neumann #define CG_SCLK_DPM_CTRL_4 0x71c 260*57e252bfSMichael Neumann # define DC_HDC(x) ((x) << 14) 261*57e252bfSMichael Neumann # define DC_HDC_MASK (0x3fff << 14) 262*57e252bfSMichael Neumann # define DC_HDC_SHIFT 14 263*57e252bfSMichael Neumann # define DC_HU(x) ((x) << 28) 264*57e252bfSMichael Neumann # define DC_HU_MASK (0xf << 28) 265*57e252bfSMichael Neumann # define DC_HU_SHIFT 28 266*57e252bfSMichael Neumann #define CG_SCLK_DPM_CTRL_5 0x720 267*57e252bfSMichael Neumann # define SCLK_FSTATE_BOOTUP(x) ((x) << 0) 268*57e252bfSMichael Neumann # define SCLK_FSTATE_BOOTUP_MASK (0x7 << 0) 269*57e252bfSMichael Neumann # define SCLK_FSTATE_BOOTUP_SHIFT 0 270*57e252bfSMichael Neumann # define TT_TP(x) ((x) << 3) 271*57e252bfSMichael Neumann # define TT_TP_MASK (0xffff << 3) 272*57e252bfSMichael Neumann # define TT_TP_SHIFT 3 273*57e252bfSMichael Neumann # define TT_TU(x) ((x) << 19) 274*57e252bfSMichael Neumann # define TT_TU_MASK (0xff << 19) 275*57e252bfSMichael Neumann # define TT_TU_SHIFT 19 276*57e252bfSMichael Neumann #define CG_SCLK_DPM_CTRL_6 0x724 277*57e252bfSMichael Neumann #define CG_AT_0 0x728 278*57e252bfSMichael Neumann # define CG_R(x) ((x) << 0) 279*57e252bfSMichael Neumann # define CG_R_MASK (0xffff << 0) 280*57e252bfSMichael Neumann # define CG_R_SHIFT 0 281*57e252bfSMichael Neumann # define CG_L(x) ((x) << 16) 282*57e252bfSMichael Neumann # define CG_L_MASK (0xffff << 16) 283*57e252bfSMichael Neumann # define CG_L_SHIFT 16 284*57e252bfSMichael Neumann #define CG_AT_1 0x72c 285*57e252bfSMichael Neumann #define CG_AT_2 0x730 286*57e252bfSMichael Neumann #define CG_THERMAL_INT 0x734 287*57e252bfSMichael Neumann #define DIG_THERM_INTH(x) ((x) << 8) 288*57e252bfSMichael Neumann #define DIG_THERM_INTH_MASK 0x0000FF00 289*57e252bfSMichael Neumann #define DIG_THERM_INTH_SHIFT 8 290*57e252bfSMichael Neumann #define DIG_THERM_INTL(x) ((x) << 16) 291*57e252bfSMichael Neumann #define DIG_THERM_INTL_MASK 0x00FF0000 292*57e252bfSMichael Neumann #define DIG_THERM_INTL_SHIFT 16 293*57e252bfSMichael Neumann #define THERM_INT_MASK_HIGH (1 << 24) 294*57e252bfSMichael Neumann #define THERM_INT_MASK_LOW (1 << 25) 295*57e252bfSMichael Neumann #define CG_AT_3 0x738 296*57e252bfSMichael Neumann #define CG_AT_4 0x73c 297*57e252bfSMichael Neumann #define CG_AT_5 0x740 298*57e252bfSMichael Neumann #define CG_AT_6 0x744 299*57e252bfSMichael Neumann #define CG_AT_7 0x748 300*57e252bfSMichael Neumann 301*57e252bfSMichael Neumann #define CG_BSP_0 0x750 302*57e252bfSMichael Neumann # define BSP(x) ((x) << 0) 303*57e252bfSMichael Neumann # define BSP_MASK (0xffff << 0) 304*57e252bfSMichael Neumann # define BSP_SHIFT 0 305*57e252bfSMichael Neumann # define BSU(x) ((x) << 16) 306*57e252bfSMichael Neumann # define BSU_MASK (0xf << 16) 307*57e252bfSMichael Neumann # define BSU_SHIFT 16 308*57e252bfSMichael Neumann 309*57e252bfSMichael Neumann #define CG_CG_VOLTAGE_CNTL 0x770 310*57e252bfSMichael Neumann # define REQ (1 << 0) 311*57e252bfSMichael Neumann # define LEVEL(x) ((x) << 1) 312*57e252bfSMichael Neumann # define LEVEL_MASK (0x3 << 1) 313*57e252bfSMichael Neumann # define LEVEL_SHIFT 1 314*57e252bfSMichael Neumann # define CG_VOLTAGE_EN (1 << 3) 315*57e252bfSMichael Neumann # define FORCE (1 << 4) 316*57e252bfSMichael Neumann # define PERIOD(x) ((x) << 8) 317*57e252bfSMichael Neumann # define PERIOD_MASK (0xffff << 8) 318*57e252bfSMichael Neumann # define PERIOD_SHIFT 8 319*57e252bfSMichael Neumann # define UNIT(x) ((x) << 24) 320*57e252bfSMichael Neumann # define UNIT_MASK (0xf << 24) 321*57e252bfSMichael Neumann # define UNIT_SHIFT 24 322*57e252bfSMichael Neumann 323*57e252bfSMichael Neumann #define CG_ACPI_VOLTAGE_CNTL 0x780 324*57e252bfSMichael Neumann # define ACPI_VOLTAGE_EN (1 << 8) 325*57e252bfSMichael Neumann 326*57e252bfSMichael Neumann #define CG_DPM_VOLTAGE_CNTL 0x788 327*57e252bfSMichael Neumann # define DPM_STATE0_LEVEL_MASK (0x3 << 0) 328*57e252bfSMichael Neumann # define DPM_STATE0_LEVEL_SHIFT 0 329*57e252bfSMichael Neumann # define DPM_VOLTAGE_EN (1 << 16) 330*57e252bfSMichael Neumann 331*57e252bfSMichael Neumann #define CG_PWR_GATING_CNTL 0x7ac 332*57e252bfSMichael Neumann # define DYN_PWR_DOWN_EN (1 << 0) 333*57e252bfSMichael Neumann # define ACPI_PWR_DOWN_EN (1 << 1) 334*57e252bfSMichael Neumann # define GFX_CLK_OFF_PWR_DOWN_EN (1 << 2) 335*57e252bfSMichael Neumann # define IOC_DISGPU_PWR_DOWN_EN (1 << 3) 336*57e252bfSMichael Neumann # define FORCE_POWR_ON (1 << 4) 337*57e252bfSMichael Neumann # define PGP(x) ((x) << 8) 338*57e252bfSMichael Neumann # define PGP_MASK (0xffff << 8) 339*57e252bfSMichael Neumann # define PGP_SHIFT 8 340*57e252bfSMichael Neumann # define PGU(x) ((x) << 24) 341*57e252bfSMichael Neumann # define PGU_MASK (0xf << 24) 342*57e252bfSMichael Neumann # define PGU_SHIFT 24 343*57e252bfSMichael Neumann 344*57e252bfSMichael Neumann #define CG_CGTT_LOCAL_0 0x7d0 345*57e252bfSMichael Neumann #define CG_CGTT_LOCAL_1 0x7d4 346*57e252bfSMichael Neumann 347*57e252bfSMichael Neumann #define DEEP_SLEEP_CNTL 0x818 348*57e252bfSMichael Neumann # define R_DIS (1 << 3) 349*57e252bfSMichael Neumann # define HS(x) ((x) << 4) 350*57e252bfSMichael Neumann # define HS_MASK (0xfff << 4) 351*57e252bfSMichael Neumann # define HS_SHIFT 4 352*57e252bfSMichael Neumann # define ENABLE_DS (1 << 31) 353*57e252bfSMichael Neumann #define DEEP_SLEEP_CNTL2 0x81c 354*57e252bfSMichael Neumann # define LB_UFP_EN (1 << 0) 355*57e252bfSMichael Neumann # define INOUT_C(x) ((x) << 4) 356*57e252bfSMichael Neumann # define INOUT_C_MASK (0xff << 4) 357*57e252bfSMichael Neumann # define INOUT_C_SHIFT 4 358*57e252bfSMichael Neumann 359*57e252bfSMichael Neumann #define CG_SCRATCH2 0x824 360*57e252bfSMichael Neumann 361*57e252bfSMichael Neumann #define CG_SCLK_DPM_CTRL_11 0x830 362*57e252bfSMichael Neumann 363*57e252bfSMichael Neumann #define HW_REV 0x5564 364*57e252bfSMichael Neumann # define ATI_REV_ID_MASK (0xf << 28) 365*57e252bfSMichael Neumann # define ATI_REV_ID_SHIFT 28 366*57e252bfSMichael Neumann /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ 367*57e252bfSMichael Neumann 368*57e252bfSMichael Neumann #define DOUT_SCRATCH3 0x611c 369*57e252bfSMichael Neumann 370*57e252bfSMichael Neumann #define GB_ADDR_CONFIG 0x98f8 371*57e252bfSMichael Neumann 372*57e252bfSMichael Neumann #endif 373