xref: /dflybsd-src/sys/dev/drm/radeon/si_dpm.h (revision c59a5c484fdf34b9afa6e283014e4fff693253cc)
157e252bfSMichael Neumann /*
257e252bfSMichael Neumann  * Copyright 2012 Advanced Micro Devices, Inc.
357e252bfSMichael Neumann  *
457e252bfSMichael Neumann  * Permission is hereby granted, free of charge, to any person obtaining a
557e252bfSMichael Neumann  * copy of this software and associated documentation files (the "Software"),
657e252bfSMichael Neumann  * to deal in the Software without restriction, including without limitation
757e252bfSMichael Neumann  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
857e252bfSMichael Neumann  * and/or sell copies of the Software, and to permit persons to whom the
957e252bfSMichael Neumann  * Software is furnished to do so, subject to the following conditions:
1057e252bfSMichael Neumann  *
1157e252bfSMichael Neumann  * The above copyright notice and this permission notice shall be included in
1257e252bfSMichael Neumann  * all copies or substantial portions of the Software.
1357e252bfSMichael Neumann  *
1457e252bfSMichael Neumann  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1557e252bfSMichael Neumann  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1657e252bfSMichael Neumann  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1757e252bfSMichael Neumann  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1857e252bfSMichael Neumann  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1957e252bfSMichael Neumann  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2057e252bfSMichael Neumann  * OTHER DEALINGS IN THE SOFTWARE.
2157e252bfSMichael Neumann  *
2257e252bfSMichael Neumann  */
2357e252bfSMichael Neumann #ifndef __SI_DPM_H__
2457e252bfSMichael Neumann #define __SI_DPM_H__
2557e252bfSMichael Neumann 
2657e252bfSMichael Neumann #include "ni_dpm.h"
2757e252bfSMichael Neumann #include "sislands_smc.h"
2857e252bfSMichael Neumann 
2957e252bfSMichael Neumann enum si_cac_config_reg_type
3057e252bfSMichael Neumann {
3157e252bfSMichael Neumann 	SISLANDS_CACCONFIG_MMR = 0,
3257e252bfSMichael Neumann 	SISLANDS_CACCONFIG_CGIND,
3357e252bfSMichael Neumann 	SISLANDS_CACCONFIG_MAX
3457e252bfSMichael Neumann };
3557e252bfSMichael Neumann 
3657e252bfSMichael Neumann struct si_cac_config_reg
3757e252bfSMichael Neumann {
3857e252bfSMichael Neumann 	u32 offset;
3957e252bfSMichael Neumann 	u32 mask;
4057e252bfSMichael Neumann 	u32 shift;
4157e252bfSMichael Neumann 	u32 value;
4257e252bfSMichael Neumann 	enum si_cac_config_reg_type type;
4357e252bfSMichael Neumann };
4457e252bfSMichael Neumann 
4557e252bfSMichael Neumann struct si_powertune_data
4657e252bfSMichael Neumann {
4757e252bfSMichael Neumann 	u32 cac_window;
4857e252bfSMichael Neumann 	u32 l2_lta_window_size_default;
4957e252bfSMichael Neumann 	u8 lts_truncate_default;
5057e252bfSMichael Neumann 	u8 shift_n_default;
5157e252bfSMichael Neumann 	u8 operating_temp;
5257e252bfSMichael Neumann 	struct ni_leakage_coeffients leakage_coefficients;
5357e252bfSMichael Neumann 	u32 fixed_kt;
5457e252bfSMichael Neumann 	u32 lkge_lut_v0_percent;
5557e252bfSMichael Neumann 	u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];
5657e252bfSMichael Neumann 	bool enable_powertune_by_default;
5757e252bfSMichael Neumann };
5857e252bfSMichael Neumann 
5957e252bfSMichael Neumann struct si_dyn_powertune_data
6057e252bfSMichael Neumann {
6157e252bfSMichael Neumann 	u32 cac_leakage;
6257e252bfSMichael Neumann 	s32 leakage_minimum_temperature;
6357e252bfSMichael Neumann 	u32 wintime;
6457e252bfSMichael Neumann 	u32 l2_lta_window_size;
6557e252bfSMichael Neumann 	u8 lts_truncate;
6657e252bfSMichael Neumann 	u8 shift_n;
6757e252bfSMichael Neumann 	u8 dc_pwr_value;
6857e252bfSMichael Neumann 	bool disable_uvd_powertune;
6957e252bfSMichael Neumann };
7057e252bfSMichael Neumann 
7157e252bfSMichael Neumann struct si_dte_data
7257e252bfSMichael Neumann {
7357e252bfSMichael Neumann 	u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
7457e252bfSMichael Neumann 	u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
7557e252bfSMichael Neumann 	u32 k;
7657e252bfSMichael Neumann 	u32 t0;
7757e252bfSMichael Neumann 	u32 max_t;
7857e252bfSMichael Neumann 	u8 window_size;
7957e252bfSMichael Neumann 	u8 temp_select;
8057e252bfSMichael Neumann 	u8 dte_mode;
8157e252bfSMichael Neumann 	u8 tdep_count;
8257e252bfSMichael Neumann 	u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
8357e252bfSMichael Neumann 	u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
8457e252bfSMichael Neumann 	u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
8557e252bfSMichael Neumann 	u32 t_threshold;
8657e252bfSMichael Neumann 	bool enable_dte_by_default;
8757e252bfSMichael Neumann };
8857e252bfSMichael Neumann 
8957e252bfSMichael Neumann struct si_clock_registers {
9057e252bfSMichael Neumann 	u32 cg_spll_func_cntl;
9157e252bfSMichael Neumann 	u32 cg_spll_func_cntl_2;
9257e252bfSMichael Neumann 	u32 cg_spll_func_cntl_3;
9357e252bfSMichael Neumann 	u32 cg_spll_func_cntl_4;
9457e252bfSMichael Neumann 	u32 cg_spll_spread_spectrum;
9557e252bfSMichael Neumann 	u32 cg_spll_spread_spectrum_2;
9657e252bfSMichael Neumann 	u32 dll_cntl;
9757e252bfSMichael Neumann 	u32 mclk_pwrmgt_cntl;
9857e252bfSMichael Neumann 	u32 mpll_ad_func_cntl;
9957e252bfSMichael Neumann 	u32 mpll_dq_func_cntl;
10057e252bfSMichael Neumann 	u32 mpll_func_cntl;
10157e252bfSMichael Neumann 	u32 mpll_func_cntl_1;
10257e252bfSMichael Neumann 	u32 mpll_func_cntl_2;
10357e252bfSMichael Neumann 	u32 mpll_ss1;
10457e252bfSMichael Neumann 	u32 mpll_ss2;
10557e252bfSMichael Neumann };
10657e252bfSMichael Neumann 
10757e252bfSMichael Neumann struct si_mc_reg_entry {
10857e252bfSMichael Neumann 	u32 mclk_max;
10957e252bfSMichael Neumann 	u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
11057e252bfSMichael Neumann };
11157e252bfSMichael Neumann 
11257e252bfSMichael Neumann struct si_mc_reg_table {
11357e252bfSMichael Neumann 	u8 last;
11457e252bfSMichael Neumann 	u8 num_entries;
11557e252bfSMichael Neumann 	u16 valid_flag;
11657e252bfSMichael Neumann 	struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
11757e252bfSMichael Neumann 	SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
11857e252bfSMichael Neumann };
11957e252bfSMichael Neumann 
12057e252bfSMichael Neumann #define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT               0
12157e252bfSMichael Neumann #define SISLANDS_MCREGISTERTABLE_ACPI_SLOT                  1
12257e252bfSMichael Neumann #define SISLANDS_MCREGISTERTABLE_ULV_SLOT                   2
12357e252bfSMichael Neumann #define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT     3
12457e252bfSMichael Neumann 
12557e252bfSMichael Neumann struct si_leakage_voltage_entry
12657e252bfSMichael Neumann {
12757e252bfSMichael Neumann 	u16 voltage;
12857e252bfSMichael Neumann 	u16 leakage_index;
12957e252bfSMichael Neumann };
13057e252bfSMichael Neumann 
13157e252bfSMichael Neumann #define SISLANDS_LEAKAGE_INDEX0     0xff01
13257e252bfSMichael Neumann #define SISLANDS_MAX_LEAKAGE_COUNT  4
13357e252bfSMichael Neumann 
13457e252bfSMichael Neumann struct si_leakage_voltage
13557e252bfSMichael Neumann {
13657e252bfSMichael Neumann 	u16 count;
13757e252bfSMichael Neumann 	struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT];
13857e252bfSMichael Neumann };
13957e252bfSMichael Neumann 
14057e252bfSMichael Neumann #define SISLANDS_MAX_HARDWARE_POWERLEVELS 5
14157e252bfSMichael Neumann 
14257e252bfSMichael Neumann struct si_ulv_param {
14357e252bfSMichael Neumann 	bool supported;
14457e252bfSMichael Neumann 	u32 cg_ulv_control;
14557e252bfSMichael Neumann 	u32 cg_ulv_parameter;
14657e252bfSMichael Neumann 	u32 volt_change_delay;
14757e252bfSMichael Neumann 	struct rv7xx_pl pl;
14857e252bfSMichael Neumann 	bool one_pcie_lane_in_ulv;
14957e252bfSMichael Neumann };
15057e252bfSMichael Neumann 
15157e252bfSMichael Neumann struct si_power_info {
15257e252bfSMichael Neumann 	/* must be first! */
15357e252bfSMichael Neumann 	struct ni_power_info ni;
15457e252bfSMichael Neumann 	struct si_clock_registers clock_registers;
15557e252bfSMichael Neumann 	struct si_mc_reg_table mc_reg_table;
15657e252bfSMichael Neumann 	struct atom_voltage_table mvdd_voltage_table;
15757e252bfSMichael Neumann 	struct atom_voltage_table vddc_phase_shed_table;
15857e252bfSMichael Neumann 	struct si_leakage_voltage leakage_voltage;
15957e252bfSMichael Neumann 	u16 mvdd_bootup_value;
16057e252bfSMichael Neumann 	struct si_ulv_param ulv;
16157e252bfSMichael Neumann 	u32 max_cu;
16257e252bfSMichael Neumann 	/* pcie gen */
16357e252bfSMichael Neumann 	enum radeon_pcie_gen force_pcie_gen;
16457e252bfSMichael Neumann 	enum radeon_pcie_gen boot_pcie_gen;
16557e252bfSMichael Neumann 	enum radeon_pcie_gen acpi_pcie_gen;
16657e252bfSMichael Neumann 	u32 sys_pcie_mask;
16757e252bfSMichael Neumann 	/* flags */
16857e252bfSMichael Neumann 	bool enable_dte;
16957e252bfSMichael Neumann 	bool enable_ppm;
17057e252bfSMichael Neumann 	bool vddc_phase_shed_control;
17157e252bfSMichael Neumann 	bool pspp_notify_required;
17257e252bfSMichael Neumann 	bool sclk_deep_sleep_above_low;
173c6f73aabSFrançois Tigeot 	bool voltage_control_svi2;
174c6f73aabSFrançois Tigeot 	bool vddci_control_svi2;
17557e252bfSMichael Neumann 	/* smc offsets */
17657e252bfSMichael Neumann 	u32 sram_end;
17757e252bfSMichael Neumann 	u32 state_table_start;
17857e252bfSMichael Neumann 	u32 soft_regs_start;
17957e252bfSMichael Neumann 	u32 mc_reg_table_start;
18057e252bfSMichael Neumann 	u32 arb_table_start;
18157e252bfSMichael Neumann 	u32 cac_table_start;
18257e252bfSMichael Neumann 	u32 dte_table_start;
18357e252bfSMichael Neumann 	u32 spll_table_start;
18457e252bfSMichael Neumann 	u32 papm_cfg_table_start;
1857dcf36dcSFrançois Tigeot 	u32 fan_table_start;
18657e252bfSMichael Neumann 	/* CAC stuff */
18757e252bfSMichael Neumann 	const struct si_cac_config_reg *cac_weights;
18857e252bfSMichael Neumann 	const struct si_cac_config_reg *lcac_config;
18957e252bfSMichael Neumann 	const struct si_cac_config_reg *cac_override;
19057e252bfSMichael Neumann 	const struct si_powertune_data *powertune_data;
19157e252bfSMichael Neumann 	struct si_dyn_powertune_data dyn_powertune_data;
19257e252bfSMichael Neumann 	/* DTE stuff */
19357e252bfSMichael Neumann 	struct si_dte_data dte_data;
19457e252bfSMichael Neumann 	/* scratch structs */
19557e252bfSMichael Neumann 	SMC_SIslands_MCRegisters smc_mc_reg_table;
19657e252bfSMichael Neumann 	SISLANDS_SMC_STATETABLE smc_statetable;
19757e252bfSMichael Neumann 	PP_SIslands_PAPMParameters papm_parm;
198c6f73aabSFrançois Tigeot 	/* SVI2 */
199c6f73aabSFrançois Tigeot 	u8 svd_gpio_id;
200c6f73aabSFrançois Tigeot 	u8 svc_gpio_id;
2017dcf36dcSFrançois Tigeot 	/* fan control */
2027dcf36dcSFrançois Tigeot 	bool fan_ctrl_is_in_default_mode;
2037dcf36dcSFrançois Tigeot 	u32 t_min;
2047dcf36dcSFrançois Tigeot 	u32 fan_ctrl_default_mode;
205*c59a5c48SFrançois Tigeot 	bool fan_is_controlled_by_smc;
20657e252bfSMichael Neumann };
20757e252bfSMichael Neumann 
20857e252bfSMichael Neumann #define SISLANDS_INITIAL_STATE_ARB_INDEX    0
20957e252bfSMichael Neumann #define SISLANDS_ACPI_STATE_ARB_INDEX       1
21057e252bfSMichael Neumann #define SISLANDS_ULV_STATE_ARB_INDEX        2
21157e252bfSMichael Neumann #define SISLANDS_DRIVER_STATE_ARB_INDEX     3
21257e252bfSMichael Neumann 
21357e252bfSMichael Neumann #define SISLANDS_DPM2_MAX_PULSE_SKIP        256
21457e252bfSMichael Neumann 
21557e252bfSMichael Neumann #define SISLANDS_DPM2_NEAR_TDP_DEC          10
21657e252bfSMichael Neumann #define SISLANDS_DPM2_ABOVE_SAFE_INC        5
21757e252bfSMichael Neumann #define SISLANDS_DPM2_BELOW_SAFE_INC        20
21857e252bfSMichael Neumann 
21957e252bfSMichael Neumann #define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT            80
22057e252bfSMichael Neumann 
22157e252bfSMichael Neumann #define SISLANDS_DPM2_MAXPS_PERCENT_H                   99
22257e252bfSMichael Neumann #define SISLANDS_DPM2_MAXPS_PERCENT_M                   99
22357e252bfSMichael Neumann 
22457e252bfSMichael Neumann #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
22557e252bfSMichael Neumann #define SISLANDS_DPM2_SQ_RAMP_MIN_POWER                 0x12
22657e252bfSMichael Neumann #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
22757e252bfSMichael Neumann #define SISLANDS_DPM2_SQ_RAMP_STI_SIZE                  0x1E
22857e252bfSMichael Neumann #define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO                 0xF
22957e252bfSMichael Neumann 
23057e252bfSMichael Neumann #define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN         10
23157e252bfSMichael Neumann 
23257e252bfSMichael Neumann #define SISLANDS_VRC_DFLT                               0xC000B3
23357e252bfSMichael Neumann #define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT             1687
23457e252bfSMichael Neumann #define SISLANDS_CGULVPARAMETER_DFLT                    0x00040035
23557e252bfSMichael Neumann #define SISLANDS_CGULVCONTROL_DFLT                      0x1f007550
23657e252bfSMichael Neumann 
23757e252bfSMichael Neumann 
23857e252bfSMichael Neumann #endif
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