1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 #include "r600_dpm.h" 29 #include "si_dpm.h" 30 #include "atom.h" 31 #include <linux/math64.h> 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x20000 40 41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43 static const struct si_cac_config_reg cac_weights_tahiti[] = 44 { 45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 105 { 0xFFFFFFFF } 106 }; 107 108 static const struct si_cac_config_reg lcac_tahiti[] = 109 { 110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0xFFFFFFFF } 197 198 }; 199 200 static const struct si_cac_config_reg cac_override_tahiti[] = 201 { 202 { 0xFFFFFFFF } 203 }; 204 205 static const struct si_powertune_data powertune_data_tahiti = 206 { 207 ((1 << 16) | 27027), 208 6, 209 0, 210 4, 211 95, 212 { 213 0UL, 214 0UL, 215 4521550UL, 216 309631529UL, 217 -1270850L, 218 4513710L, 219 40 220 }, 221 595000000UL, 222 12, 223 { 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0 232 }, 233 true 234 }; 235 236 static const struct si_dte_data dte_data_tahiti = 237 { 238 { 1159409, 0, 0, 0, 0 }, 239 { 777, 0, 0, 0, 0 }, 240 2, 241 54000, 242 127000, 243 25, 244 2, 245 10, 246 13, 247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 250 85, 251 false 252 }; 253 254 static const struct si_dte_data dte_data_tahiti_le = 255 { 256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 258 0x5, 259 0xAFC8, 260 0x64, 261 0x32, 262 1, 263 0, 264 0x10, 265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 268 85, 269 true 270 }; 271 272 static const struct si_dte_data dte_data_tahiti_pro = 273 { 274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 275 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 276 5, 277 45000, 278 100, 279 0xA, 280 1, 281 0, 282 0x10, 283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 286 90, 287 true 288 }; 289 290 static const struct si_dte_data dte_data_new_zealand = 291 { 292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 294 0x5, 295 0xAFC8, 296 0x69, 297 0x32, 298 1, 299 0, 300 0x10, 301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 304 85, 305 true 306 }; 307 308 static const struct si_dte_data dte_data_aruba_pro = 309 { 310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 311 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 312 5, 313 45000, 314 100, 315 0xA, 316 1, 317 0, 318 0x10, 319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 322 90, 323 true 324 }; 325 326 static const struct si_dte_data dte_data_malta = 327 { 328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 329 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 330 5, 331 45000, 332 100, 333 0xA, 334 1, 335 0, 336 0x10, 337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 340 90, 341 true 342 }; 343 344 struct si_cac_config_reg cac_weights_pitcairn[] = 345 { 346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 406 { 0xFFFFFFFF } 407 }; 408 409 static const struct si_cac_config_reg lcac_pitcairn[] = 410 { 411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0xFFFFFFFF } 498 }; 499 500 static const struct si_cac_config_reg cac_override_pitcairn[] = 501 { 502 { 0xFFFFFFFF } 503 }; 504 505 static const struct si_powertune_data powertune_data_pitcairn = 506 { 507 ((1 << 16) | 27027), 508 5, 509 0, 510 6, 511 100, 512 { 513 51600000UL, 514 1800000UL, 515 7194395UL, 516 309631529UL, 517 -1270850L, 518 4513710L, 519 100 520 }, 521 117830498UL, 522 12, 523 { 524 0, 525 0, 526 0, 527 0, 528 0, 529 0, 530 0, 531 0 532 }, 533 true 534 }; 535 536 static const struct si_dte_data dte_data_pitcairn = 537 { 538 { 0, 0, 0, 0, 0 }, 539 { 0, 0, 0, 0, 0 }, 540 0, 541 0, 542 0, 543 0, 544 0, 545 0, 546 0, 547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 0, 551 false 552 }; 553 554 static const struct si_dte_data dte_data_curacao_xt = 555 { 556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 557 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 558 5, 559 45000, 560 100, 561 0xA, 562 1, 563 0, 564 0x10, 565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 568 90, 569 true 570 }; 571 572 static const struct si_dte_data dte_data_curacao_pro = 573 { 574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 575 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 576 5, 577 45000, 578 100, 579 0xA, 580 1, 581 0, 582 0x10, 583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 586 90, 587 true 588 }; 589 590 static const struct si_dte_data dte_data_neptune_xt = 591 { 592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 593 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 594 5, 595 45000, 596 100, 597 0xA, 598 1, 599 0, 600 0x10, 601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 604 90, 605 true 606 }; 607 608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 609 { 610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 670 { 0xFFFFFFFF } 671 }; 672 673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 674 { 675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 735 { 0xFFFFFFFF } 736 }; 737 738 static const struct si_cac_config_reg cac_weights_heathrow[] = 739 { 740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 800 { 0xFFFFFFFF } 801 }; 802 803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 804 { 805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 865 { 0xFFFFFFFF } 866 }; 867 868 static const struct si_cac_config_reg cac_weights_cape_verde[] = 869 { 870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 930 { 0xFFFFFFFF } 931 }; 932 933 static const struct si_cac_config_reg lcac_cape_verde[] = 934 { 935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0xFFFFFFFF } 990 }; 991 992 static const struct si_cac_config_reg cac_override_cape_verde[] = 993 { 994 { 0xFFFFFFFF } 995 }; 996 997 static const struct si_powertune_data powertune_data_cape_verde = 998 { 999 ((1 << 16) | 0x6993), 1000 5, 1001 0, 1002 7, 1003 105, 1004 { 1005 0UL, 1006 0UL, 1007 7194395UL, 1008 309631529UL, 1009 -1270850L, 1010 4513710L, 1011 100 1012 }, 1013 117830498UL, 1014 12, 1015 { 1016 0, 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0 1024 }, 1025 true 1026 }; 1027 1028 static const struct si_dte_data dte_data_cape_verde = 1029 { 1030 { 0, 0, 0, 0, 0 }, 1031 { 0, 0, 0, 0, 0 }, 1032 0, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 0, 1043 false 1044 }; 1045 1046 static const struct si_dte_data dte_data_venus_xtx = 1047 { 1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1050 5, 1051 55000, 1052 0x69, 1053 0xA, 1054 1, 1055 0, 1056 0x3, 1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 90, 1061 true 1062 }; 1063 1064 static const struct si_dte_data dte_data_venus_xt = 1065 { 1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1068 5, 1069 55000, 1070 0x69, 1071 0xA, 1072 1, 1073 0, 1074 0x3, 1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 90, 1079 true 1080 }; 1081 1082 static const struct si_dte_data dte_data_venus_pro = 1083 { 1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1086 5, 1087 55000, 1088 0x69, 1089 0xA, 1090 1, 1091 0, 1092 0x3, 1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 90, 1097 true 1098 }; 1099 1100 struct si_cac_config_reg cac_weights_oland[] = 1101 { 1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1162 { 0xFFFFFFFF } 1163 }; 1164 1165 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1166 { 1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1227 { 0xFFFFFFFF } 1228 }; 1229 1230 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1231 { 1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1292 { 0xFFFFFFFF } 1293 }; 1294 1295 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1296 { 1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1357 { 0xFFFFFFFF } 1358 }; 1359 1360 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1361 { 1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1422 { 0xFFFFFFFF } 1423 }; 1424 1425 static const struct si_cac_config_reg lcac_oland[] = 1426 { 1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0xFFFFFFFF } 1470 }; 1471 1472 static const struct si_cac_config_reg lcac_mars_pro[] = 1473 { 1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0xFFFFFFFF } 1517 }; 1518 1519 static const struct si_cac_config_reg cac_override_oland[] = 1520 { 1521 { 0xFFFFFFFF } 1522 }; 1523 1524 static const struct si_powertune_data powertune_data_oland = 1525 { 1526 ((1 << 16) | 0x6993), 1527 5, 1528 0, 1529 7, 1530 105, 1531 { 1532 0UL, 1533 0UL, 1534 7194395UL, 1535 309631529UL, 1536 -1270850L, 1537 4513710L, 1538 100 1539 }, 1540 117830498UL, 1541 12, 1542 { 1543 0, 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0 1551 }, 1552 true 1553 }; 1554 1555 static const struct si_powertune_data powertune_data_mars_pro = 1556 { 1557 ((1 << 16) | 0x6993), 1558 5, 1559 0, 1560 7, 1561 105, 1562 { 1563 0UL, 1564 0UL, 1565 7194395UL, 1566 309631529UL, 1567 -1270850L, 1568 4513710L, 1569 100 1570 }, 1571 117830498UL, 1572 12, 1573 { 1574 0, 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0 1582 }, 1583 true 1584 }; 1585 1586 static const struct si_dte_data dte_data_oland = 1587 { 1588 { 0, 0, 0, 0, 0 }, 1589 { 0, 0, 0, 0, 0 }, 1590 0, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 0, 1601 false 1602 }; 1603 1604 static const struct si_dte_data dte_data_mars_pro = 1605 { 1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1607 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1608 5, 1609 55000, 1610 105, 1611 0xA, 1612 1, 1613 0, 1614 0x10, 1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1618 90, 1619 true 1620 }; 1621 1622 static const struct si_dte_data dte_data_sun_xt = 1623 { 1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1625 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1626 5, 1627 55000, 1628 105, 1629 0xA, 1630 1, 1631 0, 1632 0x10, 1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1636 90, 1637 true 1638 }; 1639 1640 1641 static const struct si_cac_config_reg cac_weights_hainan[] = 1642 { 1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1703 { 0xFFFFFFFF } 1704 }; 1705 1706 static const struct si_powertune_data powertune_data_hainan = 1707 { 1708 ((1 << 16) | 0x6993), 1709 5, 1710 0, 1711 9, 1712 105, 1713 { 1714 0UL, 1715 0UL, 1716 7194395UL, 1717 309631529UL, 1718 -1270850L, 1719 4513710L, 1720 100 1721 }, 1722 117830498UL, 1723 12, 1724 { 1725 0, 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0 1733 }, 1734 true 1735 }; 1736 1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1741 1742 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); 1743 1744 static int si_populate_voltage_value(struct radeon_device *rdev, 1745 const struct atom_voltage_table *table, 1746 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1747 static int si_get_std_voltage_value(struct radeon_device *rdev, 1748 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1749 u16 *std_voltage); 1750 static int si_write_smc_soft_register(struct radeon_device *rdev, 1751 u16 reg_offset, u32 value); 1752 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1753 struct rv7xx_pl *pl, 1754 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1755 static int si_calculate_sclk_params(struct radeon_device *rdev, 1756 u32 engine_clock, 1757 SISLANDS_SMC_SCLK_VALUE *sclk); 1758 1759 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1760 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1761 1762 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1763 { 1764 struct si_power_info *pi = rdev->pm.dpm.priv; 1765 1766 return pi; 1767 } 1768 1769 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1770 u16 v, s32 t, u32 ileakage, u32 *leakage) 1771 { 1772 s64 kt, kv, leakage_w, i_leakage, vddc; 1773 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1774 s64 tmp; 1775 1776 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1777 vddc = div64_s64(drm_int2fixp(v), 1000); 1778 temperature = div64_s64(drm_int2fixp(t), 1000); 1779 1780 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1781 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1782 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1783 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1784 t_ref = drm_int2fixp(coeff->t_ref); 1785 1786 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1787 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1788 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1789 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1790 1791 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1792 1793 *leakage = drm_fixp2int(leakage_w * 1000); 1794 } 1795 1796 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1797 const struct ni_leakage_coeffients *coeff, 1798 u16 v, 1799 s32 t, 1800 u32 i_leakage, 1801 u32 *leakage) 1802 { 1803 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1804 } 1805 1806 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1807 const u32 fixed_kt, u16 v, 1808 u32 ileakage, u32 *leakage) 1809 { 1810 s64 kt, kv, leakage_w, i_leakage, vddc; 1811 1812 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1813 vddc = div64_s64(drm_int2fixp(v), 1000); 1814 1815 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1816 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1817 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1818 1819 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1820 1821 *leakage = drm_fixp2int(leakage_w * 1000); 1822 } 1823 1824 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1825 const struct ni_leakage_coeffients *coeff, 1826 const u32 fixed_kt, 1827 u16 v, 1828 u32 i_leakage, 1829 u32 *leakage) 1830 { 1831 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1832 } 1833 1834 1835 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1836 struct si_dte_data *dte_data) 1837 { 1838 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1839 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1840 u32 k = dte_data->k; 1841 u32 t_max = dte_data->max_t; 1842 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1843 u32 t_0 = dte_data->t0; 1844 u32 i; 1845 1846 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1847 dte_data->tdep_count = 3; 1848 1849 for (i = 0; i < k; i++) { 1850 dte_data->r[i] = 1851 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1852 (p_limit2 * (u32)100); 1853 } 1854 1855 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1856 1857 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1858 dte_data->tdep_r[i] = dte_data->r[4]; 1859 } 1860 } else { 1861 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1862 } 1863 } 1864 1865 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1866 { 1867 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1868 struct si_power_info *si_pi = si_get_pi(rdev); 1869 bool update_dte_from_pl2 = false; 1870 1871 if (rdev->family == CHIP_TAHITI) { 1872 si_pi->cac_weights = cac_weights_tahiti; 1873 si_pi->lcac_config = lcac_tahiti; 1874 si_pi->cac_override = cac_override_tahiti; 1875 si_pi->powertune_data = &powertune_data_tahiti; 1876 si_pi->dte_data = dte_data_tahiti; 1877 1878 switch (rdev->pdev->device) { 1879 case 0x6798: 1880 si_pi->dte_data.enable_dte_by_default = true; 1881 break; 1882 case 0x6799: 1883 si_pi->dte_data = dte_data_new_zealand; 1884 break; 1885 case 0x6790: 1886 case 0x6791: 1887 case 0x6792: 1888 case 0x679E: 1889 si_pi->dte_data = dte_data_aruba_pro; 1890 update_dte_from_pl2 = true; 1891 break; 1892 case 0x679B: 1893 si_pi->dte_data = dte_data_malta; 1894 update_dte_from_pl2 = true; 1895 break; 1896 case 0x679A: 1897 si_pi->dte_data = dte_data_tahiti_pro; 1898 update_dte_from_pl2 = true; 1899 break; 1900 default: 1901 if (si_pi->dte_data.enable_dte_by_default == true) 1902 DRM_ERROR("DTE is not enabled!\n"); 1903 break; 1904 } 1905 } else if (rdev->family == CHIP_PITCAIRN) { 1906 switch (rdev->pdev->device) { 1907 case 0x6810: 1908 case 0x6818: 1909 si_pi->cac_weights = cac_weights_pitcairn; 1910 si_pi->lcac_config = lcac_pitcairn; 1911 si_pi->cac_override = cac_override_pitcairn; 1912 si_pi->powertune_data = &powertune_data_pitcairn; 1913 si_pi->dte_data = dte_data_curacao_xt; 1914 update_dte_from_pl2 = true; 1915 break; 1916 case 0x6819: 1917 case 0x6811: 1918 si_pi->cac_weights = cac_weights_pitcairn; 1919 si_pi->lcac_config = lcac_pitcairn; 1920 si_pi->cac_override = cac_override_pitcairn; 1921 si_pi->powertune_data = &powertune_data_pitcairn; 1922 si_pi->dte_data = dte_data_curacao_pro; 1923 update_dte_from_pl2 = true; 1924 break; 1925 case 0x6800: 1926 case 0x6806: 1927 si_pi->cac_weights = cac_weights_pitcairn; 1928 si_pi->lcac_config = lcac_pitcairn; 1929 si_pi->cac_override = cac_override_pitcairn; 1930 si_pi->powertune_data = &powertune_data_pitcairn; 1931 si_pi->dte_data = dte_data_neptune_xt; 1932 update_dte_from_pl2 = true; 1933 break; 1934 default: 1935 si_pi->cac_weights = cac_weights_pitcairn; 1936 si_pi->lcac_config = lcac_pitcairn; 1937 si_pi->cac_override = cac_override_pitcairn; 1938 si_pi->powertune_data = &powertune_data_pitcairn; 1939 si_pi->dte_data = dte_data_pitcairn; 1940 break; 1941 } 1942 } else if (rdev->family == CHIP_VERDE) { 1943 si_pi->lcac_config = lcac_cape_verde; 1944 si_pi->cac_override = cac_override_cape_verde; 1945 si_pi->powertune_data = &powertune_data_cape_verde; 1946 1947 switch (rdev->pdev->device) { 1948 case 0x683B: 1949 case 0x683F: 1950 case 0x6829: 1951 case 0x6835: 1952 si_pi->cac_weights = cac_weights_cape_verde_pro; 1953 si_pi->dte_data = dte_data_cape_verde; 1954 break; 1955 case 0x682C: 1956 si_pi->cac_weights = cac_weights_cape_verde_pro; 1957 si_pi->dte_data = dte_data_sun_xt; 1958 break; 1959 case 0x6825: 1960 case 0x6827: 1961 si_pi->cac_weights = cac_weights_heathrow; 1962 si_pi->dte_data = dte_data_cape_verde; 1963 break; 1964 case 0x6824: 1965 case 0x682D: 1966 si_pi->cac_weights = cac_weights_chelsea_xt; 1967 si_pi->dte_data = dte_data_cape_verde; 1968 break; 1969 case 0x682F: 1970 si_pi->cac_weights = cac_weights_chelsea_pro; 1971 si_pi->dte_data = dte_data_cape_verde; 1972 break; 1973 case 0x6820: 1974 si_pi->cac_weights = cac_weights_heathrow; 1975 si_pi->dte_data = dte_data_venus_xtx; 1976 break; 1977 case 0x6821: 1978 si_pi->cac_weights = cac_weights_heathrow; 1979 si_pi->dte_data = dte_data_venus_xt; 1980 break; 1981 case 0x6823: 1982 case 0x682B: 1983 case 0x6822: 1984 case 0x682A: 1985 si_pi->cac_weights = cac_weights_chelsea_pro; 1986 si_pi->dte_data = dte_data_venus_pro; 1987 break; 1988 default: 1989 si_pi->cac_weights = cac_weights_cape_verde; 1990 si_pi->dte_data = dte_data_cape_verde; 1991 break; 1992 } 1993 } else if (rdev->family == CHIP_OLAND) { 1994 switch (rdev->pdev->device) { 1995 case 0x6601: 1996 case 0x6621: 1997 case 0x6603: 1998 case 0x6605: 1999 si_pi->cac_weights = cac_weights_mars_pro; 2000 si_pi->lcac_config = lcac_mars_pro; 2001 si_pi->cac_override = cac_override_oland; 2002 si_pi->powertune_data = &powertune_data_mars_pro; 2003 si_pi->dte_data = dte_data_mars_pro; 2004 update_dte_from_pl2 = true; 2005 break; 2006 case 0x6600: 2007 case 0x6606: 2008 case 0x6620: 2009 case 0x6604: 2010 si_pi->cac_weights = cac_weights_mars_xt; 2011 si_pi->lcac_config = lcac_mars_pro; 2012 si_pi->cac_override = cac_override_oland; 2013 si_pi->powertune_data = &powertune_data_mars_pro; 2014 si_pi->dte_data = dte_data_mars_pro; 2015 update_dte_from_pl2 = true; 2016 break; 2017 case 0x6611: 2018 case 0x6613: 2019 case 0x6608: 2020 si_pi->cac_weights = cac_weights_oland_pro; 2021 si_pi->lcac_config = lcac_mars_pro; 2022 si_pi->cac_override = cac_override_oland; 2023 si_pi->powertune_data = &powertune_data_mars_pro; 2024 si_pi->dte_data = dte_data_mars_pro; 2025 update_dte_from_pl2 = true; 2026 break; 2027 case 0x6610: 2028 si_pi->cac_weights = cac_weights_oland_xt; 2029 si_pi->lcac_config = lcac_mars_pro; 2030 si_pi->cac_override = cac_override_oland; 2031 si_pi->powertune_data = &powertune_data_mars_pro; 2032 si_pi->dte_data = dte_data_mars_pro; 2033 update_dte_from_pl2 = true; 2034 break; 2035 default: 2036 si_pi->cac_weights = cac_weights_oland; 2037 si_pi->lcac_config = lcac_oland; 2038 si_pi->cac_override = cac_override_oland; 2039 si_pi->powertune_data = &powertune_data_oland; 2040 si_pi->dte_data = dte_data_oland; 2041 break; 2042 } 2043 } else if (rdev->family == CHIP_HAINAN) { 2044 si_pi->cac_weights = cac_weights_hainan; 2045 si_pi->lcac_config = lcac_oland; 2046 si_pi->cac_override = cac_override_oland; 2047 si_pi->powertune_data = &powertune_data_hainan; 2048 si_pi->dte_data = dte_data_sun_xt; 2049 update_dte_from_pl2 = true; 2050 } else { 2051 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2052 return; 2053 } 2054 2055 ni_pi->enable_power_containment = false; 2056 ni_pi->enable_cac = false; 2057 ni_pi->enable_sq_ramping = false; 2058 si_pi->enable_dte = false; 2059 2060 if (si_pi->powertune_data->enable_powertune_by_default) { 2061 ni_pi->enable_power_containment= true; 2062 ni_pi->enable_cac = true; 2063 if (si_pi->dte_data.enable_dte_by_default) { 2064 si_pi->enable_dte = true; 2065 if (update_dte_from_pl2) 2066 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2067 2068 } 2069 ni_pi->enable_sq_ramping = true; 2070 } 2071 2072 ni_pi->driver_calculate_cac_leakage = true; 2073 ni_pi->cac_configuration_required = true; 2074 2075 if (ni_pi->cac_configuration_required) { 2076 ni_pi->support_cac_long_term_average = true; 2077 si_pi->dyn_powertune_data.l2_lta_window_size = 2078 si_pi->powertune_data->l2_lta_window_size_default; 2079 si_pi->dyn_powertune_data.lts_truncate = 2080 si_pi->powertune_data->lts_truncate_default; 2081 } else { 2082 ni_pi->support_cac_long_term_average = false; 2083 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2084 si_pi->dyn_powertune_data.lts_truncate = 0; 2085 } 2086 2087 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2088 } 2089 2090 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2091 { 2092 return 1; 2093 } 2094 2095 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2096 { 2097 u32 xclk; 2098 u32 wintime; 2099 u32 cac_window; 2100 u32 cac_window_size; 2101 2102 xclk = radeon_get_xclk(rdev); 2103 2104 if (xclk == 0) 2105 return 0; 2106 2107 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2108 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2109 2110 wintime = (cac_window_size * 100) / xclk; 2111 2112 return wintime; 2113 } 2114 2115 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2116 { 2117 return power_in_watts; 2118 } 2119 2120 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2121 bool adjust_polarity, 2122 u32 tdp_adjustment, 2123 u32 *tdp_limit, 2124 u32 *near_tdp_limit) 2125 { 2126 u32 adjustment_delta, max_tdp_limit; 2127 2128 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2129 return -EINVAL; 2130 2131 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2132 2133 if (adjust_polarity) { 2134 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2135 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2136 } else { 2137 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2138 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2139 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2140 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2141 else 2142 *near_tdp_limit = 0; 2143 } 2144 2145 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2146 return -EINVAL; 2147 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2148 return -EINVAL; 2149 2150 return 0; 2151 } 2152 2153 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2154 struct radeon_ps *radeon_state) 2155 { 2156 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2157 struct si_power_info *si_pi = si_get_pi(rdev); 2158 2159 if (ni_pi->enable_power_containment) { 2160 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2161 PP_SIslands_PAPMParameters *papm_parm; 2162 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2163 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2164 u32 tdp_limit; 2165 u32 near_tdp_limit; 2166 int ret; 2167 2168 if (scaling_factor == 0) 2169 return -EINVAL; 2170 2171 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2172 2173 ret = si_calculate_adjusted_tdp_limits(rdev, 2174 false, /* ??? */ 2175 rdev->pm.dpm.tdp_adjustment, 2176 &tdp_limit, 2177 &near_tdp_limit); 2178 if (ret) 2179 return ret; 2180 2181 smc_table->dpm2Params.TDPLimit = 2182 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2183 smc_table->dpm2Params.NearTDPLimit = 2184 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2185 smc_table->dpm2Params.SafePowerLimit = 2186 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2187 2188 ret = si_copy_bytes_to_smc(rdev, 2189 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2190 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2191 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2192 sizeof(u32) * 3, 2193 si_pi->sram_end); 2194 if (ret) 2195 return ret; 2196 2197 if (si_pi->enable_ppm) { 2198 papm_parm = &si_pi->papm_parm; 2199 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2200 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2201 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2202 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2203 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2204 papm_parm->PlatformPowerLimit = 0xffffffff; 2205 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2206 2207 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2208 (u8 *)papm_parm, 2209 sizeof(PP_SIslands_PAPMParameters), 2210 si_pi->sram_end); 2211 if (ret) 2212 return ret; 2213 } 2214 } 2215 return 0; 2216 } 2217 2218 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2219 struct radeon_ps *radeon_state) 2220 { 2221 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2222 struct si_power_info *si_pi = si_get_pi(rdev); 2223 2224 if (ni_pi->enable_power_containment) { 2225 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2226 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2227 int ret; 2228 2229 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2230 2231 smc_table->dpm2Params.NearTDPLimit = 2232 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2233 smc_table->dpm2Params.SafePowerLimit = 2234 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2235 2236 ret = si_copy_bytes_to_smc(rdev, 2237 (si_pi->state_table_start + 2238 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2239 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2240 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2241 sizeof(u32) * 2, 2242 si_pi->sram_end); 2243 if (ret) 2244 return ret; 2245 } 2246 2247 return 0; 2248 } 2249 2250 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2251 const u16 prev_std_vddc, 2252 const u16 curr_std_vddc) 2253 { 2254 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2255 u64 prev_vddc = (u64)prev_std_vddc; 2256 u64 curr_vddc = (u64)curr_std_vddc; 2257 u64 pwr_efficiency_ratio, n, d; 2258 2259 if ((prev_vddc == 0) || (curr_vddc == 0)) 2260 return 0; 2261 2262 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2263 d = prev_vddc * prev_vddc; 2264 pwr_efficiency_ratio = div64_u64(n, d); 2265 2266 if (pwr_efficiency_ratio > (u64)0xFFFF) 2267 return 0; 2268 2269 return (u16)pwr_efficiency_ratio; 2270 } 2271 2272 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2273 struct radeon_ps *radeon_state) 2274 { 2275 struct si_power_info *si_pi = si_get_pi(rdev); 2276 2277 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2278 radeon_state->vclk && radeon_state->dclk) 2279 return true; 2280 2281 return false; 2282 } 2283 2284 static int si_populate_power_containment_values(struct radeon_device *rdev, 2285 struct radeon_ps *radeon_state, 2286 SISLANDS_SMC_SWSTATE *smc_state) 2287 { 2288 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2289 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2290 struct ni_ps *state = ni_get_ps(radeon_state); 2291 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2292 u32 prev_sclk; 2293 u32 max_sclk; 2294 u32 min_sclk; 2295 u16 prev_std_vddc; 2296 u16 curr_std_vddc; 2297 int i; 2298 u16 pwr_efficiency_ratio; 2299 u8 max_ps_percent; 2300 bool disable_uvd_power_tune; 2301 int ret; 2302 2303 if (ni_pi->enable_power_containment == false) 2304 return 0; 2305 2306 if (state->performance_level_count == 0) 2307 return -EINVAL; 2308 2309 if (smc_state->levelCount != state->performance_level_count) 2310 return -EINVAL; 2311 2312 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2313 2314 smc_state->levels[0].dpm2.MaxPS = 0; 2315 smc_state->levels[0].dpm2.NearTDPDec = 0; 2316 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2317 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2318 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2319 2320 for (i = 1; i < state->performance_level_count; i++) { 2321 prev_sclk = state->performance_levels[i-1].sclk; 2322 max_sclk = state->performance_levels[i].sclk; 2323 if (i == 1) 2324 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2325 else 2326 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2327 2328 if (prev_sclk > max_sclk) 2329 return -EINVAL; 2330 2331 if ((max_ps_percent == 0) || 2332 (prev_sclk == max_sclk) || 2333 disable_uvd_power_tune) { 2334 min_sclk = max_sclk; 2335 } else if (i == 1) { 2336 min_sclk = prev_sclk; 2337 } else { 2338 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2339 } 2340 2341 if (min_sclk < state->performance_levels[0].sclk) 2342 min_sclk = state->performance_levels[0].sclk; 2343 2344 if (min_sclk == 0) 2345 return -EINVAL; 2346 2347 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2348 state->performance_levels[i-1].vddc, &vddc); 2349 if (ret) 2350 return ret; 2351 2352 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2353 if (ret) 2354 return ret; 2355 2356 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2357 state->performance_levels[i].vddc, &vddc); 2358 if (ret) 2359 return ret; 2360 2361 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2362 if (ret) 2363 return ret; 2364 2365 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2366 prev_std_vddc, curr_std_vddc); 2367 2368 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2369 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2370 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2371 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2372 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2373 } 2374 2375 return 0; 2376 } 2377 2378 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2379 struct radeon_ps *radeon_state, 2380 SISLANDS_SMC_SWSTATE *smc_state) 2381 { 2382 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2383 struct ni_ps *state = ni_get_ps(radeon_state); 2384 u32 sq_power_throttle, sq_power_throttle2; 2385 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2386 int i; 2387 2388 if (state->performance_level_count == 0) 2389 return -EINVAL; 2390 2391 if (smc_state->levelCount != state->performance_level_count) 2392 return -EINVAL; 2393 2394 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2395 return -EINVAL; 2396 2397 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2398 enable_sq_ramping = false; 2399 2400 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2401 enable_sq_ramping = false; 2402 2403 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2404 enable_sq_ramping = false; 2405 2406 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2407 enable_sq_ramping = false; 2408 2409 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2410 enable_sq_ramping = false; 2411 2412 for (i = 0; i < state->performance_level_count; i++) { 2413 sq_power_throttle = 0; 2414 sq_power_throttle2 = 0; 2415 2416 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2417 enable_sq_ramping) { 2418 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2419 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2420 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2421 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2422 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2423 } else { 2424 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2425 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2426 } 2427 2428 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2429 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2430 } 2431 2432 return 0; 2433 } 2434 2435 static int si_enable_power_containment(struct radeon_device *rdev, 2436 struct radeon_ps *radeon_new_state, 2437 bool enable) 2438 { 2439 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2440 PPSMC_Result smc_result; 2441 int ret = 0; 2442 2443 if (ni_pi->enable_power_containment) { 2444 if (enable) { 2445 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2446 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2447 if (smc_result != PPSMC_Result_OK) { 2448 ret = -EINVAL; 2449 ni_pi->pc_enabled = false; 2450 } else { 2451 ni_pi->pc_enabled = true; 2452 } 2453 } 2454 } else { 2455 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2456 if (smc_result != PPSMC_Result_OK) 2457 ret = -EINVAL; 2458 ni_pi->pc_enabled = false; 2459 } 2460 } 2461 2462 return ret; 2463 } 2464 2465 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2466 { 2467 struct si_power_info *si_pi = si_get_pi(rdev); 2468 int ret = 0; 2469 struct si_dte_data *dte_data = &si_pi->dte_data; 2470 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2471 u32 table_size; 2472 u8 tdep_count; 2473 u32 i; 2474 2475 if (dte_data == NULL) 2476 si_pi->enable_dte = false; 2477 2478 if (si_pi->enable_dte == false) 2479 return 0; 2480 2481 if (dte_data->k <= 0) 2482 return -EINVAL; 2483 2484 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2485 if (dte_tables == NULL) { 2486 si_pi->enable_dte = false; 2487 return -ENOMEM; 2488 } 2489 2490 table_size = dte_data->k; 2491 2492 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2493 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2494 2495 tdep_count = dte_data->tdep_count; 2496 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2497 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2498 2499 dte_tables->K = cpu_to_be32(table_size); 2500 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2501 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2502 dte_tables->WindowSize = dte_data->window_size; 2503 dte_tables->temp_select = dte_data->temp_select; 2504 dte_tables->DTE_mode = dte_data->dte_mode; 2505 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2506 2507 if (tdep_count > 0) 2508 table_size--; 2509 2510 for (i = 0; i < table_size; i++) { 2511 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2512 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2513 } 2514 2515 dte_tables->Tdep_count = tdep_count; 2516 2517 for (i = 0; i < (u32)tdep_count; i++) { 2518 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2519 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2520 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2521 } 2522 2523 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2524 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2525 kfree(dte_tables); 2526 2527 return ret; 2528 } 2529 2530 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2531 u16 *max, u16 *min) 2532 { 2533 struct si_power_info *si_pi = si_get_pi(rdev); 2534 struct radeon_cac_leakage_table *table = 2535 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2536 u32 i; 2537 u32 v0_loadline; 2538 2539 2540 if (table == NULL) 2541 return -EINVAL; 2542 2543 *max = 0; 2544 *min = 0xFFFF; 2545 2546 for (i = 0; i < table->count; i++) { 2547 if (table->entries[i].vddc > *max) 2548 *max = table->entries[i].vddc; 2549 if (table->entries[i].vddc < *min) 2550 *min = table->entries[i].vddc; 2551 } 2552 2553 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2554 return -EINVAL; 2555 2556 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2557 2558 if (v0_loadline > 0xFFFFUL) 2559 return -EINVAL; 2560 2561 *min = (u16)v0_loadline; 2562 2563 if ((*min > *max) || (*max == 0) || (*min == 0)) 2564 return -EINVAL; 2565 2566 return 0; 2567 } 2568 2569 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2570 { 2571 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2572 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2573 } 2574 2575 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2576 PP_SIslands_CacConfig *cac_tables, 2577 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2578 u16 t0, u16 t_step) 2579 { 2580 struct si_power_info *si_pi = si_get_pi(rdev); 2581 u32 leakage; 2582 unsigned int i, j; 2583 s32 t; 2584 u32 smc_leakage; 2585 u32 scaling_factor; 2586 u16 voltage; 2587 2588 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2589 2590 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2591 t = (1000 * (i * t_step + t0)); 2592 2593 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2594 voltage = vddc_max - (vddc_step * j); 2595 2596 si_calculate_leakage_for_v_and_t(rdev, 2597 &si_pi->powertune_data->leakage_coefficients, 2598 voltage, 2599 t, 2600 si_pi->dyn_powertune_data.cac_leakage, 2601 &leakage); 2602 2603 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2604 2605 if (smc_leakage > 0xFFFF) 2606 smc_leakage = 0xFFFF; 2607 2608 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2609 cpu_to_be16((u16)smc_leakage); 2610 } 2611 } 2612 return 0; 2613 } 2614 2615 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2616 PP_SIslands_CacConfig *cac_tables, 2617 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2618 { 2619 struct si_power_info *si_pi = si_get_pi(rdev); 2620 u32 leakage; 2621 unsigned int i, j; 2622 u32 smc_leakage; 2623 u32 scaling_factor; 2624 u16 voltage; 2625 2626 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2627 2628 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2629 voltage = vddc_max - (vddc_step * j); 2630 2631 si_calculate_leakage_for_v(rdev, 2632 &si_pi->powertune_data->leakage_coefficients, 2633 si_pi->powertune_data->fixed_kt, 2634 voltage, 2635 si_pi->dyn_powertune_data.cac_leakage, 2636 &leakage); 2637 2638 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2639 2640 if (smc_leakage > 0xFFFF) 2641 smc_leakage = 0xFFFF; 2642 2643 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2644 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2645 cpu_to_be16((u16)smc_leakage); 2646 } 2647 return 0; 2648 } 2649 2650 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2651 { 2652 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2653 struct si_power_info *si_pi = si_get_pi(rdev); 2654 PP_SIslands_CacConfig *cac_tables = NULL; 2655 u16 vddc_max, vddc_min, vddc_step; 2656 u16 t0, t_step; 2657 u32 load_line_slope, reg; 2658 int ret = 0; 2659 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2660 2661 if (ni_pi->enable_cac == false) 2662 return 0; 2663 2664 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2665 if (!cac_tables) 2666 return -ENOMEM; 2667 2668 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2669 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2670 WREG32(CG_CAC_CTRL, reg); 2671 2672 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2673 si_pi->dyn_powertune_data.dc_pwr_value = 2674 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2675 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2676 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2677 2678 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2679 2680 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2681 if (ret) 2682 goto done_free; 2683 2684 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2685 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2686 t_step = 4; 2687 t0 = 60; 2688 2689 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2690 ret = si_init_dte_leakage_table(rdev, cac_tables, 2691 vddc_max, vddc_min, vddc_step, 2692 t0, t_step); 2693 else 2694 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2695 vddc_max, vddc_min, vddc_step); 2696 if (ret) 2697 goto done_free; 2698 2699 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2700 2701 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2702 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2703 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2704 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2705 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2706 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2707 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2708 cac_tables->calculation_repeats = cpu_to_be32(2); 2709 cac_tables->dc_cac = cpu_to_be32(0); 2710 cac_tables->log2_PG_LKG_SCALE = 12; 2711 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2712 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2713 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2714 2715 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2716 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2717 2718 if (ret) 2719 goto done_free; 2720 2721 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2722 2723 done_free: 2724 if (ret) { 2725 ni_pi->enable_cac = false; 2726 ni_pi->enable_power_containment = false; 2727 } 2728 2729 kfree(cac_tables); 2730 2731 return 0; 2732 } 2733 2734 static int si_program_cac_config_registers(struct radeon_device *rdev, 2735 const struct si_cac_config_reg *cac_config_regs) 2736 { 2737 const struct si_cac_config_reg *config_regs = cac_config_regs; 2738 u32 data = 0, offset; 2739 2740 if (!config_regs) 2741 return -EINVAL; 2742 2743 while (config_regs->offset != 0xFFFFFFFF) { 2744 switch (config_regs->type) { 2745 case SISLANDS_CACCONFIG_CGIND: 2746 offset = SMC_CG_IND_START + config_regs->offset; 2747 if (offset < SMC_CG_IND_END) 2748 data = RREG32_SMC(offset); 2749 break; 2750 default: 2751 data = RREG32(config_regs->offset << 2); 2752 break; 2753 } 2754 2755 data &= ~config_regs->mask; 2756 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2757 2758 switch (config_regs->type) { 2759 case SISLANDS_CACCONFIG_CGIND: 2760 offset = SMC_CG_IND_START + config_regs->offset; 2761 if (offset < SMC_CG_IND_END) 2762 WREG32_SMC(offset, data); 2763 break; 2764 default: 2765 WREG32(config_regs->offset << 2, data); 2766 break; 2767 } 2768 config_regs++; 2769 } 2770 return 0; 2771 } 2772 2773 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2774 { 2775 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2776 struct si_power_info *si_pi = si_get_pi(rdev); 2777 int ret; 2778 2779 if ((ni_pi->enable_cac == false) || 2780 (ni_pi->cac_configuration_required == false)) 2781 return 0; 2782 2783 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2784 if (ret) 2785 return ret; 2786 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2787 if (ret) 2788 return ret; 2789 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2790 if (ret) 2791 return ret; 2792 2793 return 0; 2794 } 2795 2796 static int si_enable_smc_cac(struct radeon_device *rdev, 2797 struct radeon_ps *radeon_new_state, 2798 bool enable) 2799 { 2800 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2801 struct si_power_info *si_pi = si_get_pi(rdev); 2802 PPSMC_Result smc_result; 2803 int ret = 0; 2804 2805 if (ni_pi->enable_cac) { 2806 if (enable) { 2807 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2808 if (ni_pi->support_cac_long_term_average) { 2809 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2810 if (smc_result != PPSMC_Result_OK) 2811 ni_pi->support_cac_long_term_average = false; 2812 } 2813 2814 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2815 if (smc_result != PPSMC_Result_OK) { 2816 ret = -EINVAL; 2817 ni_pi->cac_enabled = false; 2818 } else { 2819 ni_pi->cac_enabled = true; 2820 } 2821 2822 if (si_pi->enable_dte) { 2823 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2824 if (smc_result != PPSMC_Result_OK) 2825 ret = -EINVAL; 2826 } 2827 } 2828 } else if (ni_pi->cac_enabled) { 2829 if (si_pi->enable_dte) 2830 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2831 2832 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2833 2834 ni_pi->cac_enabled = false; 2835 2836 if (ni_pi->support_cac_long_term_average) 2837 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2838 } 2839 } 2840 return ret; 2841 } 2842 2843 static int si_init_smc_spll_table(struct radeon_device *rdev) 2844 { 2845 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2846 struct si_power_info *si_pi = si_get_pi(rdev); 2847 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2848 SISLANDS_SMC_SCLK_VALUE sclk_params; 2849 u32 fb_div, p_div; 2850 u32 clk_s, clk_v; 2851 u32 sclk = 0; 2852 int ret = 0; 2853 u32 tmp; 2854 int i; 2855 2856 if (si_pi->spll_table_start == 0) 2857 return -EINVAL; 2858 2859 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2860 if (spll_table == NULL) 2861 return -ENOMEM; 2862 2863 for (i = 0; i < 256; i++) { 2864 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2865 if (ret) 2866 break; 2867 2868 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2869 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2870 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2871 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2872 2873 fb_div &= ~0x00001FFF; 2874 fb_div >>= 1; 2875 clk_v >>= 6; 2876 2877 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2878 ret = -EINVAL; 2879 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2880 ret = -EINVAL; 2881 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2882 ret = -EINVAL; 2883 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2884 ret = -EINVAL; 2885 2886 if (ret) 2887 break; 2888 2889 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2890 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2891 spll_table->freq[i] = cpu_to_be32(tmp); 2892 2893 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2894 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2895 spll_table->ss[i] = cpu_to_be32(tmp); 2896 2897 sclk += 512; 2898 } 2899 2900 2901 if (!ret) 2902 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2903 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2904 si_pi->sram_end); 2905 2906 if (ret) 2907 ni_pi->enable_power_containment = false; 2908 2909 kfree(spll_table); 2910 2911 return ret; 2912 } 2913 2914 struct si_dpm_quirk { 2915 u32 chip_vendor; 2916 u32 chip_device; 2917 u32 subsys_vendor; 2918 u32 subsys_device; 2919 u32 max_sclk; 2920 u32 max_mclk; 2921 }; 2922 2923 /* cards with dpm stability problems */ 2924 static struct si_dpm_quirk si_dpm_quirk_list[] = { 2925 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */ 2926 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 }, 2927 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 }, 2928 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 }, 2929 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 }, 2930 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 }, 2931 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 }, 2932 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 }, 2933 { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 }, 2934 { 0, 0, 0, 0 }, 2935 }; 2936 2937 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2938 u16 vce_voltage) 2939 { 2940 u16 highest_leakage = 0; 2941 struct si_power_info *si_pi = si_get_pi(rdev); 2942 int i; 2943 2944 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2945 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2946 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2947 } 2948 2949 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2950 return highest_leakage; 2951 2952 return vce_voltage; 2953 } 2954 2955 static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2956 u32 evclk, u32 ecclk, u16 *voltage) 2957 { 2958 u32 i; 2959 int ret = -EINVAL; 2960 struct radeon_vce_clock_voltage_dependency_table *table = 2961 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2962 2963 if (((evclk == 0) && (ecclk == 0)) || 2964 (table && (table->count == 0))) { 2965 *voltage = 0; 2966 return 0; 2967 } 2968 2969 for (i = 0; i < table->count; i++) { 2970 if ((evclk <= table->entries[i].evclk) && 2971 (ecclk <= table->entries[i].ecclk)) { 2972 *voltage = table->entries[i].v; 2973 ret = 0; 2974 break; 2975 } 2976 } 2977 2978 /* if no match return the highest voltage */ 2979 if (ret) 2980 *voltage = table->entries[table->count - 1].v; 2981 2982 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2983 2984 return ret; 2985 } 2986 2987 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2988 struct radeon_ps *rps) 2989 { 2990 struct ni_ps *ps = ni_get_ps(rps); 2991 struct radeon_clock_and_voltage_limits *max_limits; 2992 bool disable_mclk_switching = false; 2993 bool disable_sclk_switching = false; 2994 u32 mclk, sclk; 2995 u16 vddc, vddci, min_vce_voltage = 0; 2996 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2997 u32 max_sclk = 0, max_mclk = 0; 2998 int i; 2999 struct si_dpm_quirk *p = si_dpm_quirk_list; 3000 3001 /* Apply dpm quirks */ 3002 while (p && p->chip_device != 0) { 3003 if (rdev->pdev->vendor == p->chip_vendor && 3004 rdev->pdev->device == p->chip_device && 3005 rdev->pdev->subsystem_vendor == p->subsys_vendor && 3006 rdev->pdev->subsystem_device == p->subsys_device) { 3007 max_sclk = p->max_sclk; 3008 max_mclk = p->max_mclk; 3009 break; 3010 } 3011 ++p; 3012 } 3013 /* limit mclk on all R7 370 parts for stability */ 3014 if (rdev->pdev->device == 0x6811 && 3015 rdev->pdev->revision == 0x81) 3016 max_mclk = 120000; 3017 /* limit sclk/mclk on Jet parts for stability */ 3018 if (rdev->pdev->device == 0x6665 && 3019 rdev->pdev->revision == 0xc3) { 3020 max_sclk = 75000; 3021 max_mclk = 80000; 3022 } 3023 3024 if (rps->vce_active) { 3025 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 3026 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 3027 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 3028 &min_vce_voltage); 3029 } else { 3030 rps->evclk = 0; 3031 rps->ecclk = 0; 3032 } 3033 3034 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 3035 ni_dpm_vblank_too_short(rdev)) 3036 disable_mclk_switching = true; 3037 3038 if (rps->vclk || rps->dclk) { 3039 disable_mclk_switching = true; 3040 disable_sclk_switching = true; 3041 } 3042 3043 if (rdev->pm.dpm.ac_power) 3044 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3045 else 3046 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3047 3048 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3049 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3050 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3051 } 3052 if (rdev->pm.dpm.ac_power == false) { 3053 for (i = 0; i < ps->performance_level_count; i++) { 3054 if (ps->performance_levels[i].mclk > max_limits->mclk) 3055 ps->performance_levels[i].mclk = max_limits->mclk; 3056 if (ps->performance_levels[i].sclk > max_limits->sclk) 3057 ps->performance_levels[i].sclk = max_limits->sclk; 3058 if (ps->performance_levels[i].vddc > max_limits->vddc) 3059 ps->performance_levels[i].vddc = max_limits->vddc; 3060 if (ps->performance_levels[i].vddci > max_limits->vddci) 3061 ps->performance_levels[i].vddci = max_limits->vddci; 3062 } 3063 } 3064 3065 /* limit clocks to max supported clocks based on voltage dependency tables */ 3066 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3067 &max_sclk_vddc); 3068 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3069 &max_mclk_vddci); 3070 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3071 &max_mclk_vddc); 3072 3073 for (i = 0; i < ps->performance_level_count; i++) { 3074 if (max_sclk_vddc) { 3075 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3076 ps->performance_levels[i].sclk = max_sclk_vddc; 3077 } 3078 if (max_mclk_vddci) { 3079 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3080 ps->performance_levels[i].mclk = max_mclk_vddci; 3081 } 3082 if (max_mclk_vddc) { 3083 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3084 ps->performance_levels[i].mclk = max_mclk_vddc; 3085 } 3086 if (max_mclk) { 3087 if (ps->performance_levels[i].mclk > max_mclk) 3088 ps->performance_levels[i].mclk = max_mclk; 3089 } 3090 if (max_sclk) { 3091 if (ps->performance_levels[i].sclk > max_sclk) 3092 ps->performance_levels[i].sclk = max_sclk; 3093 } 3094 } 3095 3096 /* XXX validate the min clocks required for display */ 3097 3098 if (disable_mclk_switching) { 3099 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3100 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3101 } else { 3102 mclk = ps->performance_levels[0].mclk; 3103 vddci = ps->performance_levels[0].vddci; 3104 } 3105 3106 if (disable_sclk_switching) { 3107 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3108 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3109 } else { 3110 sclk = ps->performance_levels[0].sclk; 3111 vddc = ps->performance_levels[0].vddc; 3112 } 3113 3114 if (rps->vce_active) { 3115 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3116 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3117 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3118 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3119 } 3120 3121 /* adjusted low state */ 3122 ps->performance_levels[0].sclk = sclk; 3123 ps->performance_levels[0].mclk = mclk; 3124 ps->performance_levels[0].vddc = vddc; 3125 ps->performance_levels[0].vddci = vddci; 3126 3127 if (disable_sclk_switching) { 3128 sclk = ps->performance_levels[0].sclk; 3129 for (i = 1; i < ps->performance_level_count; i++) { 3130 if (sclk < ps->performance_levels[i].sclk) 3131 sclk = ps->performance_levels[i].sclk; 3132 } 3133 for (i = 0; i < ps->performance_level_count; i++) { 3134 ps->performance_levels[i].sclk = sclk; 3135 ps->performance_levels[i].vddc = vddc; 3136 } 3137 } else { 3138 for (i = 1; i < ps->performance_level_count; i++) { 3139 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3140 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3141 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3142 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3143 } 3144 } 3145 3146 if (disable_mclk_switching) { 3147 mclk = ps->performance_levels[0].mclk; 3148 for (i = 1; i < ps->performance_level_count; i++) { 3149 if (mclk < ps->performance_levels[i].mclk) 3150 mclk = ps->performance_levels[i].mclk; 3151 } 3152 for (i = 0; i < ps->performance_level_count; i++) { 3153 ps->performance_levels[i].mclk = mclk; 3154 ps->performance_levels[i].vddci = vddci; 3155 } 3156 } else { 3157 for (i = 1; i < ps->performance_level_count; i++) { 3158 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3159 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3160 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3161 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3162 } 3163 } 3164 3165 for (i = 0; i < ps->performance_level_count; i++) 3166 btc_adjust_clock_combinations(rdev, max_limits, 3167 &ps->performance_levels[i]); 3168 3169 for (i = 0; i < ps->performance_level_count; i++) { 3170 if (ps->performance_levels[i].vddc < min_vce_voltage) 3171 ps->performance_levels[i].vddc = min_vce_voltage; 3172 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3173 ps->performance_levels[i].sclk, 3174 max_limits->vddc, &ps->performance_levels[i].vddc); 3175 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3176 ps->performance_levels[i].mclk, 3177 max_limits->vddci, &ps->performance_levels[i].vddci); 3178 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3179 ps->performance_levels[i].mclk, 3180 max_limits->vddc, &ps->performance_levels[i].vddc); 3181 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3182 rdev->clock.current_dispclk, 3183 max_limits->vddc, &ps->performance_levels[i].vddc); 3184 } 3185 3186 for (i = 0; i < ps->performance_level_count; i++) { 3187 btc_apply_voltage_delta_rules(rdev, 3188 max_limits->vddc, max_limits->vddci, 3189 &ps->performance_levels[i].vddc, 3190 &ps->performance_levels[i].vddci); 3191 } 3192 3193 ps->dc_compatible = true; 3194 for (i = 0; i < ps->performance_level_count; i++) { 3195 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3196 ps->dc_compatible = false; 3197 } 3198 } 3199 3200 #if 0 3201 static int si_read_smc_soft_register(struct radeon_device *rdev, 3202 u16 reg_offset, u32 *value) 3203 { 3204 struct si_power_info *si_pi = si_get_pi(rdev); 3205 3206 return si_read_smc_sram_dword(rdev, 3207 si_pi->soft_regs_start + reg_offset, value, 3208 si_pi->sram_end); 3209 } 3210 #endif 3211 3212 static int si_write_smc_soft_register(struct radeon_device *rdev, 3213 u16 reg_offset, u32 value) 3214 { 3215 struct si_power_info *si_pi = si_get_pi(rdev); 3216 3217 return si_write_smc_sram_dword(rdev, 3218 si_pi->soft_regs_start + reg_offset, 3219 value, si_pi->sram_end); 3220 } 3221 3222 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3223 { 3224 bool ret = false; 3225 u32 tmp, width, row, column, bank, density; 3226 bool is_memory_gddr5, is_special; 3227 3228 tmp = RREG32(MC_SEQ_MISC0); 3229 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3230 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3231 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3232 3233 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3234 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3235 3236 tmp = RREG32(MC_ARB_RAMCFG); 3237 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3238 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3239 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3240 3241 density = (1 << (row + column - 20 + bank)) * width; 3242 3243 if ((rdev->pdev->device == 0x6819) && 3244 is_memory_gddr5 && is_special && (density == 0x400)) 3245 ret = true; 3246 3247 return ret; 3248 } 3249 3250 static void si_get_leakage_vddc(struct radeon_device *rdev) 3251 { 3252 struct si_power_info *si_pi = si_get_pi(rdev); 3253 u16 vddc, count = 0; 3254 int i, ret; 3255 3256 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3257 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3258 3259 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3260 si_pi->leakage_voltage.entries[count].voltage = vddc; 3261 si_pi->leakage_voltage.entries[count].leakage_index = 3262 SISLANDS_LEAKAGE_INDEX0 + i; 3263 count++; 3264 } 3265 } 3266 si_pi->leakage_voltage.count = count; 3267 } 3268 3269 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3270 u32 index, u16 *leakage_voltage) 3271 { 3272 struct si_power_info *si_pi = si_get_pi(rdev); 3273 int i; 3274 3275 if (leakage_voltage == NULL) 3276 return -EINVAL; 3277 3278 if ((index & 0xff00) != 0xff00) 3279 return -EINVAL; 3280 3281 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3282 return -EINVAL; 3283 3284 if (index < SISLANDS_LEAKAGE_INDEX0) 3285 return -EINVAL; 3286 3287 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3288 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3289 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3290 return 0; 3291 } 3292 } 3293 return -EAGAIN; 3294 } 3295 3296 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3297 { 3298 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3299 bool want_thermal_protection; 3300 enum radeon_dpm_event_src dpm_event_src; 3301 3302 switch (sources) { 3303 case 0: 3304 default: 3305 want_thermal_protection = false; 3306 break; 3307 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3308 want_thermal_protection = true; 3309 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3310 break; 3311 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3312 want_thermal_protection = true; 3313 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3314 break; 3315 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3316 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3317 want_thermal_protection = true; 3318 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3319 break; 3320 } 3321 3322 if (want_thermal_protection) { 3323 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3324 if (pi->thermal_protection) 3325 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3326 } else { 3327 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3328 } 3329 } 3330 3331 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3332 enum radeon_dpm_auto_throttle_src source, 3333 bool enable) 3334 { 3335 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3336 3337 if (enable) { 3338 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3339 pi->active_auto_throttle_sources |= 1 << source; 3340 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3341 } 3342 } else { 3343 if (pi->active_auto_throttle_sources & (1 << source)) { 3344 pi->active_auto_throttle_sources &= ~(1 << source); 3345 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3346 } 3347 } 3348 } 3349 3350 static void si_start_dpm(struct radeon_device *rdev) 3351 { 3352 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3353 } 3354 3355 static void si_stop_dpm(struct radeon_device *rdev) 3356 { 3357 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3358 } 3359 3360 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3361 { 3362 if (enable) 3363 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3364 else 3365 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3366 3367 } 3368 3369 #if 0 3370 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3371 u32 thermal_level) 3372 { 3373 PPSMC_Result ret; 3374 3375 if (thermal_level == 0) { 3376 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3377 if (ret == PPSMC_Result_OK) 3378 return 0; 3379 else 3380 return -EINVAL; 3381 } 3382 return 0; 3383 } 3384 3385 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3386 { 3387 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3388 } 3389 #endif 3390 3391 #if 0 3392 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3393 { 3394 if (ac_power) 3395 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3396 0 : -EINVAL; 3397 3398 return 0; 3399 } 3400 #endif 3401 3402 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3403 PPSMC_Msg msg, u32 parameter) 3404 { 3405 WREG32(SMC_SCRATCH0, parameter); 3406 return si_send_msg_to_smc(rdev, msg); 3407 } 3408 3409 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3410 { 3411 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3412 return -EINVAL; 3413 3414 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3415 0 : -EINVAL; 3416 } 3417 3418 int si_dpm_force_performance_level(struct radeon_device *rdev, 3419 enum radeon_dpm_forced_level level) 3420 { 3421 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3422 struct ni_ps *ps = ni_get_ps(rps); 3423 u32 levels = ps->performance_level_count; 3424 3425 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3426 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3427 return -EINVAL; 3428 3429 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3430 return -EINVAL; 3431 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3432 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3433 return -EINVAL; 3434 3435 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3436 return -EINVAL; 3437 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3438 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3439 return -EINVAL; 3440 3441 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3442 return -EINVAL; 3443 } 3444 3445 rdev->pm.dpm.forced_level = level; 3446 3447 return 0; 3448 } 3449 3450 #if 0 3451 static int si_set_boot_state(struct radeon_device *rdev) 3452 { 3453 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3454 0 : -EINVAL; 3455 } 3456 #endif 3457 3458 static int si_set_sw_state(struct radeon_device *rdev) 3459 { 3460 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3461 0 : -EINVAL; 3462 } 3463 3464 static int si_halt_smc(struct radeon_device *rdev) 3465 { 3466 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3467 return -EINVAL; 3468 3469 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3470 0 : -EINVAL; 3471 } 3472 3473 static int si_resume_smc(struct radeon_device *rdev) 3474 { 3475 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3476 return -EINVAL; 3477 3478 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3479 0 : -EINVAL; 3480 } 3481 3482 static void si_dpm_start_smc(struct radeon_device *rdev) 3483 { 3484 si_program_jump_on_start(rdev); 3485 si_start_smc(rdev); 3486 si_start_smc_clock(rdev); 3487 } 3488 3489 static void si_dpm_stop_smc(struct radeon_device *rdev) 3490 { 3491 si_reset_smc(rdev); 3492 si_stop_smc_clock(rdev); 3493 } 3494 3495 static int si_process_firmware_header(struct radeon_device *rdev) 3496 { 3497 struct si_power_info *si_pi = si_get_pi(rdev); 3498 u32 tmp; 3499 int ret; 3500 3501 ret = si_read_smc_sram_dword(rdev, 3502 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3503 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3504 &tmp, si_pi->sram_end); 3505 if (ret) 3506 return ret; 3507 3508 si_pi->state_table_start = tmp; 3509 3510 ret = si_read_smc_sram_dword(rdev, 3511 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3512 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3513 &tmp, si_pi->sram_end); 3514 if (ret) 3515 return ret; 3516 3517 si_pi->soft_regs_start = tmp; 3518 3519 ret = si_read_smc_sram_dword(rdev, 3520 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3521 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3522 &tmp, si_pi->sram_end); 3523 if (ret) 3524 return ret; 3525 3526 si_pi->mc_reg_table_start = tmp; 3527 3528 ret = si_read_smc_sram_dword(rdev, 3529 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3530 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3531 &tmp, si_pi->sram_end); 3532 if (ret) 3533 return ret; 3534 3535 si_pi->fan_table_start = tmp; 3536 3537 ret = si_read_smc_sram_dword(rdev, 3538 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3539 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3540 &tmp, si_pi->sram_end); 3541 if (ret) 3542 return ret; 3543 3544 si_pi->arb_table_start = tmp; 3545 3546 ret = si_read_smc_sram_dword(rdev, 3547 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3548 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3549 &tmp, si_pi->sram_end); 3550 if (ret) 3551 return ret; 3552 3553 si_pi->cac_table_start = tmp; 3554 3555 ret = si_read_smc_sram_dword(rdev, 3556 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3557 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3558 &tmp, si_pi->sram_end); 3559 if (ret) 3560 return ret; 3561 3562 si_pi->dte_table_start = tmp; 3563 3564 ret = si_read_smc_sram_dword(rdev, 3565 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3566 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3567 &tmp, si_pi->sram_end); 3568 if (ret) 3569 return ret; 3570 3571 si_pi->spll_table_start = tmp; 3572 3573 ret = si_read_smc_sram_dword(rdev, 3574 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3575 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3576 &tmp, si_pi->sram_end); 3577 if (ret) 3578 return ret; 3579 3580 si_pi->papm_cfg_table_start = tmp; 3581 3582 return ret; 3583 } 3584 3585 static void si_read_clock_registers(struct radeon_device *rdev) 3586 { 3587 struct si_power_info *si_pi = si_get_pi(rdev); 3588 3589 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3590 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3591 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3592 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3593 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3594 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3595 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3596 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3597 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3598 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3599 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3600 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3601 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3602 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3603 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3604 } 3605 3606 static void si_enable_thermal_protection(struct radeon_device *rdev, 3607 bool enable) 3608 { 3609 if (enable) 3610 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3611 else 3612 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3613 } 3614 3615 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3616 { 3617 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3618 } 3619 3620 #if 0 3621 static int si_enter_ulp_state(struct radeon_device *rdev) 3622 { 3623 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3624 3625 udelay(25000); 3626 3627 return 0; 3628 } 3629 3630 static int si_exit_ulp_state(struct radeon_device *rdev) 3631 { 3632 int i; 3633 3634 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3635 3636 udelay(7000); 3637 3638 for (i = 0; i < rdev->usec_timeout; i++) { 3639 if (RREG32(SMC_RESP_0) == 1) 3640 break; 3641 udelay(1000); 3642 } 3643 3644 return 0; 3645 } 3646 #endif 3647 3648 static int si_notify_smc_display_change(struct radeon_device *rdev, 3649 bool has_display) 3650 { 3651 PPSMC_Msg msg = has_display ? 3652 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3653 3654 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3655 0 : -EINVAL; 3656 } 3657 3658 static void si_program_response_times(struct radeon_device *rdev) 3659 { 3660 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3661 u32 vddc_dly, acpi_dly, vbi_dly; 3662 u32 reference_clock; 3663 3664 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3665 3666 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3667 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3668 3669 if (voltage_response_time == 0) 3670 voltage_response_time = 1000; 3671 3672 acpi_delay_time = 15000; 3673 vbi_time_out = 100000; 3674 3675 reference_clock = radeon_get_xclk(rdev); 3676 3677 vddc_dly = (voltage_response_time * reference_clock) / 100; 3678 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3679 vbi_dly = (vbi_time_out * reference_clock) / 100; 3680 3681 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3682 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3683 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3684 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3685 } 3686 3687 static void si_program_ds_registers(struct radeon_device *rdev) 3688 { 3689 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3690 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3691 3692 if (eg_pi->sclk_deep_sleep) { 3693 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3694 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3695 ~AUTOSCALE_ON_SS_CLEAR); 3696 } 3697 } 3698 3699 static void si_program_display_gap(struct radeon_device *rdev) 3700 { 3701 u32 tmp, pipe; 3702 int i; 3703 3704 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3705 if (rdev->pm.dpm.new_active_crtc_count > 0) 3706 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3707 else 3708 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3709 3710 if (rdev->pm.dpm.new_active_crtc_count > 1) 3711 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3712 else 3713 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3714 3715 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3716 3717 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3718 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3719 3720 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3721 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3722 /* find the first active crtc */ 3723 for (i = 0; i < rdev->num_crtc; i++) { 3724 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3725 break; 3726 } 3727 if (i == rdev->num_crtc) 3728 pipe = 0; 3729 else 3730 pipe = i; 3731 3732 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3733 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3734 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3735 } 3736 3737 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3738 * This can be a problem on PowerXpress systems or if you want to use the card 3739 * for offscreen rendering or compute if there are no crtcs enabled. 3740 */ 3741 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3742 } 3743 3744 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3745 { 3746 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3747 3748 if (enable) { 3749 if (pi->sclk_ss) 3750 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3751 } else { 3752 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3753 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3754 } 3755 } 3756 3757 static void si_setup_bsp(struct radeon_device *rdev) 3758 { 3759 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3760 u32 xclk = radeon_get_xclk(rdev); 3761 3762 r600_calculate_u_and_p(pi->asi, 3763 xclk, 3764 16, 3765 &pi->bsp, 3766 &pi->bsu); 3767 3768 r600_calculate_u_and_p(pi->pasi, 3769 xclk, 3770 16, 3771 &pi->pbsp, 3772 &pi->pbsu); 3773 3774 3775 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3776 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3777 3778 WREG32(CG_BSP, pi->dsp); 3779 } 3780 3781 static void si_program_git(struct radeon_device *rdev) 3782 { 3783 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3784 } 3785 3786 static void si_program_tp(struct radeon_device *rdev) 3787 { 3788 int i; 3789 enum r600_td td = R600_TD_DFLT; 3790 3791 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3792 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3793 3794 if (td == R600_TD_AUTO) 3795 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3796 else 3797 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3798 3799 if (td == R600_TD_UP) 3800 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3801 3802 if (td == R600_TD_DOWN) 3803 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3804 } 3805 3806 static void si_program_tpp(struct radeon_device *rdev) 3807 { 3808 WREG32(CG_TPC, R600_TPC_DFLT); 3809 } 3810 3811 static void si_program_sstp(struct radeon_device *rdev) 3812 { 3813 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3814 } 3815 3816 static void si_enable_display_gap(struct radeon_device *rdev) 3817 { 3818 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3819 3820 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3821 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3822 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3823 3824 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3825 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3826 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3827 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3828 } 3829 3830 static void si_program_vc(struct radeon_device *rdev) 3831 { 3832 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3833 3834 WREG32(CG_FTV, pi->vrc); 3835 } 3836 3837 static void si_clear_vc(struct radeon_device *rdev) 3838 { 3839 WREG32(CG_FTV, 0); 3840 } 3841 3842 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3843 { 3844 u8 mc_para_index; 3845 3846 if (memory_clock < 10000) 3847 mc_para_index = 0; 3848 else if (memory_clock >= 80000) 3849 mc_para_index = 0x0f; 3850 else 3851 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3852 return mc_para_index; 3853 } 3854 3855 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3856 { 3857 u8 mc_para_index; 3858 3859 if (strobe_mode) { 3860 if (memory_clock < 12500) 3861 mc_para_index = 0x00; 3862 else if (memory_clock > 47500) 3863 mc_para_index = 0x0f; 3864 else 3865 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3866 } else { 3867 if (memory_clock < 65000) 3868 mc_para_index = 0x00; 3869 else if (memory_clock > 135000) 3870 mc_para_index = 0x0f; 3871 else 3872 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3873 } 3874 return mc_para_index; 3875 } 3876 3877 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3878 { 3879 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3880 bool strobe_mode = false; 3881 u8 result = 0; 3882 3883 if (mclk <= pi->mclk_strobe_mode_threshold) 3884 strobe_mode = true; 3885 3886 if (pi->mem_gddr5) 3887 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3888 else 3889 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3890 3891 if (strobe_mode) 3892 result |= SISLANDS_SMC_STROBE_ENABLE; 3893 3894 return result; 3895 } 3896 3897 static int si_upload_firmware(struct radeon_device *rdev) 3898 { 3899 struct si_power_info *si_pi = si_get_pi(rdev); 3900 int ret; 3901 3902 si_reset_smc(rdev); 3903 si_stop_smc_clock(rdev); 3904 3905 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3906 3907 return ret; 3908 } 3909 3910 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3911 const struct atom_voltage_table *table, 3912 const struct radeon_phase_shedding_limits_table *limits) 3913 { 3914 u32 data, num_bits, num_levels; 3915 3916 if ((table == NULL) || (limits == NULL)) 3917 return false; 3918 3919 data = table->mask_low; 3920 3921 num_bits = hweight32(data); 3922 3923 if (num_bits == 0) 3924 return false; 3925 3926 num_levels = (1 << num_bits); 3927 3928 if (table->count != num_levels) 3929 return false; 3930 3931 if (limits->count != (num_levels - 1)) 3932 return false; 3933 3934 return true; 3935 } 3936 3937 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3938 u32 max_voltage_steps, 3939 struct atom_voltage_table *voltage_table) 3940 { 3941 unsigned int i, diff; 3942 3943 if (voltage_table->count <= max_voltage_steps) 3944 return; 3945 3946 diff = voltage_table->count - max_voltage_steps; 3947 3948 for (i= 0; i < max_voltage_steps; i++) 3949 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3950 3951 voltage_table->count = max_voltage_steps; 3952 } 3953 3954 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3955 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3956 struct atom_voltage_table *voltage_table) 3957 { 3958 u32 i; 3959 3960 if (voltage_dependency_table == NULL) 3961 return -EINVAL; 3962 3963 voltage_table->mask_low = 0; 3964 voltage_table->phase_delay = 0; 3965 3966 voltage_table->count = voltage_dependency_table->count; 3967 for (i = 0; i < voltage_table->count; i++) { 3968 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3969 voltage_table->entries[i].smio_low = 0; 3970 } 3971 3972 return 0; 3973 } 3974 3975 static int si_construct_voltage_tables(struct radeon_device *rdev) 3976 { 3977 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3978 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3979 struct si_power_info *si_pi = si_get_pi(rdev); 3980 int ret; 3981 3982 if (pi->voltage_control) { 3983 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3984 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3985 if (ret) 3986 return ret; 3987 3988 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3989 si_trim_voltage_table_to_fit_state_table(rdev, 3990 SISLANDS_MAX_NO_VREG_STEPS, 3991 &eg_pi->vddc_voltage_table); 3992 } else if (si_pi->voltage_control_svi2) { 3993 ret = si_get_svi2_voltage_table(rdev, 3994 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3995 &eg_pi->vddc_voltage_table); 3996 if (ret) 3997 return ret; 3998 } else { 3999 return -EINVAL; 4000 } 4001 4002 if (eg_pi->vddci_control) { 4003 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 4004 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 4005 if (ret) 4006 return ret; 4007 4008 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4009 si_trim_voltage_table_to_fit_state_table(rdev, 4010 SISLANDS_MAX_NO_VREG_STEPS, 4011 &eg_pi->vddci_voltage_table); 4012 } 4013 if (si_pi->vddci_control_svi2) { 4014 ret = si_get_svi2_voltage_table(rdev, 4015 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 4016 &eg_pi->vddci_voltage_table); 4017 if (ret) 4018 return ret; 4019 } 4020 4021 if (pi->mvdd_control) { 4022 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 4023 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4024 4025 if (ret) { 4026 pi->mvdd_control = false; 4027 return ret; 4028 } 4029 4030 if (si_pi->mvdd_voltage_table.count == 0) { 4031 pi->mvdd_control = false; 4032 return -EINVAL; 4033 } 4034 4035 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4036 si_trim_voltage_table_to_fit_state_table(rdev, 4037 SISLANDS_MAX_NO_VREG_STEPS, 4038 &si_pi->mvdd_voltage_table); 4039 } 4040 4041 if (si_pi->vddc_phase_shed_control) { 4042 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4043 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4044 if (ret) 4045 si_pi->vddc_phase_shed_control = false; 4046 4047 if ((si_pi->vddc_phase_shed_table.count == 0) || 4048 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4049 si_pi->vddc_phase_shed_control = false; 4050 } 4051 4052 return 0; 4053 } 4054 4055 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 4056 const struct atom_voltage_table *voltage_table, 4057 SISLANDS_SMC_STATETABLE *table) 4058 { 4059 unsigned int i; 4060 4061 for (i = 0; i < voltage_table->count; i++) 4062 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4063 } 4064 4065 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 4066 SISLANDS_SMC_STATETABLE *table) 4067 { 4068 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4069 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4070 struct si_power_info *si_pi = si_get_pi(rdev); 4071 u8 i; 4072 4073 if (si_pi->voltage_control_svi2) { 4074 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4075 si_pi->svc_gpio_id); 4076 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4077 si_pi->svd_gpio_id); 4078 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4079 2); 4080 } else { 4081 if (eg_pi->vddc_voltage_table.count) { 4082 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4083 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4084 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4085 4086 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4087 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4088 table->maxVDDCIndexInPPTable = i; 4089 break; 4090 } 4091 } 4092 } 4093 4094 if (eg_pi->vddci_voltage_table.count) { 4095 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4096 4097 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4098 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4099 } 4100 4101 4102 if (si_pi->mvdd_voltage_table.count) { 4103 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4104 4105 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4106 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4107 } 4108 4109 if (si_pi->vddc_phase_shed_control) { 4110 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4111 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4112 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4113 4114 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4115 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4116 4117 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4118 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4119 } else { 4120 si_pi->vddc_phase_shed_control = false; 4121 } 4122 } 4123 } 4124 4125 return 0; 4126 } 4127 4128 static int si_populate_voltage_value(struct radeon_device *rdev, 4129 const struct atom_voltage_table *table, 4130 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4131 { 4132 unsigned int i; 4133 4134 for (i = 0; i < table->count; i++) { 4135 if (value <= table->entries[i].value) { 4136 voltage->index = (u8)i; 4137 voltage->value = cpu_to_be16(table->entries[i].value); 4138 break; 4139 } 4140 } 4141 4142 if (i >= table->count) 4143 return -EINVAL; 4144 4145 return 0; 4146 } 4147 4148 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4149 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4150 { 4151 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4152 struct si_power_info *si_pi = si_get_pi(rdev); 4153 4154 if (pi->mvdd_control) { 4155 if (mclk <= pi->mvdd_split_frequency) 4156 voltage->index = 0; 4157 else 4158 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4159 4160 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4161 } 4162 return 0; 4163 } 4164 4165 static int si_get_std_voltage_value(struct radeon_device *rdev, 4166 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4167 u16 *std_voltage) 4168 { 4169 u16 v_index; 4170 bool voltage_found = false; 4171 *std_voltage = be16_to_cpu(voltage->value); 4172 4173 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4174 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4175 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4176 return -EINVAL; 4177 4178 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4179 if (be16_to_cpu(voltage->value) == 4180 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4181 voltage_found = true; 4182 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4183 *std_voltage = 4184 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4185 else 4186 *std_voltage = 4187 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4188 break; 4189 } 4190 } 4191 4192 if (!voltage_found) { 4193 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4194 if (be16_to_cpu(voltage->value) <= 4195 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4196 voltage_found = true; 4197 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4198 *std_voltage = 4199 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4200 else 4201 *std_voltage = 4202 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4203 break; 4204 } 4205 } 4206 } 4207 } else { 4208 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4209 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4210 } 4211 } 4212 4213 return 0; 4214 } 4215 4216 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4217 u16 value, u8 index, 4218 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4219 { 4220 voltage->index = index; 4221 voltage->value = cpu_to_be16(value); 4222 4223 return 0; 4224 } 4225 4226 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4227 const struct radeon_phase_shedding_limits_table *limits, 4228 u16 voltage, u32 sclk, u32 mclk, 4229 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4230 { 4231 unsigned int i; 4232 4233 for (i = 0; i < limits->count; i++) { 4234 if ((voltage <= limits->entries[i].voltage) && 4235 (sclk <= limits->entries[i].sclk) && 4236 (mclk <= limits->entries[i].mclk)) 4237 break; 4238 } 4239 4240 smc_voltage->phase_settings = (u8)i; 4241 4242 return 0; 4243 } 4244 4245 static int si_init_arb_table_index(struct radeon_device *rdev) 4246 { 4247 struct si_power_info *si_pi = si_get_pi(rdev); 4248 u32 tmp; 4249 int ret; 4250 4251 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4252 if (ret) 4253 return ret; 4254 4255 tmp &= 0x00FFFFFF; 4256 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4257 4258 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4259 } 4260 4261 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4262 { 4263 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4264 } 4265 4266 static int si_reset_to_default(struct radeon_device *rdev) 4267 { 4268 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4269 0 : -EINVAL; 4270 } 4271 4272 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4273 { 4274 struct si_power_info *si_pi = si_get_pi(rdev); 4275 u32 tmp; 4276 int ret; 4277 4278 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4279 &tmp, si_pi->sram_end); 4280 if (ret) 4281 return ret; 4282 4283 tmp = (tmp >> 24) & 0xff; 4284 4285 if (tmp == MC_CG_ARB_FREQ_F0) 4286 return 0; 4287 4288 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4289 } 4290 4291 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4292 u32 engine_clock) 4293 { 4294 u32 dram_rows; 4295 u32 dram_refresh_rate; 4296 u32 mc_arb_rfsh_rate; 4297 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4298 4299 if (tmp >= 4) 4300 dram_rows = 16384; 4301 else 4302 dram_rows = 1 << (tmp + 10); 4303 4304 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4305 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4306 4307 return mc_arb_rfsh_rate; 4308 } 4309 4310 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4311 struct rv7xx_pl *pl, 4312 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4313 { 4314 u32 dram_timing; 4315 u32 dram_timing2; 4316 u32 burst_time; 4317 4318 arb_regs->mc_arb_rfsh_rate = 4319 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4320 4321 radeon_atom_set_engine_dram_timings(rdev, 4322 pl->sclk, 4323 pl->mclk); 4324 4325 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4326 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4327 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4328 4329 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4330 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4331 arb_regs->mc_arb_burst_time = (u8)burst_time; 4332 4333 return 0; 4334 } 4335 4336 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4337 struct radeon_ps *radeon_state, 4338 unsigned int first_arb_set) 4339 { 4340 struct si_power_info *si_pi = si_get_pi(rdev); 4341 struct ni_ps *state = ni_get_ps(radeon_state); 4342 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4343 int i, ret = 0; 4344 4345 for (i = 0; i < state->performance_level_count; i++) { 4346 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4347 if (ret) 4348 break; 4349 ret = si_copy_bytes_to_smc(rdev, 4350 si_pi->arb_table_start + 4351 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4352 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4353 (u8 *)&arb_regs, 4354 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4355 si_pi->sram_end); 4356 if (ret) 4357 break; 4358 } 4359 4360 return ret; 4361 } 4362 4363 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4364 struct radeon_ps *radeon_new_state) 4365 { 4366 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4367 SISLANDS_DRIVER_STATE_ARB_INDEX); 4368 } 4369 4370 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4371 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4372 { 4373 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4374 struct si_power_info *si_pi = si_get_pi(rdev); 4375 4376 if (pi->mvdd_control) 4377 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4378 si_pi->mvdd_bootup_value, voltage); 4379 4380 return 0; 4381 } 4382 4383 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4384 struct radeon_ps *radeon_initial_state, 4385 SISLANDS_SMC_STATETABLE *table) 4386 { 4387 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4388 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4389 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4390 struct si_power_info *si_pi = si_get_pi(rdev); 4391 u32 reg; 4392 int ret; 4393 4394 table->initialState.levels[0].mclk.vDLL_CNTL = 4395 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4396 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4397 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4398 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4399 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4400 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4401 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4402 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4403 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4404 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4405 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4406 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4407 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4408 table->initialState.levels[0].mclk.vMPLL_SS = 4409 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4410 table->initialState.levels[0].mclk.vMPLL_SS2 = 4411 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4412 4413 table->initialState.levels[0].mclk.mclk_value = 4414 cpu_to_be32(initial_state->performance_levels[0].mclk); 4415 4416 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4417 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4418 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4419 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4420 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4421 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4422 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4423 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4424 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4425 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4426 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4427 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4428 4429 table->initialState.levels[0].sclk.sclk_value = 4430 cpu_to_be32(initial_state->performance_levels[0].sclk); 4431 4432 table->initialState.levels[0].arbRefreshState = 4433 SISLANDS_INITIAL_STATE_ARB_INDEX; 4434 4435 table->initialState.levels[0].ACIndex = 0; 4436 4437 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4438 initial_state->performance_levels[0].vddc, 4439 &table->initialState.levels[0].vddc); 4440 4441 if (!ret) { 4442 u16 std_vddc; 4443 4444 ret = si_get_std_voltage_value(rdev, 4445 &table->initialState.levels[0].vddc, 4446 &std_vddc); 4447 if (!ret) 4448 si_populate_std_voltage_value(rdev, std_vddc, 4449 table->initialState.levels[0].vddc.index, 4450 &table->initialState.levels[0].std_vddc); 4451 } 4452 4453 if (eg_pi->vddci_control) 4454 si_populate_voltage_value(rdev, 4455 &eg_pi->vddci_voltage_table, 4456 initial_state->performance_levels[0].vddci, 4457 &table->initialState.levels[0].vddci); 4458 4459 if (si_pi->vddc_phase_shed_control) 4460 si_populate_phase_shedding_value(rdev, 4461 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4462 initial_state->performance_levels[0].vddc, 4463 initial_state->performance_levels[0].sclk, 4464 initial_state->performance_levels[0].mclk, 4465 &table->initialState.levels[0].vddc); 4466 4467 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4468 4469 reg = CG_R(0xffff) | CG_L(0); 4470 table->initialState.levels[0].aT = cpu_to_be32(reg); 4471 4472 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4473 4474 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4475 4476 if (pi->mem_gddr5) { 4477 table->initialState.levels[0].strobeMode = 4478 si_get_strobe_mode_settings(rdev, 4479 initial_state->performance_levels[0].mclk); 4480 4481 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4482 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4483 else 4484 table->initialState.levels[0].mcFlags = 0; 4485 } 4486 4487 table->initialState.levelCount = 1; 4488 4489 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4490 4491 table->initialState.levels[0].dpm2.MaxPS = 0; 4492 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4493 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4494 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4495 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4496 4497 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4498 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4499 4500 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4501 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4502 4503 return 0; 4504 } 4505 4506 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4507 SISLANDS_SMC_STATETABLE *table) 4508 { 4509 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4510 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4511 struct si_power_info *si_pi = si_get_pi(rdev); 4512 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4513 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4514 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4515 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4516 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4517 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4518 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4519 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4520 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4521 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4522 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4523 u32 reg; 4524 int ret; 4525 4526 table->ACPIState = table->initialState; 4527 4528 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4529 4530 if (pi->acpi_vddc) { 4531 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4532 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4533 if (!ret) { 4534 u16 std_vddc; 4535 4536 ret = si_get_std_voltage_value(rdev, 4537 &table->ACPIState.levels[0].vddc, &std_vddc); 4538 if (!ret) 4539 si_populate_std_voltage_value(rdev, std_vddc, 4540 table->ACPIState.levels[0].vddc.index, 4541 &table->ACPIState.levels[0].std_vddc); 4542 } 4543 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4544 4545 if (si_pi->vddc_phase_shed_control) { 4546 si_populate_phase_shedding_value(rdev, 4547 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4548 pi->acpi_vddc, 4549 0, 4550 0, 4551 &table->ACPIState.levels[0].vddc); 4552 } 4553 } else { 4554 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4555 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4556 if (!ret) { 4557 u16 std_vddc; 4558 4559 ret = si_get_std_voltage_value(rdev, 4560 &table->ACPIState.levels[0].vddc, &std_vddc); 4561 4562 if (!ret) 4563 si_populate_std_voltage_value(rdev, std_vddc, 4564 table->ACPIState.levels[0].vddc.index, 4565 &table->ACPIState.levels[0].std_vddc); 4566 } 4567 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4568 si_pi->sys_pcie_mask, 4569 si_pi->boot_pcie_gen, 4570 RADEON_PCIE_GEN1); 4571 4572 if (si_pi->vddc_phase_shed_control) 4573 si_populate_phase_shedding_value(rdev, 4574 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4575 pi->min_vddc_in_table, 4576 0, 4577 0, 4578 &table->ACPIState.levels[0].vddc); 4579 } 4580 4581 if (pi->acpi_vddc) { 4582 if (eg_pi->acpi_vddci) 4583 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4584 eg_pi->acpi_vddci, 4585 &table->ACPIState.levels[0].vddci); 4586 } 4587 4588 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4589 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4590 4591 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4592 4593 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4594 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4595 4596 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4597 cpu_to_be32(dll_cntl); 4598 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4599 cpu_to_be32(mclk_pwrmgt_cntl); 4600 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4601 cpu_to_be32(mpll_ad_func_cntl); 4602 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4603 cpu_to_be32(mpll_dq_func_cntl); 4604 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4605 cpu_to_be32(mpll_func_cntl); 4606 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4607 cpu_to_be32(mpll_func_cntl_1); 4608 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4609 cpu_to_be32(mpll_func_cntl_2); 4610 table->ACPIState.levels[0].mclk.vMPLL_SS = 4611 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4612 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4613 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4614 4615 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4616 cpu_to_be32(spll_func_cntl); 4617 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4618 cpu_to_be32(spll_func_cntl_2); 4619 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4620 cpu_to_be32(spll_func_cntl_3); 4621 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4622 cpu_to_be32(spll_func_cntl_4); 4623 4624 table->ACPIState.levels[0].mclk.mclk_value = 0; 4625 table->ACPIState.levels[0].sclk.sclk_value = 0; 4626 4627 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4628 4629 if (eg_pi->dynamic_ac_timing) 4630 table->ACPIState.levels[0].ACIndex = 0; 4631 4632 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4633 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4634 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4635 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4636 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4637 4638 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4639 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4640 4641 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4642 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4643 4644 return 0; 4645 } 4646 4647 static int si_populate_ulv_state(struct radeon_device *rdev, 4648 SISLANDS_SMC_SWSTATE *state) 4649 { 4650 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4651 struct si_power_info *si_pi = si_get_pi(rdev); 4652 struct si_ulv_param *ulv = &si_pi->ulv; 4653 u32 sclk_in_sr = 1350; /* ??? */ 4654 int ret; 4655 4656 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4657 &state->levels[0]); 4658 if (!ret) { 4659 if (eg_pi->sclk_deep_sleep) { 4660 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4661 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4662 else 4663 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4664 } 4665 if (ulv->one_pcie_lane_in_ulv) 4666 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4667 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4668 state->levels[0].ACIndex = 1; 4669 state->levels[0].std_vddc = state->levels[0].vddc; 4670 state->levelCount = 1; 4671 4672 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4673 } 4674 4675 return ret; 4676 } 4677 4678 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4679 { 4680 struct si_power_info *si_pi = si_get_pi(rdev); 4681 struct si_ulv_param *ulv = &si_pi->ulv; 4682 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4683 int ret; 4684 4685 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4686 &arb_regs); 4687 if (ret) 4688 return ret; 4689 4690 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4691 ulv->volt_change_delay); 4692 4693 ret = si_copy_bytes_to_smc(rdev, 4694 si_pi->arb_table_start + 4695 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4696 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4697 (u8 *)&arb_regs, 4698 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4699 si_pi->sram_end); 4700 4701 return ret; 4702 } 4703 4704 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4705 { 4706 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4707 4708 pi->mvdd_split_frequency = 30000; 4709 } 4710 4711 static int si_init_smc_table(struct radeon_device *rdev) 4712 { 4713 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4714 struct si_power_info *si_pi = si_get_pi(rdev); 4715 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4716 const struct si_ulv_param *ulv = &si_pi->ulv; 4717 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4718 int ret; 4719 u32 lane_width; 4720 u32 vr_hot_gpio; 4721 4722 si_populate_smc_voltage_tables(rdev, table); 4723 4724 switch (rdev->pm.int_thermal_type) { 4725 case THERMAL_TYPE_SI: 4726 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4727 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4728 break; 4729 case THERMAL_TYPE_NONE: 4730 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4731 break; 4732 default: 4733 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4734 break; 4735 } 4736 4737 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4738 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4739 4740 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4741 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4742 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4743 } 4744 4745 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4746 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4747 4748 if (pi->mem_gddr5) 4749 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4750 4751 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4752 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4753 4754 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4755 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4756 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4757 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4758 vr_hot_gpio); 4759 } 4760 4761 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4762 if (ret) 4763 return ret; 4764 4765 ret = si_populate_smc_acpi_state(rdev, table); 4766 if (ret) 4767 return ret; 4768 4769 table->driverState = table->initialState; 4770 4771 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4772 SISLANDS_INITIAL_STATE_ARB_INDEX); 4773 if (ret) 4774 return ret; 4775 4776 if (ulv->supported && ulv->pl.vddc) { 4777 ret = si_populate_ulv_state(rdev, &table->ULVState); 4778 if (ret) 4779 return ret; 4780 4781 ret = si_program_ulv_memory_timing_parameters(rdev); 4782 if (ret) 4783 return ret; 4784 4785 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4786 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4787 4788 lane_width = radeon_get_pcie_lanes(rdev); 4789 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4790 } else { 4791 table->ULVState = table->initialState; 4792 } 4793 4794 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4795 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4796 si_pi->sram_end); 4797 } 4798 4799 static int si_calculate_sclk_params(struct radeon_device *rdev, 4800 u32 engine_clock, 4801 SISLANDS_SMC_SCLK_VALUE *sclk) 4802 { 4803 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4804 struct si_power_info *si_pi = si_get_pi(rdev); 4805 struct atom_clock_dividers dividers; 4806 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4807 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4808 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4809 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4810 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4811 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4812 u64 tmp; 4813 u32 reference_clock = rdev->clock.spll.reference_freq; 4814 u32 reference_divider; 4815 u32 fbdiv; 4816 int ret; 4817 4818 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4819 engine_clock, false, ÷rs); 4820 if (ret) 4821 return ret; 4822 4823 reference_divider = 1 + dividers.ref_div; 4824 4825 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4826 do_div(tmp, reference_clock); 4827 fbdiv = (u32) tmp; 4828 4829 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4830 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4831 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4832 4833 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4834 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4835 4836 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4837 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4838 spll_func_cntl_3 |= SPLL_DITHEN; 4839 4840 if (pi->sclk_ss) { 4841 struct radeon_atom_ss ss; 4842 u32 vco_freq = engine_clock * dividers.post_div; 4843 4844 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4845 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4846 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4847 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4848 4849 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4850 cg_spll_spread_spectrum |= CLK_S(clk_s); 4851 cg_spll_spread_spectrum |= SSEN; 4852 4853 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4854 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4855 } 4856 } 4857 4858 sclk->sclk_value = engine_clock; 4859 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4860 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4861 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4862 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4863 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4864 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4865 4866 return 0; 4867 } 4868 4869 static int si_populate_sclk_value(struct radeon_device *rdev, 4870 u32 engine_clock, 4871 SISLANDS_SMC_SCLK_VALUE *sclk) 4872 { 4873 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4874 int ret; 4875 4876 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4877 if (!ret) { 4878 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4879 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4880 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4881 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4882 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4883 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4884 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4885 } 4886 4887 return ret; 4888 } 4889 4890 static int si_populate_mclk_value(struct radeon_device *rdev, 4891 u32 engine_clock, 4892 u32 memory_clock, 4893 SISLANDS_SMC_MCLK_VALUE *mclk, 4894 bool strobe_mode, 4895 bool dll_state_on) 4896 { 4897 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4898 struct si_power_info *si_pi = si_get_pi(rdev); 4899 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4900 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4901 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4902 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4903 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4904 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4905 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4906 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4907 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4908 struct atom_mpll_param mpll_param; 4909 int ret; 4910 4911 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4912 if (ret) 4913 return ret; 4914 4915 mpll_func_cntl &= ~BWCTRL_MASK; 4916 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4917 4918 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4919 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4920 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4921 4922 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4923 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4924 4925 if (pi->mem_gddr5) { 4926 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4927 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4928 YCLK_POST_DIV(mpll_param.post_div); 4929 } 4930 4931 if (pi->mclk_ss) { 4932 struct radeon_atom_ss ss; 4933 u32 freq_nom; 4934 u32 tmp; 4935 u32 reference_clock = rdev->clock.mpll.reference_freq; 4936 4937 if (pi->mem_gddr5) 4938 freq_nom = memory_clock * 4; 4939 else 4940 freq_nom = memory_clock * 2; 4941 4942 tmp = freq_nom / reference_clock; 4943 tmp = tmp * tmp; 4944 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4945 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4946 u32 clks = reference_clock * 5 / ss.rate; 4947 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4948 4949 mpll_ss1 &= ~CLKV_MASK; 4950 mpll_ss1 |= CLKV(clkv); 4951 4952 mpll_ss2 &= ~CLKS_MASK; 4953 mpll_ss2 |= CLKS(clks); 4954 } 4955 } 4956 4957 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4958 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4959 4960 if (dll_state_on) 4961 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4962 else 4963 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4964 4965 mclk->mclk_value = cpu_to_be32(memory_clock); 4966 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4967 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4968 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4969 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4970 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4971 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4972 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4973 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4974 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4975 4976 return 0; 4977 } 4978 4979 static void si_populate_smc_sp(struct radeon_device *rdev, 4980 struct radeon_ps *radeon_state, 4981 SISLANDS_SMC_SWSTATE *smc_state) 4982 { 4983 struct ni_ps *ps = ni_get_ps(radeon_state); 4984 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4985 int i; 4986 4987 for (i = 0; i < ps->performance_level_count - 1; i++) 4988 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4989 4990 smc_state->levels[ps->performance_level_count - 1].bSP = 4991 cpu_to_be32(pi->psp); 4992 } 4993 4994 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4995 struct rv7xx_pl *pl, 4996 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4997 { 4998 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4999 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5000 struct si_power_info *si_pi = si_get_pi(rdev); 5001 int ret; 5002 bool dll_state_on; 5003 u16 std_vddc; 5004 bool gmc_pg = false; 5005 5006 if (eg_pi->pcie_performance_request && 5007 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 5008 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 5009 else 5010 level->gen2PCIE = (u8)pl->pcie_gen; 5011 5012 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 5013 if (ret) 5014 return ret; 5015 5016 level->mcFlags = 0; 5017 5018 if (pi->mclk_stutter_mode_threshold && 5019 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5020 !eg_pi->uvd_enabled && 5021 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 5022 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 5023 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5024 5025 if (gmc_pg) 5026 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 5027 } 5028 5029 if (pi->mem_gddr5) { 5030 if (pl->mclk > pi->mclk_edc_enable_threshold) 5031 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5032 5033 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5034 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5035 5036 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 5037 5038 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5039 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5040 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5041 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5042 else 5043 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5044 } else { 5045 dll_state_on = false; 5046 } 5047 } else { 5048 level->strobeMode = si_get_strobe_mode_settings(rdev, 5049 pl->mclk); 5050 5051 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5052 } 5053 5054 ret = si_populate_mclk_value(rdev, 5055 pl->sclk, 5056 pl->mclk, 5057 &level->mclk, 5058 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5059 if (ret) 5060 return ret; 5061 5062 ret = si_populate_voltage_value(rdev, 5063 &eg_pi->vddc_voltage_table, 5064 pl->vddc, &level->vddc); 5065 if (ret) 5066 return ret; 5067 5068 5069 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 5070 if (ret) 5071 return ret; 5072 5073 ret = si_populate_std_voltage_value(rdev, std_vddc, 5074 level->vddc.index, &level->std_vddc); 5075 if (ret) 5076 return ret; 5077 5078 if (eg_pi->vddci_control) { 5079 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5080 pl->vddci, &level->vddci); 5081 if (ret) 5082 return ret; 5083 } 5084 5085 if (si_pi->vddc_phase_shed_control) { 5086 ret = si_populate_phase_shedding_value(rdev, 5087 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5088 pl->vddc, 5089 pl->sclk, 5090 pl->mclk, 5091 &level->vddc); 5092 if (ret) 5093 return ret; 5094 } 5095 5096 level->MaxPoweredUpCU = si_pi->max_cu; 5097 5098 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5099 5100 return ret; 5101 } 5102 5103 static int si_populate_smc_t(struct radeon_device *rdev, 5104 struct radeon_ps *radeon_state, 5105 SISLANDS_SMC_SWSTATE *smc_state) 5106 { 5107 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5108 struct ni_ps *state = ni_get_ps(radeon_state); 5109 u32 a_t; 5110 u32 t_l, t_h; 5111 u32 high_bsp; 5112 int i, ret; 5113 5114 if (state->performance_level_count >= 9) 5115 return -EINVAL; 5116 5117 if (state->performance_level_count < 2) { 5118 a_t = CG_R(0xffff) | CG_L(0); 5119 smc_state->levels[0].aT = cpu_to_be32(a_t); 5120 return 0; 5121 } 5122 5123 smc_state->levels[0].aT = cpu_to_be32(0); 5124 5125 for (i = 0; i <= state->performance_level_count - 2; i++) { 5126 ret = r600_calculate_at( 5127 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5128 100 * R600_AH_DFLT, 5129 state->performance_levels[i + 1].sclk, 5130 state->performance_levels[i].sclk, 5131 &t_l, 5132 &t_h); 5133 5134 if (ret) { 5135 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5136 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5137 } 5138 5139 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5140 a_t |= CG_R(t_l * pi->bsp / 20000); 5141 smc_state->levels[i].aT = cpu_to_be32(a_t); 5142 5143 high_bsp = (i == state->performance_level_count - 2) ? 5144 pi->pbsp : pi->bsp; 5145 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5146 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5147 } 5148 5149 return 0; 5150 } 5151 5152 static int si_disable_ulv(struct radeon_device *rdev) 5153 { 5154 struct si_power_info *si_pi = si_get_pi(rdev); 5155 struct si_ulv_param *ulv = &si_pi->ulv; 5156 5157 if (ulv->supported) 5158 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5159 0 : -EINVAL; 5160 5161 return 0; 5162 } 5163 5164 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5165 struct radeon_ps *radeon_state) 5166 { 5167 const struct si_power_info *si_pi = si_get_pi(rdev); 5168 const struct si_ulv_param *ulv = &si_pi->ulv; 5169 const struct ni_ps *state = ni_get_ps(radeon_state); 5170 int i; 5171 5172 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5173 return false; 5174 5175 /* XXX validate against display requirements! */ 5176 5177 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5178 if (rdev->clock.current_dispclk <= 5179 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5180 if (ulv->pl.vddc < 5181 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5182 return false; 5183 } 5184 } 5185 5186 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5187 return false; 5188 5189 return true; 5190 } 5191 5192 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5193 struct radeon_ps *radeon_new_state) 5194 { 5195 const struct si_power_info *si_pi = si_get_pi(rdev); 5196 const struct si_ulv_param *ulv = &si_pi->ulv; 5197 5198 if (ulv->supported) { 5199 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5200 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5201 0 : -EINVAL; 5202 } 5203 return 0; 5204 } 5205 5206 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5207 struct radeon_ps *radeon_state, 5208 SISLANDS_SMC_SWSTATE *smc_state) 5209 { 5210 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5211 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5212 struct si_power_info *si_pi = si_get_pi(rdev); 5213 struct ni_ps *state = ni_get_ps(radeon_state); 5214 int i, ret; 5215 u32 threshold; 5216 u32 sclk_in_sr = 1350; /* ??? */ 5217 5218 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5219 return -EINVAL; 5220 5221 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5222 5223 if (radeon_state->vclk && radeon_state->dclk) { 5224 eg_pi->uvd_enabled = true; 5225 if (eg_pi->smu_uvd_hs) 5226 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5227 } else { 5228 eg_pi->uvd_enabled = false; 5229 } 5230 5231 if (state->dc_compatible) 5232 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5233 5234 smc_state->levelCount = 0; 5235 for (i = 0; i < state->performance_level_count; i++) { 5236 if (eg_pi->sclk_deep_sleep) { 5237 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5238 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5239 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5240 else 5241 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5242 } 5243 } 5244 5245 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5246 &smc_state->levels[i]); 5247 smc_state->levels[i].arbRefreshState = 5248 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5249 5250 if (ret) 5251 return ret; 5252 5253 if (ni_pi->enable_power_containment) 5254 smc_state->levels[i].displayWatermark = 5255 (state->performance_levels[i].sclk < threshold) ? 5256 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5257 else 5258 smc_state->levels[i].displayWatermark = (i < 2) ? 5259 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5260 5261 if (eg_pi->dynamic_ac_timing) 5262 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5263 else 5264 smc_state->levels[i].ACIndex = 0; 5265 5266 smc_state->levelCount++; 5267 } 5268 5269 si_write_smc_soft_register(rdev, 5270 SI_SMC_SOFT_REGISTER_watermark_threshold, 5271 threshold / 512); 5272 5273 si_populate_smc_sp(rdev, radeon_state, smc_state); 5274 5275 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5276 if (ret) 5277 ni_pi->enable_power_containment = false; 5278 5279 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5280 if (ret) 5281 ni_pi->enable_sq_ramping = false; 5282 5283 return si_populate_smc_t(rdev, radeon_state, smc_state); 5284 } 5285 5286 static int si_upload_sw_state(struct radeon_device *rdev, 5287 struct radeon_ps *radeon_new_state) 5288 { 5289 struct si_power_info *si_pi = si_get_pi(rdev); 5290 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5291 int ret; 5292 u32 address = si_pi->state_table_start + 5293 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5294 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5295 ((new_state->performance_level_count - 1) * 5296 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5297 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5298 5299 memset(smc_state, 0, state_size); 5300 5301 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5302 if (ret) 5303 return ret; 5304 5305 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5306 state_size, si_pi->sram_end); 5307 5308 return ret; 5309 } 5310 5311 static int si_upload_ulv_state(struct radeon_device *rdev) 5312 { 5313 struct si_power_info *si_pi = si_get_pi(rdev); 5314 struct si_ulv_param *ulv = &si_pi->ulv; 5315 int ret = 0; 5316 5317 if (ulv->supported && ulv->pl.vddc) { 5318 u32 address = si_pi->state_table_start + 5319 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5320 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5321 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5322 5323 memset(smc_state, 0, state_size); 5324 5325 ret = si_populate_ulv_state(rdev, smc_state); 5326 if (!ret) 5327 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5328 state_size, si_pi->sram_end); 5329 } 5330 5331 return ret; 5332 } 5333 5334 static int si_upload_smc_data(struct radeon_device *rdev) 5335 { 5336 struct radeon_crtc *radeon_crtc = NULL; 5337 int i; 5338 5339 if (rdev->pm.dpm.new_active_crtc_count == 0) 5340 return 0; 5341 5342 for (i = 0; i < rdev->num_crtc; i++) { 5343 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5344 radeon_crtc = rdev->mode_info.crtcs[i]; 5345 break; 5346 } 5347 } 5348 5349 if (radeon_crtc == NULL) 5350 return 0; 5351 5352 if (radeon_crtc->line_time <= 0) 5353 return 0; 5354 5355 if (si_write_smc_soft_register(rdev, 5356 SI_SMC_SOFT_REGISTER_crtc_index, 5357 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5358 return 0; 5359 5360 if (si_write_smc_soft_register(rdev, 5361 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5362 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5363 return 0; 5364 5365 if (si_write_smc_soft_register(rdev, 5366 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5367 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5368 return 0; 5369 5370 return 0; 5371 } 5372 5373 static int si_set_mc_special_registers(struct radeon_device *rdev, 5374 struct si_mc_reg_table *table) 5375 { 5376 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5377 u8 i, j, k; 5378 u32 temp_reg; 5379 5380 for (i = 0, j = table->last; i < table->last; i++) { 5381 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5382 return -EINVAL; 5383 switch (table->mc_reg_address[i].s1 << 2) { 5384 case MC_SEQ_MISC1: 5385 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5386 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5387 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5388 for (k = 0; k < table->num_entries; k++) 5389 table->mc_reg_table_entry[k].mc_data[j] = 5390 ((temp_reg & 0xffff0000)) | 5391 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5392 j++; 5393 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5394 return -EINVAL; 5395 5396 temp_reg = RREG32(MC_PMG_CMD_MRS); 5397 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5398 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5399 for (k = 0; k < table->num_entries; k++) { 5400 table->mc_reg_table_entry[k].mc_data[j] = 5401 (temp_reg & 0xffff0000) | 5402 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5403 if (!pi->mem_gddr5) 5404 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5405 } 5406 j++; 5407 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5408 return -EINVAL; 5409 5410 if (!pi->mem_gddr5) { 5411 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5412 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5413 for (k = 0; k < table->num_entries; k++) 5414 table->mc_reg_table_entry[k].mc_data[j] = 5415 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5416 j++; 5417 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5418 return -EINVAL; 5419 } 5420 break; 5421 case MC_SEQ_RESERVE_M: 5422 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5423 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5424 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5425 for(k = 0; k < table->num_entries; k++) 5426 table->mc_reg_table_entry[k].mc_data[j] = 5427 (temp_reg & 0xffff0000) | 5428 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5429 j++; 5430 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5431 return -EINVAL; 5432 break; 5433 default: 5434 break; 5435 } 5436 } 5437 5438 table->last = j; 5439 5440 return 0; 5441 } 5442 5443 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5444 { 5445 bool result = true; 5446 5447 switch (in_reg) { 5448 case MC_SEQ_RAS_TIMING >> 2: 5449 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5450 break; 5451 case MC_SEQ_CAS_TIMING >> 2: 5452 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5453 break; 5454 case MC_SEQ_MISC_TIMING >> 2: 5455 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5456 break; 5457 case MC_SEQ_MISC_TIMING2 >> 2: 5458 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5459 break; 5460 case MC_SEQ_RD_CTL_D0 >> 2: 5461 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5462 break; 5463 case MC_SEQ_RD_CTL_D1 >> 2: 5464 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5465 break; 5466 case MC_SEQ_WR_CTL_D0 >> 2: 5467 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5468 break; 5469 case MC_SEQ_WR_CTL_D1 >> 2: 5470 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5471 break; 5472 case MC_PMG_CMD_EMRS >> 2: 5473 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5474 break; 5475 case MC_PMG_CMD_MRS >> 2: 5476 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5477 break; 5478 case MC_PMG_CMD_MRS1 >> 2: 5479 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5480 break; 5481 case MC_SEQ_PMG_TIMING >> 2: 5482 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5483 break; 5484 case MC_PMG_CMD_MRS2 >> 2: 5485 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5486 break; 5487 case MC_SEQ_WR_CTL_2 >> 2: 5488 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5489 break; 5490 default: 5491 result = false; 5492 break; 5493 } 5494 5495 return result; 5496 } 5497 5498 static void si_set_valid_flag(struct si_mc_reg_table *table) 5499 { 5500 u8 i, j; 5501 5502 for (i = 0; i < table->last; i++) { 5503 for (j = 1; j < table->num_entries; j++) { 5504 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5505 table->valid_flag |= 1 << i; 5506 break; 5507 } 5508 } 5509 } 5510 } 5511 5512 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5513 { 5514 u32 i; 5515 u16 address; 5516 5517 for (i = 0; i < table->last; i++) 5518 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5519 address : table->mc_reg_address[i].s1; 5520 5521 } 5522 5523 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5524 struct si_mc_reg_table *si_table) 5525 { 5526 u8 i, j; 5527 5528 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5529 return -EINVAL; 5530 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5531 return -EINVAL; 5532 5533 for (i = 0; i < table->last; i++) 5534 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5535 si_table->last = table->last; 5536 5537 for (i = 0; i < table->num_entries; i++) { 5538 si_table->mc_reg_table_entry[i].mclk_max = 5539 table->mc_reg_table_entry[i].mclk_max; 5540 for (j = 0; j < table->last; j++) { 5541 si_table->mc_reg_table_entry[i].mc_data[j] = 5542 table->mc_reg_table_entry[i].mc_data[j]; 5543 } 5544 } 5545 si_table->num_entries = table->num_entries; 5546 5547 return 0; 5548 } 5549 5550 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5551 { 5552 struct si_power_info *si_pi = si_get_pi(rdev); 5553 struct atom_mc_reg_table *table; 5554 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5555 u8 module_index = rv770_get_memory_module_index(rdev); 5556 int ret; 5557 5558 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5559 if (!table) 5560 return -ENOMEM; 5561 5562 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5563 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5564 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5565 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5566 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5567 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5568 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5569 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5570 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5571 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5572 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5573 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5574 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5575 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5576 5577 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5578 if (ret) 5579 goto init_mc_done; 5580 5581 ret = si_copy_vbios_mc_reg_table(table, si_table); 5582 if (ret) 5583 goto init_mc_done; 5584 5585 si_set_s0_mc_reg_index(si_table); 5586 5587 ret = si_set_mc_special_registers(rdev, si_table); 5588 if (ret) 5589 goto init_mc_done; 5590 5591 si_set_valid_flag(si_table); 5592 5593 init_mc_done: 5594 kfree(table); 5595 5596 return ret; 5597 5598 } 5599 5600 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5601 SMC_SIslands_MCRegisters *mc_reg_table) 5602 { 5603 struct si_power_info *si_pi = si_get_pi(rdev); 5604 u32 i, j; 5605 5606 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5607 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5608 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5609 break; 5610 mc_reg_table->address[i].s0 = 5611 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5612 mc_reg_table->address[i].s1 = 5613 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5614 i++; 5615 } 5616 } 5617 mc_reg_table->last = (u8)i; 5618 } 5619 5620 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5621 SMC_SIslands_MCRegisterSet *data, 5622 u32 num_entries, u32 valid_flag) 5623 { 5624 u32 i, j; 5625 5626 for(i = 0, j = 0; j < num_entries; j++) { 5627 if (valid_flag & (1 << j)) { 5628 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5629 i++; 5630 } 5631 } 5632 } 5633 5634 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5635 struct rv7xx_pl *pl, 5636 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5637 { 5638 struct si_power_info *si_pi = si_get_pi(rdev); 5639 u32 i = 0; 5640 5641 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5642 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5643 break; 5644 } 5645 5646 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5647 --i; 5648 5649 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5650 mc_reg_table_data, si_pi->mc_reg_table.last, 5651 si_pi->mc_reg_table.valid_flag); 5652 } 5653 5654 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5655 struct radeon_ps *radeon_state, 5656 SMC_SIslands_MCRegisters *mc_reg_table) 5657 { 5658 struct ni_ps *state = ni_get_ps(radeon_state); 5659 int i; 5660 5661 for (i = 0; i < state->performance_level_count; i++) { 5662 si_convert_mc_reg_table_entry_to_smc(rdev, 5663 &state->performance_levels[i], 5664 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5665 } 5666 } 5667 5668 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5669 struct radeon_ps *radeon_boot_state) 5670 { 5671 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5672 struct si_power_info *si_pi = si_get_pi(rdev); 5673 struct si_ulv_param *ulv = &si_pi->ulv; 5674 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5675 5676 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5677 5678 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5679 5680 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5681 5682 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5683 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5684 5685 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5686 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5687 si_pi->mc_reg_table.last, 5688 si_pi->mc_reg_table.valid_flag); 5689 5690 if (ulv->supported && ulv->pl.vddc != 0) 5691 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5692 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5693 else 5694 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5695 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5696 si_pi->mc_reg_table.last, 5697 si_pi->mc_reg_table.valid_flag); 5698 5699 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5700 5701 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5702 (u8 *)smc_mc_reg_table, 5703 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5704 } 5705 5706 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5707 struct radeon_ps *radeon_new_state) 5708 { 5709 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5710 struct si_power_info *si_pi = si_get_pi(rdev); 5711 u32 address = si_pi->mc_reg_table_start + 5712 offsetof(SMC_SIslands_MCRegisters, 5713 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5714 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5715 5716 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5717 5718 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5719 5720 5721 return si_copy_bytes_to_smc(rdev, address, 5722 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5723 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5724 si_pi->sram_end); 5725 5726 } 5727 5728 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5729 { 5730 if (enable) 5731 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5732 else 5733 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5734 } 5735 5736 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5737 struct radeon_ps *radeon_state) 5738 { 5739 struct ni_ps *state = ni_get_ps(radeon_state); 5740 int i; 5741 u16 pcie_speed, max_speed = 0; 5742 5743 for (i = 0; i < state->performance_level_count; i++) { 5744 pcie_speed = state->performance_levels[i].pcie_gen; 5745 if (max_speed < pcie_speed) 5746 max_speed = pcie_speed; 5747 } 5748 return max_speed; 5749 } 5750 5751 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5752 { 5753 u32 speed_cntl; 5754 5755 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5756 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5757 5758 return (u16)speed_cntl; 5759 } 5760 5761 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5762 struct radeon_ps *radeon_new_state, 5763 struct radeon_ps *radeon_current_state) 5764 { 5765 struct si_power_info *si_pi = si_get_pi(rdev); 5766 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5767 enum radeon_pcie_gen current_link_speed; 5768 5769 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5770 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5771 else 5772 current_link_speed = si_pi->force_pcie_gen; 5773 5774 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5775 si_pi->pspp_notify_required = false; 5776 if (target_link_speed > current_link_speed) { 5777 switch (target_link_speed) { 5778 #if defined(CONFIG_ACPI) 5779 case RADEON_PCIE_GEN3: 5780 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5781 break; 5782 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5783 if (current_link_speed == RADEON_PCIE_GEN2) 5784 break; 5785 case RADEON_PCIE_GEN2: 5786 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5787 break; 5788 #endif 5789 default: 5790 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5791 break; 5792 } 5793 } else { 5794 if (target_link_speed < current_link_speed) 5795 si_pi->pspp_notify_required = true; 5796 } 5797 } 5798 5799 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5800 struct radeon_ps *radeon_new_state, 5801 struct radeon_ps *radeon_current_state) 5802 { 5803 struct si_power_info *si_pi = si_get_pi(rdev); 5804 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5805 u8 request; 5806 5807 if (si_pi->pspp_notify_required) { 5808 if (target_link_speed == RADEON_PCIE_GEN3) 5809 request = PCIE_PERF_REQ_PECI_GEN3; 5810 else if (target_link_speed == RADEON_PCIE_GEN2) 5811 request = PCIE_PERF_REQ_PECI_GEN2; 5812 else 5813 request = PCIE_PERF_REQ_PECI_GEN1; 5814 5815 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5816 (si_get_current_pcie_speed(rdev) > 0)) 5817 return; 5818 5819 #if defined(CONFIG_ACPI) 5820 radeon_acpi_pcie_performance_request(rdev, request, false); 5821 #endif 5822 } 5823 } 5824 5825 #if 0 5826 static int si_ds_request(struct radeon_device *rdev, 5827 bool ds_status_on, u32 count_write) 5828 { 5829 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5830 5831 if (eg_pi->sclk_deep_sleep) { 5832 if (ds_status_on) 5833 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5834 PPSMC_Result_OK) ? 5835 0 : -EINVAL; 5836 else 5837 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5838 PPSMC_Result_OK) ? 0 : -EINVAL; 5839 } 5840 return 0; 5841 } 5842 #endif 5843 5844 static void si_set_max_cu_value(struct radeon_device *rdev) 5845 { 5846 struct si_power_info *si_pi = si_get_pi(rdev); 5847 5848 if (rdev->family == CHIP_VERDE) { 5849 switch (rdev->pdev->device) { 5850 case 0x6820: 5851 case 0x6825: 5852 case 0x6821: 5853 case 0x6823: 5854 case 0x6827: 5855 si_pi->max_cu = 10; 5856 break; 5857 case 0x682D: 5858 case 0x6824: 5859 case 0x682F: 5860 case 0x6826: 5861 si_pi->max_cu = 8; 5862 break; 5863 case 0x6828: 5864 case 0x6830: 5865 case 0x6831: 5866 case 0x6838: 5867 case 0x6839: 5868 case 0x683D: 5869 si_pi->max_cu = 10; 5870 break; 5871 case 0x683B: 5872 case 0x683F: 5873 case 0x6829: 5874 si_pi->max_cu = 8; 5875 break; 5876 default: 5877 si_pi->max_cu = 0; 5878 break; 5879 } 5880 } else { 5881 si_pi->max_cu = 0; 5882 } 5883 } 5884 5885 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5886 struct radeon_clock_voltage_dependency_table *table) 5887 { 5888 u32 i; 5889 int j; 5890 u16 leakage_voltage; 5891 5892 if (table) { 5893 for (i = 0; i < table->count; i++) { 5894 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5895 table->entries[i].v, 5896 &leakage_voltage)) { 5897 case 0: 5898 table->entries[i].v = leakage_voltage; 5899 break; 5900 case -EAGAIN: 5901 return -EINVAL; 5902 case -EINVAL: 5903 default: 5904 break; 5905 } 5906 } 5907 5908 for (j = (table->count - 2); j >= 0; j--) { 5909 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5910 table->entries[j].v : table->entries[j + 1].v; 5911 } 5912 } 5913 return 0; 5914 } 5915 5916 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5917 { 5918 int ret = 0; 5919 5920 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5921 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5922 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5923 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5924 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5925 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5926 return ret; 5927 } 5928 5929 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5930 struct radeon_ps *radeon_new_state, 5931 struct radeon_ps *radeon_current_state) 5932 { 5933 u32 lane_width; 5934 u32 new_lane_width = 5935 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5936 u32 current_lane_width = 5937 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5938 5939 if (new_lane_width != current_lane_width) { 5940 radeon_set_pcie_lanes(rdev, new_lane_width); 5941 lane_width = radeon_get_pcie_lanes(rdev); 5942 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5943 } 5944 } 5945 5946 static void si_set_vce_clock(struct radeon_device *rdev, 5947 struct radeon_ps *new_rps, 5948 struct radeon_ps *old_rps) 5949 { 5950 if ((old_rps->evclk != new_rps->evclk) || 5951 (old_rps->ecclk != new_rps->ecclk)) { 5952 /* turn the clocks on when encoding, off otherwise */ 5953 if (new_rps->evclk || new_rps->ecclk) 5954 vce_v1_0_enable_mgcg(rdev, false); 5955 else 5956 vce_v1_0_enable_mgcg(rdev, true); 5957 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 5958 } 5959 } 5960 5961 void si_dpm_setup_asic(struct radeon_device *rdev) 5962 { 5963 int r; 5964 5965 r = si_mc_load_microcode(rdev); 5966 if (r) 5967 DRM_ERROR("Failed to load MC firmware!\n"); 5968 rv770_get_memory_type(rdev); 5969 si_read_clock_registers(rdev); 5970 si_enable_acpi_power_management(rdev); 5971 } 5972 5973 static int si_thermal_enable_alert(struct radeon_device *rdev, 5974 bool enable) 5975 { 5976 u32 thermal_int = RREG32(CG_THERMAL_INT); 5977 5978 if (enable) { 5979 PPSMC_Result result; 5980 5981 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5982 WREG32(CG_THERMAL_INT, thermal_int); 5983 rdev->irq.dpm_thermal = false; 5984 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5985 if (result != PPSMC_Result_OK) { 5986 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5987 return -EINVAL; 5988 } 5989 } else { 5990 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5991 WREG32(CG_THERMAL_INT, thermal_int); 5992 rdev->irq.dpm_thermal = true; 5993 } 5994 5995 return 0; 5996 } 5997 5998 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5999 int min_temp, int max_temp) 6000 { 6001 int low_temp = 0 * 1000; 6002 int high_temp = 255 * 1000; 6003 6004 if (low_temp < min_temp) 6005 low_temp = min_temp; 6006 if (high_temp > max_temp) 6007 high_temp = max_temp; 6008 if (high_temp < low_temp) { 6009 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 6010 return -EINVAL; 6011 } 6012 6013 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 6014 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 6015 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 6016 6017 rdev->pm.dpm.thermal.min_temp = low_temp; 6018 rdev->pm.dpm.thermal.max_temp = high_temp; 6019 6020 return 0; 6021 } 6022 6023 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 6024 { 6025 struct si_power_info *si_pi = si_get_pi(rdev); 6026 u32 tmp; 6027 6028 if (si_pi->fan_ctrl_is_in_default_mode) { 6029 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 6030 si_pi->fan_ctrl_default_mode = tmp; 6031 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 6032 si_pi->t_min = tmp; 6033 si_pi->fan_ctrl_is_in_default_mode = false; 6034 } 6035 6036 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6037 tmp |= TMIN(0); 6038 WREG32(CG_FDO_CTRL2, tmp); 6039 6040 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6041 tmp |= FDO_PWM_MODE(mode); 6042 WREG32(CG_FDO_CTRL2, tmp); 6043 } 6044 6045 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 6046 { 6047 struct si_power_info *si_pi = si_get_pi(rdev); 6048 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6049 u32 duty100; 6050 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6051 u16 fdo_min, slope1, slope2; 6052 u32 reference_clock, tmp; 6053 int ret; 6054 u64 tmp64; 6055 6056 if (!si_pi->fan_table_start) { 6057 rdev->pm.dpm.fan.ucode_fan_control = false; 6058 return 0; 6059 } 6060 6061 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6062 6063 if (duty100 == 0) { 6064 rdev->pm.dpm.fan.ucode_fan_control = false; 6065 return 0; 6066 } 6067 6068 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 6069 do_div(tmp64, 10000); 6070 fdo_min = (u16)tmp64; 6071 6072 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6073 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6074 6075 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6076 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6077 6078 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6079 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6080 6081 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6082 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6083 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6084 6085 fan_table.slope1 = cpu_to_be16(slope1); 6086 fan_table.slope2 = cpu_to_be16(slope2); 6087 6088 fan_table.fdo_min = cpu_to_be16(fdo_min); 6089 6090 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6091 6092 fan_table.hys_up = cpu_to_be16(1); 6093 6094 fan_table.hys_slope = cpu_to_be16(1); 6095 6096 fan_table.temp_resp_lim = cpu_to_be16(5); 6097 6098 reference_clock = radeon_get_xclk(rdev); 6099 6100 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6101 reference_clock) / 1600); 6102 6103 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6104 6105 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6106 fan_table.temp_src = (uint8_t)tmp; 6107 6108 ret = si_copy_bytes_to_smc(rdev, 6109 si_pi->fan_table_start, 6110 (u8 *)(&fan_table), 6111 sizeof(fan_table), 6112 si_pi->sram_end); 6113 6114 if (ret) { 6115 DRM_ERROR("Failed to load fan table to the SMC."); 6116 rdev->pm.dpm.fan.ucode_fan_control = false; 6117 } 6118 6119 return 0; 6120 } 6121 6122 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6123 { 6124 struct si_power_info *si_pi = si_get_pi(rdev); 6125 PPSMC_Result ret; 6126 6127 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6128 if (ret == PPSMC_Result_OK) { 6129 si_pi->fan_is_controlled_by_smc = true; 6130 return 0; 6131 } else { 6132 return -EINVAL; 6133 } 6134 } 6135 6136 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6137 { 6138 struct si_power_info *si_pi = si_get_pi(rdev); 6139 PPSMC_Result ret; 6140 6141 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6142 6143 if (ret == PPSMC_Result_OK) { 6144 si_pi->fan_is_controlled_by_smc = false; 6145 return 0; 6146 } else { 6147 return -EINVAL; 6148 } 6149 } 6150 6151 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6152 u32 *speed) 6153 { 6154 u32 duty, duty100; 6155 u64 tmp64; 6156 6157 if (rdev->pm.no_fan) 6158 return -ENOENT; 6159 6160 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6161 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6162 6163 if (duty100 == 0) 6164 return -EINVAL; 6165 6166 tmp64 = (u64)duty * 100; 6167 do_div(tmp64, duty100); 6168 *speed = (u32)tmp64; 6169 6170 if (*speed > 100) 6171 *speed = 100; 6172 6173 return 0; 6174 } 6175 6176 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6177 u32 speed) 6178 { 6179 struct si_power_info *si_pi = si_get_pi(rdev); 6180 u32 tmp; 6181 u32 duty, duty100; 6182 u64 tmp64; 6183 6184 if (rdev->pm.no_fan) 6185 return -ENOENT; 6186 6187 if (si_pi->fan_is_controlled_by_smc) 6188 return -EINVAL; 6189 6190 if (speed > 100) 6191 return -EINVAL; 6192 6193 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6194 6195 if (duty100 == 0) 6196 return -EINVAL; 6197 6198 tmp64 = (u64)speed * duty100; 6199 do_div(tmp64, 100); 6200 duty = (u32)tmp64; 6201 6202 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6203 tmp |= FDO_STATIC_DUTY(duty); 6204 WREG32(CG_FDO_CTRL0, tmp); 6205 6206 return 0; 6207 } 6208 6209 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6210 { 6211 if (mode) { 6212 /* stop auto-manage */ 6213 if (rdev->pm.dpm.fan.ucode_fan_control) 6214 si_fan_ctrl_stop_smc_fan_control(rdev); 6215 si_fan_ctrl_set_static_mode(rdev, mode); 6216 } else { 6217 /* restart auto-manage */ 6218 if (rdev->pm.dpm.fan.ucode_fan_control) 6219 si_thermal_start_smc_fan_control(rdev); 6220 else 6221 si_fan_ctrl_set_default_mode(rdev); 6222 } 6223 } 6224 6225 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6226 { 6227 struct si_power_info *si_pi = si_get_pi(rdev); 6228 u32 tmp; 6229 6230 if (si_pi->fan_is_controlled_by_smc) 6231 return 0; 6232 6233 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6234 return (tmp >> FDO_PWM_MODE_SHIFT); 6235 } 6236 6237 #if 0 6238 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6239 u32 *speed) 6240 { 6241 u32 tach_period; 6242 u32 xclk = radeon_get_xclk(rdev); 6243 6244 if (rdev->pm.no_fan) 6245 return -ENOENT; 6246 6247 if (rdev->pm.fan_pulses_per_revolution == 0) 6248 return -ENOENT; 6249 6250 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6251 if (tach_period == 0) 6252 return -ENOENT; 6253 6254 *speed = 60 * xclk * 10000 / tach_period; 6255 6256 return 0; 6257 } 6258 6259 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6260 u32 speed) 6261 { 6262 u32 tach_period, tmp; 6263 u32 xclk = radeon_get_xclk(rdev); 6264 6265 if (rdev->pm.no_fan) 6266 return -ENOENT; 6267 6268 if (rdev->pm.fan_pulses_per_revolution == 0) 6269 return -ENOENT; 6270 6271 if ((speed < rdev->pm.fan_min_rpm) || 6272 (speed > rdev->pm.fan_max_rpm)) 6273 return -EINVAL; 6274 6275 if (rdev->pm.dpm.fan.ucode_fan_control) 6276 si_fan_ctrl_stop_smc_fan_control(rdev); 6277 6278 tach_period = 60 * xclk * 10000 / (8 * speed); 6279 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6280 tmp |= TARGET_PERIOD(tach_period); 6281 WREG32(CG_TACH_CTRL, tmp); 6282 6283 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6284 6285 return 0; 6286 } 6287 #endif 6288 6289 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6290 { 6291 struct si_power_info *si_pi = si_get_pi(rdev); 6292 u32 tmp; 6293 6294 if (!si_pi->fan_ctrl_is_in_default_mode) { 6295 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6296 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6297 WREG32(CG_FDO_CTRL2, tmp); 6298 6299 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6300 tmp |= TMIN(si_pi->t_min); 6301 WREG32(CG_FDO_CTRL2, tmp); 6302 si_pi->fan_ctrl_is_in_default_mode = true; 6303 } 6304 } 6305 6306 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6307 { 6308 if (rdev->pm.dpm.fan.ucode_fan_control) { 6309 si_fan_ctrl_start_smc_fan_control(rdev); 6310 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6311 } 6312 } 6313 6314 static void si_thermal_initialize(struct radeon_device *rdev) 6315 { 6316 u32 tmp; 6317 6318 if (rdev->pm.fan_pulses_per_revolution) { 6319 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6320 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6321 WREG32(CG_TACH_CTRL, tmp); 6322 } 6323 6324 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6325 tmp |= TACH_PWM_RESP_RATE(0x28); 6326 WREG32(CG_FDO_CTRL2, tmp); 6327 } 6328 6329 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6330 { 6331 int ret; 6332 6333 si_thermal_initialize(rdev); 6334 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6335 if (ret) 6336 return ret; 6337 ret = si_thermal_enable_alert(rdev, true); 6338 if (ret) 6339 return ret; 6340 if (rdev->pm.dpm.fan.ucode_fan_control) { 6341 ret = si_halt_smc(rdev); 6342 if (ret) 6343 return ret; 6344 ret = si_thermal_setup_fan_table(rdev); 6345 if (ret) 6346 return ret; 6347 ret = si_resume_smc(rdev); 6348 if (ret) 6349 return ret; 6350 si_thermal_start_smc_fan_control(rdev); 6351 } 6352 6353 return 0; 6354 } 6355 6356 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6357 { 6358 if (!rdev->pm.no_fan) { 6359 si_fan_ctrl_set_default_mode(rdev); 6360 si_fan_ctrl_stop_smc_fan_control(rdev); 6361 } 6362 } 6363 6364 int si_dpm_enable(struct radeon_device *rdev) 6365 { 6366 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6367 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6368 struct si_power_info *si_pi = si_get_pi(rdev); 6369 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6370 int ret; 6371 6372 if (si_is_smc_running(rdev)) 6373 return -EINVAL; 6374 if (pi->voltage_control || si_pi->voltage_control_svi2) 6375 si_enable_voltage_control(rdev, true); 6376 if (pi->mvdd_control) 6377 si_get_mvdd_configuration(rdev); 6378 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6379 ret = si_construct_voltage_tables(rdev); 6380 if (ret) { 6381 DRM_ERROR("si_construct_voltage_tables failed\n"); 6382 return ret; 6383 } 6384 } 6385 if (eg_pi->dynamic_ac_timing) { 6386 ret = si_initialize_mc_reg_table(rdev); 6387 if (ret) 6388 eg_pi->dynamic_ac_timing = false; 6389 } 6390 if (pi->dynamic_ss) 6391 si_enable_spread_spectrum(rdev, true); 6392 if (pi->thermal_protection) 6393 si_enable_thermal_protection(rdev, true); 6394 si_setup_bsp(rdev); 6395 si_program_git(rdev); 6396 si_program_tp(rdev); 6397 si_program_tpp(rdev); 6398 si_program_sstp(rdev); 6399 si_enable_display_gap(rdev); 6400 si_program_vc(rdev); 6401 ret = si_upload_firmware(rdev); 6402 if (ret) { 6403 DRM_ERROR("si_upload_firmware failed\n"); 6404 return ret; 6405 } 6406 ret = si_process_firmware_header(rdev); 6407 if (ret) { 6408 DRM_ERROR("si_process_firmware_header failed\n"); 6409 return ret; 6410 } 6411 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6412 if (ret) { 6413 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6414 return ret; 6415 } 6416 ret = si_init_smc_table(rdev); 6417 if (ret) { 6418 DRM_ERROR("si_init_smc_table failed\n"); 6419 return ret; 6420 } 6421 ret = si_init_smc_spll_table(rdev); 6422 if (ret) { 6423 DRM_ERROR("si_init_smc_spll_table failed\n"); 6424 return ret; 6425 } 6426 ret = si_init_arb_table_index(rdev); 6427 if (ret) { 6428 DRM_ERROR("si_init_arb_table_index failed\n"); 6429 return ret; 6430 } 6431 if (eg_pi->dynamic_ac_timing) { 6432 ret = si_populate_mc_reg_table(rdev, boot_ps); 6433 if (ret) { 6434 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6435 return ret; 6436 } 6437 } 6438 ret = si_initialize_smc_cac_tables(rdev); 6439 if (ret) { 6440 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6441 return ret; 6442 } 6443 ret = si_initialize_hardware_cac_manager(rdev); 6444 if (ret) { 6445 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6446 return ret; 6447 } 6448 ret = si_initialize_smc_dte_tables(rdev); 6449 if (ret) { 6450 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6451 return ret; 6452 } 6453 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6454 if (ret) { 6455 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6456 return ret; 6457 } 6458 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6459 if (ret) { 6460 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6461 return ret; 6462 } 6463 si_program_response_times(rdev); 6464 si_program_ds_registers(rdev); 6465 si_dpm_start_smc(rdev); 6466 ret = si_notify_smc_display_change(rdev, false); 6467 if (ret) { 6468 DRM_ERROR("si_notify_smc_display_change failed\n"); 6469 return ret; 6470 } 6471 si_enable_sclk_control(rdev, true); 6472 si_start_dpm(rdev); 6473 6474 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6475 6476 si_thermal_start_thermal_controller(rdev); 6477 6478 ni_update_current_ps(rdev, boot_ps); 6479 6480 return 0; 6481 } 6482 6483 static int si_set_temperature_range(struct radeon_device *rdev) 6484 { 6485 int ret; 6486 6487 ret = si_thermal_enable_alert(rdev, false); 6488 if (ret) 6489 return ret; 6490 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6491 if (ret) 6492 return ret; 6493 ret = si_thermal_enable_alert(rdev, true); 6494 if (ret) 6495 return ret; 6496 6497 return ret; 6498 } 6499 6500 int si_dpm_late_enable(struct radeon_device *rdev) 6501 { 6502 int ret; 6503 6504 ret = si_set_temperature_range(rdev); 6505 if (ret) 6506 return ret; 6507 6508 return ret; 6509 } 6510 6511 void si_dpm_disable(struct radeon_device *rdev) 6512 { 6513 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6514 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6515 6516 if (!si_is_smc_running(rdev)) 6517 return; 6518 si_thermal_stop_thermal_controller(rdev); 6519 si_disable_ulv(rdev); 6520 si_clear_vc(rdev); 6521 if (pi->thermal_protection) 6522 si_enable_thermal_protection(rdev, false); 6523 si_enable_power_containment(rdev, boot_ps, false); 6524 si_enable_smc_cac(rdev, boot_ps, false); 6525 si_enable_spread_spectrum(rdev, false); 6526 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6527 si_stop_dpm(rdev); 6528 si_reset_to_default(rdev); 6529 si_dpm_stop_smc(rdev); 6530 si_force_switch_to_arb_f0(rdev); 6531 6532 ni_update_current_ps(rdev, boot_ps); 6533 } 6534 6535 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6536 { 6537 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6538 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6539 struct radeon_ps *new_ps = &requested_ps; 6540 6541 ni_update_requested_ps(rdev, new_ps); 6542 6543 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6544 6545 return 0; 6546 } 6547 6548 static int si_power_control_set_level(struct radeon_device *rdev) 6549 { 6550 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6551 int ret; 6552 6553 ret = si_restrict_performance_levels_before_switch(rdev); 6554 if (ret) 6555 return ret; 6556 ret = si_halt_smc(rdev); 6557 if (ret) 6558 return ret; 6559 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6560 if (ret) 6561 return ret; 6562 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6563 if (ret) 6564 return ret; 6565 ret = si_resume_smc(rdev); 6566 if (ret) 6567 return ret; 6568 ret = si_set_sw_state(rdev); 6569 if (ret) 6570 return ret; 6571 return 0; 6572 } 6573 6574 int si_dpm_set_power_state(struct radeon_device *rdev) 6575 { 6576 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6577 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6578 struct radeon_ps *old_ps = &eg_pi->current_rps; 6579 int ret; 6580 6581 ret = si_disable_ulv(rdev); 6582 if (ret) { 6583 DRM_ERROR("si_disable_ulv failed\n"); 6584 return ret; 6585 } 6586 ret = si_restrict_performance_levels_before_switch(rdev); 6587 if (ret) { 6588 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6589 return ret; 6590 } 6591 if (eg_pi->pcie_performance_request) 6592 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6593 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6594 ret = si_enable_power_containment(rdev, new_ps, false); 6595 if (ret) { 6596 DRM_ERROR("si_enable_power_containment failed\n"); 6597 return ret; 6598 } 6599 ret = si_enable_smc_cac(rdev, new_ps, false); 6600 if (ret) { 6601 DRM_ERROR("si_enable_smc_cac failed\n"); 6602 return ret; 6603 } 6604 ret = si_halt_smc(rdev); 6605 if (ret) { 6606 DRM_ERROR("si_halt_smc failed\n"); 6607 return ret; 6608 } 6609 ret = si_upload_sw_state(rdev, new_ps); 6610 if (ret) { 6611 DRM_ERROR("si_upload_sw_state failed\n"); 6612 return ret; 6613 } 6614 ret = si_upload_smc_data(rdev); 6615 if (ret) { 6616 DRM_ERROR("si_upload_smc_data failed\n"); 6617 return ret; 6618 } 6619 ret = si_upload_ulv_state(rdev); 6620 if (ret) { 6621 DRM_ERROR("si_upload_ulv_state failed\n"); 6622 return ret; 6623 } 6624 if (eg_pi->dynamic_ac_timing) { 6625 ret = si_upload_mc_reg_table(rdev, new_ps); 6626 if (ret) { 6627 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6628 return ret; 6629 } 6630 } 6631 ret = si_program_memory_timing_parameters(rdev, new_ps); 6632 if (ret) { 6633 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6634 return ret; 6635 } 6636 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6637 6638 ret = si_resume_smc(rdev); 6639 if (ret) { 6640 DRM_ERROR("si_resume_smc failed\n"); 6641 return ret; 6642 } 6643 ret = si_set_sw_state(rdev); 6644 if (ret) { 6645 DRM_ERROR("si_set_sw_state failed\n"); 6646 return ret; 6647 } 6648 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6649 si_set_vce_clock(rdev, new_ps, old_ps); 6650 if (eg_pi->pcie_performance_request) 6651 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6652 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6653 if (ret) { 6654 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6655 return ret; 6656 } 6657 ret = si_enable_smc_cac(rdev, new_ps, true); 6658 if (ret) { 6659 DRM_ERROR("si_enable_smc_cac failed\n"); 6660 return ret; 6661 } 6662 ret = si_enable_power_containment(rdev, new_ps, true); 6663 if (ret) { 6664 DRM_ERROR("si_enable_power_containment failed\n"); 6665 return ret; 6666 } 6667 6668 ret = si_power_control_set_level(rdev); 6669 if (ret) { 6670 DRM_ERROR("si_power_control_set_level failed\n"); 6671 return ret; 6672 } 6673 6674 return 0; 6675 } 6676 6677 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6678 { 6679 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6680 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6681 6682 ni_update_current_ps(rdev, new_ps); 6683 } 6684 6685 #if 0 6686 void si_dpm_reset_asic(struct radeon_device *rdev) 6687 { 6688 si_restrict_performance_levels_before_switch(rdev); 6689 si_disable_ulv(rdev); 6690 si_set_boot_state(rdev); 6691 } 6692 #endif 6693 6694 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6695 { 6696 si_program_display_gap(rdev); 6697 } 6698 6699 union power_info { 6700 struct _ATOM_POWERPLAY_INFO info; 6701 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6702 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6703 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6704 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6705 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6706 }; 6707 6708 union pplib_clock_info { 6709 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6710 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6711 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6712 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6713 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6714 }; 6715 6716 union pplib_power_state { 6717 struct _ATOM_PPLIB_STATE v1; 6718 struct _ATOM_PPLIB_STATE_V2 v2; 6719 }; 6720 6721 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6722 struct radeon_ps *rps, 6723 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6724 u8 table_rev) 6725 { 6726 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6727 rps->class = le16_to_cpu(non_clock_info->usClassification); 6728 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6729 6730 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6731 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6732 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6733 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6734 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6735 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6736 } else { 6737 rps->vclk = 0; 6738 rps->dclk = 0; 6739 } 6740 6741 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6742 rdev->pm.dpm.boot_ps = rps; 6743 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6744 rdev->pm.dpm.uvd_ps = rps; 6745 } 6746 6747 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6748 struct radeon_ps *rps, int index, 6749 union pplib_clock_info *clock_info) 6750 { 6751 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6752 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6753 struct si_power_info *si_pi = si_get_pi(rdev); 6754 struct ni_ps *ps = ni_get_ps(rps); 6755 u16 leakage_voltage; 6756 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6757 int ret; 6758 6759 ps->performance_level_count = index + 1; 6760 6761 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6762 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6763 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6764 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6765 6766 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6767 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6768 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6769 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6770 si_pi->sys_pcie_mask, 6771 si_pi->boot_pcie_gen, 6772 clock_info->si.ucPCIEGen); 6773 6774 /* patch up vddc if necessary */ 6775 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6776 &leakage_voltage); 6777 if (ret == 0) 6778 pl->vddc = leakage_voltage; 6779 6780 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6781 pi->acpi_vddc = pl->vddc; 6782 eg_pi->acpi_vddci = pl->vddci; 6783 si_pi->acpi_pcie_gen = pl->pcie_gen; 6784 } 6785 6786 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6787 index == 0) { 6788 /* XXX disable for A0 tahiti */ 6789 si_pi->ulv.supported = false; 6790 si_pi->ulv.pl = *pl; 6791 si_pi->ulv.one_pcie_lane_in_ulv = false; 6792 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6793 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6794 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6795 } 6796 6797 if (pi->min_vddc_in_table > pl->vddc) 6798 pi->min_vddc_in_table = pl->vddc; 6799 6800 if (pi->max_vddc_in_table < pl->vddc) 6801 pi->max_vddc_in_table = pl->vddc; 6802 6803 /* patch up boot state */ 6804 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6805 u16 vddc, vddci, mvdd; 6806 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6807 pl->mclk = rdev->clock.default_mclk; 6808 pl->sclk = rdev->clock.default_sclk; 6809 pl->vddc = vddc; 6810 pl->vddci = vddci; 6811 si_pi->mvdd_bootup_value = mvdd; 6812 } 6813 6814 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6815 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6816 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6817 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6818 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6819 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6820 } 6821 } 6822 6823 static int si_parse_power_table(struct radeon_device *rdev) 6824 { 6825 struct radeon_mode_info *mode_info = &rdev->mode_info; 6826 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6827 union pplib_power_state *power_state; 6828 int i, j, k, non_clock_array_index, clock_array_index; 6829 union pplib_clock_info *clock_info; 6830 struct _StateArray *state_array; 6831 struct _ClockInfoArray *clock_info_array; 6832 struct _NonClockInfoArray *non_clock_info_array; 6833 union power_info *power_info; 6834 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6835 u16 data_offset; 6836 u8 frev, crev; 6837 u8 *power_state_offset; 6838 struct ni_ps *ps; 6839 6840 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6841 &frev, &crev, &data_offset)) 6842 return -EINVAL; 6843 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6844 6845 state_array = (struct _StateArray *) 6846 (mode_info->atom_context->bios + data_offset + 6847 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6848 clock_info_array = (struct _ClockInfoArray *) 6849 (mode_info->atom_context->bios + data_offset + 6850 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6851 non_clock_info_array = (struct _NonClockInfoArray *) 6852 (mode_info->atom_context->bios + data_offset + 6853 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6854 6855 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6856 state_array->ucNumEntries, GFP_KERNEL); 6857 if (!rdev->pm.dpm.ps) 6858 return -ENOMEM; 6859 power_state_offset = (u8 *)state_array->states; 6860 for (i = 0; i < state_array->ucNumEntries; i++) { 6861 u8 *idx; 6862 power_state = (union pplib_power_state *)power_state_offset; 6863 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6864 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6865 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6866 if (!rdev->pm.power_state[i].clock_info) 6867 return -EINVAL; 6868 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6869 if (ps == NULL) { 6870 kfree(rdev->pm.dpm.ps); 6871 return -ENOMEM; 6872 } 6873 rdev->pm.dpm.ps[i].ps_priv = ps; 6874 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6875 non_clock_info, 6876 non_clock_info_array->ucEntrySize); 6877 k = 0; 6878 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6879 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6880 clock_array_index = idx[j]; 6881 if (clock_array_index >= clock_info_array->ucNumEntries) 6882 continue; 6883 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6884 break; 6885 clock_info = (union pplib_clock_info *) 6886 ((u8 *)&clock_info_array->clockInfo[0] + 6887 (clock_array_index * clock_info_array->ucEntrySize)); 6888 si_parse_pplib_clock_info(rdev, 6889 &rdev->pm.dpm.ps[i], k, 6890 clock_info); 6891 k++; 6892 } 6893 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6894 } 6895 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6896 6897 /* fill in the vce power states */ 6898 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6899 u32 sclk, mclk; 6900 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6901 clock_info = (union pplib_clock_info *) 6902 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6903 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6904 sclk |= clock_info->si.ucEngineClockHigh << 16; 6905 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6906 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6907 rdev->pm.dpm.vce_states[i].sclk = sclk; 6908 rdev->pm.dpm.vce_states[i].mclk = mclk; 6909 } 6910 6911 return 0; 6912 } 6913 6914 int si_dpm_init(struct radeon_device *rdev) 6915 { 6916 struct rv7xx_power_info *pi; 6917 struct evergreen_power_info *eg_pi; 6918 struct ni_power_info *ni_pi; 6919 struct si_power_info *si_pi; 6920 struct atom_clock_dividers dividers; 6921 int ret; 6922 u32 mask; 6923 6924 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6925 if (si_pi == NULL) 6926 return -ENOMEM; 6927 rdev->pm.dpm.priv = si_pi; 6928 ni_pi = &si_pi->ni; 6929 eg_pi = &ni_pi->eg; 6930 pi = &eg_pi->rv7xx; 6931 6932 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6933 if (ret) 6934 si_pi->sys_pcie_mask = 0; 6935 else 6936 si_pi->sys_pcie_mask = mask; 6937 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6938 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6939 6940 si_set_max_cu_value(rdev); 6941 6942 rv770_get_max_vddc(rdev); 6943 si_get_leakage_vddc(rdev); 6944 si_patch_dependency_tables_based_on_leakage(rdev); 6945 6946 pi->acpi_vddc = 0; 6947 eg_pi->acpi_vddci = 0; 6948 pi->min_vddc_in_table = 0; 6949 pi->max_vddc_in_table = 0; 6950 6951 ret = r600_get_platform_caps(rdev); 6952 if (ret) 6953 return ret; 6954 6955 ret = r600_parse_extended_power_table(rdev); 6956 if (ret) 6957 return ret; 6958 6959 ret = si_parse_power_table(rdev); 6960 if (ret) 6961 return ret; 6962 6963 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6964 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6965 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6966 r600_free_extended_power_table(rdev); 6967 return -ENOMEM; 6968 } 6969 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6970 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6971 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6972 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6973 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6974 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6975 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6976 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6977 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6978 6979 if (rdev->pm.dpm.voltage_response_time == 0) 6980 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6981 if (rdev->pm.dpm.backbias_response_time == 0) 6982 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6983 6984 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6985 0, false, ÷rs); 6986 if (ret) 6987 pi->ref_div = dividers.ref_div + 1; 6988 else 6989 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6990 6991 eg_pi->smu_uvd_hs = false; 6992 6993 pi->mclk_strobe_mode_threshold = 40000; 6994 if (si_is_special_1gb_platform(rdev)) 6995 pi->mclk_stutter_mode_threshold = 0; 6996 else 6997 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6998 pi->mclk_edc_enable_threshold = 40000; 6999 eg_pi->mclk_edc_wr_enable_threshold = 40000; 7000 7001 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7002 7003 pi->voltage_control = 7004 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7005 VOLTAGE_OBJ_GPIO_LUT); 7006 if (!pi->voltage_control) { 7007 si_pi->voltage_control_svi2 = 7008 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7009 VOLTAGE_OBJ_SVID2); 7010 if (si_pi->voltage_control_svi2) 7011 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7012 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7013 } 7014 7015 pi->mvdd_control = 7016 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7017 VOLTAGE_OBJ_GPIO_LUT); 7018 7019 eg_pi->vddci_control = 7020 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7021 VOLTAGE_OBJ_GPIO_LUT); 7022 if (!eg_pi->vddci_control) 7023 si_pi->vddci_control_svi2 = 7024 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7025 VOLTAGE_OBJ_SVID2); 7026 7027 si_pi->vddc_phase_shed_control = 7028 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7029 VOLTAGE_OBJ_PHASE_LUT); 7030 7031 rv770_get_engine_memory_ss(rdev); 7032 7033 pi->asi = RV770_ASI_DFLT; 7034 pi->pasi = CYPRESS_HASI_DFLT; 7035 pi->vrc = SISLANDS_VRC_DFLT; 7036 7037 pi->gfx_clock_gating = true; 7038 7039 eg_pi->sclk_deep_sleep = true; 7040 si_pi->sclk_deep_sleep_above_low = false; 7041 7042 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7043 pi->thermal_protection = true; 7044 else 7045 pi->thermal_protection = false; 7046 7047 eg_pi->dynamic_ac_timing = true; 7048 7049 eg_pi->light_sleep = true; 7050 #if defined(CONFIG_ACPI) 7051 eg_pi->pcie_performance_request = 7052 radeon_acpi_is_pcie_performance_request_supported(rdev); 7053 #else 7054 eg_pi->pcie_performance_request = false; 7055 #endif 7056 7057 si_pi->sram_end = SMC_RAM_END; 7058 7059 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7060 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7061 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7062 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7063 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7064 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7065 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7066 7067 si_initialize_powertune_defaults(rdev); 7068 7069 /* make sure dc limits are valid */ 7070 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7071 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7072 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7073 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7074 7075 si_pi->fan_ctrl_is_in_default_mode = true; 7076 7077 return 0; 7078 } 7079 7080 void si_dpm_fini(struct radeon_device *rdev) 7081 { 7082 int i; 7083 7084 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7085 kfree(rdev->pm.dpm.ps[i].ps_priv); 7086 } 7087 kfree(rdev->pm.dpm.ps); 7088 kfree(rdev->pm.dpm.priv); 7089 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7090 r600_free_extended_power_table(rdev); 7091 } 7092 7093 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7094 struct seq_file *m) 7095 { 7096 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7097 struct radeon_ps *rps = &eg_pi->current_rps; 7098 struct ni_ps *ps = ni_get_ps(rps); 7099 struct rv7xx_pl *pl; 7100 u32 current_index = 7101 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7102 CURRENT_STATE_INDEX_SHIFT; 7103 7104 if (current_index >= ps->performance_level_count) { 7105 seq_printf(m, "invalid dpm profile %d\n", current_index); 7106 } else { 7107 pl = &ps->performance_levels[current_index]; 7108 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7109 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7110 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7111 } 7112 } 7113 7114 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7115 { 7116 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7117 struct radeon_ps *rps = &eg_pi->current_rps; 7118 struct ni_ps *ps = ni_get_ps(rps); 7119 struct rv7xx_pl *pl; 7120 u32 current_index = 7121 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7122 CURRENT_STATE_INDEX_SHIFT; 7123 7124 if (current_index >= ps->performance_level_count) { 7125 return 0; 7126 } else { 7127 pl = &ps->performance_levels[current_index]; 7128 return pl->sclk; 7129 } 7130 } 7131 7132 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7133 { 7134 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7135 struct radeon_ps *rps = &eg_pi->current_rps; 7136 struct ni_ps *ps = ni_get_ps(rps); 7137 struct rv7xx_pl *pl; 7138 u32 current_index = 7139 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7140 CURRENT_STATE_INDEX_SHIFT; 7141 7142 if (current_index >= ps->performance_level_count) { 7143 return 0; 7144 } else { 7145 pl = &ps->performance_levels[current_index]; 7146 return pl->mclk; 7147 } 7148 } 7149