1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/firmware.h> 29 #include <drm/drmP.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "radeon_audio.h" 33 #include <drm/radeon_drm.h> 34 #include "rv770d.h" 35 #include "atom.h" 36 #include "avivod.h" 37 38 #define R700_PFP_UCODE_SIZE 848 39 #define R700_PM4_UCODE_SIZE 1360 40 41 static void rv770_gpu_init(struct radeon_device *rdev); 42 static void rv770_pcie_gen2_enable(struct radeon_device *rdev); 43 44 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 45 { 46 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; 47 int r; 48 49 /* RV740 uses evergreen uvd clk programming */ 50 if (rdev->family == CHIP_RV740) 51 return evergreen_set_uvd_clocks(rdev, vclk, dclk); 52 53 /* bypass vclk and dclk with bclk */ 54 WREG32_P(CG_UPLL_FUNC_CNTL_2, 55 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 56 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 57 58 if (!vclk || !dclk) { 59 /* keep the Bypass mode, put PLL to sleep */ 60 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 61 return 0; 62 } 63 64 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, 65 43663, 0x03FFFFFE, 1, 30, ~0, 66 &fb_div, &vclk_div, &dclk_div); 67 if (r) 68 return r; 69 70 fb_div |= 1; 71 vclk_div -= 1; 72 dclk_div -= 1; 73 74 /* set UPLL_FB_DIV to 0x50000 */ 75 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); 76 77 /* deassert UPLL_RESET and UPLL_SLEEP */ 78 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); 79 80 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ 81 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); 82 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); 83 84 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 85 if (r) 86 return r; 87 88 /* assert PLL_RESET */ 89 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 90 91 /* set the required FB_DIV, REF_DIV, Post divder values */ 92 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); 93 WREG32_P(CG_UPLL_FUNC_CNTL_2, 94 UPLL_SW_HILEN(vclk_div >> 1) | 95 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | 96 UPLL_SW_HILEN2(dclk_div >> 1) | 97 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)), 98 ~UPLL_SW_MASK); 99 100 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), 101 ~UPLL_FB_DIV_MASK); 102 103 /* give the PLL some time to settle */ 104 mdelay(15); 105 106 /* deassert PLL_RESET */ 107 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 108 109 mdelay(15); 110 111 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ 112 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 113 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); 114 115 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 116 if (r) 117 return r; 118 119 /* switch VCLK and DCLK selection */ 120 WREG32_P(CG_UPLL_FUNC_CNTL_2, 121 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 122 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 123 124 mdelay(100); 125 126 return 0; 127 } 128 129 static const u32 r7xx_golden_registers[] = 130 { 131 0x8d00, 0xffffffff, 0x0e0e0074, 132 0x8d04, 0xffffffff, 0x013a2b34, 133 0x9508, 0xffffffff, 0x00000002, 134 0x8b20, 0xffffffff, 0, 135 0x88c4, 0xffffffff, 0x000000c2, 136 0x28350, 0xffffffff, 0, 137 0x9058, 0xffffffff, 0x0fffc40f, 138 0x240c, 0xffffffff, 0x00000380, 139 0x733c, 0xffffffff, 0x00000002, 140 0x2650, 0x00040000, 0, 141 0x20bc, 0x00040000, 0, 142 0x7300, 0xffffffff, 0x001000f0 143 }; 144 145 static const u32 r7xx_golden_dyn_gpr_registers[] = 146 { 147 0x8db0, 0xffffffff, 0x98989898, 148 0x8db4, 0xffffffff, 0x98989898, 149 0x8db8, 0xffffffff, 0x98989898, 150 0x8dbc, 0xffffffff, 0x98989898, 151 0x8dc0, 0xffffffff, 0x98989898, 152 0x8dc4, 0xffffffff, 0x98989898, 153 0x8dc8, 0xffffffff, 0x98989898, 154 0x8dcc, 0xffffffff, 0x98989898, 155 0x88c4, 0xffffffff, 0x00000082 156 }; 157 158 static const u32 rv770_golden_registers[] = 159 { 160 0x562c, 0xffffffff, 0, 161 0x3f90, 0xffffffff, 0, 162 0x9148, 0xffffffff, 0, 163 0x3f94, 0xffffffff, 0, 164 0x914c, 0xffffffff, 0, 165 0x9698, 0x18000000, 0x18000000 166 }; 167 168 static const u32 rv770ce_golden_registers[] = 169 { 170 0x562c, 0xffffffff, 0, 171 0x3f90, 0xffffffff, 0x00cc0000, 172 0x9148, 0xffffffff, 0x00cc0000, 173 0x3f94, 0xffffffff, 0x00cc0000, 174 0x914c, 0xffffffff, 0x00cc0000, 175 0x9b7c, 0xffffffff, 0x00fa0000, 176 0x3f8c, 0xffffffff, 0x00fa0000, 177 0x9698, 0x18000000, 0x18000000 178 }; 179 180 static const u32 rv770_mgcg_init[] = 181 { 182 0x8bcc, 0xffffffff, 0x130300f9, 183 0x5448, 0xffffffff, 0x100, 184 0x55e4, 0xffffffff, 0x100, 185 0x160c, 0xffffffff, 0x100, 186 0x5644, 0xffffffff, 0x100, 187 0xc164, 0xffffffff, 0x100, 188 0x8a18, 0xffffffff, 0x100, 189 0x897c, 0xffffffff, 0x8000100, 190 0x8b28, 0xffffffff, 0x3c000100, 191 0x9144, 0xffffffff, 0x100, 192 0x9a1c, 0xffffffff, 0x10000, 193 0x9a50, 0xffffffff, 0x100, 194 0x9a1c, 0xffffffff, 0x10001, 195 0x9a50, 0xffffffff, 0x100, 196 0x9a1c, 0xffffffff, 0x10002, 197 0x9a50, 0xffffffff, 0x100, 198 0x9a1c, 0xffffffff, 0x10003, 199 0x9a50, 0xffffffff, 0x100, 200 0x9a1c, 0xffffffff, 0x0, 201 0x9870, 0xffffffff, 0x100, 202 0x8d58, 0xffffffff, 0x100, 203 0x9500, 0xffffffff, 0x0, 204 0x9510, 0xffffffff, 0x100, 205 0x9500, 0xffffffff, 0x1, 206 0x9510, 0xffffffff, 0x100, 207 0x9500, 0xffffffff, 0x2, 208 0x9510, 0xffffffff, 0x100, 209 0x9500, 0xffffffff, 0x3, 210 0x9510, 0xffffffff, 0x100, 211 0x9500, 0xffffffff, 0x4, 212 0x9510, 0xffffffff, 0x100, 213 0x9500, 0xffffffff, 0x5, 214 0x9510, 0xffffffff, 0x100, 215 0x9500, 0xffffffff, 0x6, 216 0x9510, 0xffffffff, 0x100, 217 0x9500, 0xffffffff, 0x7, 218 0x9510, 0xffffffff, 0x100, 219 0x9500, 0xffffffff, 0x8, 220 0x9510, 0xffffffff, 0x100, 221 0x9500, 0xffffffff, 0x9, 222 0x9510, 0xffffffff, 0x100, 223 0x9500, 0xffffffff, 0x8000, 224 0x9490, 0xffffffff, 0x0, 225 0x949c, 0xffffffff, 0x100, 226 0x9490, 0xffffffff, 0x1, 227 0x949c, 0xffffffff, 0x100, 228 0x9490, 0xffffffff, 0x2, 229 0x949c, 0xffffffff, 0x100, 230 0x9490, 0xffffffff, 0x3, 231 0x949c, 0xffffffff, 0x100, 232 0x9490, 0xffffffff, 0x4, 233 0x949c, 0xffffffff, 0x100, 234 0x9490, 0xffffffff, 0x5, 235 0x949c, 0xffffffff, 0x100, 236 0x9490, 0xffffffff, 0x6, 237 0x949c, 0xffffffff, 0x100, 238 0x9490, 0xffffffff, 0x7, 239 0x949c, 0xffffffff, 0x100, 240 0x9490, 0xffffffff, 0x8, 241 0x949c, 0xffffffff, 0x100, 242 0x9490, 0xffffffff, 0x9, 243 0x949c, 0xffffffff, 0x100, 244 0x9490, 0xffffffff, 0x8000, 245 0x9604, 0xffffffff, 0x0, 246 0x9654, 0xffffffff, 0x100, 247 0x9604, 0xffffffff, 0x1, 248 0x9654, 0xffffffff, 0x100, 249 0x9604, 0xffffffff, 0x2, 250 0x9654, 0xffffffff, 0x100, 251 0x9604, 0xffffffff, 0x3, 252 0x9654, 0xffffffff, 0x100, 253 0x9604, 0xffffffff, 0x4, 254 0x9654, 0xffffffff, 0x100, 255 0x9604, 0xffffffff, 0x5, 256 0x9654, 0xffffffff, 0x100, 257 0x9604, 0xffffffff, 0x6, 258 0x9654, 0xffffffff, 0x100, 259 0x9604, 0xffffffff, 0x7, 260 0x9654, 0xffffffff, 0x100, 261 0x9604, 0xffffffff, 0x8, 262 0x9654, 0xffffffff, 0x100, 263 0x9604, 0xffffffff, 0x9, 264 0x9654, 0xffffffff, 0x100, 265 0x9604, 0xffffffff, 0x80000000, 266 0x9030, 0xffffffff, 0x100, 267 0x9034, 0xffffffff, 0x100, 268 0x9038, 0xffffffff, 0x100, 269 0x903c, 0xffffffff, 0x100, 270 0x9040, 0xffffffff, 0x100, 271 0xa200, 0xffffffff, 0x100, 272 0xa204, 0xffffffff, 0x100, 273 0xa208, 0xffffffff, 0x100, 274 0xa20c, 0xffffffff, 0x100, 275 0x971c, 0xffffffff, 0x100, 276 0x915c, 0xffffffff, 0x00020001, 277 0x9160, 0xffffffff, 0x00040003, 278 0x916c, 0xffffffff, 0x00060005, 279 0x9170, 0xffffffff, 0x00080007, 280 0x9174, 0xffffffff, 0x000a0009, 281 0x9178, 0xffffffff, 0x000c000b, 282 0x917c, 0xffffffff, 0x000e000d, 283 0x9180, 0xffffffff, 0x0010000f, 284 0x918c, 0xffffffff, 0x00120011, 285 0x9190, 0xffffffff, 0x00140013, 286 0x9194, 0xffffffff, 0x00020001, 287 0x9198, 0xffffffff, 0x00040003, 288 0x919c, 0xffffffff, 0x00060005, 289 0x91a8, 0xffffffff, 0x00080007, 290 0x91ac, 0xffffffff, 0x000a0009, 291 0x91b0, 0xffffffff, 0x000c000b, 292 0x91b4, 0xffffffff, 0x000e000d, 293 0x91b8, 0xffffffff, 0x0010000f, 294 0x91c4, 0xffffffff, 0x00120011, 295 0x91c8, 0xffffffff, 0x00140013, 296 0x91cc, 0xffffffff, 0x00020001, 297 0x91d0, 0xffffffff, 0x00040003, 298 0x91d4, 0xffffffff, 0x00060005, 299 0x91e0, 0xffffffff, 0x00080007, 300 0x91e4, 0xffffffff, 0x000a0009, 301 0x91e8, 0xffffffff, 0x000c000b, 302 0x91ec, 0xffffffff, 0x00020001, 303 0x91f0, 0xffffffff, 0x00040003, 304 0x91f4, 0xffffffff, 0x00060005, 305 0x9200, 0xffffffff, 0x00080007, 306 0x9204, 0xffffffff, 0x000a0009, 307 0x9208, 0xffffffff, 0x000c000b, 308 0x920c, 0xffffffff, 0x000e000d, 309 0x9210, 0xffffffff, 0x0010000f, 310 0x921c, 0xffffffff, 0x00120011, 311 0x9220, 0xffffffff, 0x00140013, 312 0x9224, 0xffffffff, 0x00020001, 313 0x9228, 0xffffffff, 0x00040003, 314 0x922c, 0xffffffff, 0x00060005, 315 0x9238, 0xffffffff, 0x00080007, 316 0x923c, 0xffffffff, 0x000a0009, 317 0x9240, 0xffffffff, 0x000c000b, 318 0x9244, 0xffffffff, 0x000e000d, 319 0x9248, 0xffffffff, 0x0010000f, 320 0x9254, 0xffffffff, 0x00120011, 321 0x9258, 0xffffffff, 0x00140013, 322 0x925c, 0xffffffff, 0x00020001, 323 0x9260, 0xffffffff, 0x00040003, 324 0x9264, 0xffffffff, 0x00060005, 325 0x9270, 0xffffffff, 0x00080007, 326 0x9274, 0xffffffff, 0x000a0009, 327 0x9278, 0xffffffff, 0x000c000b, 328 0x927c, 0xffffffff, 0x000e000d, 329 0x9280, 0xffffffff, 0x0010000f, 330 0x928c, 0xffffffff, 0x00120011, 331 0x9290, 0xffffffff, 0x00140013, 332 0x9294, 0xffffffff, 0x00020001, 333 0x929c, 0xffffffff, 0x00040003, 334 0x92a0, 0xffffffff, 0x00060005, 335 0x92a4, 0xffffffff, 0x00080007 336 }; 337 338 static const u32 rv710_golden_registers[] = 339 { 340 0x3f90, 0x00ff0000, 0x00fc0000, 341 0x9148, 0x00ff0000, 0x00fc0000, 342 0x3f94, 0x00ff0000, 0x00fc0000, 343 0x914c, 0x00ff0000, 0x00fc0000, 344 0xb4c, 0x00000020, 0x00000020, 345 0xa180, 0xffffffff, 0x00003f3f 346 }; 347 348 static const u32 rv710_mgcg_init[] = 349 { 350 0x8bcc, 0xffffffff, 0x13030040, 351 0x5448, 0xffffffff, 0x100, 352 0x55e4, 0xffffffff, 0x100, 353 0x160c, 0xffffffff, 0x100, 354 0x5644, 0xffffffff, 0x100, 355 0xc164, 0xffffffff, 0x100, 356 0x8a18, 0xffffffff, 0x100, 357 0x897c, 0xffffffff, 0x8000100, 358 0x8b28, 0xffffffff, 0x3c000100, 359 0x9144, 0xffffffff, 0x100, 360 0x9a1c, 0xffffffff, 0x10000, 361 0x9a50, 0xffffffff, 0x100, 362 0x9a1c, 0xffffffff, 0x0, 363 0x9870, 0xffffffff, 0x100, 364 0x8d58, 0xffffffff, 0x100, 365 0x9500, 0xffffffff, 0x0, 366 0x9510, 0xffffffff, 0x100, 367 0x9500, 0xffffffff, 0x1, 368 0x9510, 0xffffffff, 0x100, 369 0x9500, 0xffffffff, 0x8000, 370 0x9490, 0xffffffff, 0x0, 371 0x949c, 0xffffffff, 0x100, 372 0x9490, 0xffffffff, 0x1, 373 0x949c, 0xffffffff, 0x100, 374 0x9490, 0xffffffff, 0x8000, 375 0x9604, 0xffffffff, 0x0, 376 0x9654, 0xffffffff, 0x100, 377 0x9604, 0xffffffff, 0x1, 378 0x9654, 0xffffffff, 0x100, 379 0x9604, 0xffffffff, 0x80000000, 380 0x9030, 0xffffffff, 0x100, 381 0x9034, 0xffffffff, 0x100, 382 0x9038, 0xffffffff, 0x100, 383 0x903c, 0xffffffff, 0x100, 384 0x9040, 0xffffffff, 0x100, 385 0xa200, 0xffffffff, 0x100, 386 0xa204, 0xffffffff, 0x100, 387 0xa208, 0xffffffff, 0x100, 388 0xa20c, 0xffffffff, 0x100, 389 0x971c, 0xffffffff, 0x100, 390 0x915c, 0xffffffff, 0x00020001, 391 0x9174, 0xffffffff, 0x00000003, 392 0x9178, 0xffffffff, 0x00050001, 393 0x917c, 0xffffffff, 0x00030002, 394 0x918c, 0xffffffff, 0x00000004, 395 0x9190, 0xffffffff, 0x00070006, 396 0x9194, 0xffffffff, 0x00050001, 397 0x9198, 0xffffffff, 0x00030002, 398 0x91a8, 0xffffffff, 0x00000004, 399 0x91ac, 0xffffffff, 0x00070006, 400 0x91e8, 0xffffffff, 0x00000001, 401 0x9294, 0xffffffff, 0x00000001, 402 0x929c, 0xffffffff, 0x00000002, 403 0x92a0, 0xffffffff, 0x00040003, 404 0x9150, 0xffffffff, 0x4d940000 405 }; 406 407 static const u32 rv730_golden_registers[] = 408 { 409 0x3f90, 0x00ff0000, 0x00f00000, 410 0x9148, 0x00ff0000, 0x00f00000, 411 0x3f94, 0x00ff0000, 0x00f00000, 412 0x914c, 0x00ff0000, 0x00f00000, 413 0x900c, 0xffffffff, 0x003b033f, 414 0xb4c, 0x00000020, 0x00000020, 415 0xa180, 0xffffffff, 0x00003f3f 416 }; 417 418 static const u32 rv730_mgcg_init[] = 419 { 420 0x8bcc, 0xffffffff, 0x130300f9, 421 0x5448, 0xffffffff, 0x100, 422 0x55e4, 0xffffffff, 0x100, 423 0x160c, 0xffffffff, 0x100, 424 0x5644, 0xffffffff, 0x100, 425 0xc164, 0xffffffff, 0x100, 426 0x8a18, 0xffffffff, 0x100, 427 0x897c, 0xffffffff, 0x8000100, 428 0x8b28, 0xffffffff, 0x3c000100, 429 0x9144, 0xffffffff, 0x100, 430 0x9a1c, 0xffffffff, 0x10000, 431 0x9a50, 0xffffffff, 0x100, 432 0x9a1c, 0xffffffff, 0x10001, 433 0x9a50, 0xffffffff, 0x100, 434 0x9a1c, 0xffffffff, 0x0, 435 0x9870, 0xffffffff, 0x100, 436 0x8d58, 0xffffffff, 0x100, 437 0x9500, 0xffffffff, 0x0, 438 0x9510, 0xffffffff, 0x100, 439 0x9500, 0xffffffff, 0x1, 440 0x9510, 0xffffffff, 0x100, 441 0x9500, 0xffffffff, 0x2, 442 0x9510, 0xffffffff, 0x100, 443 0x9500, 0xffffffff, 0x3, 444 0x9510, 0xffffffff, 0x100, 445 0x9500, 0xffffffff, 0x4, 446 0x9510, 0xffffffff, 0x100, 447 0x9500, 0xffffffff, 0x5, 448 0x9510, 0xffffffff, 0x100, 449 0x9500, 0xffffffff, 0x6, 450 0x9510, 0xffffffff, 0x100, 451 0x9500, 0xffffffff, 0x7, 452 0x9510, 0xffffffff, 0x100, 453 0x9500, 0xffffffff, 0x8000, 454 0x9490, 0xffffffff, 0x0, 455 0x949c, 0xffffffff, 0x100, 456 0x9490, 0xffffffff, 0x1, 457 0x949c, 0xffffffff, 0x100, 458 0x9490, 0xffffffff, 0x2, 459 0x949c, 0xffffffff, 0x100, 460 0x9490, 0xffffffff, 0x3, 461 0x949c, 0xffffffff, 0x100, 462 0x9490, 0xffffffff, 0x4, 463 0x949c, 0xffffffff, 0x100, 464 0x9490, 0xffffffff, 0x5, 465 0x949c, 0xffffffff, 0x100, 466 0x9490, 0xffffffff, 0x6, 467 0x949c, 0xffffffff, 0x100, 468 0x9490, 0xffffffff, 0x7, 469 0x949c, 0xffffffff, 0x100, 470 0x9490, 0xffffffff, 0x8000, 471 0x9604, 0xffffffff, 0x0, 472 0x9654, 0xffffffff, 0x100, 473 0x9604, 0xffffffff, 0x1, 474 0x9654, 0xffffffff, 0x100, 475 0x9604, 0xffffffff, 0x2, 476 0x9654, 0xffffffff, 0x100, 477 0x9604, 0xffffffff, 0x3, 478 0x9654, 0xffffffff, 0x100, 479 0x9604, 0xffffffff, 0x4, 480 0x9654, 0xffffffff, 0x100, 481 0x9604, 0xffffffff, 0x5, 482 0x9654, 0xffffffff, 0x100, 483 0x9604, 0xffffffff, 0x6, 484 0x9654, 0xffffffff, 0x100, 485 0x9604, 0xffffffff, 0x7, 486 0x9654, 0xffffffff, 0x100, 487 0x9604, 0xffffffff, 0x80000000, 488 0x9030, 0xffffffff, 0x100, 489 0x9034, 0xffffffff, 0x100, 490 0x9038, 0xffffffff, 0x100, 491 0x903c, 0xffffffff, 0x100, 492 0x9040, 0xffffffff, 0x100, 493 0xa200, 0xffffffff, 0x100, 494 0xa204, 0xffffffff, 0x100, 495 0xa208, 0xffffffff, 0x100, 496 0xa20c, 0xffffffff, 0x100, 497 0x971c, 0xffffffff, 0x100, 498 0x915c, 0xffffffff, 0x00020001, 499 0x916c, 0xffffffff, 0x00040003, 500 0x9170, 0xffffffff, 0x00000005, 501 0x9178, 0xffffffff, 0x00050001, 502 0x917c, 0xffffffff, 0x00030002, 503 0x918c, 0xffffffff, 0x00000004, 504 0x9190, 0xffffffff, 0x00070006, 505 0x9194, 0xffffffff, 0x00050001, 506 0x9198, 0xffffffff, 0x00030002, 507 0x91a8, 0xffffffff, 0x00000004, 508 0x91ac, 0xffffffff, 0x00070006, 509 0x91b0, 0xffffffff, 0x00050001, 510 0x91b4, 0xffffffff, 0x00030002, 511 0x91c4, 0xffffffff, 0x00000004, 512 0x91c8, 0xffffffff, 0x00070006, 513 0x91cc, 0xffffffff, 0x00050001, 514 0x91d0, 0xffffffff, 0x00030002, 515 0x91e0, 0xffffffff, 0x00000004, 516 0x91e4, 0xffffffff, 0x00070006, 517 0x91e8, 0xffffffff, 0x00000001, 518 0x91ec, 0xffffffff, 0x00050001, 519 0x91f0, 0xffffffff, 0x00030002, 520 0x9200, 0xffffffff, 0x00000004, 521 0x9204, 0xffffffff, 0x00070006, 522 0x9208, 0xffffffff, 0x00050001, 523 0x920c, 0xffffffff, 0x00030002, 524 0x921c, 0xffffffff, 0x00000004, 525 0x9220, 0xffffffff, 0x00070006, 526 0x9224, 0xffffffff, 0x00050001, 527 0x9228, 0xffffffff, 0x00030002, 528 0x9238, 0xffffffff, 0x00000004, 529 0x923c, 0xffffffff, 0x00070006, 530 0x9240, 0xffffffff, 0x00050001, 531 0x9244, 0xffffffff, 0x00030002, 532 0x9254, 0xffffffff, 0x00000004, 533 0x9258, 0xffffffff, 0x00070006, 534 0x9294, 0xffffffff, 0x00000001, 535 0x929c, 0xffffffff, 0x00000002, 536 0x92a0, 0xffffffff, 0x00040003, 537 0x92a4, 0xffffffff, 0x00000005 538 }; 539 540 static const u32 rv740_golden_registers[] = 541 { 542 0x88c4, 0xffffffff, 0x00000082, 543 0x28a50, 0xfffffffc, 0x00000004, 544 0x2650, 0x00040000, 0, 545 0x20bc, 0x00040000, 0, 546 0x733c, 0xffffffff, 0x00000002, 547 0x7300, 0xffffffff, 0x001000f0, 548 0x3f90, 0x00ff0000, 0, 549 0x9148, 0x00ff0000, 0, 550 0x3f94, 0x00ff0000, 0, 551 0x914c, 0x00ff0000, 0, 552 0x240c, 0xffffffff, 0x00000380, 553 0x8a14, 0x00000007, 0x00000007, 554 0x8b24, 0xffffffff, 0x00ff0fff, 555 0x28a4c, 0xffffffff, 0x00004000, 556 0xa180, 0xffffffff, 0x00003f3f, 557 0x8d00, 0xffffffff, 0x0e0e003a, 558 0x8d04, 0xffffffff, 0x013a0e2a, 559 0x8c00, 0xffffffff, 0xe400000f, 560 0x8db0, 0xffffffff, 0x98989898, 561 0x8db4, 0xffffffff, 0x98989898, 562 0x8db8, 0xffffffff, 0x98989898, 563 0x8dbc, 0xffffffff, 0x98989898, 564 0x8dc0, 0xffffffff, 0x98989898, 565 0x8dc4, 0xffffffff, 0x98989898, 566 0x8dc8, 0xffffffff, 0x98989898, 567 0x8dcc, 0xffffffff, 0x98989898, 568 0x9058, 0xffffffff, 0x0fffc40f, 569 0x900c, 0xffffffff, 0x003b033f, 570 0x28350, 0xffffffff, 0, 571 0x8cf0, 0x1fffffff, 0x08e00420, 572 0x9508, 0xffffffff, 0x00000002, 573 0x88c4, 0xffffffff, 0x000000c2, 574 0x9698, 0x18000000, 0x18000000 575 }; 576 577 static const u32 rv740_mgcg_init[] = 578 { 579 0x8bcc, 0xffffffff, 0x13030100, 580 0x5448, 0xffffffff, 0x100, 581 0x55e4, 0xffffffff, 0x100, 582 0x160c, 0xffffffff, 0x100, 583 0x5644, 0xffffffff, 0x100, 584 0xc164, 0xffffffff, 0x100, 585 0x8a18, 0xffffffff, 0x100, 586 0x897c, 0xffffffff, 0x100, 587 0x8b28, 0xffffffff, 0x100, 588 0x9144, 0xffffffff, 0x100, 589 0x9a1c, 0xffffffff, 0x10000, 590 0x9a50, 0xffffffff, 0x100, 591 0x9a1c, 0xffffffff, 0x10001, 592 0x9a50, 0xffffffff, 0x100, 593 0x9a1c, 0xffffffff, 0x10002, 594 0x9a50, 0xffffffff, 0x100, 595 0x9a1c, 0xffffffff, 0x10003, 596 0x9a50, 0xffffffff, 0x100, 597 0x9a1c, 0xffffffff, 0x0, 598 0x9870, 0xffffffff, 0x100, 599 0x8d58, 0xffffffff, 0x100, 600 0x9500, 0xffffffff, 0x0, 601 0x9510, 0xffffffff, 0x100, 602 0x9500, 0xffffffff, 0x1, 603 0x9510, 0xffffffff, 0x100, 604 0x9500, 0xffffffff, 0x2, 605 0x9510, 0xffffffff, 0x100, 606 0x9500, 0xffffffff, 0x3, 607 0x9510, 0xffffffff, 0x100, 608 0x9500, 0xffffffff, 0x4, 609 0x9510, 0xffffffff, 0x100, 610 0x9500, 0xffffffff, 0x5, 611 0x9510, 0xffffffff, 0x100, 612 0x9500, 0xffffffff, 0x6, 613 0x9510, 0xffffffff, 0x100, 614 0x9500, 0xffffffff, 0x7, 615 0x9510, 0xffffffff, 0x100, 616 0x9500, 0xffffffff, 0x8000, 617 0x9490, 0xffffffff, 0x0, 618 0x949c, 0xffffffff, 0x100, 619 0x9490, 0xffffffff, 0x1, 620 0x949c, 0xffffffff, 0x100, 621 0x9490, 0xffffffff, 0x2, 622 0x949c, 0xffffffff, 0x100, 623 0x9490, 0xffffffff, 0x3, 624 0x949c, 0xffffffff, 0x100, 625 0x9490, 0xffffffff, 0x4, 626 0x949c, 0xffffffff, 0x100, 627 0x9490, 0xffffffff, 0x5, 628 0x949c, 0xffffffff, 0x100, 629 0x9490, 0xffffffff, 0x6, 630 0x949c, 0xffffffff, 0x100, 631 0x9490, 0xffffffff, 0x7, 632 0x949c, 0xffffffff, 0x100, 633 0x9490, 0xffffffff, 0x8000, 634 0x9604, 0xffffffff, 0x0, 635 0x9654, 0xffffffff, 0x100, 636 0x9604, 0xffffffff, 0x1, 637 0x9654, 0xffffffff, 0x100, 638 0x9604, 0xffffffff, 0x2, 639 0x9654, 0xffffffff, 0x100, 640 0x9604, 0xffffffff, 0x3, 641 0x9654, 0xffffffff, 0x100, 642 0x9604, 0xffffffff, 0x4, 643 0x9654, 0xffffffff, 0x100, 644 0x9604, 0xffffffff, 0x5, 645 0x9654, 0xffffffff, 0x100, 646 0x9604, 0xffffffff, 0x6, 647 0x9654, 0xffffffff, 0x100, 648 0x9604, 0xffffffff, 0x7, 649 0x9654, 0xffffffff, 0x100, 650 0x9604, 0xffffffff, 0x80000000, 651 0x9030, 0xffffffff, 0x100, 652 0x9034, 0xffffffff, 0x100, 653 0x9038, 0xffffffff, 0x100, 654 0x903c, 0xffffffff, 0x100, 655 0x9040, 0xffffffff, 0x100, 656 0xa200, 0xffffffff, 0x100, 657 0xa204, 0xffffffff, 0x100, 658 0xa208, 0xffffffff, 0x100, 659 0xa20c, 0xffffffff, 0x100, 660 0x971c, 0xffffffff, 0x100, 661 0x915c, 0xffffffff, 0x00020001, 662 0x9160, 0xffffffff, 0x00040003, 663 0x916c, 0xffffffff, 0x00060005, 664 0x9170, 0xffffffff, 0x00080007, 665 0x9174, 0xffffffff, 0x000a0009, 666 0x9178, 0xffffffff, 0x000c000b, 667 0x917c, 0xffffffff, 0x000e000d, 668 0x9180, 0xffffffff, 0x0010000f, 669 0x918c, 0xffffffff, 0x00120011, 670 0x9190, 0xffffffff, 0x00140013, 671 0x9194, 0xffffffff, 0x00020001, 672 0x9198, 0xffffffff, 0x00040003, 673 0x919c, 0xffffffff, 0x00060005, 674 0x91a8, 0xffffffff, 0x00080007, 675 0x91ac, 0xffffffff, 0x000a0009, 676 0x91b0, 0xffffffff, 0x000c000b, 677 0x91b4, 0xffffffff, 0x000e000d, 678 0x91b8, 0xffffffff, 0x0010000f, 679 0x91c4, 0xffffffff, 0x00120011, 680 0x91c8, 0xffffffff, 0x00140013, 681 0x91cc, 0xffffffff, 0x00020001, 682 0x91d0, 0xffffffff, 0x00040003, 683 0x91d4, 0xffffffff, 0x00060005, 684 0x91e0, 0xffffffff, 0x00080007, 685 0x91e4, 0xffffffff, 0x000a0009, 686 0x91e8, 0xffffffff, 0x000c000b, 687 0x91ec, 0xffffffff, 0x00020001, 688 0x91f0, 0xffffffff, 0x00040003, 689 0x91f4, 0xffffffff, 0x00060005, 690 0x9200, 0xffffffff, 0x00080007, 691 0x9204, 0xffffffff, 0x000a0009, 692 0x9208, 0xffffffff, 0x000c000b, 693 0x920c, 0xffffffff, 0x000e000d, 694 0x9210, 0xffffffff, 0x0010000f, 695 0x921c, 0xffffffff, 0x00120011, 696 0x9220, 0xffffffff, 0x00140013, 697 0x9224, 0xffffffff, 0x00020001, 698 0x9228, 0xffffffff, 0x00040003, 699 0x922c, 0xffffffff, 0x00060005, 700 0x9238, 0xffffffff, 0x00080007, 701 0x923c, 0xffffffff, 0x000a0009, 702 0x9240, 0xffffffff, 0x000c000b, 703 0x9244, 0xffffffff, 0x000e000d, 704 0x9248, 0xffffffff, 0x0010000f, 705 0x9254, 0xffffffff, 0x00120011, 706 0x9258, 0xffffffff, 0x00140013, 707 0x9294, 0xffffffff, 0x00020001, 708 0x929c, 0xffffffff, 0x00040003, 709 0x92a0, 0xffffffff, 0x00060005, 710 0x92a4, 0xffffffff, 0x00080007 711 }; 712 713 static void rv770_init_golden_registers(struct radeon_device *rdev) 714 { 715 switch (rdev->family) { 716 case CHIP_RV770: 717 radeon_program_register_sequence(rdev, 718 r7xx_golden_registers, 719 (const u32)ARRAY_SIZE(r7xx_golden_registers)); 720 radeon_program_register_sequence(rdev, 721 r7xx_golden_dyn_gpr_registers, 722 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 723 if (rdev->pdev->device == 0x994e) 724 radeon_program_register_sequence(rdev, 725 rv770ce_golden_registers, 726 (const u32)ARRAY_SIZE(rv770ce_golden_registers)); 727 else 728 radeon_program_register_sequence(rdev, 729 rv770_golden_registers, 730 (const u32)ARRAY_SIZE(rv770_golden_registers)); 731 radeon_program_register_sequence(rdev, 732 rv770_mgcg_init, 733 (const u32)ARRAY_SIZE(rv770_mgcg_init)); 734 break; 735 case CHIP_RV730: 736 radeon_program_register_sequence(rdev, 737 r7xx_golden_registers, 738 (const u32)ARRAY_SIZE(r7xx_golden_registers)); 739 radeon_program_register_sequence(rdev, 740 r7xx_golden_dyn_gpr_registers, 741 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 742 radeon_program_register_sequence(rdev, 743 rv730_golden_registers, 744 (const u32)ARRAY_SIZE(rv730_golden_registers)); 745 radeon_program_register_sequence(rdev, 746 rv730_mgcg_init, 747 (const u32)ARRAY_SIZE(rv730_mgcg_init)); 748 break; 749 case CHIP_RV710: 750 radeon_program_register_sequence(rdev, 751 r7xx_golden_registers, 752 (const u32)ARRAY_SIZE(r7xx_golden_registers)); 753 radeon_program_register_sequence(rdev, 754 r7xx_golden_dyn_gpr_registers, 755 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 756 radeon_program_register_sequence(rdev, 757 rv710_golden_registers, 758 (const u32)ARRAY_SIZE(rv710_golden_registers)); 759 radeon_program_register_sequence(rdev, 760 rv710_mgcg_init, 761 (const u32)ARRAY_SIZE(rv710_mgcg_init)); 762 break; 763 case CHIP_RV740: 764 radeon_program_register_sequence(rdev, 765 rv740_golden_registers, 766 (const u32)ARRAY_SIZE(rv740_golden_registers)); 767 radeon_program_register_sequence(rdev, 768 rv740_mgcg_init, 769 (const u32)ARRAY_SIZE(rv740_mgcg_init)); 770 break; 771 default: 772 break; 773 } 774 } 775 776 #define PCIE_BUS_CLK 10000 777 #define TCLK (PCIE_BUS_CLK / 10) 778 779 /** 780 * rv770_get_xclk - get the xclk 781 * 782 * @rdev: radeon_device pointer 783 * 784 * Returns the reference clock used by the gfx engine 785 * (r7xx-cayman). 786 */ 787 u32 rv770_get_xclk(struct radeon_device *rdev) 788 { 789 u32 reference_clock = rdev->clock.spll.reference_freq; 790 u32 tmp = RREG32(CG_CLKPIN_CNTL); 791 792 if (tmp & MUX_TCLK_TO_XCLK) 793 return TCLK; 794 795 if (tmp & XTALIN_DIVIDE) 796 return reference_clock / 4; 797 798 return reference_clock; 799 } 800 801 void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 802 { 803 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 804 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 805 int i; 806 807 /* Lock the graphics update lock */ 808 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 809 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 810 811 /* update the scanout addresses */ 812 if (radeon_crtc->crtc_id) { 813 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 814 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 815 } else { 816 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 817 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 818 } 819 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 820 (u32)crtc_base); 821 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 822 (u32)crtc_base); 823 824 /* Wait for update_pending to go high. */ 825 for (i = 0; i < rdev->usec_timeout; i++) { 826 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 827 break; 828 udelay(1); 829 } 830 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 831 832 /* Unlock the lock, so double-buffering can take place inside vblank */ 833 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 834 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 835 } 836 837 bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc_id) 838 { 839 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 840 841 /* Return current update_pending status: */ 842 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & 843 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING); 844 } 845 846 /* get temperature in millidegrees */ 847 int rv770_get_temp(struct radeon_device *rdev) 848 { 849 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> 850 ASIC_T_SHIFT; 851 int actual_temp; 852 853 if (temp & 0x400) 854 actual_temp = -256; 855 else if (temp & 0x200) 856 actual_temp = 255; 857 else if (temp & 0x100) { 858 actual_temp = temp & 0x1ff; 859 actual_temp |= ~0x1ff; 860 } else 861 actual_temp = temp & 0xff; 862 863 return (actual_temp * 1000) / 2; 864 } 865 866 void rv770_pm_misc(struct radeon_device *rdev) 867 { 868 int req_ps_idx = rdev->pm.requested_power_state_index; 869 int req_cm_idx = rdev->pm.requested_clock_mode_index; 870 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 871 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 872 873 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 874 /* 0xff01 is a flag rather then an actual voltage */ 875 if (voltage->voltage == 0xff01) 876 return; 877 if (voltage->voltage != rdev->pm.current_vddc) { 878 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 879 rdev->pm.current_vddc = voltage->voltage; 880 DRM_DEBUG("Setting: v: %d\n", voltage->voltage); 881 } 882 } 883 } 884 885 /* 886 * GART 887 */ 888 static int rv770_pcie_gart_enable(struct radeon_device *rdev) 889 { 890 u32 tmp; 891 int r, i; 892 893 if (rdev->gart.robj == NULL) { 894 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 895 return -EINVAL; 896 } 897 r = radeon_gart_table_vram_pin(rdev); 898 if (r) 899 return r; 900 /* Setup L2 cache */ 901 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 902 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 903 EFFECTIVE_L2_QUEUE_SIZE(7)); 904 WREG32(VM_L2_CNTL2, 0); 905 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 906 /* Setup TLB control */ 907 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 908 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 909 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 910 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 911 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 912 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 913 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 914 if (rdev->family == CHIP_RV740) 915 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); 916 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 917 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 918 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 919 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 920 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 921 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 922 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 923 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 924 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 925 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 926 (u32)(rdev->dummy_page.addr >> 12)); 927 for (i = 1; i < 7; i++) 928 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 929 930 r600_pcie_gart_tlb_flush(rdev); 931 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 932 (unsigned)(rdev->mc.gtt_size >> 20), 933 (unsigned long long)rdev->gart.table_addr); 934 rdev->gart.ready = true; 935 return 0; 936 } 937 938 static void rv770_pcie_gart_disable(struct radeon_device *rdev) 939 { 940 u32 tmp; 941 int i; 942 943 /* Disable all tables */ 944 for (i = 0; i < 7; i++) 945 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 946 947 /* Setup L2 cache */ 948 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 949 EFFECTIVE_L2_QUEUE_SIZE(7)); 950 WREG32(VM_L2_CNTL2, 0); 951 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 952 /* Setup TLB control */ 953 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 954 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 955 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 956 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 957 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 958 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 959 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 960 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 961 radeon_gart_table_vram_unpin(rdev); 962 } 963 964 static void rv770_pcie_gart_fini(struct radeon_device *rdev) 965 { 966 radeon_gart_fini(rdev); 967 rv770_pcie_gart_disable(rdev); 968 radeon_gart_table_vram_free(rdev); 969 } 970 971 972 static void rv770_agp_enable(struct radeon_device *rdev) 973 { 974 u32 tmp; 975 int i; 976 977 /* Setup L2 cache */ 978 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 979 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 980 EFFECTIVE_L2_QUEUE_SIZE(7)); 981 WREG32(VM_L2_CNTL2, 0); 982 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 983 /* Setup TLB control */ 984 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 985 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 986 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 987 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 988 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 989 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 990 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 991 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 992 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 993 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 994 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 995 for (i = 0; i < 7; i++) 996 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 997 } 998 999 static void rv770_mc_program(struct radeon_device *rdev) 1000 { 1001 struct rv515_mc_save save; 1002 u32 tmp; 1003 int i, j; 1004 1005 /* Initialize HDP */ 1006 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1007 WREG32((0x2c14 + j), 0x00000000); 1008 WREG32((0x2c18 + j), 0x00000000); 1009 WREG32((0x2c1c + j), 0x00000000); 1010 WREG32((0x2c20 + j), 0x00000000); 1011 WREG32((0x2c24 + j), 0x00000000); 1012 } 1013 /* r7xx hw bug. Read from HDP_DEBUG1 rather 1014 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL 1015 */ 1016 tmp = RREG32(HDP_DEBUG1); 1017 1018 rv515_mc_stop(rdev, &save); 1019 if (r600_mc_wait_for_idle(rdev)) { 1020 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1021 } 1022 /* Lockout access through VGA aperture*/ 1023 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1024 /* Update configuration */ 1025 if (rdev->flags & RADEON_IS_AGP) { 1026 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1027 /* VRAM before AGP */ 1028 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1029 rdev->mc.vram_start >> 12); 1030 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1031 rdev->mc.gtt_end >> 12); 1032 } else { 1033 /* VRAM after AGP */ 1034 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1035 rdev->mc.gtt_start >> 12); 1036 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1037 rdev->mc.vram_end >> 12); 1038 } 1039 } else { 1040 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1041 rdev->mc.vram_start >> 12); 1042 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1043 rdev->mc.vram_end >> 12); 1044 } 1045 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1046 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1047 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1048 WREG32(MC_VM_FB_LOCATION, tmp); 1049 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1050 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1051 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1052 if (rdev->flags & RADEON_IS_AGP) { 1053 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 1054 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 1055 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1056 } else { 1057 WREG32(MC_VM_AGP_BASE, 0); 1058 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1059 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1060 } 1061 if (r600_mc_wait_for_idle(rdev)) { 1062 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1063 } 1064 rv515_mc_resume(rdev, &save); 1065 /* we need to own VRAM, so turn off the VGA renderer here 1066 * to stop it overwriting our objects */ 1067 rv515_vga_render_disable(rdev); 1068 } 1069 1070 1071 /* 1072 * CP. 1073 */ 1074 void r700_cp_stop(struct radeon_device *rdev) 1075 { 1076 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 1077 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1078 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 1079 WREG32(SCRATCH_UMSK, 0); 1080 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1081 } 1082 1083 static int rv770_cp_load_microcode(struct radeon_device *rdev) 1084 { 1085 const __be32 *fw_data; 1086 int i; 1087 1088 if (!rdev->me_fw || !rdev->pfp_fw) 1089 return -EINVAL; 1090 1091 r700_cp_stop(rdev); 1092 WREG32(CP_RB_CNTL, 1093 #ifdef __BIG_ENDIAN 1094 BUF_SWAP_32BIT | 1095 #endif 1096 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 1097 1098 /* Reset cp */ 1099 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 1100 RREG32(GRBM_SOFT_RESET); 1101 mdelay(15); 1102 WREG32(GRBM_SOFT_RESET, 0); 1103 1104 fw_data = (const __be32 *)rdev->pfp_fw->data; 1105 WREG32(CP_PFP_UCODE_ADDR, 0); 1106 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 1107 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1108 WREG32(CP_PFP_UCODE_ADDR, 0); 1109 1110 fw_data = (const __be32 *)rdev->me_fw->data; 1111 WREG32(CP_ME_RAM_WADDR, 0); 1112 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 1113 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1114 1115 WREG32(CP_PFP_UCODE_ADDR, 0); 1116 WREG32(CP_ME_RAM_WADDR, 0); 1117 WREG32(CP_ME_RAM_RADDR, 0); 1118 return 0; 1119 } 1120 1121 void r700_cp_fini(struct radeon_device *rdev) 1122 { 1123 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1124 r700_cp_stop(rdev); 1125 radeon_ring_fini(rdev, ring); 1126 radeon_scratch_free(rdev, ring->rptr_save_reg); 1127 } 1128 1129 void rv770_set_clk_bypass_mode(struct radeon_device *rdev) 1130 { 1131 u32 tmp, i; 1132 1133 if (rdev->flags & RADEON_IS_IGP) 1134 return; 1135 1136 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); 1137 tmp &= SCLK_MUX_SEL_MASK; 1138 tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE; 1139 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); 1140 1141 for (i = 0; i < rdev->usec_timeout; i++) { 1142 if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS) 1143 break; 1144 udelay(1); 1145 } 1146 1147 tmp &= ~SCLK_MUX_UPDATE; 1148 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); 1149 1150 tmp = RREG32(MPLL_CNTL_MODE); 1151 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730)) 1152 tmp &= ~RV730_MPLL_MCLK_SEL; 1153 else 1154 tmp &= ~MPLL_MCLK_SEL; 1155 WREG32(MPLL_CNTL_MODE, tmp); 1156 } 1157 1158 /* 1159 * Core functions 1160 */ 1161 static void rv770_gpu_init(struct radeon_device *rdev) 1162 { 1163 int i, j, num_qd_pipes; 1164 u32 ta_aux_cntl; 1165 u32 sx_debug_1; 1166 u32 smx_dc_ctl0; 1167 u32 db_debug3; 1168 u32 num_gs_verts_per_thread; 1169 u32 vgt_gs_per_es; 1170 u32 gs_prim_buffer_depth = 0; 1171 u32 sq_ms_fifo_sizes; 1172 u32 sq_config; 1173 u32 sq_thread_resource_mgmt; 1174 u32 hdp_host_path_cntl; 1175 u32 sq_dyn_gpr_size_simd_ab_0; 1176 u32 gb_tiling_config = 0; 1177 u32 cc_gc_shader_pipe_config = 0; 1178 u32 mc_arb_ramcfg; 1179 u32 db_debug4, tmp; 1180 u32 inactive_pipes, shader_pipe_config; 1181 u32 disabled_rb_mask; 1182 unsigned active_number; 1183 1184 /* setup chip specs */ 1185 rdev->config.rv770.tiling_group_size = 256; 1186 switch (rdev->family) { 1187 case CHIP_RV770: 1188 rdev->config.rv770.max_pipes = 4; 1189 rdev->config.rv770.max_tile_pipes = 8; 1190 rdev->config.rv770.max_simds = 10; 1191 rdev->config.rv770.max_backends = 4; 1192 rdev->config.rv770.max_gprs = 256; 1193 rdev->config.rv770.max_threads = 248; 1194 rdev->config.rv770.max_stack_entries = 512; 1195 rdev->config.rv770.max_hw_contexts = 8; 1196 rdev->config.rv770.max_gs_threads = 16 * 2; 1197 rdev->config.rv770.sx_max_export_size = 128; 1198 rdev->config.rv770.sx_max_export_pos_size = 16; 1199 rdev->config.rv770.sx_max_export_smx_size = 112; 1200 rdev->config.rv770.sq_num_cf_insts = 2; 1201 1202 rdev->config.rv770.sx_num_of_sets = 7; 1203 rdev->config.rv770.sc_prim_fifo_size = 0xF9; 1204 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1205 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1206 break; 1207 case CHIP_RV730: 1208 rdev->config.rv770.max_pipes = 2; 1209 rdev->config.rv770.max_tile_pipes = 4; 1210 rdev->config.rv770.max_simds = 8; 1211 rdev->config.rv770.max_backends = 2; 1212 rdev->config.rv770.max_gprs = 128; 1213 rdev->config.rv770.max_threads = 248; 1214 rdev->config.rv770.max_stack_entries = 256; 1215 rdev->config.rv770.max_hw_contexts = 8; 1216 rdev->config.rv770.max_gs_threads = 16 * 2; 1217 rdev->config.rv770.sx_max_export_size = 256; 1218 rdev->config.rv770.sx_max_export_pos_size = 32; 1219 rdev->config.rv770.sx_max_export_smx_size = 224; 1220 rdev->config.rv770.sq_num_cf_insts = 2; 1221 1222 rdev->config.rv770.sx_num_of_sets = 7; 1223 rdev->config.rv770.sc_prim_fifo_size = 0xf9; 1224 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1225 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1226 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 1227 rdev->config.rv770.sx_max_export_pos_size -= 16; 1228 rdev->config.rv770.sx_max_export_smx_size += 16; 1229 } 1230 break; 1231 case CHIP_RV710: 1232 rdev->config.rv770.max_pipes = 2; 1233 rdev->config.rv770.max_tile_pipes = 2; 1234 rdev->config.rv770.max_simds = 2; 1235 rdev->config.rv770.max_backends = 1; 1236 rdev->config.rv770.max_gprs = 256; 1237 rdev->config.rv770.max_threads = 192; 1238 rdev->config.rv770.max_stack_entries = 256; 1239 rdev->config.rv770.max_hw_contexts = 4; 1240 rdev->config.rv770.max_gs_threads = 8 * 2; 1241 rdev->config.rv770.sx_max_export_size = 128; 1242 rdev->config.rv770.sx_max_export_pos_size = 16; 1243 rdev->config.rv770.sx_max_export_smx_size = 112; 1244 rdev->config.rv770.sq_num_cf_insts = 1; 1245 1246 rdev->config.rv770.sx_num_of_sets = 7; 1247 rdev->config.rv770.sc_prim_fifo_size = 0x40; 1248 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1249 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1250 break; 1251 case CHIP_RV740: 1252 rdev->config.rv770.max_pipes = 4; 1253 rdev->config.rv770.max_tile_pipes = 4; 1254 rdev->config.rv770.max_simds = 8; 1255 rdev->config.rv770.max_backends = 4; 1256 rdev->config.rv770.max_gprs = 256; 1257 rdev->config.rv770.max_threads = 248; 1258 rdev->config.rv770.max_stack_entries = 512; 1259 rdev->config.rv770.max_hw_contexts = 8; 1260 rdev->config.rv770.max_gs_threads = 16 * 2; 1261 rdev->config.rv770.sx_max_export_size = 256; 1262 rdev->config.rv770.sx_max_export_pos_size = 32; 1263 rdev->config.rv770.sx_max_export_smx_size = 224; 1264 rdev->config.rv770.sq_num_cf_insts = 2; 1265 1266 rdev->config.rv770.sx_num_of_sets = 7; 1267 rdev->config.rv770.sc_prim_fifo_size = 0x100; 1268 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 1269 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 1270 1271 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 1272 rdev->config.rv770.sx_max_export_pos_size -= 16; 1273 rdev->config.rv770.sx_max_export_smx_size += 16; 1274 } 1275 break; 1276 default: 1277 break; 1278 } 1279 1280 /* Initialize HDP */ 1281 j = 0; 1282 for (i = 0; i < 32; i++) { 1283 WREG32((0x2c14 + j), 0x00000000); 1284 WREG32((0x2c18 + j), 0x00000000); 1285 WREG32((0x2c1c + j), 0x00000000); 1286 WREG32((0x2c20 + j), 0x00000000); 1287 WREG32((0x2c24 + j), 0x00000000); 1288 j += 0x18; 1289 } 1290 1291 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1292 1293 /* setup tiling, simd, pipe config */ 1294 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1295 1296 shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); 1297 inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; 1298 for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) { 1299 if (!(inactive_pipes & tmp)) { 1300 active_number++; 1301 } 1302 tmp <<= 1; 1303 } 1304 if (active_number == 1) { 1305 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); 1306 } else { 1307 WREG32(SPI_CONFIG_CNTL, 0); 1308 } 1309 1310 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 1311 tmp = rdev->config.rv770.max_simds - 1312 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); 1313 rdev->config.rv770.active_simds = tmp; 1314 1315 switch (rdev->config.rv770.max_tile_pipes) { 1316 case 1: 1317 default: 1318 gb_tiling_config = PIPE_TILING(0); 1319 break; 1320 case 2: 1321 gb_tiling_config = PIPE_TILING(1); 1322 break; 1323 case 4: 1324 gb_tiling_config = PIPE_TILING(2); 1325 break; 1326 case 8: 1327 gb_tiling_config = PIPE_TILING(3); 1328 break; 1329 } 1330 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; 1331 1332 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; 1333 tmp = 0; 1334 for (i = 0; i < rdev->config.rv770.max_backends; i++) 1335 tmp |= (1 << i); 1336 /* if all the backends are disabled, fix it up here */ 1337 if ((disabled_rb_mask & tmp) == tmp) { 1338 for (i = 0; i < rdev->config.rv770.max_backends; i++) 1339 disabled_rb_mask &= ~(1 << i); 1340 } 1341 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1342 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, 1343 R7XX_MAX_BACKENDS, disabled_rb_mask); 1344 gb_tiling_config |= tmp << 16; 1345 rdev->config.rv770.backend_map = tmp; 1346 1347 if (rdev->family == CHIP_RV770) 1348 gb_tiling_config |= BANK_TILING(1); 1349 else { 1350 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 1351 gb_tiling_config |= BANK_TILING(1); 1352 else 1353 gb_tiling_config |= BANK_TILING(0); 1354 } 1355 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); 1356 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1357 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { 1358 gb_tiling_config |= ROW_TILING(3); 1359 gb_tiling_config |= SAMPLE_SPLIT(3); 1360 } else { 1361 gb_tiling_config |= 1362 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 1363 gb_tiling_config |= 1364 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 1365 } 1366 1367 gb_tiling_config |= BANK_SWAPS(1); 1368 rdev->config.rv770.tile_config = gb_tiling_config; 1369 1370 WREG32(GB_TILING_CONFIG, gb_tiling_config); 1371 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1372 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1373 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1374 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); 1375 if (rdev->family == CHIP_RV730) { 1376 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1377 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1378 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1379 } 1380 1381 WREG32(CGTS_SYS_TCC_DISABLE, 0); 1382 WREG32(CGTS_TCC_DISABLE, 0); 1383 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 1384 WREG32(CGTS_USER_TCC_DISABLE, 0); 1385 1386 1387 num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1388 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); 1389 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1390 1391 /* set HW defaults for 3D engine */ 1392 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1393 ROQ_IB2_START(0x2b))); 1394 1395 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 1396 1397 ta_aux_cntl = RREG32(TA_CNTL_AUX); 1398 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); 1399 1400 sx_debug_1 = RREG32(SX_DEBUG_1); 1401 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 1402 WREG32(SX_DEBUG_1, sx_debug_1); 1403 1404 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 1405 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); 1406 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); 1407 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 1408 1409 if (rdev->family != CHIP_RV740) 1410 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | 1411 GS_FLUSH_CTL(4) | 1412 ACK_FLUSH_CTL(3) | 1413 SYNC_FLUSH_CTL)); 1414 1415 if (rdev->family != CHIP_RV770) 1416 WREG32(SMX_SAR_CTL0, 0x00003f3f); 1417 1418 db_debug3 = RREG32(DB_DEBUG3); 1419 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); 1420 switch (rdev->family) { 1421 case CHIP_RV770: 1422 case CHIP_RV740: 1423 db_debug3 |= DB_CLK_OFF_DELAY(0x1f); 1424 break; 1425 case CHIP_RV710: 1426 case CHIP_RV730: 1427 default: 1428 db_debug3 |= DB_CLK_OFF_DELAY(2); 1429 break; 1430 } 1431 WREG32(DB_DEBUG3, db_debug3); 1432 1433 if (rdev->family != CHIP_RV770) { 1434 db_debug4 = RREG32(DB_DEBUG4); 1435 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; 1436 WREG32(DB_DEBUG4, db_debug4); 1437 } 1438 1439 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | 1440 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | 1441 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); 1442 1443 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | 1444 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | 1445 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); 1446 1447 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1448 1449 WREG32(VGT_NUM_INSTANCES, 1); 1450 1451 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 1452 1453 WREG32(CP_PERFMON_CNTL, 0); 1454 1455 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | 1456 DONE_FIFO_HIWATER(0xe0) | 1457 ALU_UPDATE_FIFO_HIWATER(0x8)); 1458 switch (rdev->family) { 1459 case CHIP_RV770: 1460 case CHIP_RV730: 1461 case CHIP_RV710: 1462 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); 1463 break; 1464 case CHIP_RV740: 1465 default: 1466 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); 1467 break; 1468 } 1469 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1470 1471 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1472 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1473 */ 1474 sq_config = RREG32(SQ_CONFIG); 1475 sq_config &= ~(PS_PRIO(3) | 1476 VS_PRIO(3) | 1477 GS_PRIO(3) | 1478 ES_PRIO(3)); 1479 sq_config |= (DX9_CONSTS | 1480 VC_ENABLE | 1481 EXPORT_SRC_C | 1482 PS_PRIO(0) | 1483 VS_PRIO(1) | 1484 GS_PRIO(2) | 1485 ES_PRIO(3)); 1486 if (rdev->family == CHIP_RV710) 1487 /* no vertex cache */ 1488 sq_config &= ~VC_ENABLE; 1489 1490 WREG32(SQ_CONFIG, sq_config); 1491 1492 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 1493 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 1494 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); 1495 1496 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | 1497 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); 1498 1499 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | 1500 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | 1501 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); 1502 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) 1503 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); 1504 else 1505 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); 1506 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1507 1508 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 1509 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 1510 1511 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 1512 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 1513 1514 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | 1515 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | 1516 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | 1517 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); 1518 1519 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1520 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1521 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1522 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1523 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1524 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1525 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1526 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1527 1528 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1529 FORCE_EOV_MAX_REZ_CNT(255))); 1530 1531 if (rdev->family == CHIP_RV710) 1532 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | 1533 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 1534 else 1535 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | 1536 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 1537 1538 switch (rdev->family) { 1539 case CHIP_RV770: 1540 case CHIP_RV730: 1541 case CHIP_RV740: 1542 gs_prim_buffer_depth = 384; 1543 break; 1544 case CHIP_RV710: 1545 gs_prim_buffer_depth = 128; 1546 break; 1547 default: 1548 break; 1549 } 1550 1551 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; 1552 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1553 /* Max value for this is 256 */ 1554 if (vgt_gs_per_es > 256) 1555 vgt_gs_per_es = 256; 1556 1557 WREG32(VGT_ES_PER_GS, 128); 1558 WREG32(VGT_GS_PER_ES, vgt_gs_per_es); 1559 WREG32(VGT_GS_PER_VS, 2); 1560 1561 /* more default values. 2D/3D driver should adjust as needed */ 1562 WREG32(VGT_GS_VERTEX_REUSE, 16); 1563 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1564 WREG32(VGT_STRMOUT_EN, 0); 1565 WREG32(SX_MISC, 0); 1566 WREG32(PA_SC_MODE_CNTL, 0); 1567 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); 1568 WREG32(PA_SC_AA_CONFIG, 0); 1569 WREG32(PA_SC_CLIPRECT_RULE, 0xffff); 1570 WREG32(PA_SC_LINE_STIPPLE, 0); 1571 WREG32(SPI_INPUT_Z, 0); 1572 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 1573 WREG32(CB_COLOR7_FRAG, 0); 1574 1575 /* clear render buffer base addresses */ 1576 WREG32(CB_COLOR0_BASE, 0); 1577 WREG32(CB_COLOR1_BASE, 0); 1578 WREG32(CB_COLOR2_BASE, 0); 1579 WREG32(CB_COLOR3_BASE, 0); 1580 WREG32(CB_COLOR4_BASE, 0); 1581 WREG32(CB_COLOR5_BASE, 0); 1582 WREG32(CB_COLOR6_BASE, 0); 1583 WREG32(CB_COLOR7_BASE, 0); 1584 1585 WREG32(TCP_CNTL, 0); 1586 1587 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1588 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1589 1590 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1591 1592 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 1593 NUM_CLIP_SEQ(3))); 1594 WREG32(VC_ENHANCE, 0); 1595 } 1596 1597 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1598 { 1599 u64 size_bf, size_af; 1600 1601 if (mc->mc_vram_size > 0xE0000000) { 1602 /* leave room for at least 512M GTT */ 1603 dev_warn(rdev->dev, "limiting VRAM\n"); 1604 mc->real_vram_size = 0xE0000000; 1605 mc->mc_vram_size = 0xE0000000; 1606 } 1607 if (rdev->flags & RADEON_IS_AGP) { 1608 size_bf = mc->gtt_start; 1609 size_af = mc->mc_mask - mc->gtt_end; 1610 if (size_bf > size_af) { 1611 if (mc->mc_vram_size > size_bf) { 1612 dev_warn(rdev->dev, "limiting VRAM\n"); 1613 mc->real_vram_size = size_bf; 1614 mc->mc_vram_size = size_bf; 1615 } 1616 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1617 } else { 1618 if (mc->mc_vram_size > size_af) { 1619 dev_warn(rdev->dev, "limiting VRAM\n"); 1620 mc->real_vram_size = size_af; 1621 mc->mc_vram_size = size_af; 1622 } 1623 mc->vram_start = mc->gtt_end + 1; 1624 } 1625 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1626 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 1627 mc->mc_vram_size >> 20, mc->vram_start, 1628 mc->vram_end, mc->real_vram_size >> 20); 1629 } else { 1630 radeon_vram_location(rdev, &rdev->mc, 0); 1631 rdev->mc.gtt_base_align = 0; 1632 radeon_gtt_location(rdev, mc); 1633 } 1634 } 1635 1636 static int rv770_mc_init(struct radeon_device *rdev) 1637 { 1638 u32 tmp; 1639 int chansize, numchan; 1640 1641 /* Get VRAM informations */ 1642 rdev->mc.vram_is_ddr = true; 1643 tmp = RREG32(MC_ARB_RAMCFG); 1644 if (tmp & CHANSIZE_OVERRIDE) { 1645 chansize = 16; 1646 } else if (tmp & CHANSIZE_MASK) { 1647 chansize = 64; 1648 } else { 1649 chansize = 32; 1650 } 1651 tmp = RREG32(MC_SHARED_CHMAP); 1652 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1653 case 0: 1654 default: 1655 numchan = 1; 1656 break; 1657 case 1: 1658 numchan = 2; 1659 break; 1660 case 2: 1661 numchan = 4; 1662 break; 1663 case 3: 1664 numchan = 8; 1665 break; 1666 } 1667 rdev->mc.vram_width = numchan * chansize; 1668 /* Could aper size report 0 ? */ 1669 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1670 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1671 /* Setup GPU memory space */ 1672 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1673 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1674 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1675 r700_vram_gtt_location(rdev, &rdev->mc); 1676 radeon_update_bandwidth_info(rdev); 1677 1678 return 0; 1679 } 1680 1681 static int rv770_startup(struct radeon_device *rdev) 1682 { 1683 struct radeon_ring *ring; 1684 int r; 1685 1686 /* enable pcie gen2 link */ 1687 rv770_pcie_gen2_enable(rdev); 1688 1689 /* scratch needs to be initialized before MC */ 1690 r = r600_vram_scratch_init(rdev); 1691 if (r) 1692 return r; 1693 1694 rv770_mc_program(rdev); 1695 1696 if (rdev->flags & RADEON_IS_AGP) { 1697 rv770_agp_enable(rdev); 1698 } else { 1699 r = rv770_pcie_gart_enable(rdev); 1700 if (r) 1701 return r; 1702 } 1703 1704 rv770_gpu_init(rdev); 1705 1706 /* allocate wb buffer */ 1707 r = radeon_wb_init(rdev); 1708 if (r) 1709 return r; 1710 1711 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1712 if (r) { 1713 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1714 return r; 1715 } 1716 1717 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 1718 if (r) { 1719 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 1720 return r; 1721 } 1722 1723 r = uvd_v2_2_resume(rdev); 1724 if (!r) { 1725 r = radeon_fence_driver_start_ring(rdev, 1726 R600_RING_TYPE_UVD_INDEX); 1727 if (r) 1728 dev_err(rdev->dev, "UVD fences init error (%d).\n", r); 1729 } 1730 1731 if (r) 1732 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 1733 1734 /* Enable IRQ */ 1735 if (!rdev->irq.installed) { 1736 r = radeon_irq_kms_init(rdev); 1737 if (r) 1738 return r; 1739 } 1740 1741 r = r600_irq_init(rdev); 1742 if (r) { 1743 DRM_ERROR("radeon: IH init failed (%d).\n", r); 1744 radeon_irq_kms_fini(rdev); 1745 return r; 1746 } 1747 r600_irq_set(rdev); 1748 1749 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1750 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 1751 RADEON_CP_PACKET2); 1752 if (r) 1753 return r; 1754 1755 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 1756 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 1757 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 1758 if (r) 1759 return r; 1760 1761 r = rv770_cp_load_microcode(rdev); 1762 if (r) 1763 return r; 1764 r = r600_cp_resume(rdev); 1765 if (r) 1766 return r; 1767 1768 r = r600_dma_resume(rdev); 1769 if (r) 1770 return r; 1771 1772 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 1773 if (ring->ring_size) { 1774 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 1775 RADEON_CP_PACKET2); 1776 if (!r) 1777 r = uvd_v1_0_init(rdev); 1778 1779 if (r) 1780 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 1781 } 1782 1783 r = radeon_ib_pool_init(rdev); 1784 if (r) { 1785 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1786 return r; 1787 } 1788 1789 r = radeon_audio_init(rdev); 1790 if (r) { 1791 DRM_ERROR("radeon: audio init failed\n"); 1792 return r; 1793 } 1794 1795 return 0; 1796 } 1797 1798 int rv770_resume(struct radeon_device *rdev) 1799 { 1800 int r; 1801 1802 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 1803 * posting will perform necessary task to bring back GPU into good 1804 * shape. 1805 */ 1806 /* post card */ 1807 atom_asic_init(rdev->mode_info.atom_context); 1808 1809 /* init golden registers */ 1810 rv770_init_golden_registers(rdev); 1811 1812 if (rdev->pm.pm_method == PM_METHOD_DPM) 1813 radeon_pm_resume(rdev); 1814 1815 rdev->accel_working = true; 1816 r = rv770_startup(rdev); 1817 if (r) { 1818 DRM_ERROR("r600 startup failed on resume\n"); 1819 rdev->accel_working = false; 1820 return r; 1821 } 1822 1823 return r; 1824 1825 } 1826 1827 int rv770_suspend(struct radeon_device *rdev) 1828 { 1829 radeon_pm_suspend(rdev); 1830 radeon_audio_fini(rdev); 1831 uvd_v1_0_fini(rdev); 1832 radeon_uvd_suspend(rdev); 1833 r700_cp_stop(rdev); 1834 r600_dma_stop(rdev); 1835 r600_irq_suspend(rdev); 1836 radeon_wb_disable(rdev); 1837 rv770_pcie_gart_disable(rdev); 1838 1839 return 0; 1840 } 1841 1842 /* Plan is to move initialization in that function and use 1843 * helper function so that radeon_device_init pretty much 1844 * do nothing more than calling asic specific function. This 1845 * should also allow to remove a bunch of callback function 1846 * like vram_info. 1847 */ 1848 int rv770_init(struct radeon_device *rdev) 1849 { 1850 int r; 1851 1852 /* Read BIOS */ 1853 if (!radeon_get_bios(rdev)) { 1854 if (ASIC_IS_AVIVO(rdev)) 1855 return -EINVAL; 1856 } 1857 /* Must be an ATOMBIOS */ 1858 if (!rdev->is_atom_bios) { 1859 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 1860 return -EINVAL; 1861 } 1862 r = radeon_atombios_init(rdev); 1863 if (r) 1864 return r; 1865 /* Post card if necessary */ 1866 if (!radeon_card_posted(rdev)) { 1867 if (!rdev->bios) { 1868 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 1869 return -EINVAL; 1870 } 1871 DRM_INFO("GPU not posted. posting now...\n"); 1872 atom_asic_init(rdev->mode_info.atom_context); 1873 } 1874 /* init golden registers */ 1875 rv770_init_golden_registers(rdev); 1876 /* Initialize scratch registers */ 1877 r600_scratch_init(rdev); 1878 /* Initialize surface registers */ 1879 radeon_surface_init(rdev); 1880 /* Initialize clocks */ 1881 radeon_get_clock_info(rdev->ddev); 1882 /* Fence driver */ 1883 r = radeon_fence_driver_init(rdev); 1884 if (r) 1885 return r; 1886 /* initialize AGP */ 1887 if (rdev->flags & RADEON_IS_AGP) { 1888 r = radeon_agp_init(rdev); 1889 if (r) 1890 radeon_agp_disable(rdev); 1891 } 1892 r = rv770_mc_init(rdev); 1893 if (r) 1894 return r; 1895 /* Memory manager */ 1896 r = radeon_bo_init(rdev); 1897 if (r) 1898 return r; 1899 1900 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 1901 r = r600_init_microcode(rdev); 1902 if (r) { 1903 DRM_ERROR("Failed to load firmware!\n"); 1904 return r; 1905 } 1906 } 1907 1908 /* Initialize power management */ 1909 radeon_pm_init(rdev); 1910 1911 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 1912 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 1913 1914 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 1915 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 1916 1917 r = radeon_uvd_init(rdev); 1918 if (!r) { 1919 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 1920 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 1921 4096); 1922 } 1923 1924 rdev->ih.ring_obj = NULL; 1925 r600_ih_ring_init(rdev, 64 * 1024); 1926 1927 r = r600_pcie_gart_init(rdev); 1928 if (r) 1929 return r; 1930 1931 rdev->accel_working = true; 1932 r = rv770_startup(rdev); 1933 if (r) { 1934 dev_err(rdev->dev, "disabling GPU acceleration\n"); 1935 r700_cp_fini(rdev); 1936 r600_dma_fini(rdev); 1937 r600_irq_fini(rdev); 1938 radeon_wb_fini(rdev); 1939 radeon_ib_pool_fini(rdev); 1940 radeon_irq_kms_fini(rdev); 1941 rv770_pcie_gart_fini(rdev); 1942 rdev->accel_working = false; 1943 } 1944 1945 return 0; 1946 } 1947 1948 void rv770_fini(struct radeon_device *rdev) 1949 { 1950 radeon_pm_fini(rdev); 1951 r700_cp_fini(rdev); 1952 r600_dma_fini(rdev); 1953 r600_irq_fini(rdev); 1954 radeon_wb_fini(rdev); 1955 radeon_ib_pool_fini(rdev); 1956 radeon_irq_kms_fini(rdev); 1957 uvd_v1_0_fini(rdev); 1958 radeon_uvd_fini(rdev); 1959 rv770_pcie_gart_fini(rdev); 1960 r600_vram_scratch_fini(rdev); 1961 radeon_gem_fini(rdev); 1962 radeon_fence_driver_fini(rdev); 1963 radeon_agp_fini(rdev); 1964 radeon_bo_fini(rdev); 1965 radeon_atombios_fini(rdev); 1966 r600_fini_microcode(rdev); 1967 kfree(rdev->bios); 1968 rdev->bios = NULL; 1969 } 1970 1971 static void rv770_pcie_gen2_enable(struct radeon_device *rdev) 1972 { 1973 u32 link_width_cntl, lanes, speed_cntl, tmp; 1974 u16 link_cntl2; 1975 u32 mask; 1976 int ret; 1977 1978 if (radeon_pcie_gen2 == 0) 1979 return; 1980 1981 if (rdev->flags & RADEON_IS_IGP) 1982 return; 1983 1984 if (!(rdev->flags & RADEON_IS_PCIE)) 1985 return; 1986 1987 /* x2 cards have a special sequence */ 1988 if (ASIC_IS_X2(rdev)) 1989 return; 1990 1991 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 1992 if (ret != 0) 1993 return; 1994 1995 if (!(mask & DRM_PCIE_SPEED_50)) 1996 return; 1997 1998 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 1999 2000 /* advertise upconfig capability */ 2001 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 2002 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 2003 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2004 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 2005 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 2006 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 2007 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 2008 LC_RECONFIG_ARC_MISSING_ESCAPE); 2009 link_width_cntl |= lanes | LC_RECONFIG_NOW | 2010 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; 2011 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2012 } else { 2013 link_width_cntl |= LC_UPCONFIGURE_DIS; 2014 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2015 } 2016 2017 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2018 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 2019 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 2020 2021 tmp = RREG32(0x541c); 2022 WREG32(0x541c, tmp | 0x8); 2023 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 2024 link_cntl2 = RREG16(0x4088); 2025 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 2026 link_cntl2 |= 0x2; 2027 WREG16(0x4088, link_cntl2); 2028 WREG32(MM_CFGREGS_CNTL, 0); 2029 2030 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2031 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 2032 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2033 2034 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2035 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 2036 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2037 2038 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2039 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 2040 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2041 2042 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2043 speed_cntl |= LC_GEN2_EN_STRAP; 2044 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2045 2046 } else { 2047 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 2048 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 2049 if (1) 2050 link_width_cntl |= LC_UPCONFIGURE_DIS; 2051 else 2052 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 2053 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2054 } 2055 } 2056