1*57e252bfSMichael Neumann /* 2*57e252bfSMichael Neumann * Copyright 2011 Advanced Micro Devices, Inc. 3*57e252bfSMichael Neumann * 4*57e252bfSMichael Neumann * Permission is hereby granted, free of charge, to any person obtaining a 5*57e252bfSMichael Neumann * copy of this software and associated documentation files (the "Software"), 6*57e252bfSMichael Neumann * to deal in the Software without restriction, including without limitation 7*57e252bfSMichael Neumann * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*57e252bfSMichael Neumann * and/or sell copies of the Software, and to permit persons to whom the 9*57e252bfSMichael Neumann * Software is furnished to do so, subject to the following conditions: 10*57e252bfSMichael Neumann * 11*57e252bfSMichael Neumann * The above copyright notice and this permission notice shall be included in 12*57e252bfSMichael Neumann * all copies or substantial portions of the Software. 13*57e252bfSMichael Neumann * 14*57e252bfSMichael Neumann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*57e252bfSMichael Neumann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*57e252bfSMichael Neumann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*57e252bfSMichael Neumann * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*57e252bfSMichael Neumann * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*57e252bfSMichael Neumann * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*57e252bfSMichael Neumann * OTHER DEALINGS IN THE SOFTWARE. 21*57e252bfSMichael Neumann * 22*57e252bfSMichael Neumann */ 23*57e252bfSMichael Neumann #ifndef __RS780D_H__ 24*57e252bfSMichael Neumann #define __RS780D_H__ 25*57e252bfSMichael Neumann 26*57e252bfSMichael Neumann #define CG_SPLL_FUNC_CNTL 0x600 27*57e252bfSMichael Neumann # define SPLL_RESET (1 << 0) 28*57e252bfSMichael Neumann # define SPLL_SLEEP (1 << 1) 29*57e252bfSMichael Neumann # define SPLL_REF_DIV(x) ((x) << 2) 30*57e252bfSMichael Neumann # define SPLL_REF_DIV_MASK (7 << 2) 31*57e252bfSMichael Neumann # define SPLL_REF_DIV_SHIFT 2 32*57e252bfSMichael Neumann # define SPLL_FB_DIV(x) ((x) << 5) 33*57e252bfSMichael Neumann # define SPLL_FB_DIV_MASK (0xff << 2) 34*57e252bfSMichael Neumann # define SPLL_FB_DIV_SHIFT 2 35*57e252bfSMichael Neumann # define SPLL_PULSEEN (1 << 13) 36*57e252bfSMichael Neumann # define SPLL_PULSENUM(x) ((x) << 14) 37*57e252bfSMichael Neumann # define SPLL_PULSENUM_MASK (3 << 14) 38*57e252bfSMichael Neumann # define SPLL_SW_HILEN(x) ((x) << 16) 39*57e252bfSMichael Neumann # define SPLL_SW_HILEN_MASK (0xf << 16) 40*57e252bfSMichael Neumann # define SPLL_SW_HILEN_SHIFT 16 41*57e252bfSMichael Neumann # define SPLL_SW_LOLEN(x) ((x) << 20) 42*57e252bfSMichael Neumann # define SPLL_SW_LOLEN_MASK (0xf << 20) 43*57e252bfSMichael Neumann # define SPLL_SW_LOLEN_SHIFT 20 44*57e252bfSMichael Neumann # define SPLL_DIVEN (1 << 24) 45*57e252bfSMichael Neumann # define SPLL_BYPASS_EN (1 << 25) 46*57e252bfSMichael Neumann # define SPLL_CHG_STATUS (1 << 29) 47*57e252bfSMichael Neumann # define SPLL_CTLREQ (1 << 30) 48*57e252bfSMichael Neumann # define SPLL_CTLACK (1 << 31) 49*57e252bfSMichael Neumann 50*57e252bfSMichael Neumann /* RS780/RS880 PM */ 51*57e252bfSMichael Neumann #define FVTHROT_CNTRL_REG 0x3000 52*57e252bfSMichael Neumann #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0) 53*57e252bfSMichael Neumann #define MINIMUM_CIP(x) ((x) << 1) 54*57e252bfSMichael Neumann #define MINIMUM_CIP_SHIFT 1 55*57e252bfSMichael Neumann #define MINIMUM_CIP_MASK 0x1fffffe 56*57e252bfSMichael Neumann #define REFRESH_RATE_DIVISOR(x) ((x) << 25) 57*57e252bfSMichael Neumann #define REFRESH_RATE_DIVISOR_SHIFT 25 58*57e252bfSMichael Neumann #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25) 59*57e252bfSMichael Neumann #define ENABLE_FV_THROT (1 << 27) 60*57e252bfSMichael Neumann #define ENABLE_FV_UPDATE (1 << 28) 61*57e252bfSMichael Neumann #define TREND_SEL_MODE (1 << 29) 62*57e252bfSMichael Neumann #define FORCE_TREND_SEL (1 << 30) 63*57e252bfSMichael Neumann #define ENABLE_FV_THROT_IO (1 << 31) 64*57e252bfSMichael Neumann #define FVTHROT_TARGET_REG 0x3004 65*57e252bfSMichael Neumann #define TARGET_IDLE_COUNT(x) ((x) << 0) 66*57e252bfSMichael Neumann #define TARGET_IDLE_COUNT_MASK 0xffffff 67*57e252bfSMichael Neumann #define TARGET_IDLE_COUNT_SHIFT 0 68*57e252bfSMichael Neumann #define FVTHROT_CB1 0x3008 69*57e252bfSMichael Neumann #define FVTHROT_CB2 0x300c 70*57e252bfSMichael Neumann #define FVTHROT_CB3 0x3010 71*57e252bfSMichael Neumann #define FVTHROT_CB4 0x3014 72*57e252bfSMichael Neumann #define FVTHROT_UTC0 0x3018 73*57e252bfSMichael Neumann #define FVTHROT_UTC1 0x301c 74*57e252bfSMichael Neumann #define FVTHROT_UTC2 0x3020 75*57e252bfSMichael Neumann #define FVTHROT_UTC3 0x3024 76*57e252bfSMichael Neumann #define FVTHROT_UTC4 0x3028 77*57e252bfSMichael Neumann #define FVTHROT_DTC0 0x302c 78*57e252bfSMichael Neumann #define FVTHROT_DTC1 0x3030 79*57e252bfSMichael Neumann #define FVTHROT_DTC2 0x3034 80*57e252bfSMichael Neumann #define FVTHROT_DTC3 0x3038 81*57e252bfSMichael Neumann #define FVTHROT_DTC4 0x303c 82*57e252bfSMichael Neumann #define FVTHROT_FBDIV_REG0 0x3040 83*57e252bfSMichael Neumann #define MIN_FEEDBACK_DIV(x) ((x) << 0) 84*57e252bfSMichael Neumann #define MIN_FEEDBACK_DIV_MASK 0xfff 85*57e252bfSMichael Neumann #define MIN_FEEDBACK_DIV_SHIFT 0 86*57e252bfSMichael Neumann #define MAX_FEEDBACK_DIV(x) ((x) << 12) 87*57e252bfSMichael Neumann #define MAX_FEEDBACK_DIV_MASK (0xfff << 12) 88*57e252bfSMichael Neumann #define MAX_FEEDBACK_DIV_SHIFT 12 89*57e252bfSMichael Neumann #define FVTHROT_FBDIV_REG1 0x3044 90*57e252bfSMichael Neumann #define MAX_FEEDBACK_STEP(x) ((x) << 0) 91*57e252bfSMichael Neumann #define MAX_FEEDBACK_STEP_MASK 0xfff 92*57e252bfSMichael Neumann #define MAX_FEEDBACK_STEP_SHIFT 0 93*57e252bfSMichael Neumann #define STARTING_FEEDBACK_DIV(x) ((x) << 12) 94*57e252bfSMichael Neumann #define STARTING_FEEDBACK_DIV_MASK (0xfff << 12) 95*57e252bfSMichael Neumann #define STARTING_FEEDBACK_DIV_SHIFT 12 96*57e252bfSMichael Neumann #define FORCE_FEEDBACK_DIV (1 << 24) 97*57e252bfSMichael Neumann #define FVTHROT_FBDIV_REG2 0x3048 98*57e252bfSMichael Neumann #define FORCED_FEEDBACK_DIV(x) ((x) << 0) 99*57e252bfSMichael Neumann #define FORCED_FEEDBACK_DIV_MASK 0xfff 100*57e252bfSMichael Neumann #define FORCED_FEEDBACK_DIV_SHIFT 0 101*57e252bfSMichael Neumann #define FB_DIV_TIMER_VAL(x) ((x) << 12) 102*57e252bfSMichael Neumann #define FB_DIV_TIMER_VAL_MASK (0xffff << 12) 103*57e252bfSMichael Neumann #define FB_DIV_TIMER_VAL_SHIFT 12 104*57e252bfSMichael Neumann #define FVTHROT_FB_US_REG0 0x304c 105*57e252bfSMichael Neumann #define FVTHROT_FB_US_REG1 0x3050 106*57e252bfSMichael Neumann #define FVTHROT_FB_DS_REG0 0x3054 107*57e252bfSMichael Neumann #define FVTHROT_FB_DS_REG1 0x3058 108*57e252bfSMichael Neumann #define FVTHROT_PWM_CTRL_REG0 0x305c 109*57e252bfSMichael Neumann #define STARTING_PWM_HIGHTIME(x) ((x) << 0) 110*57e252bfSMichael Neumann #define STARTING_PWM_HIGHTIME_MASK 0xfff 111*57e252bfSMichael Neumann #define STARTING_PWM_HIGHTIME_SHIFT 0 112*57e252bfSMichael Neumann #define NUMBER_OF_CYCLES_IN_PERIOD(x) ((x) << 12) 113*57e252bfSMichael Neumann #define NUMBER_OF_CYCLES_IN_PERIOD_MASK (0xfff << 12) 114*57e252bfSMichael Neumann #define NUMBER_OF_CYCLES_IN_PERIOD_SHIFT 12 115*57e252bfSMichael Neumann #define FORCE_STARTING_PWM_HIGHTIME (1 << 24) 116*57e252bfSMichael Neumann #define INVERT_PWM_WAVEFORM (1 << 25) 117*57e252bfSMichael Neumann #define FVTHROT_PWM_CTRL_REG1 0x3060 118*57e252bfSMichael Neumann #define MIN_PWM_HIGHTIME(x) ((x) << 0) 119*57e252bfSMichael Neumann #define MIN_PWM_HIGHTIME_MASK 0xfff 120*57e252bfSMichael Neumann #define MIN_PWM_HIGHTIME_SHIFT 0 121*57e252bfSMichael Neumann #define MAX_PWM_HIGHTIME(x) ((x) << 12) 122*57e252bfSMichael Neumann #define MAX_PWM_HIGHTIME_MASK (0xfff << 12) 123*57e252bfSMichael Neumann #define MAX_PWM_HIGHTIME_SHIFT 12 124*57e252bfSMichael Neumann #define FVTHROT_PWM_US_REG0 0x3064 125*57e252bfSMichael Neumann #define FVTHROT_PWM_US_REG1 0x3068 126*57e252bfSMichael Neumann #define FVTHROT_PWM_DS_REG0 0x306c 127*57e252bfSMichael Neumann #define FVTHROT_PWM_DS_REG1 0x3070 128*57e252bfSMichael Neumann #define FVTHROT_STATUS_REG0 0x3074 129*57e252bfSMichael Neumann #define CURRENT_FEEDBACK_DIV_MASK 0xfff 130*57e252bfSMichael Neumann #define CURRENT_FEEDBACK_DIV_SHIFT 0 131*57e252bfSMichael Neumann #define FVTHROT_STATUS_REG1 0x3078 132*57e252bfSMichael Neumann #define FVTHROT_STATUS_REG2 0x307c 133*57e252bfSMichael Neumann #define CG_INTGFX_MISC 0x3080 134*57e252bfSMichael Neumann #define FVTHROT_VBLANK_SEL (1 << 9) 135*57e252bfSMichael Neumann #define FVTHROT_PWM_FEEDBACK_DIV_REG1 0x308c 136*57e252bfSMichael Neumann #define RANGE0_PWM_FEEDBACK_DIV(x) ((x) << 0) 137*57e252bfSMichael Neumann #define RANGE0_PWM_FEEDBACK_DIV_MASK 0xfff 138*57e252bfSMichael Neumann #define RANGE0_PWM_FEEDBACK_DIV_SHIFT 0 139*57e252bfSMichael Neumann #define RANGE_PWM_FEEDBACK_DIV_EN (1 << 12) 140*57e252bfSMichael Neumann #define FVTHROT_PWM_FEEDBACK_DIV_REG2 0x3090 141*57e252bfSMichael Neumann #define RANGE1_PWM_FEEDBACK_DIV(x) ((x) << 0) 142*57e252bfSMichael Neumann #define RANGE1_PWM_FEEDBACK_DIV_MASK 0xfff 143*57e252bfSMichael Neumann #define RANGE1_PWM_FEEDBACK_DIV_SHIFT 0 144*57e252bfSMichael Neumann #define RANGE2_PWM_FEEDBACK_DIV(x) ((x) << 12) 145*57e252bfSMichael Neumann #define RANGE2_PWM_FEEDBACK_DIV_MASK (0xfff << 12) 146*57e252bfSMichael Neumann #define RANGE2_PWM_FEEDBACK_DIV_SHIFT 12 147*57e252bfSMichael Neumann #define FVTHROT_PWM_FEEDBACK_DIV_REG3 0x3094 148*57e252bfSMichael Neumann #define RANGE0_PWM(x) ((x) << 0) 149*57e252bfSMichael Neumann #define RANGE0_PWM_MASK 0xfff 150*57e252bfSMichael Neumann #define RANGE0_PWM_SHIFT 0 151*57e252bfSMichael Neumann #define RANGE1_PWM(x) ((x) << 12) 152*57e252bfSMichael Neumann #define RANGE1_PWM_MASK (0xfff << 12) 153*57e252bfSMichael Neumann #define RANGE1_PWM_SHIFT 12 154*57e252bfSMichael Neumann #define FVTHROT_PWM_FEEDBACK_DIV_REG4 0x3098 155*57e252bfSMichael Neumann #define RANGE2_PWM(x) ((x) << 0) 156*57e252bfSMichael Neumann #define RANGE2_PWM_MASK 0xfff 157*57e252bfSMichael Neumann #define RANGE2_PWM_SHIFT 0 158*57e252bfSMichael Neumann #define RANGE3_PWM(x) ((x) << 12) 159*57e252bfSMichael Neumann #define RANGE3_PWM_MASK (0xfff << 12) 160*57e252bfSMichael Neumann #define RANGE3_PWM_SHIFT 12 161*57e252bfSMichael Neumann #define FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1 0x30ac 162*57e252bfSMichael Neumann #define RANGE0_SLOW_CLK_FEEDBACK_DIV(x) ((x) << 0) 163*57e252bfSMichael Neumann #define RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK 0xfff 164*57e252bfSMichael Neumann #define RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT 0 165*57e252bfSMichael Neumann #define RANGE_SLOW_CLK_FEEDBACK_DIV_EN (1 << 12) 166*57e252bfSMichael Neumann 167*57e252bfSMichael Neumann #define GFX_MACRO_BYPASS_CNTL 0x30c0 168*57e252bfSMichael Neumann #define SPLL_BYPASS_CNTL (1 << 0) 169*57e252bfSMichael Neumann #define UPLL_BYPASS_CNTL (1 << 1) 170*57e252bfSMichael Neumann 171*57e252bfSMichael Neumann #endif 172