1*57e252bfSMichael Neumann /* 2*57e252bfSMichael Neumann * Copyright 2011 Advanced Micro Devices, Inc. 3*57e252bfSMichael Neumann * 4*57e252bfSMichael Neumann * Permission is hereby granted, free of charge, to any person obtaining a 5*57e252bfSMichael Neumann * copy of this software and associated documentation files (the "Software"), 6*57e252bfSMichael Neumann * to deal in the Software without restriction, including without limitation 7*57e252bfSMichael Neumann * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*57e252bfSMichael Neumann * and/or sell copies of the Software, and to permit persons to whom the 9*57e252bfSMichael Neumann * Software is furnished to do so, subject to the following conditions: 10*57e252bfSMichael Neumann * 11*57e252bfSMichael Neumann * The above copyright notice and this permission notice shall be included in 12*57e252bfSMichael Neumann * all copies or substantial portions of the Software. 13*57e252bfSMichael Neumann * 14*57e252bfSMichael Neumann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*57e252bfSMichael Neumann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*57e252bfSMichael Neumann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*57e252bfSMichael Neumann * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*57e252bfSMichael Neumann * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*57e252bfSMichael Neumann * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*57e252bfSMichael Neumann * OTHER DEALINGS IN THE SOFTWARE. 21*57e252bfSMichael Neumann * 22*57e252bfSMichael Neumann */ 23*57e252bfSMichael Neumann #ifndef __RS780_DPM_H__ 24*57e252bfSMichael Neumann #define __RS780_DPM_H__ 25*57e252bfSMichael Neumann 26*57e252bfSMichael Neumann enum rs780_vddc_level { 27*57e252bfSMichael Neumann RS780_VDDC_LEVEL_UNKNOWN = 0, 28*57e252bfSMichael Neumann RS780_VDDC_LEVEL_LOW = 1, 29*57e252bfSMichael Neumann RS780_VDDC_LEVEL_HIGH = 2, 30*57e252bfSMichael Neumann }; 31*57e252bfSMichael Neumann 32*57e252bfSMichael Neumann struct igp_power_info { 33*57e252bfSMichael Neumann /* flags */ 34*57e252bfSMichael Neumann bool invert_pwm_required; 35*57e252bfSMichael Neumann bool pwm_voltage_control; 36*57e252bfSMichael Neumann bool voltage_control; 37*57e252bfSMichael Neumann bool gfx_clock_gating; 38*57e252bfSMichael Neumann /* stored values */ 39*57e252bfSMichael Neumann u32 system_config; 40*57e252bfSMichael Neumann u32 bootup_uma_clk; 41*57e252bfSMichael Neumann u16 max_voltage; 42*57e252bfSMichael Neumann u16 min_voltage; 43*57e252bfSMichael Neumann u16 boot_voltage; 44*57e252bfSMichael Neumann u16 inter_voltage_low; 45*57e252bfSMichael Neumann u16 inter_voltage_high; 46*57e252bfSMichael Neumann u16 num_of_cycles_in_period; 47*57e252bfSMichael Neumann /* variable */ 48*57e252bfSMichael Neumann int crtc_id; 49*57e252bfSMichael Neumann int refresh_rate; 50*57e252bfSMichael Neumann }; 51*57e252bfSMichael Neumann 52*57e252bfSMichael Neumann struct igp_ps { 53*57e252bfSMichael Neumann enum rs780_vddc_level min_voltage; 54*57e252bfSMichael Neumann enum rs780_vddc_level max_voltage; 55*57e252bfSMichael Neumann u32 sclk_low; 56*57e252bfSMichael Neumann u32 sclk_high; 57*57e252bfSMichael Neumann u32 flags; 58*57e252bfSMichael Neumann }; 59*57e252bfSMichael Neumann 60*57e252bfSMichael Neumann #define RS780_CGFTV_DFLT 0x0303000f 61*57e252bfSMichael Neumann #define RS780_FBDIVTIMERVAL_DFLT 0x2710 62*57e252bfSMichael Neumann 63*57e252bfSMichael Neumann #define RS780_FVTHROTUTC0_DFLT 0x04010040 64*57e252bfSMichael Neumann #define RS780_FVTHROTUTC1_DFLT 0x04010040 65*57e252bfSMichael Neumann #define RS780_FVTHROTUTC2_DFLT 0x04010040 66*57e252bfSMichael Neumann #define RS780_FVTHROTUTC3_DFLT 0x04010040 67*57e252bfSMichael Neumann #define RS780_FVTHROTUTC4_DFLT 0x04010040 68*57e252bfSMichael Neumann 69*57e252bfSMichael Neumann #define RS780_FVTHROTDTC0_DFLT 0x04010040 70*57e252bfSMichael Neumann #define RS780_FVTHROTDTC1_DFLT 0x04010040 71*57e252bfSMichael Neumann #define RS780_FVTHROTDTC2_DFLT 0x04010040 72*57e252bfSMichael Neumann #define RS780_FVTHROTDTC3_DFLT 0x04010040 73*57e252bfSMichael Neumann #define RS780_FVTHROTDTC4_DFLT 0x04010040 74*57e252bfSMichael Neumann 75*57e252bfSMichael Neumann #define RS780_FVTHROTFBUSREG0_DFLT 0x00001001 76*57e252bfSMichael Neumann #define RS780_FVTHROTFBUSREG1_DFLT 0x00002002 77*57e252bfSMichael Neumann #define RS780_FVTHROTFBDSREG0_DFLT 0x00004001 78*57e252bfSMichael Neumann #define RS780_FVTHROTFBDSREG1_DFLT 0x00020010 79*57e252bfSMichael Neumann 80*57e252bfSMichael Neumann #define RS780_FVTHROTPWMUSREG0_DFLT 0x00002001 81*57e252bfSMichael Neumann #define RS780_FVTHROTPWMUSREG1_DFLT 0x00004003 82*57e252bfSMichael Neumann #define RS780_FVTHROTPWMDSREG0_DFLT 0x00002001 83*57e252bfSMichael Neumann #define RS780_FVTHROTPWMDSREG1_DFLT 0x00004003 84*57e252bfSMichael Neumann 85*57e252bfSMichael Neumann #define RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x37 86*57e252bfSMichael Neumann #define RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x4b 87*57e252bfSMichael Neumann #define RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT 0x8b 88*57e252bfSMichael Neumann 89*57e252bfSMichael Neumann #define RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x8b 90*57e252bfSMichael Neumann #define RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x8c 91*57e252bfSMichael Neumann #define RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT 0xb5 92*57e252bfSMichael Neumann 93*57e252bfSMichael Neumann #define RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x8d 94*57e252bfSMichael Neumann #define RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x8e 95*57e252bfSMichael Neumann #define RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT 0xBa 96*57e252bfSMichael Neumann 97*57e252bfSMichael Neumann #define RS780_FVTHROTPWMRANGE0_GPIO_DFLT 0x1a 98*57e252bfSMichael Neumann #define RS780_FVTHROTPWMRANGE1_GPIO_DFLT 0x1a 99*57e252bfSMichael Neumann #define RS780_FVTHROTPWMRANGE2_GPIO_DFLT 0x0 100*57e252bfSMichael Neumann #define RS780_FVTHROTPWMRANGE3_GPIO_DFLT 0x0 101*57e252bfSMichael Neumann 102*57e252bfSMichael Neumann #define RS780_SLOWCLKFEEDBACKDIV_DFLT 110 103*57e252bfSMichael Neumann 104*57e252bfSMichael Neumann #define RS780_CGCLKGATING_DFLT 0x0000E204 105*57e252bfSMichael Neumann 106*57e252bfSMichael Neumann #define RS780_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ 107*57e252bfSMichael Neumann #define RS780_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ 108*57e252bfSMichael Neumann 109*57e252bfSMichael Neumann #endif 110