1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #ifndef __RADEON_OBJECT_H__ 30 #define __RADEON_OBJECT_H__ 31 32 #include <uapi_drm/radeon_drm.h> 33 #include "radeon.h" 34 35 /* 36 * Undefine max_offset (defined in vm/vm_map.h), because it conflicts 37 * with an argument of the function radeon_bo_pin_restricted(). 38 */ 39 #undef max_offset 40 41 /** 42 * radeon_mem_type_to_domain - return domain corresponding to mem_type 43 * @mem_type: ttm memory type 44 * 45 * Returns corresponding domain of the ttm mem_type 46 */ 47 static inline unsigned radeon_mem_type_to_domain(u32 mem_type) 48 { 49 switch (mem_type) { 50 case TTM_PL_VRAM: 51 return RADEON_GEM_DOMAIN_VRAM; 52 case TTM_PL_TT: 53 return RADEON_GEM_DOMAIN_GTT; 54 case TTM_PL_SYSTEM: 55 return RADEON_GEM_DOMAIN_CPU; 56 default: 57 break; 58 } 59 return 0; 60 } 61 62 /** 63 * radeon_bo_reserve - reserve bo 64 * @bo: bo structure 65 * @no_intr: don't return -ERESTARTSYS on pending signal 66 * 67 * Returns: 68 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 69 * a signal. Release all buffer reservations and return to user-space. 70 */ 71 static inline int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr) 72 { 73 int r; 74 75 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0); 76 if (unlikely(r != 0)) { 77 if (r != -ERESTARTSYS) 78 dev_err(bo->rdev->dev, "%p reserve failed\n", bo); 79 return r; 80 } 81 return 0; 82 } 83 84 static inline void radeon_bo_unreserve(struct radeon_bo *bo) 85 { 86 ttm_bo_unreserve(&bo->tbo); 87 } 88 89 /** 90 * radeon_bo_gpu_offset - return GPU offset of bo 91 * @bo: radeon object for which we query the offset 92 * 93 * Returns current GPU offset of the object. 94 * 95 * Note: object should either be pinned or reserved when calling this 96 * function, it might be useful to add check for this for debugging. 97 */ 98 static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo) 99 { 100 return bo->tbo.offset; 101 } 102 103 static inline unsigned long radeon_bo_size(struct radeon_bo *bo) 104 { 105 return bo->tbo.num_pages << PAGE_SHIFT; 106 } 107 108 static inline bool radeon_bo_is_reserved(struct radeon_bo *bo) 109 { 110 return ttm_bo_is_reserved(&bo->tbo); 111 } 112 113 static inline unsigned radeon_bo_ngpu_pages(struct radeon_bo *bo) 114 { 115 return (bo->tbo.num_pages << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE; 116 } 117 118 static inline unsigned radeon_bo_gpu_page_alignment(struct radeon_bo *bo) 119 { 120 return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE; 121 } 122 123 /** 124 * radeon_bo_mmap_offset - return mmap offset of bo 125 * @bo: radeon object for which we query the offset 126 * 127 * Returns mmap offset of the object. 128 * 129 * Note: addr_space_offset is constant after ttm bo init thus isn't protected 130 * by any lock. 131 */ 132 static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo) 133 { 134 return bo->tbo.addr_space_offset; 135 } 136 137 extern int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, 138 bool no_wait); 139 140 extern int radeon_bo_create(struct radeon_device *rdev, 141 unsigned long size, int byte_align, 142 bool kernel, u32 domain, u32 flags, 143 struct sg_table *sg, 144 struct radeon_bo **bo_ptr); 145 extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr); 146 extern void radeon_bo_kunmap(struct radeon_bo *bo); 147 extern struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo); 148 extern void radeon_bo_unref(struct radeon_bo **bo); 149 extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr); 150 extern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, 151 u64 max_offset, u64 *gpu_addr); 152 extern int radeon_bo_unpin(struct radeon_bo *bo); 153 extern int radeon_bo_evict_vram(struct radeon_device *rdev); 154 extern void radeon_bo_force_delete(struct radeon_device *rdev); 155 extern int radeon_bo_init(struct radeon_device *rdev); 156 extern void radeon_bo_fini(struct radeon_device *rdev); 157 extern int radeon_bo_list_validate(struct radeon_device *rdev, 158 struct ww_acquire_ctx *ticket, 159 struct list_head *head, int ring); 160 extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 161 u32 tiling_flags, u32 pitch); 162 extern void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 163 u32 *tiling_flags, u32 *pitch); 164 extern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 165 bool force_drop); 166 extern void radeon_bo_move_notify(struct ttm_buffer_object *bo, 167 struct ttm_mem_reg *new_mem); 168 extern int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 169 extern int radeon_bo_get_surface_reg(struct radeon_bo *bo); 170 171 /* 172 * sub allocation 173 */ 174 175 static inline uint64_t radeon_sa_bo_gpu_addr(struct radeon_sa_bo *sa_bo) 176 { 177 return sa_bo->manager->gpu_addr + sa_bo->soffset; 178 } 179 180 static inline void * radeon_sa_bo_cpu_addr(struct radeon_sa_bo *sa_bo) 181 { 182 return (char *)sa_bo->manager->cpu_ptr + sa_bo->soffset; 183 } 184 185 extern int radeon_sa_bo_manager_init(struct radeon_device *rdev, 186 struct radeon_sa_manager *sa_manager, 187 unsigned size, u32 align, u32 domain, 188 u32 flags); 189 extern void radeon_sa_bo_manager_fini(struct radeon_device *rdev, 190 struct radeon_sa_manager *sa_manager); 191 extern int radeon_sa_bo_manager_start(struct radeon_device *rdev, 192 struct radeon_sa_manager *sa_manager); 193 extern int radeon_sa_bo_manager_suspend(struct radeon_device *rdev, 194 struct radeon_sa_manager *sa_manager); 195 extern int radeon_sa_bo_new(struct radeon_device *rdev, 196 struct radeon_sa_manager *sa_manager, 197 struct radeon_sa_bo **sa_bo, 198 unsigned size, unsigned align); 199 extern void radeon_sa_bo_free(struct radeon_device *rdev, 200 struct radeon_sa_bo **sa_bo, 201 struct radeon_fence *fence); 202 #if defined(CONFIG_DEBUG_FS) 203 extern void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager, 204 struct seq_file *m); 205 #endif 206 207 208 #endif 209