1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <drm/drmP.h> 33 #include <drm/radeon_drm.h> 34 #include "radeon.h" 35 #ifdef TRACE_TODO 36 #include "radeon_trace.h" 37 #endif 38 #include <linux/io.h> 39 40 41 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 42 43 /* 44 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 45 * function are calling it. 46 */ 47 48 static void radeon_update_memory_usage(struct radeon_bo *bo, 49 unsigned mem_type, int sign) 50 { 51 struct radeon_device *rdev = bo->rdev; 52 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT; 53 54 switch (mem_type) { 55 case TTM_PL_TT: 56 if (sign > 0) 57 atomic64_add(size, &rdev->gtt_usage); 58 else 59 atomic64_sub(size, &rdev->gtt_usage); 60 break; 61 case TTM_PL_VRAM: 62 if (sign > 0) 63 atomic64_add(size, &rdev->vram_usage); 64 else 65 atomic64_sub(size, &rdev->vram_usage); 66 break; 67 } 68 } 69 70 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 71 { 72 struct radeon_bo *bo; 73 74 bo = container_of(tbo, struct radeon_bo, tbo); 75 76 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); 77 radeon_mn_unregister(bo); 78 79 mutex_lock(&bo->rdev->gem.mutex); 80 list_del_init(&bo->list); 81 mutex_unlock(&bo->rdev->gem.mutex); 82 radeon_bo_clear_surface_reg(bo); 83 WARN_ON(!list_empty(&bo->va)); 84 drm_gem_object_release(&bo->gem_base); 85 kfree(bo); 86 } 87 88 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 89 { 90 if (bo->destroy == &radeon_ttm_bo_destroy) 91 return true; 92 return false; 93 } 94 95 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 96 { 97 u32 c = 0, i; 98 99 rbo->placement.placement = rbo->placements; 100 rbo->placement.busy_placement = rbo->placements; 101 if (domain & RADEON_GEM_DOMAIN_VRAM) 102 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 103 TTM_PL_FLAG_UNCACHED | 104 TTM_PL_FLAG_VRAM; 105 106 if (domain & RADEON_GEM_DOMAIN_GTT) { 107 if (rbo->flags & RADEON_GEM_GTT_UC) { 108 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | 109 TTM_PL_FLAG_TT; 110 111 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 112 (rbo->rdev->flags & RADEON_IS_AGP)) { 113 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 114 TTM_PL_FLAG_UNCACHED | 115 TTM_PL_FLAG_TT; 116 } else { 117 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | 118 TTM_PL_FLAG_TT; 119 } 120 } 121 122 if (domain & RADEON_GEM_DOMAIN_CPU) { 123 if (rbo->flags & RADEON_GEM_GTT_UC) { 124 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | 125 TTM_PL_FLAG_SYSTEM; 126 127 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 128 rbo->rdev->flags & RADEON_IS_AGP) { 129 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 130 TTM_PL_FLAG_UNCACHED | 131 TTM_PL_FLAG_SYSTEM; 132 } else { 133 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | 134 TTM_PL_FLAG_SYSTEM; 135 } 136 } 137 if (!c) 138 rbo->placements[c++].flags = TTM_PL_MASK_CACHING | 139 TTM_PL_FLAG_SYSTEM; 140 141 rbo->placement.num_placement = c; 142 rbo->placement.num_busy_placement = c; 143 144 for (i = 0; i < c; ++i) { 145 rbo->placements[i].fpfn = 0; 146 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && 147 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) 148 rbo->placements[i].lpfn = 149 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 150 else 151 rbo->placements[i].lpfn = 0; 152 } 153 154 /* 155 * Use two-ended allocation depending on the buffer size to 156 * improve fragmentation quality. 157 * 512kb was measured as the most optimal number. 158 */ 159 if (!((rbo->flags & RADEON_GEM_CPU_ACCESS) && 160 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) && 161 rbo->tbo.mem.size > 512 * 1024) { 162 for (i = 0; i < c; i++) { 163 rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN; 164 } 165 } 166 } 167 168 int radeon_bo_create(struct radeon_device *rdev, 169 unsigned long size, int byte_align, bool kernel, u32 domain, 170 u32 flags, struct sg_table *sg, struct radeon_bo **bo_ptr) 171 { 172 struct radeon_bo *bo; 173 enum ttm_bo_type type; 174 unsigned long page_align = roundup2(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 175 size_t acc_size; 176 int r; 177 178 size = ALIGN(size, PAGE_SIZE); 179 180 if (kernel) { 181 type = ttm_bo_type_kernel; 182 } else if (sg) { 183 type = ttm_bo_type_sg; 184 } else { 185 type = ttm_bo_type_device; 186 } 187 *bo_ptr = NULL; 188 189 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 190 sizeof(struct radeon_bo)); 191 192 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 193 if (bo == NULL) 194 return -ENOMEM; 195 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); 196 if (unlikely(r)) { 197 kfree(bo); 198 return r; 199 } 200 bo->rdev = rdev; 201 bo->surface_reg = -1; 202 INIT_LIST_HEAD(&bo->list); 203 INIT_LIST_HEAD(&bo->va); 204 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | 205 RADEON_GEM_DOMAIN_GTT | 206 RADEON_GEM_DOMAIN_CPU); 207 208 bo->flags = flags; 209 /* PCI GART is always snooped */ 210 if (!(rdev->flags & RADEON_IS_PCIE)) 211 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 212 213 #ifdef CONFIG_X86_32 214 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 215 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 216 */ 217 bo->flags &= ~RADEON_GEM_GTT_WC; 218 #endif 219 220 radeon_ttm_placement_from_domain(bo, domain); 221 /* Kernel allocation are uninterruptible */ 222 lockmgr(&rdev->pm.mclk_lock, LK_SHARED); 223 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 224 &bo->placement, page_align, !kernel, NULL, 225 acc_size, sg, NULL, &radeon_ttm_bo_destroy); 226 up_read(&rdev->pm.mclk_lock); 227 if (unlikely(r != 0)) { 228 return r; 229 } 230 *bo_ptr = bo; 231 232 #ifdef TRACE_TODO 233 trace_radeon_bo_create(bo); 234 #endif 235 236 return 0; 237 } 238 239 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 240 { 241 bool is_iomem; 242 int r; 243 244 if (bo->kptr) { 245 if (ptr) { 246 *ptr = bo->kptr; 247 } 248 return 0; 249 } 250 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 251 if (r) { 252 return r; 253 } 254 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 255 if (ptr) { 256 *ptr = bo->kptr; 257 } 258 radeon_bo_check_tiling(bo, 0, 0); 259 return 0; 260 } 261 262 void radeon_bo_kunmap(struct radeon_bo *bo) 263 { 264 if (bo->kptr == NULL) 265 return; 266 bo->kptr = NULL; 267 radeon_bo_check_tiling(bo, 0, 0); 268 ttm_bo_kunmap(&bo->kmap); 269 } 270 271 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) 272 { 273 if (bo == NULL) 274 return NULL; 275 276 ttm_bo_reference(&bo->tbo); 277 return bo; 278 } 279 280 void radeon_bo_unref(struct radeon_bo **bo) 281 { 282 struct ttm_buffer_object *tbo; 283 struct radeon_device *rdev; 284 struct radeon_bo *rbo; 285 286 if ((rbo = *bo) == NULL) 287 return; 288 *bo = NULL; 289 rdev = rbo->rdev; 290 tbo = &rbo->tbo; 291 ttm_bo_unref(&tbo); 292 } 293 294 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 295 u64 *gpu_addr) 296 { 297 int r, i; 298 299 if (bo->pin_count) { 300 bo->pin_count++; 301 if (gpu_addr) 302 *gpu_addr = radeon_bo_gpu_offset(bo); 303 304 if (max_offset != 0) { 305 u64 domain_start; 306 307 if (domain == RADEON_GEM_DOMAIN_VRAM) 308 domain_start = bo->rdev->mc.vram_start; 309 else 310 domain_start = bo->rdev->mc.gtt_start; 311 if (max_offset < (radeon_bo_gpu_offset(bo) - domain_start)) { 312 DRM_ERROR("radeon_bo_pin_restricted: " 313 "max_offset(%ju) < " 314 "(radeon_bo_gpu_offset(%ju) - " 315 "domain_start(%ju)", 316 (uintmax_t)max_offset, (uintmax_t)radeon_bo_gpu_offset(bo), 317 (uintmax_t)domain_start); 318 } 319 } 320 321 return 0; 322 } 323 radeon_ttm_placement_from_domain(bo, domain); 324 for (i = 0; i < bo->placement.num_placement; i++) { 325 /* force to pin into visible video ram */ 326 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 327 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && 328 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) 329 bo->placements[i].lpfn = 330 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 331 else 332 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; 333 334 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 335 } 336 337 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 338 if (likely(r == 0)) { 339 bo->pin_count = 1; 340 if (gpu_addr != NULL) 341 *gpu_addr = radeon_bo_gpu_offset(bo); 342 if (domain == RADEON_GEM_DOMAIN_VRAM) 343 bo->rdev->vram_pin_size += radeon_bo_size(bo); 344 else 345 bo->rdev->gart_pin_size += radeon_bo_size(bo); 346 } else { 347 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 348 } 349 return r; 350 } 351 352 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 353 { 354 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 355 } 356 357 int radeon_bo_unpin(struct radeon_bo *bo) 358 { 359 int r, i; 360 361 if (!bo->pin_count) { 362 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 363 return 0; 364 } 365 bo->pin_count--; 366 if (bo->pin_count) 367 return 0; 368 for (i = 0; i < bo->placement.num_placement; i++) { 369 bo->placements[i].lpfn = 0; 370 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 371 } 372 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 373 if (likely(r == 0)) { 374 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 375 bo->rdev->vram_pin_size -= radeon_bo_size(bo); 376 else 377 bo->rdev->gart_pin_size -= radeon_bo_size(bo); 378 } else { 379 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 380 } 381 return r; 382 } 383 384 int radeon_bo_evict_vram(struct radeon_device *rdev) 385 { 386 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 387 if (0 && (rdev->flags & RADEON_IS_IGP)) { 388 if (rdev->mc.igp_sideport_enabled == false) 389 /* Useless to evict on IGP chips */ 390 return 0; 391 } 392 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 393 } 394 395 void radeon_bo_force_delete(struct radeon_device *rdev) 396 { 397 struct radeon_bo *bo, *n; 398 399 if (list_empty(&rdev->gem.objects)) { 400 return; 401 } 402 dev_err(rdev->dev, "Userspace still has active objects !\n"); 403 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 404 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 405 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 406 *((unsigned long *)&bo->gem_base.refcount)); 407 mutex_lock(&bo->rdev->gem.mutex); 408 list_del_init(&bo->list); 409 mutex_unlock(&bo->rdev->gem.mutex); 410 /* this should unref the ttm bo */ 411 drm_gem_object_unreference(&bo->gem_base); 412 } 413 } 414 415 int radeon_bo_init(struct radeon_device *rdev) 416 { 417 /* Add an MTRR for the VRAM */ 418 if (!rdev->fastfb_working) { 419 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, 420 rdev->mc.aper_size); 421 } 422 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 423 rdev->mc.mc_vram_size >> 20, 424 (unsigned long long)rdev->mc.aper_size >> 20); 425 DRM_INFO("RAM width %dbits %cDR\n", 426 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 427 return radeon_ttm_init(rdev); 428 } 429 430 void radeon_bo_fini(struct radeon_device *rdev) 431 { 432 radeon_ttm_fini(rdev); 433 arch_phys_wc_del(rdev->mc.vram_mtrr); 434 } 435 436 /* Returns how many bytes TTM can move per IB. 437 */ 438 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) 439 { 440 u64 real_vram_size = rdev->mc.real_vram_size; 441 u64 vram_usage = atomic64_read(&rdev->vram_usage); 442 443 /* This function is based on the current VRAM usage. 444 * 445 * - If all of VRAM is free, allow relocating the number of bytes that 446 * is equal to 1/4 of the size of VRAM for this IB. 447 448 * - If more than one half of VRAM is occupied, only allow relocating 449 * 1 MB of data for this IB. 450 * 451 * - From 0 to one half of used VRAM, the threshold decreases 452 * linearly. 453 * __________________ 454 * 1/4 of -|\ | 455 * VRAM | \ | 456 * | \ | 457 * | \ | 458 * | \ | 459 * | \ | 460 * | \ | 461 * | \________|1 MB 462 * |----------------| 463 * VRAM 0 % 100 % 464 * used used 465 * 466 * Note: It's a threshold, not a limit. The threshold must be crossed 467 * for buffer relocations to stop, so any buffer of an arbitrary size 468 * can be moved as long as the threshold isn't crossed before 469 * the relocation takes place. We don't want to disable buffer 470 * relocations completely. 471 * 472 * The idea is that buffers should be placed in VRAM at creation time 473 * and TTM should only do a minimum number of relocations during 474 * command submission. In practice, you need to submit at least 475 * a dozen IBs to move all buffers to VRAM if they are in GTT. 476 * 477 * Also, things can get pretty crazy under memory pressure and actual 478 * VRAM usage can change a lot, so playing safe even at 50% does 479 * consistently increase performance. 480 */ 481 482 u64 half_vram = real_vram_size >> 1; 483 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; 484 u64 bytes_moved_threshold = half_free_vram >> 1; 485 return max(bytes_moved_threshold, 1024*1024ull); 486 } 487 488 int radeon_bo_list_validate(struct radeon_device *rdev, 489 struct ww_acquire_ctx *ticket, 490 struct list_head *head, int ring) 491 { 492 struct radeon_cs_reloc *lobj; 493 struct radeon_bo *bo; 494 int r; 495 u64 bytes_moved = 0, initial_bytes_moved; 496 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); 497 498 r = ttm_eu_reserve_buffers(ticket, head, true); 499 if (unlikely(r != 0)) { 500 return r; 501 } 502 503 list_for_each_entry(lobj, head, tv.head) { 504 bo = lobj->robj; 505 if (!bo->pin_count) { 506 u32 domain = lobj->prefered_domains; 507 u32 allowed = lobj->allowed_domains; 508 u32 current_domain = 509 radeon_mem_type_to_domain(bo->tbo.mem.mem_type); 510 511 /* Check if this buffer will be moved and don't move it 512 * if we have moved too many buffers for this IB already. 513 * 514 * Note that this allows moving at least one buffer of 515 * any size, because it doesn't take the current "bo" 516 * into account. We don't want to disallow buffer moves 517 * completely. 518 */ 519 if ((allowed & current_domain) != 0 && 520 (domain & current_domain) == 0 && /* will be moved */ 521 bytes_moved > bytes_moved_threshold) { 522 /* don't move it */ 523 domain = current_domain; 524 } 525 526 retry: 527 radeon_ttm_placement_from_domain(bo, domain); 528 if (ring == R600_RING_TYPE_UVD_INDEX) 529 radeon_uvd_force_into_uvd_segment(bo, allowed); 530 531 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); 532 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 533 bytes_moved += atomic64_read(&rdev->num_bytes_moved) - 534 initial_bytes_moved; 535 536 if (unlikely(r)) { 537 if (r != -ERESTARTSYS && 538 domain != lobj->allowed_domains) { 539 domain = lobj->allowed_domains; 540 goto retry; 541 } 542 ttm_eu_backoff_reservation(ticket, head); 543 return r; 544 } 545 } 546 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 547 lobj->tiling_flags = bo->tiling_flags; 548 } 549 return 0; 550 } 551 552 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 553 { 554 struct radeon_device *rdev = bo->rdev; 555 struct radeon_surface_reg *reg; 556 struct radeon_bo *old_object; 557 int steal; 558 int i; 559 560 if (!bo->tiling_flags) 561 return 0; 562 563 if (bo->surface_reg >= 0) { 564 reg = &rdev->surface_regs[bo->surface_reg]; 565 i = bo->surface_reg; 566 goto out; 567 } 568 569 steal = -1; 570 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 571 572 reg = &rdev->surface_regs[i]; 573 if (!reg->bo) 574 break; 575 576 old_object = reg->bo; 577 if (old_object->pin_count == 0) 578 steal = i; 579 } 580 581 /* if we are all out */ 582 if (i == RADEON_GEM_MAX_SURFACES) { 583 if (steal == -1) 584 return -ENOMEM; 585 /* find someone with a surface reg and nuke their BO */ 586 reg = &rdev->surface_regs[steal]; 587 old_object = reg->bo; 588 /* blow away the mapping */ 589 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 590 ttm_bo_unmap_virtual(&old_object->tbo); 591 old_object->surface_reg = -1; 592 i = steal; 593 } 594 595 bo->surface_reg = i; 596 reg->bo = bo; 597 598 out: 599 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 600 bo->tbo.mem.start << PAGE_SHIFT, 601 bo->tbo.num_pages << PAGE_SHIFT); 602 return 0; 603 } 604 605 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 606 { 607 struct radeon_device *rdev = bo->rdev; 608 struct radeon_surface_reg *reg; 609 610 if (bo->surface_reg == -1) 611 return; 612 613 reg = &rdev->surface_regs[bo->surface_reg]; 614 radeon_clear_surface_reg(rdev, bo->surface_reg); 615 616 reg->bo = NULL; 617 bo->surface_reg = -1; 618 } 619 620 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 621 uint32_t tiling_flags, uint32_t pitch) 622 { 623 struct radeon_device *rdev = bo->rdev; 624 int r; 625 626 if (rdev->family >= CHIP_CEDAR) { 627 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 628 629 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 630 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 631 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 632 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 633 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 634 switch (bankw) { 635 case 0: 636 case 1: 637 case 2: 638 case 4: 639 case 8: 640 break; 641 default: 642 return -EINVAL; 643 } 644 switch (bankh) { 645 case 0: 646 case 1: 647 case 2: 648 case 4: 649 case 8: 650 break; 651 default: 652 return -EINVAL; 653 } 654 switch (mtaspect) { 655 case 0: 656 case 1: 657 case 2: 658 case 4: 659 case 8: 660 break; 661 default: 662 return -EINVAL; 663 } 664 if (tilesplit > 6) { 665 return -EINVAL; 666 } 667 if (stilesplit > 6) { 668 return -EINVAL; 669 } 670 } 671 r = radeon_bo_reserve(bo, false); 672 if (unlikely(r != 0)) 673 return r; 674 bo->tiling_flags = tiling_flags; 675 bo->pitch = pitch; 676 radeon_bo_unreserve(bo); 677 return 0; 678 } 679 680 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 681 uint32_t *tiling_flags, 682 uint32_t *pitch) 683 { 684 if (tiling_flags) 685 *tiling_flags = bo->tiling_flags; 686 if (pitch) 687 *pitch = bo->pitch; 688 } 689 690 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 691 bool force_drop) 692 { 693 694 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 695 return 0; 696 697 if (force_drop) { 698 radeon_bo_clear_surface_reg(bo); 699 return 0; 700 } 701 702 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 703 if (!has_moved) 704 return 0; 705 706 if (bo->surface_reg >= 0) 707 radeon_bo_clear_surface_reg(bo); 708 return 0; 709 } 710 711 if ((bo->surface_reg >= 0) && !has_moved) 712 return 0; 713 714 return radeon_bo_get_surface_reg(bo); 715 } 716 717 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 718 struct ttm_mem_reg *new_mem) 719 { 720 struct radeon_bo *rbo; 721 722 if (!radeon_ttm_bo_is_radeon_bo(bo)) 723 return; 724 725 rbo = container_of(bo, struct radeon_bo, tbo); 726 radeon_bo_check_tiling(rbo, 0, 1); 727 radeon_vm_bo_invalidate(rbo->rdev, rbo); 728 729 /* update statistics */ 730 if (!new_mem) 731 return; 732 733 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); 734 radeon_update_memory_usage(rbo, new_mem->mem_type, 1); 735 } 736 737 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 738 { 739 struct radeon_device *rdev; 740 struct radeon_bo *rbo; 741 unsigned long offset, size; 742 int r; 743 744 if (!radeon_ttm_bo_is_radeon_bo(bo)) 745 return 0; 746 rbo = container_of(bo, struct radeon_bo, tbo); 747 radeon_bo_check_tiling(rbo, 0, 0); 748 rdev = rbo->rdev; 749 if (bo->mem.mem_type != TTM_PL_VRAM) 750 return 0; 751 752 size = bo->mem.num_pages << PAGE_SHIFT; 753 offset = bo->mem.start << PAGE_SHIFT; 754 if ((offset + size) <= rdev->mc.visible_vram_size) 755 return 0; 756 757 /* hurrah the memory is not visible ! */ 758 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 759 rbo->placements[0].lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 760 r = ttm_bo_validate(bo, &rbo->placement, false, false); 761 if (unlikely(r == -ENOMEM)) { 762 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 763 return ttm_bo_validate(bo, &rbo->placement, false, false); 764 } else if (unlikely(r != 0)) { 765 return r; 766 } 767 768 offset = bo->mem.start << PAGE_SHIFT; 769 /* this should never happen */ 770 if ((offset + size) > rdev->mc.visible_vram_size) 771 return -EINVAL; 772 773 return 0; 774 } 775 776 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) 777 { 778 int r; 779 780 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL); 781 if (unlikely(r != 0)) 782 return r; 783 if (mem_type) 784 *mem_type = bo->tbo.mem.mem_type; 785 786 r = ttm_bo_wait(&bo->tbo, true, true, no_wait); 787 ttm_bo_unreserve(&bo->tbo); 788 return r; 789 } 790 791 792 /** 793 * radeon_bo_reserve - reserve bo 794 * @bo: bo structure 795 * @no_intr: don't return -ERESTARTSYS on pending signal 796 * 797 * Returns: 798 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 799 * a signal. Release all buffer reservations and return to user-space. 800 */ 801 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr) 802 { 803 int r; 804 805 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0); 806 if (unlikely(r != 0)) { 807 if (r != -ERESTARTSYS) 808 dev_err(bo->rdev->dev, "%p reserve failed\n", bo); 809 return r; 810 } 811 return 0; 812 } 813