1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <drm/drmP.h> 34 #include <drm/radeon_drm.h> 35 #include "radeon.h" 36 #include "radeon_trace.h" 37 38 39 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 40 41 /* 42 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 43 * function are calling it. 44 */ 45 46 static void radeon_update_memory_usage(struct radeon_bo *bo, 47 unsigned mem_type, int sign) 48 { 49 struct radeon_device *rdev = bo->rdev; 50 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT; 51 52 switch (mem_type) { 53 case TTM_PL_TT: 54 if (sign > 0) 55 atomic64_add(size, &rdev->gtt_usage); 56 else 57 atomic64_sub(size, &rdev->gtt_usage); 58 break; 59 case TTM_PL_VRAM: 60 if (sign > 0) 61 atomic64_add(size, &rdev->vram_usage); 62 else 63 atomic64_sub(size, &rdev->vram_usage); 64 break; 65 } 66 } 67 68 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 69 { 70 struct radeon_bo *bo; 71 72 bo = container_of(tbo, struct radeon_bo, tbo); 73 74 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); 75 radeon_mn_unregister(bo); 76 77 mutex_lock(&bo->rdev->gem.mutex); 78 list_del_init(&bo->list); 79 mutex_unlock(&bo->rdev->gem.mutex); 80 radeon_bo_clear_surface_reg(bo); 81 WARN_ON(!list_empty(&bo->va)); 82 drm_gem_object_release(&bo->gem_base); 83 kfree(bo); 84 } 85 86 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 87 { 88 if (bo->destroy == &radeon_ttm_bo_destroy) 89 return true; 90 return false; 91 } 92 93 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 94 { 95 u32 c = 0, i; 96 97 rbo->placement.placement = rbo->placements; 98 rbo->placement.busy_placement = rbo->placements; 99 if (domain & RADEON_GEM_DOMAIN_VRAM) { 100 /* Try placing BOs which don't need CPU access outside of the 101 * CPU accessible part of VRAM 102 */ 103 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && 104 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { 105 rbo->placements[c].fpfn = 106 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 107 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 108 TTM_PL_FLAG_UNCACHED | 109 TTM_PL_FLAG_VRAM; 110 } 111 112 rbo->placements[c].fpfn = 0; 113 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 114 TTM_PL_FLAG_UNCACHED | 115 TTM_PL_FLAG_VRAM; 116 } 117 118 if (domain & RADEON_GEM_DOMAIN_GTT) { 119 if (rbo->flags & RADEON_GEM_GTT_UC) { 120 rbo->placements[c].fpfn = 0; 121 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | 122 TTM_PL_FLAG_TT; 123 124 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 125 (rbo->rdev->flags & RADEON_IS_AGP)) { 126 rbo->placements[c].fpfn = 0; 127 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 128 TTM_PL_FLAG_UNCACHED | 129 TTM_PL_FLAG_TT; 130 } else { 131 rbo->placements[c].fpfn = 0; 132 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | 133 TTM_PL_FLAG_TT; 134 } 135 } 136 137 if (domain & RADEON_GEM_DOMAIN_CPU) { 138 if (rbo->flags & RADEON_GEM_GTT_UC) { 139 rbo->placements[c].fpfn = 0; 140 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | 141 TTM_PL_FLAG_SYSTEM; 142 143 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 144 rbo->rdev->flags & RADEON_IS_AGP) { 145 rbo->placements[c].fpfn = 0; 146 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 147 TTM_PL_FLAG_UNCACHED | 148 TTM_PL_FLAG_SYSTEM; 149 } else { 150 rbo->placements[c].fpfn = 0; 151 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | 152 TTM_PL_FLAG_SYSTEM; 153 } 154 } 155 if (!c) { 156 rbo->placements[c].fpfn = 0; 157 rbo->placements[c++].flags = TTM_PL_MASK_CACHING | 158 TTM_PL_FLAG_SYSTEM; 159 } 160 161 rbo->placement.num_placement = c; 162 rbo->placement.num_busy_placement = c; 163 164 for (i = 0; i < c; ++i) { 165 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && 166 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && 167 !rbo->placements[i].fpfn) 168 rbo->placements[i].lpfn = 169 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 170 else 171 rbo->placements[i].lpfn = 0; 172 } 173 } 174 175 int radeon_bo_create(struct radeon_device *rdev, 176 unsigned long size, int byte_align, bool kernel, 177 u32 domain, u32 flags, struct sg_table *sg, 178 struct reservation_object *resv, 179 struct radeon_bo **bo_ptr) 180 { 181 struct radeon_bo *bo; 182 enum ttm_bo_type type; 183 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 184 size_t acc_size; 185 int r; 186 187 size = ALIGN(size, PAGE_SIZE); 188 189 if (kernel) { 190 type = ttm_bo_type_kernel; 191 } else if (sg) { 192 type = ttm_bo_type_sg; 193 } else { 194 type = ttm_bo_type_device; 195 } 196 *bo_ptr = NULL; 197 198 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 199 sizeof(struct radeon_bo)); 200 201 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 202 if (bo == NULL) 203 return -ENOMEM; 204 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); 205 if (unlikely(r)) { 206 kfree(bo); 207 return r; 208 } 209 bo->rdev = rdev; 210 bo->surface_reg = -1; 211 INIT_LIST_HEAD(&bo->list); 212 INIT_LIST_HEAD(&bo->va); 213 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | 214 RADEON_GEM_DOMAIN_GTT | 215 RADEON_GEM_DOMAIN_CPU); 216 217 bo->flags = flags; 218 /* PCI GART is always snooped */ 219 if (!(rdev->flags & RADEON_IS_PCIE)) 220 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 221 222 #ifdef CONFIG_X86_32 223 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 224 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 225 */ 226 bo->flags &= ~RADEON_GEM_GTT_WC; 227 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 228 /* Don't try to enable write-combining when it can't work, or things 229 * may be slow 230 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 231 */ 232 233 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 234 thanks to write-combining 235 236 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 237 "better performance thanks to write-combining\n"); 238 bo->flags &= ~RADEON_GEM_GTT_WC; 239 #endif 240 241 radeon_ttm_placement_from_domain(bo, domain); 242 /* Kernel allocation are uninterruptible */ 243 down_read(&rdev->pm.mclk_lock); 244 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 245 &bo->placement, page_align, !kernel, NULL, 246 acc_size, sg, resv, &radeon_ttm_bo_destroy); 247 up_read(&rdev->pm.mclk_lock); 248 if (unlikely(r != 0)) { 249 return r; 250 } 251 *bo_ptr = bo; 252 253 trace_radeon_bo_create(bo); 254 255 return 0; 256 } 257 258 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 259 { 260 bool is_iomem; 261 int r; 262 263 if (bo->kptr) { 264 if (ptr) { 265 *ptr = bo->kptr; 266 } 267 return 0; 268 } 269 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 270 if (r) { 271 return r; 272 } 273 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 274 if (ptr) { 275 *ptr = bo->kptr; 276 } 277 radeon_bo_check_tiling(bo, 0, 0); 278 return 0; 279 } 280 281 void radeon_bo_kunmap(struct radeon_bo *bo) 282 { 283 if (bo->kptr == NULL) 284 return; 285 bo->kptr = NULL; 286 radeon_bo_check_tiling(bo, 0, 0); 287 ttm_bo_kunmap(&bo->kmap); 288 } 289 290 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) 291 { 292 if (bo == NULL) 293 return NULL; 294 295 ttm_bo_reference(&bo->tbo); 296 return bo; 297 } 298 299 void radeon_bo_unref(struct radeon_bo **bo) 300 { 301 struct ttm_buffer_object *tbo; 302 struct radeon_device *rdev; 303 304 if ((*bo) == NULL) 305 return; 306 rdev = (*bo)->rdev; 307 tbo = &((*bo)->tbo); 308 ttm_bo_unref(&tbo); 309 if (tbo == NULL) 310 *bo = NULL; 311 } 312 313 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 314 u64 *gpu_addr) 315 { 316 int r, i; 317 318 if (bo->pin_count) { 319 bo->pin_count++; 320 if (gpu_addr) 321 *gpu_addr = radeon_bo_gpu_offset(bo); 322 323 if (max_offset != 0) { 324 u64 domain_start; 325 326 if (domain == RADEON_GEM_DOMAIN_VRAM) 327 domain_start = bo->rdev->mc.vram_start; 328 else 329 domain_start = bo->rdev->mc.gtt_start; 330 WARN_ON_ONCE(max_offset < 331 (radeon_bo_gpu_offset(bo) - domain_start)); 332 } 333 334 return 0; 335 } 336 radeon_ttm_placement_from_domain(bo, domain); 337 for (i = 0; i < bo->placement.num_placement; i++) { 338 /* force to pin into visible video ram */ 339 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 340 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && 341 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) 342 bo->placements[i].lpfn = 343 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 344 else 345 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; 346 347 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 348 } 349 350 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 351 if (likely(r == 0)) { 352 bo->pin_count = 1; 353 if (gpu_addr != NULL) 354 *gpu_addr = radeon_bo_gpu_offset(bo); 355 if (domain == RADEON_GEM_DOMAIN_VRAM) 356 bo->rdev->vram_pin_size += radeon_bo_size(bo); 357 else 358 bo->rdev->gart_pin_size += radeon_bo_size(bo); 359 } else { 360 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 361 } 362 return r; 363 } 364 365 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 366 { 367 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 368 } 369 370 int radeon_bo_unpin(struct radeon_bo *bo) 371 { 372 int r, i; 373 374 if (!bo->pin_count) { 375 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 376 return 0; 377 } 378 bo->pin_count--; 379 if (bo->pin_count) 380 return 0; 381 for (i = 0; i < bo->placement.num_placement; i++) { 382 bo->placements[i].lpfn = 0; 383 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 384 } 385 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 386 if (likely(r == 0)) { 387 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 388 bo->rdev->vram_pin_size -= radeon_bo_size(bo); 389 else 390 bo->rdev->gart_pin_size -= radeon_bo_size(bo); 391 } else { 392 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 393 } 394 return r; 395 } 396 397 int radeon_bo_evict_vram(struct radeon_device *rdev) 398 { 399 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 400 if (0 && (rdev->flags & RADEON_IS_IGP)) { 401 if (rdev->mc.igp_sideport_enabled == false) 402 /* Useless to evict on IGP chips */ 403 return 0; 404 } 405 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 406 } 407 408 void radeon_bo_force_delete(struct radeon_device *rdev) 409 { 410 struct radeon_bo *bo, *n; 411 412 if (list_empty(&rdev->gem.objects)) { 413 return; 414 } 415 dev_err(rdev->dev, "Userspace still has active objects !\n"); 416 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 417 mutex_lock(&rdev->ddev->struct_mutex); 418 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 419 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 420 *((unsigned long *)&bo->gem_base.refcount)); 421 mutex_lock(&bo->rdev->gem.mutex); 422 list_del_init(&bo->list); 423 mutex_unlock(&bo->rdev->gem.mutex); 424 /* this should unref the ttm bo */ 425 drm_gem_object_unreference(&bo->gem_base); 426 mutex_unlock(&rdev->ddev->struct_mutex); 427 } 428 } 429 430 int radeon_bo_init(struct radeon_device *rdev) 431 { 432 /* Add an MTRR for the VRAM */ 433 if (!rdev->fastfb_working) { 434 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, 435 rdev->mc.aper_size); 436 } 437 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 438 rdev->mc.mc_vram_size >> 20, 439 (unsigned long long)rdev->mc.aper_size >> 20); 440 DRM_INFO("RAM width %dbits %cDR\n", 441 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 442 return radeon_ttm_init(rdev); 443 } 444 445 void radeon_bo_fini(struct radeon_device *rdev) 446 { 447 radeon_ttm_fini(rdev); 448 arch_phys_wc_del(rdev->mc.vram_mtrr); 449 } 450 451 /* Returns how many bytes TTM can move per IB. 452 */ 453 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) 454 { 455 u64 real_vram_size = rdev->mc.real_vram_size; 456 u64 vram_usage = atomic64_read(&rdev->vram_usage); 457 458 /* This function is based on the current VRAM usage. 459 * 460 * - If all of VRAM is free, allow relocating the number of bytes that 461 * is equal to 1/4 of the size of VRAM for this IB. 462 463 * - If more than one half of VRAM is occupied, only allow relocating 464 * 1 MB of data for this IB. 465 * 466 * - From 0 to one half of used VRAM, the threshold decreases 467 * linearly. 468 * __________________ 469 * 1/4 of -|\ | 470 * VRAM | \ | 471 * | \ | 472 * | \ | 473 * | \ | 474 * | \ | 475 * | \ | 476 * | \________|1 MB 477 * |----------------| 478 * VRAM 0 % 100 % 479 * used used 480 * 481 * Note: It's a threshold, not a limit. The threshold must be crossed 482 * for buffer relocations to stop, so any buffer of an arbitrary size 483 * can be moved as long as the threshold isn't crossed before 484 * the relocation takes place. We don't want to disable buffer 485 * relocations completely. 486 * 487 * The idea is that buffers should be placed in VRAM at creation time 488 * and TTM should only do a minimum number of relocations during 489 * command submission. In practice, you need to submit at least 490 * a dozen IBs to move all buffers to VRAM if they are in GTT. 491 * 492 * Also, things can get pretty crazy under memory pressure and actual 493 * VRAM usage can change a lot, so playing safe even at 50% does 494 * consistently increase performance. 495 */ 496 497 u64 half_vram = real_vram_size >> 1; 498 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; 499 u64 bytes_moved_threshold = half_free_vram >> 1; 500 return max(bytes_moved_threshold, 1024*1024ull); 501 } 502 503 int radeon_bo_list_validate(struct radeon_device *rdev, 504 struct ww_acquire_ctx *ticket, 505 struct list_head *head, int ring) 506 { 507 struct radeon_bo_list *lobj; 508 struct list_head duplicates; 509 int r; 510 u64 bytes_moved = 0, initial_bytes_moved; 511 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); 512 513 INIT_LIST_HEAD(&duplicates); 514 r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates); 515 if (unlikely(r != 0)) { 516 return r; 517 } 518 519 list_for_each_entry(lobj, head, tv.head) { 520 struct radeon_bo *bo = lobj->robj; 521 if (!bo->pin_count) { 522 u32 domain = lobj->prefered_domains; 523 u32 allowed = lobj->allowed_domains; 524 u32 current_domain = 525 radeon_mem_type_to_domain(bo->tbo.mem.mem_type); 526 527 /* Check if this buffer will be moved and don't move it 528 * if we have moved too many buffers for this IB already. 529 * 530 * Note that this allows moving at least one buffer of 531 * any size, because it doesn't take the current "bo" 532 * into account. We don't want to disallow buffer moves 533 * completely. 534 */ 535 if ((allowed & current_domain) != 0 && 536 (domain & current_domain) == 0 && /* will be moved */ 537 bytes_moved > bytes_moved_threshold) { 538 /* don't move it */ 539 domain = current_domain; 540 } 541 542 retry: 543 radeon_ttm_placement_from_domain(bo, domain); 544 if (ring == R600_RING_TYPE_UVD_INDEX) 545 radeon_uvd_force_into_uvd_segment(bo, allowed); 546 547 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); 548 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 549 bytes_moved += atomic64_read(&rdev->num_bytes_moved) - 550 initial_bytes_moved; 551 552 if (unlikely(r)) { 553 if (r != -ERESTARTSYS && 554 domain != lobj->allowed_domains) { 555 domain = lobj->allowed_domains; 556 goto retry; 557 } 558 ttm_eu_backoff_reservation(ticket, head); 559 return r; 560 } 561 } 562 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 563 lobj->tiling_flags = bo->tiling_flags; 564 } 565 566 list_for_each_entry(lobj, &duplicates, tv.head) { 567 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); 568 lobj->tiling_flags = lobj->robj->tiling_flags; 569 } 570 571 return 0; 572 } 573 574 int radeon_bo_fbdev_mmap(struct radeon_bo *bo, 575 struct vm_area_struct *vma) 576 { 577 return ttm_fbdev_mmap(vma, &bo->tbo); 578 } 579 580 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 581 { 582 struct radeon_device *rdev = bo->rdev; 583 struct radeon_surface_reg *reg; 584 struct radeon_bo *old_object; 585 int steal; 586 int i; 587 588 lockdep_assert_held(&bo->tbo.resv->lock.base); 589 590 if (!bo->tiling_flags) 591 return 0; 592 593 if (bo->surface_reg >= 0) { 594 reg = &rdev->surface_regs[bo->surface_reg]; 595 i = bo->surface_reg; 596 goto out; 597 } 598 599 steal = -1; 600 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 601 602 reg = &rdev->surface_regs[i]; 603 if (!reg->bo) 604 break; 605 606 old_object = reg->bo; 607 if (old_object->pin_count == 0) 608 steal = i; 609 } 610 611 /* if we are all out */ 612 if (i == RADEON_GEM_MAX_SURFACES) { 613 if (steal == -1) 614 return -ENOMEM; 615 /* find someone with a surface reg and nuke their BO */ 616 reg = &rdev->surface_regs[steal]; 617 old_object = reg->bo; 618 /* blow away the mapping */ 619 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 620 ttm_bo_unmap_virtual(&old_object->tbo); 621 old_object->surface_reg = -1; 622 i = steal; 623 } 624 625 bo->surface_reg = i; 626 reg->bo = bo; 627 628 out: 629 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 630 bo->tbo.mem.start << PAGE_SHIFT, 631 bo->tbo.num_pages << PAGE_SHIFT); 632 return 0; 633 } 634 635 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 636 { 637 struct radeon_device *rdev = bo->rdev; 638 struct radeon_surface_reg *reg; 639 640 if (bo->surface_reg == -1) 641 return; 642 643 reg = &rdev->surface_regs[bo->surface_reg]; 644 radeon_clear_surface_reg(rdev, bo->surface_reg); 645 646 reg->bo = NULL; 647 bo->surface_reg = -1; 648 } 649 650 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 651 uint32_t tiling_flags, uint32_t pitch) 652 { 653 struct radeon_device *rdev = bo->rdev; 654 int r; 655 656 if (rdev->family >= CHIP_CEDAR) { 657 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 658 659 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 660 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 661 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 662 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 663 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 664 switch (bankw) { 665 case 0: 666 case 1: 667 case 2: 668 case 4: 669 case 8: 670 break; 671 default: 672 return -EINVAL; 673 } 674 switch (bankh) { 675 case 0: 676 case 1: 677 case 2: 678 case 4: 679 case 8: 680 break; 681 default: 682 return -EINVAL; 683 } 684 switch (mtaspect) { 685 case 0: 686 case 1: 687 case 2: 688 case 4: 689 case 8: 690 break; 691 default: 692 return -EINVAL; 693 } 694 if (tilesplit > 6) { 695 return -EINVAL; 696 } 697 if (stilesplit > 6) { 698 return -EINVAL; 699 } 700 } 701 r = radeon_bo_reserve(bo, false); 702 if (unlikely(r != 0)) 703 return r; 704 bo->tiling_flags = tiling_flags; 705 bo->pitch = pitch; 706 radeon_bo_unreserve(bo); 707 return 0; 708 } 709 710 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 711 uint32_t *tiling_flags, 712 uint32_t *pitch) 713 { 714 lockdep_assert_held(&bo->tbo.resv->lock.base); 715 716 if (tiling_flags) 717 *tiling_flags = bo->tiling_flags; 718 if (pitch) 719 *pitch = bo->pitch; 720 } 721 722 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 723 bool force_drop) 724 { 725 if (!force_drop) 726 lockdep_assert_held(&bo->tbo.resv->lock.base); 727 728 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 729 return 0; 730 731 if (force_drop) { 732 radeon_bo_clear_surface_reg(bo); 733 return 0; 734 } 735 736 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 737 if (!has_moved) 738 return 0; 739 740 if (bo->surface_reg >= 0) 741 radeon_bo_clear_surface_reg(bo); 742 return 0; 743 } 744 745 if ((bo->surface_reg >= 0) && !has_moved) 746 return 0; 747 748 return radeon_bo_get_surface_reg(bo); 749 } 750 751 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 752 struct ttm_mem_reg *new_mem) 753 { 754 struct radeon_bo *rbo; 755 756 if (!radeon_ttm_bo_is_radeon_bo(bo)) 757 return; 758 759 rbo = container_of(bo, struct radeon_bo, tbo); 760 radeon_bo_check_tiling(rbo, 0, 1); 761 radeon_vm_bo_invalidate(rbo->rdev, rbo); 762 763 /* update statistics */ 764 if (!new_mem) 765 return; 766 767 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); 768 radeon_update_memory_usage(rbo, new_mem->mem_type, 1); 769 } 770 771 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 772 { 773 struct radeon_device *rdev; 774 struct radeon_bo *rbo; 775 unsigned long offset, size, lpfn; 776 int i, r; 777 778 if (!radeon_ttm_bo_is_radeon_bo(bo)) 779 return 0; 780 rbo = container_of(bo, struct radeon_bo, tbo); 781 radeon_bo_check_tiling(rbo, 0, 0); 782 rdev = rbo->rdev; 783 if (bo->mem.mem_type != TTM_PL_VRAM) 784 return 0; 785 786 size = bo->mem.num_pages << PAGE_SHIFT; 787 offset = bo->mem.start << PAGE_SHIFT; 788 if ((offset + size) <= rdev->mc.visible_vram_size) 789 return 0; 790 791 /* hurrah the memory is not visible ! */ 792 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 793 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 794 for (i = 0; i < rbo->placement.num_placement; i++) { 795 /* Force into visible VRAM */ 796 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && 797 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) 798 rbo->placements[i].lpfn = lpfn; 799 } 800 r = ttm_bo_validate(bo, &rbo->placement, false, false); 801 if (unlikely(r == -ENOMEM)) { 802 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 803 return ttm_bo_validate(bo, &rbo->placement, false, false); 804 } else if (unlikely(r != 0)) { 805 return r; 806 } 807 808 offset = bo->mem.start << PAGE_SHIFT; 809 /* this should never happen */ 810 if ((offset + size) > rdev->mc.visible_vram_size) 811 return -EINVAL; 812 813 return 0; 814 } 815 816 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) 817 { 818 int r; 819 820 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL); 821 if (unlikely(r != 0)) 822 return r; 823 if (mem_type) 824 *mem_type = bo->tbo.mem.mem_type; 825 826 r = ttm_bo_wait(&bo->tbo, true, true, no_wait); 827 ttm_bo_unreserve(&bo->tbo); 828 return r; 829 } 830 831 /** 832 * radeon_bo_fence - add fence to buffer object 833 * 834 * @bo: buffer object in question 835 * @fence: fence to add 836 * @shared: true if fence should be added shared 837 * 838 */ 839 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, 840 bool shared) 841 { 842 struct reservation_object *resv = bo->tbo.resv; 843 844 if (shared) 845 reservation_object_add_shared_fence(resv, &fence->base); 846 else 847 reservation_object_add_excl_fence(resv, &fence->base); 848 } 849