1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 * 32 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_object.c 254885 2013-08-25 19:37:15Z dumbbell $ 33 */ 34 35 #include <drm/drmP.h> 36 #include <uapi_drm/radeon_drm.h> 37 #include "radeon.h" 38 #ifdef DUMBBELL_WIP 39 #include "radeon_trace.h" 40 #endif /* DUMBBELL_WIP */ 41 42 43 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 44 45 /* 46 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 47 * function are calling it. 48 */ 49 50 static void radeon_bo_clear_va(struct radeon_bo *bo) 51 { 52 struct radeon_bo_va *bo_va, *tmp; 53 54 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) { 55 /* remove from all vm address space */ 56 radeon_vm_bo_rmv(bo->rdev, bo_va); 57 } 58 } 59 60 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 61 { 62 struct radeon_bo *bo; 63 64 bo = container_of(tbo, struct radeon_bo, tbo); 65 spin_lock(&bo->rdev->gem.mutex); 66 list_del_init(&bo->list); 67 spin_unlock(&bo->rdev->gem.mutex); 68 radeon_bo_clear_surface_reg(bo); 69 radeon_bo_clear_va(bo); 70 drm_gem_object_release(&bo->gem_base); 71 drm_free(bo, M_DRM); 72 } 73 74 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 75 { 76 if (bo->destroy == &radeon_ttm_bo_destroy) 77 return true; 78 return false; 79 } 80 81 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 82 { 83 u32 c = 0; 84 85 rbo->placement.fpfn = 0; 86 rbo->placement.lpfn = 0; 87 rbo->placement.placement = rbo->placements; 88 rbo->placement.busy_placement = rbo->placements; 89 if (domain & RADEON_GEM_DOMAIN_VRAM) 90 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 91 TTM_PL_FLAG_VRAM; 92 if (domain & RADEON_GEM_DOMAIN_GTT) { 93 if (rbo->rdev->flags & RADEON_IS_AGP) { 94 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT; 95 } else { 96 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; 97 } 98 } 99 if (domain & RADEON_GEM_DOMAIN_CPU) { 100 if (rbo->rdev->flags & RADEON_IS_AGP) { 101 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM; 102 } else { 103 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; 104 } 105 } 106 if (!c) 107 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 108 rbo->placement.num_placement = c; 109 rbo->placement.num_busy_placement = c; 110 } 111 112 int radeon_bo_create(struct radeon_device *rdev, 113 unsigned long size, int byte_align, bool kernel, u32 domain, 114 struct sg_table *sg, struct radeon_bo **bo_ptr) 115 { 116 struct radeon_bo *bo; 117 enum ttm_bo_type type; 118 unsigned long page_align = roundup2(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 119 size_t acc_size; 120 int r; 121 122 size = roundup2(size, PAGE_SIZE); 123 124 if (kernel) { 125 type = ttm_bo_type_kernel; 126 } else if (sg) { 127 type = ttm_bo_type_sg; 128 } else { 129 type = ttm_bo_type_device; 130 } 131 *bo_ptr = NULL; 132 133 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 134 sizeof(struct radeon_bo)); 135 136 bo = kmalloc(sizeof(struct radeon_bo), M_DRM, 137 M_ZERO | M_WAITOK); 138 if (bo == NULL) 139 return -ENOMEM; 140 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); 141 if (unlikely(r)) { 142 drm_free(bo, M_DRM); 143 return r; 144 } 145 bo->rdev = rdev; 146 bo->surface_reg = -1; 147 INIT_LIST_HEAD(&bo->list); 148 INIT_LIST_HEAD(&bo->va); 149 radeon_ttm_placement_from_domain(bo, domain); 150 /* Kernel allocation are uninterruptible */ 151 lockmgr(&rdev->pm.mclk_lock, LK_SHARED); 152 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 153 &bo->placement, page_align, !kernel, NULL, 154 acc_size, sg, &radeon_ttm_bo_destroy); 155 lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); 156 if (unlikely(r != 0)) { 157 return r; 158 } 159 *bo_ptr = bo; 160 161 #ifdef DUMBBELL_WIP 162 trace_radeon_bo_create(bo); 163 #endif /* DUMBBELL_WIP */ 164 165 return 0; 166 } 167 168 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 169 { 170 bool is_iomem; 171 int r; 172 173 if (bo->kptr) { 174 if (ptr) { 175 *ptr = bo->kptr; 176 } 177 return 0; 178 } 179 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 180 if (r) { 181 return r; 182 } 183 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 184 if (ptr) { 185 *ptr = bo->kptr; 186 } 187 radeon_bo_check_tiling(bo, 0, 0); 188 return 0; 189 } 190 191 void radeon_bo_kunmap(struct radeon_bo *bo) 192 { 193 if (bo->kptr == NULL) 194 return; 195 bo->kptr = NULL; 196 radeon_bo_check_tiling(bo, 0, 0); 197 ttm_bo_kunmap(&bo->kmap); 198 } 199 200 void radeon_bo_unref(struct radeon_bo **bo) 201 { 202 struct ttm_buffer_object *tbo; 203 struct radeon_device *rdev; 204 struct radeon_bo *rbo; 205 206 if ((rbo = *bo) == NULL) 207 return; 208 *bo = NULL; 209 rdev = rbo->rdev; 210 tbo = &rbo->tbo; 211 lockmgr(&rdev->pm.mclk_lock, LK_SHARED); 212 ttm_bo_unref(&tbo); 213 lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); 214 } 215 216 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 217 u64 *gpu_addr) 218 { 219 int r, i; 220 221 if (bo->pin_count) { 222 bo->pin_count++; 223 if (gpu_addr) 224 *gpu_addr = radeon_bo_gpu_offset(bo); 225 226 if (max_offset != 0) { 227 u64 domain_start; 228 229 if (domain == RADEON_GEM_DOMAIN_VRAM) 230 domain_start = bo->rdev->mc.vram_start; 231 else 232 domain_start = bo->rdev->mc.gtt_start; 233 if (max_offset < (radeon_bo_gpu_offset(bo) - domain_start)) { 234 DRM_ERROR("radeon_bo_pin_restricted: " 235 "max_offset(%ju) < " 236 "(radeon_bo_gpu_offset(%ju) - " 237 "domain_start(%ju)", 238 (uintmax_t)max_offset, (uintmax_t)radeon_bo_gpu_offset(bo), 239 (uintmax_t)domain_start); 240 } 241 } 242 243 return 0; 244 } 245 radeon_ttm_placement_from_domain(bo, domain); 246 if (domain == RADEON_GEM_DOMAIN_VRAM) { 247 /* force to pin into visible video ram */ 248 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 249 } 250 if (max_offset) { 251 u64 lpfn = max_offset >> PAGE_SHIFT; 252 253 if (!bo->placement.lpfn) 254 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; 255 256 if (lpfn < bo->placement.lpfn) 257 bo->placement.lpfn = lpfn; 258 } 259 for (i = 0; i < bo->placement.num_placement; i++) 260 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; 261 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 262 if (likely(r == 0)) { 263 bo->pin_count = 1; 264 if (gpu_addr != NULL) 265 *gpu_addr = radeon_bo_gpu_offset(bo); 266 } 267 if (unlikely(r != 0)) 268 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 269 return r; 270 } 271 272 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 273 { 274 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 275 } 276 277 int radeon_bo_unpin(struct radeon_bo *bo) 278 { 279 int r, i; 280 281 if (!bo->pin_count) { 282 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 283 return 0; 284 } 285 bo->pin_count--; 286 if (bo->pin_count) 287 return 0; 288 for (i = 0; i < bo->placement.num_placement; i++) 289 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; 290 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 291 if (unlikely(r != 0)) 292 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 293 return r; 294 } 295 296 int radeon_bo_evict_vram(struct radeon_device *rdev) 297 { 298 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 299 if (0 && (rdev->flags & RADEON_IS_IGP)) { 300 if (rdev->mc.igp_sideport_enabled == false) 301 /* Useless to evict on IGP chips */ 302 return 0; 303 } 304 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 305 } 306 307 void radeon_bo_force_delete(struct radeon_device *rdev) 308 { 309 struct radeon_bo *bo, *n; 310 311 if (list_empty(&rdev->gem.objects)) { 312 return; 313 } 314 dev_err(rdev->dev, "Userspace still has active objects !\n"); 315 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 316 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 317 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 318 *((unsigned long *)&bo->gem_base.refcount)); 319 spin_lock(&bo->rdev->gem.mutex); 320 list_del_init(&bo->list); 321 spin_unlock(&bo->rdev->gem.mutex); 322 /* this should unref the ttm bo */ 323 drm_gem_object_unreference(&bo->gem_base); 324 } 325 } 326 327 int radeon_bo_init(struct radeon_device *rdev) 328 { 329 /* Add an MTRR for the VRAM */ 330 rdev->mc.vram_mtrr = drm_mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, 331 DRM_MTRR_WC); 332 DRM_INFO("Detected VRAM RAM=%juM, BAR=%juM\n", 333 (uintmax_t)rdev->mc.mc_vram_size >> 20, 334 (uintmax_t)rdev->mc.aper_size >> 20); 335 DRM_INFO("RAM width %dbits %cDR\n", 336 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 337 return radeon_ttm_init(rdev); 338 } 339 340 void radeon_bo_fini(struct radeon_device *rdev) 341 { 342 radeon_ttm_fini(rdev); 343 } 344 345 void radeon_bo_list_add_object(struct radeon_bo_list *lobj, 346 struct list_head *head) 347 { 348 if (lobj->wdomain) { 349 list_add(&lobj->tv.head, head); 350 } else { 351 list_add_tail(&lobj->tv.head, head); 352 } 353 } 354 355 int radeon_bo_list_validate(struct list_head *head) 356 { 357 struct radeon_bo_list *lobj; 358 struct radeon_bo *bo; 359 u32 domain; 360 int r; 361 362 r = ttm_eu_reserve_buffers(head); 363 if (unlikely(r != 0)) { 364 return r; 365 } 366 list_for_each_entry(lobj, head, tv.head) { 367 bo = lobj->bo; 368 if (!bo->pin_count) { 369 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain; 370 371 retry: 372 radeon_ttm_placement_from_domain(bo, domain); 373 r = ttm_bo_validate(&bo->tbo, &bo->placement, 374 true, false); 375 if (unlikely(r)) { 376 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) { 377 domain |= RADEON_GEM_DOMAIN_GTT; 378 goto retry; 379 } 380 return r; 381 } 382 } 383 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 384 lobj->tiling_flags = bo->tiling_flags; 385 } 386 return 0; 387 } 388 389 #ifdef DUMBBELL_WIP 390 int radeon_bo_fbdev_mmap(struct radeon_bo *bo, 391 struct vm_area_struct *vma) 392 { 393 return ttm_fbdev_mmap(vma, &bo->tbo); 394 } 395 #endif /* DUMBBELL_WIP */ 396 397 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 398 { 399 struct radeon_device *rdev = bo->rdev; 400 struct radeon_surface_reg *reg; 401 struct radeon_bo *old_object; 402 int steal; 403 int i; 404 405 KASSERT(radeon_bo_is_reserved(bo), 406 ("radeon_bo_get_surface_reg: radeon_bo is not reserved")); 407 408 if (!bo->tiling_flags) 409 return 0; 410 411 if (bo->surface_reg >= 0) { 412 reg = &rdev->surface_regs[bo->surface_reg]; 413 i = bo->surface_reg; 414 goto out; 415 } 416 417 steal = -1; 418 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 419 420 reg = &rdev->surface_regs[i]; 421 if (!reg->bo) 422 break; 423 424 old_object = reg->bo; 425 if (old_object->pin_count == 0) 426 steal = i; 427 } 428 429 /* if we are all out */ 430 if (i == RADEON_GEM_MAX_SURFACES) { 431 if (steal == -1) 432 return -ENOMEM; 433 /* find someone with a surface reg and nuke their BO */ 434 reg = &rdev->surface_regs[steal]; 435 old_object = reg->bo; 436 /* blow away the mapping */ 437 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 438 ttm_bo_unmap_virtual(&old_object->tbo); 439 old_object->surface_reg = -1; 440 i = steal; 441 } 442 443 bo->surface_reg = i; 444 reg->bo = bo; 445 446 out: 447 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 448 bo->tbo.mem.start << PAGE_SHIFT, 449 bo->tbo.num_pages << PAGE_SHIFT); 450 return 0; 451 } 452 453 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 454 { 455 struct radeon_device *rdev = bo->rdev; 456 struct radeon_surface_reg *reg; 457 458 if (bo->surface_reg == -1) 459 return; 460 461 reg = &rdev->surface_regs[bo->surface_reg]; 462 radeon_clear_surface_reg(rdev, bo->surface_reg); 463 464 reg->bo = NULL; 465 bo->surface_reg = -1; 466 } 467 468 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 469 uint32_t tiling_flags, uint32_t pitch) 470 { 471 struct radeon_device *rdev = bo->rdev; 472 int r; 473 474 if (rdev->family >= CHIP_CEDAR) { 475 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 476 477 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 478 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 479 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 480 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 481 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 482 switch (bankw) { 483 case 0: 484 case 1: 485 case 2: 486 case 4: 487 case 8: 488 break; 489 default: 490 return -EINVAL; 491 } 492 switch (bankh) { 493 case 0: 494 case 1: 495 case 2: 496 case 4: 497 case 8: 498 break; 499 default: 500 return -EINVAL; 501 } 502 switch (mtaspect) { 503 case 0: 504 case 1: 505 case 2: 506 case 4: 507 case 8: 508 break; 509 default: 510 return -EINVAL; 511 } 512 if (tilesplit > 6) { 513 return -EINVAL; 514 } 515 if (stilesplit > 6) { 516 return -EINVAL; 517 } 518 } 519 r = radeon_bo_reserve(bo, false); 520 if (unlikely(r != 0)) 521 return r; 522 bo->tiling_flags = tiling_flags; 523 bo->pitch = pitch; 524 radeon_bo_unreserve(bo); 525 return 0; 526 } 527 528 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 529 uint32_t *tiling_flags, 530 uint32_t *pitch) 531 { 532 KASSERT(radeon_bo_is_reserved(bo), 533 ("radeon_bo_get_tiling_flags: radeon_bo is not reserved")); 534 if (tiling_flags) 535 *tiling_flags = bo->tiling_flags; 536 if (pitch) 537 *pitch = bo->pitch; 538 } 539 540 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 541 bool force_drop) 542 { 543 KASSERT((radeon_bo_is_reserved(bo) || force_drop), 544 ("radeon_bo_check_tiling: radeon_bo is not reserved && !force_drop")); 545 546 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 547 return 0; 548 549 if (force_drop) { 550 radeon_bo_clear_surface_reg(bo); 551 return 0; 552 } 553 554 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 555 if (!has_moved) 556 return 0; 557 558 if (bo->surface_reg >= 0) 559 radeon_bo_clear_surface_reg(bo); 560 return 0; 561 } 562 563 if ((bo->surface_reg >= 0) && !has_moved) 564 return 0; 565 566 return radeon_bo_get_surface_reg(bo); 567 } 568 569 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 570 struct ttm_mem_reg *mem) 571 { 572 struct radeon_bo *rbo; 573 if (!radeon_ttm_bo_is_radeon_bo(bo)) 574 return; 575 rbo = container_of(bo, struct radeon_bo, tbo); 576 radeon_bo_check_tiling(rbo, 0, 1); 577 radeon_vm_bo_invalidate(rbo->rdev, rbo); 578 } 579 580 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 581 { 582 struct radeon_device *rdev; 583 struct radeon_bo *rbo; 584 unsigned long offset, size; 585 int r; 586 587 if (!radeon_ttm_bo_is_radeon_bo(bo)) 588 return 0; 589 rbo = container_of(bo, struct radeon_bo, tbo); 590 radeon_bo_check_tiling(rbo, 0, 0); 591 rdev = rbo->rdev; 592 if (bo->mem.mem_type == TTM_PL_VRAM) { 593 size = bo->mem.num_pages << PAGE_SHIFT; 594 offset = bo->mem.start << PAGE_SHIFT; 595 if ((offset + size) > rdev->mc.visible_vram_size) { 596 /* hurrah the memory is not visible ! */ 597 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 598 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 599 r = ttm_bo_validate(bo, &rbo->placement, false, false); 600 if (unlikely(r != 0)) 601 return r; 602 offset = bo->mem.start << PAGE_SHIFT; 603 /* this should not happen */ 604 if ((offset + size) > rdev->mc.visible_vram_size) 605 return -EINVAL; 606 } 607 } 608 return 0; 609 } 610 611 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) 612 { 613 int r; 614 615 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 616 if (unlikely(r != 0)) 617 return r; 618 lockmgr(&bo->tbo.bdev->fence_lock, LK_EXCLUSIVE); 619 if (mem_type) 620 *mem_type = bo->tbo.mem.mem_type; 621 if (bo->tbo.sync_obj) 622 r = ttm_bo_wait(&bo->tbo, true, true, no_wait); 623 lockmgr(&bo->tbo.bdev->fence_lock, LK_RELEASE); 624 ttm_bo_unreserve(&bo->tbo); 625 return r; 626 } 627 628 629 /** 630 * radeon_bo_reserve - reserve bo 631 * @bo: bo structure 632 * @no_intr: don't return -ERESTARTSYS on pending signal 633 * 634 * Returns: 635 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 636 * a signal. Release all buffer reservations and return to user-space. 637 */ 638 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr) 639 { 640 int r; 641 642 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0); 643 if (unlikely(r != 0)) { 644 if (r != -ERESTARTSYS) 645 dev_err(bo->rdev->dev, "%p reserve failed\n", bo); 646 return r; 647 } 648 return 0; 649 } 650