1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef RADEON_MODE_H 31 #define RADEON_MODE_H 32 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_fixed.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <linux/i2c.h> 39 #include <linux/i2c-algo-bit.h> 40 41 42 struct radeon_bo; 43 struct radeon_device; 44 45 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 46 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 47 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 48 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 49 50 #define RADEON_MAX_HPD_PINS 7 51 #define RADEON_MAX_CRTCS 6 52 #define RADEON_MAX_AFMT_BLOCKS 7 53 54 enum radeon_rmx_type { 55 RMX_OFF, 56 RMX_FULL, 57 RMX_CENTER, 58 RMX_ASPECT 59 }; 60 61 enum radeon_tv_std { 62 TV_STD_NTSC, 63 TV_STD_PAL, 64 TV_STD_PAL_M, 65 TV_STD_PAL_60, 66 TV_STD_NTSC_J, 67 TV_STD_SCART_PAL, 68 TV_STD_SECAM, 69 TV_STD_PAL_CN, 70 TV_STD_PAL_N, 71 }; 72 73 enum radeon_underscan_type { 74 UNDERSCAN_OFF, 75 UNDERSCAN_ON, 76 UNDERSCAN_AUTO, 77 }; 78 79 enum radeon_hpd_id { 80 RADEON_HPD_1 = 0, 81 RADEON_HPD_2, 82 RADEON_HPD_3, 83 RADEON_HPD_4, 84 RADEON_HPD_5, 85 RADEON_HPD_6, 86 RADEON_HPD_NONE = 0xff, 87 }; 88 89 enum radeon_output_csc { 90 RADEON_OUTPUT_CSC_BYPASS = 0, 91 RADEON_OUTPUT_CSC_TVRGB = 1, 92 RADEON_OUTPUT_CSC_YCBCR601 = 2, 93 RADEON_OUTPUT_CSC_YCBCR709 = 3, 94 }; 95 96 #define RADEON_MAX_I2C_BUS 16 97 98 /* radeon gpio-based i2c 99 * 1. "mask" reg and bits 100 * grabs the gpio pins for software use 101 * 0=not held 1=held 102 * 2. "a" reg and bits 103 * output pin value 104 * 0=low 1=high 105 * 3. "en" reg and bits 106 * sets the pin direction 107 * 0=input 1=output 108 * 4. "y" reg and bits 109 * input pin value 110 * 0=low 1=high 111 */ 112 struct radeon_i2c_bus_rec { 113 bool valid; 114 /* id used by atom */ 115 uint8_t i2c_id; 116 /* id used by atom */ 117 enum radeon_hpd_id hpd; 118 /* can be used with hw i2c engine */ 119 bool hw_capable; 120 /* uses multi-media i2c engine */ 121 bool mm_i2c; 122 /* regs and bits */ 123 uint32_t mask_clk_reg; 124 uint32_t mask_data_reg; 125 uint32_t a_clk_reg; 126 uint32_t a_data_reg; 127 uint32_t en_clk_reg; 128 uint32_t en_data_reg; 129 uint32_t y_clk_reg; 130 uint32_t y_data_reg; 131 uint32_t mask_clk_mask; 132 uint32_t mask_data_mask; 133 uint32_t a_clk_mask; 134 uint32_t a_data_mask; 135 uint32_t en_clk_mask; 136 uint32_t en_data_mask; 137 uint32_t y_clk_mask; 138 uint32_t y_data_mask; 139 }; 140 141 struct radeon_tmds_pll { 142 uint32_t freq; 143 uint32_t value; 144 }; 145 146 #define RADEON_MAX_BIOS_CONNECTOR 16 147 148 /* pll flags */ 149 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 150 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 151 #define RADEON_PLL_USE_REF_DIV (1 << 2) 152 #define RADEON_PLL_LEGACY (1 << 3) 153 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 154 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 155 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 156 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 157 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 158 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 159 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 160 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 161 #define RADEON_PLL_USE_POST_DIV (1 << 12) 162 #define RADEON_PLL_IS_LCD (1 << 13) 163 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 164 165 struct radeon_pll { 166 /* reference frequency */ 167 uint32_t reference_freq; 168 169 /* fixed dividers */ 170 uint32_t reference_div; 171 uint32_t post_div; 172 173 /* pll in/out limits */ 174 uint32_t pll_in_min; 175 uint32_t pll_in_max; 176 uint32_t pll_out_min; 177 uint32_t pll_out_max; 178 uint32_t lcd_pll_out_min; 179 uint32_t lcd_pll_out_max; 180 uint32_t best_vco; 181 182 /* divider limits */ 183 uint32_t min_ref_div; 184 uint32_t max_ref_div; 185 uint32_t min_post_div; 186 uint32_t max_post_div; 187 uint32_t min_feedback_div; 188 uint32_t max_feedback_div; 189 uint32_t min_frac_feedback_div; 190 uint32_t max_frac_feedback_div; 191 192 /* flags for the current clock */ 193 uint32_t flags; 194 195 /* pll id */ 196 uint32_t id; 197 }; 198 199 struct radeon_i2c_chan { 200 struct i2c_adapter adapter; 201 struct drm_device *dev; 202 struct i2c_algo_bit_data bit; 203 struct radeon_i2c_bus_rec rec; 204 struct drm_dp_aux aux; 205 bool has_aux; 206 struct lock mutex; 207 char name[48]; 208 device_t iic_bus; 209 device_t adapter_dev; 210 }; 211 212 /* mostly for macs, but really any system without connector tables */ 213 enum radeon_connector_table { 214 CT_NONE = 0, 215 CT_GENERIC, 216 CT_IBOOK, 217 CT_POWERBOOK_EXTERNAL, 218 CT_POWERBOOK_INTERNAL, 219 CT_POWERBOOK_VGA, 220 CT_MINI_EXTERNAL, 221 CT_MINI_INTERNAL, 222 CT_IMAC_G5_ISIGHT, 223 CT_EMAC, 224 CT_RN50_POWER, 225 CT_MAC_X800, 226 CT_MAC_G5_9600, 227 CT_SAM440EP, 228 CT_MAC_G4_SILVER 229 }; 230 231 enum radeon_dvo_chip { 232 DVO_SIL164, 233 DVO_SIL1178, 234 }; 235 236 struct radeon_fbdev; 237 238 struct radeon_afmt { 239 bool enabled; 240 int offset; 241 bool last_buffer_filled_status; 242 int id; 243 }; 244 245 struct radeon_mode_info { 246 struct atom_context *atom_context; 247 struct card_info *atom_card_info; 248 enum radeon_connector_table connector_table; 249 bool mode_config_initialized; 250 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; 251 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; 252 /* DVI-I properties */ 253 struct drm_property *coherent_mode_property; 254 /* DAC enable load detect */ 255 struct drm_property *load_detect_property; 256 /* TV standard */ 257 struct drm_property *tv_std_property; 258 /* legacy TMDS PLL detect */ 259 struct drm_property *tmds_pll_property; 260 /* underscan */ 261 struct drm_property *underscan_property; 262 struct drm_property *underscan_hborder_property; 263 struct drm_property *underscan_vborder_property; 264 /* audio */ 265 struct drm_property *audio_property; 266 /* FMT dithering */ 267 struct drm_property *dither_property; 268 /* Output CSC */ 269 struct drm_property *output_csc_property; 270 /* hardcoded DFP edid from BIOS */ 271 struct edid *bios_hardcoded_edid; 272 int bios_hardcoded_edid_size; 273 274 /* pointer to fbdev info structure */ 275 struct radeon_fbdev *rfbdev; 276 /* firmware flags */ 277 u16 firmware_flags; 278 /* pointer to backlight encoder */ 279 struct radeon_encoder *bl_encoder; 280 281 /* bitmask for active encoder frontends */ 282 uint32_t active_encoders; 283 }; 284 285 #define RADEON_MAX_BL_LEVEL 0xFF 286 287 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 288 289 struct radeon_backlight_privdata { 290 struct radeon_encoder *encoder; 291 uint8_t negative; 292 }; 293 294 #endif 295 296 #define MAX_H_CODE_TIMING_LEN 32 297 #define MAX_V_CODE_TIMING_LEN 32 298 299 /* need to store these as reading 300 back code tables is excessive */ 301 struct radeon_tv_regs { 302 uint32_t tv_uv_adr; 303 uint32_t timing_cntl; 304 uint32_t hrestart; 305 uint32_t vrestart; 306 uint32_t frestart; 307 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 308 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 309 }; 310 311 struct radeon_atom_ss { 312 uint16_t percentage; 313 uint16_t percentage_divider; 314 uint8_t type; 315 uint16_t step; 316 uint8_t delay; 317 uint8_t range; 318 uint8_t refdiv; 319 /* asic_ss */ 320 uint16_t rate; 321 uint16_t amount; 322 }; 323 324 enum radeon_flip_status { 325 RADEON_FLIP_NONE, 326 RADEON_FLIP_PENDING, 327 RADEON_FLIP_SUBMITTED 328 }; 329 330 struct radeon_crtc { 331 struct drm_crtc base; 332 int crtc_id; 333 u16 lut_r[256], lut_g[256], lut_b[256]; 334 bool enabled; 335 bool can_tile; 336 uint32_t crtc_offset; 337 struct drm_gem_object *cursor_bo; 338 uint64_t cursor_addr; 339 int cursor_x; 340 int cursor_y; 341 int cursor_hot_x; 342 int cursor_hot_y; 343 int cursor_width; 344 int cursor_height; 345 int max_cursor_width; 346 int max_cursor_height; 347 uint32_t legacy_display_base_addr; 348 enum radeon_rmx_type rmx_type; 349 u8 h_border; 350 u8 v_border; 351 fixed20_12 vsc; 352 fixed20_12 hsc; 353 struct drm_display_mode native_mode; 354 int pll_id; 355 /* page flipping */ 356 struct workqueue_struct *flip_queue; 357 struct radeon_flip_work *flip_work; 358 enum radeon_flip_status flip_status; 359 /* pll sharing */ 360 struct radeon_atom_ss ss; 361 bool ss_enabled; 362 u32 adjusted_clock; 363 int bpc; 364 u32 pll_reference_div; 365 u32 pll_post_div; 366 u32 pll_flags; 367 struct drm_encoder *encoder; 368 struct drm_connector *connector; 369 /* for dpm */ 370 u32 line_time; 371 u32 wm_low; 372 u32 wm_high; 373 u32 lb_vblank_lead_lines; 374 struct drm_display_mode hw_mode; 375 enum radeon_output_csc output_csc; 376 }; 377 378 struct radeon_encoder_primary_dac { 379 /* legacy primary dac */ 380 uint32_t ps2_pdac_adj; 381 }; 382 383 struct radeon_encoder_lvds { 384 /* legacy lvds */ 385 uint16_t panel_vcc_delay; 386 uint8_t panel_pwr_delay; 387 uint8_t panel_digon_delay; 388 uint8_t panel_blon_delay; 389 uint16_t panel_ref_divider; 390 uint8_t panel_post_divider; 391 uint16_t panel_fb_divider; 392 bool use_bios_dividers; 393 uint32_t lvds_gen_cntl; 394 /* panel mode */ 395 struct drm_display_mode native_mode; 396 struct backlight_device *bl_dev; 397 int dpms_mode; 398 uint8_t backlight_level; 399 }; 400 401 struct radeon_encoder_tv_dac { 402 /* legacy tv dac */ 403 uint32_t ps2_tvdac_adj; 404 uint32_t ntsc_tvdac_adj; 405 uint32_t pal_tvdac_adj; 406 407 int h_pos; 408 int v_pos; 409 int h_size; 410 int supported_tv_stds; 411 bool tv_on; 412 enum radeon_tv_std tv_std; 413 struct radeon_tv_regs tv; 414 }; 415 416 struct radeon_encoder_int_tmds { 417 /* legacy int tmds */ 418 struct radeon_tmds_pll tmds_pll[4]; 419 }; 420 421 struct radeon_encoder_ext_tmds { 422 /* tmds over dvo */ 423 struct radeon_i2c_chan *i2c_bus; 424 uint8_t slave_addr; 425 enum radeon_dvo_chip dvo_chip; 426 }; 427 428 /* spread spectrum */ 429 struct radeon_encoder_atom_dig { 430 bool linkb; 431 /* atom dig */ 432 bool coherent_mode; 433 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 434 /* atom lvds/edp */ 435 uint32_t lcd_misc; 436 uint16_t panel_pwr_delay; 437 uint32_t lcd_ss_id; 438 /* panel mode */ 439 struct drm_display_mode native_mode; 440 struct backlight_device *bl_dev; 441 int dpms_mode; 442 uint8_t backlight_level; 443 int panel_mode; 444 struct radeon_afmt *afmt; 445 struct r600_audio_pin *pin; 446 }; 447 448 struct radeon_encoder_atom_dac { 449 enum radeon_tv_std tv_std; 450 }; 451 452 struct radeon_encoder { 453 struct drm_encoder base; 454 uint32_t encoder_enum; 455 uint32_t encoder_id; 456 uint32_t devices; 457 uint32_t active_device; 458 uint32_t flags; 459 uint32_t pixel_clock; 460 enum radeon_rmx_type rmx_type; 461 enum radeon_underscan_type underscan_type; 462 uint32_t underscan_hborder; 463 uint32_t underscan_vborder; 464 struct drm_display_mode native_mode; 465 void *enc_priv; 466 int audio_polling_active; 467 bool is_ext_encoder; 468 u16 caps; 469 struct radeon_audio_funcs *audio; 470 enum radeon_output_csc output_csc; 471 }; 472 473 struct radeon_connector_atom_dig { 474 uint32_t igp_lane_info; 475 /* displayport */ 476 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 477 u8 dp_sink_type; 478 int dp_clock; 479 int dp_lane_count; 480 bool edp_on; 481 }; 482 483 struct radeon_gpio_rec { 484 bool valid; 485 u8 id; 486 u32 reg; 487 u32 mask; 488 u32 shift; 489 }; 490 491 struct radeon_hpd { 492 enum radeon_hpd_id hpd; 493 u8 plugged_state; 494 struct radeon_gpio_rec gpio; 495 }; 496 497 struct radeon_router { 498 u32 router_id; 499 struct radeon_i2c_bus_rec i2c_info; 500 u8 i2c_addr; 501 /* i2c mux */ 502 bool ddc_valid; 503 u8 ddc_mux_type; 504 u8 ddc_mux_control_pin; 505 u8 ddc_mux_state; 506 /* clock/data mux */ 507 bool cd_valid; 508 u8 cd_mux_type; 509 u8 cd_mux_control_pin; 510 u8 cd_mux_state; 511 }; 512 513 enum radeon_connector_audio { 514 RADEON_AUDIO_DISABLE = 0, 515 RADEON_AUDIO_ENABLE = 1, 516 RADEON_AUDIO_AUTO = 2 517 }; 518 519 enum radeon_connector_dither { 520 RADEON_FMT_DITHER_DISABLE = 0, 521 RADEON_FMT_DITHER_ENABLE = 1, 522 }; 523 524 struct radeon_connector { 525 struct drm_connector base; 526 uint32_t connector_id; 527 uint32_t devices; 528 struct radeon_i2c_chan *ddc_bus; 529 /* some systems have an hdmi and vga port with a shared ddc line */ 530 bool shared_ddc; 531 bool use_digital; 532 /* we need to mind the EDID between detect 533 and get modes due to analog/digital/tvencoder */ 534 struct edid *edid; 535 void *con_priv; 536 bool dac_load_detect; 537 bool detected_by_load; /* if the connection status was determined by load */ 538 uint16_t connector_object_id; 539 struct radeon_hpd hpd; 540 struct radeon_router router; 541 struct radeon_i2c_chan *router_bus; 542 enum radeon_connector_audio audio; 543 enum radeon_connector_dither dither; 544 int pixelclock_for_modeset; 545 }; 546 547 struct radeon_framebuffer { 548 struct drm_framebuffer base; 549 struct drm_gem_object *obj; 550 }; 551 552 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 553 ((em) == ATOM_ENCODER_MODE_DP_MST)) 554 555 struct atom_clock_dividers { 556 u32 post_div; 557 union { 558 struct { 559 #ifdef __BIG_ENDIAN 560 u32 reserved : 6; 561 u32 whole_fb_div : 12; 562 u32 frac_fb_div : 14; 563 #else 564 u32 frac_fb_div : 14; 565 u32 whole_fb_div : 12; 566 u32 reserved : 6; 567 #endif 568 }; 569 u32 fb_div; 570 }; 571 u32 ref_div; 572 bool enable_post_div; 573 bool enable_dithen; 574 u32 vco_mode; 575 u32 real_clock; 576 /* added for CI */ 577 u32 post_divider; 578 u32 flags; 579 }; 580 581 struct atom_mpll_param { 582 union { 583 struct { 584 #ifdef __BIG_ENDIAN 585 u32 reserved : 8; 586 u32 clkfrac : 12; 587 u32 clkf : 12; 588 #else 589 u32 clkf : 12; 590 u32 clkfrac : 12; 591 u32 reserved : 8; 592 #endif 593 }; 594 u32 fb_div; 595 }; 596 u32 post_div; 597 u32 bwcntl; 598 u32 dll_speed; 599 u32 vco_mode; 600 u32 yclk_sel; 601 u32 qdr; 602 u32 half_rate; 603 }; 604 605 #define MEM_TYPE_GDDR5 0x50 606 #define MEM_TYPE_GDDR4 0x40 607 #define MEM_TYPE_GDDR3 0x30 608 #define MEM_TYPE_DDR2 0x20 609 #define MEM_TYPE_GDDR1 0x10 610 #define MEM_TYPE_DDR3 0xb0 611 #define MEM_TYPE_MASK 0xf0 612 613 struct atom_memory_info { 614 u8 mem_vendor; 615 u8 mem_type; 616 }; 617 618 #define MAX_AC_TIMING_ENTRIES 16 619 620 struct atom_memory_clock_range_table 621 { 622 u8 num_entries; 623 u8 rsv[3]; 624 u32 mclk[MAX_AC_TIMING_ENTRIES]; 625 }; 626 627 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 628 #define VBIOS_MAX_AC_TIMING_ENTRIES 20 629 630 struct atom_mc_reg_entry { 631 u32 mclk_max; 632 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 633 }; 634 635 struct atom_mc_register_address { 636 u16 s1; 637 u8 pre_reg_data; 638 }; 639 640 struct atom_mc_reg_table { 641 u8 last; 642 u8 num_entries; 643 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 644 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 645 }; 646 647 #define MAX_VOLTAGE_ENTRIES 32 648 649 struct atom_voltage_table_entry 650 { 651 u16 value; 652 u32 smio_low; 653 }; 654 655 struct atom_voltage_table 656 { 657 u32 count; 658 u32 mask_low; 659 u32 phase_delay; 660 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 661 }; 662 663 /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */ 664 #define USE_REAL_VBLANKSTART (1 << 30) 665 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 666 667 extern void 668 radeon_add_atom_connector(struct drm_device *dev, 669 uint32_t connector_id, 670 uint32_t supported_device, 671 int connector_type, 672 struct radeon_i2c_bus_rec *i2c_bus, 673 uint32_t igp_lane_info, 674 uint16_t connector_object_id, 675 struct radeon_hpd *hpd, 676 struct radeon_router *router); 677 extern void 678 radeon_add_legacy_connector(struct drm_device *dev, 679 uint32_t connector_id, 680 uint32_t supported_device, 681 int connector_type, 682 struct radeon_i2c_bus_rec *i2c_bus, 683 uint16_t connector_object_id, 684 struct radeon_hpd *hpd); 685 extern uint32_t 686 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 687 uint8_t dac); 688 extern void radeon_link_encoder_connector(struct drm_device *dev); 689 690 extern enum radeon_tv_std 691 radeon_combios_get_tv_info(struct radeon_device *rdev); 692 extern enum radeon_tv_std 693 radeon_atombios_get_tv_info(struct radeon_device *rdev); 694 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 695 u16 *vddc, u16 *vddci, u16 *mvdd); 696 697 extern void 698 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 699 struct drm_encoder *encoder, 700 bool connected); 701 extern void 702 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 703 struct drm_encoder *encoder, 704 bool connected); 705 706 extern struct drm_connector * 707 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 708 extern struct drm_connector * 709 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 710 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 711 u32 pixel_clock); 712 713 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 714 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 715 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 716 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 717 718 extern struct edid *radeon_connector_edid(struct drm_connector *connector); 719 720 extern void radeon_connector_hotplug(struct drm_connector *connector); 721 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 722 struct drm_display_mode *mode); 723 extern void radeon_dp_set_link_config(struct drm_connector *connector, 724 const struct drm_display_mode *mode); 725 extern void radeon_dp_link_train(struct drm_encoder *encoder, 726 struct drm_connector *connector); 727 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 728 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 729 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 730 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 731 struct drm_connector *connector); 732 extern int radeon_dp_get_dp_link_config(struct drm_connector *connector, 733 const u8 *dpcd, 734 unsigned pix_clock, 735 unsigned *dp_lanes, unsigned *dp_rate); 736 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, 737 u8 power_state); 738 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); 739 extern ssize_t 740 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); 741 742 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 743 extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override); 744 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 745 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 746 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 747 int action, uint8_t lane_num, 748 uint8_t lane_set); 749 extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, 750 int action, uint8_t lane_num, 751 uint8_t lane_set, int fe); 752 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 753 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 754 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 755 756 extern void radeon_i2c_init(struct radeon_device *rdev); 757 extern void radeon_i2c_fini(struct radeon_device *rdev); 758 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 759 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 760 extern void radeon_i2c_add(struct radeon_device *rdev, 761 struct radeon_i2c_bus_rec *rec, 762 const char *name); 763 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 764 struct radeon_i2c_bus_rec *i2c_bus); 765 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 766 struct radeon_i2c_bus_rec *rec, 767 const char *name); 768 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 769 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 770 u8 slave_addr, 771 u8 addr, 772 u8 *val); 773 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 774 u8 slave_addr, 775 u8 addr, 776 u8 val); 777 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 778 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 779 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 780 781 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 782 struct radeon_atom_ss *ss, 783 int id); 784 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 785 struct radeon_atom_ss *ss, 786 int id, u32 clock); 787 extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 788 u8 id); 789 790 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 791 uint64_t freq, 792 uint32_t *dot_clock_p, 793 uint32_t *fb_div_p, 794 uint32_t *frac_fb_div_p, 795 uint32_t *ref_div_p, 796 uint32_t *post_div_p); 797 798 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 799 u32 freq, 800 u32 *dot_clock_p, 801 u32 *fb_div_p, 802 u32 *frac_fb_div_p, 803 u32 *ref_div_p, 804 u32 *post_div_p); 805 806 extern void radeon_setup_encoder_clones(struct drm_device *dev); 807 808 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 809 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 810 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 811 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 812 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 813 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 814 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 815 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 816 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 817 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 818 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); 819 820 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 821 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 822 struct drm_framebuffer *old_fb); 823 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 824 struct drm_framebuffer *fb, 825 int x, int y, 826 enum mode_set_atomic state); 827 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 828 struct drm_display_mode *mode, 829 struct drm_display_mode *adjusted_mode, 830 int x, int y, 831 struct drm_framebuffer *old_fb); 832 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 833 834 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 835 struct drm_framebuffer *old_fb); 836 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 837 struct drm_framebuffer *fb, 838 int x, int y, 839 enum mode_set_atomic state); 840 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 841 struct drm_framebuffer *fb, 842 int x, int y, int atomic); 843 extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 844 struct drm_file *file_priv, 845 uint32_t handle, 846 uint32_t width, 847 uint32_t height, 848 int32_t hot_x, 849 int32_t hot_y); 850 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 851 int x, int y); 852 extern void radeon_cursor_reset(struct drm_crtc *crtc); 853 854 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 855 unsigned int flags, int *vpos, int *hpos, 856 ktime_t *stime, ktime_t *etime, 857 const struct drm_display_mode *mode); 858 859 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 860 extern struct edid * 861 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 862 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 863 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 864 extern struct radeon_encoder_atom_dig * 865 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 866 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 867 struct radeon_encoder_int_tmds *tmds); 868 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 869 struct radeon_encoder_int_tmds *tmds); 870 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 871 struct radeon_encoder_int_tmds *tmds); 872 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 873 struct radeon_encoder_ext_tmds *tmds); 874 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 875 struct radeon_encoder_ext_tmds *tmds); 876 extern struct radeon_encoder_primary_dac * 877 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 878 extern struct radeon_encoder_tv_dac * 879 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 880 extern struct radeon_encoder_lvds * 881 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 882 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 883 extern struct radeon_encoder_tv_dac * 884 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 885 extern struct radeon_encoder_primary_dac * 886 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 887 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 888 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 889 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 890 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 891 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 892 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 893 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 894 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 895 extern void 896 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 897 extern void 898 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 899 extern void 900 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 901 extern void 902 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 903 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 904 u16 blue, int regno); 905 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 906 u16 *blue, int regno); 907 int radeon_framebuffer_init(struct drm_device *dev, 908 struct radeon_framebuffer *rfb, 909 const struct drm_mode_fb_cmd2 *mode_cmd, 910 struct drm_gem_object *obj); 911 912 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 913 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 914 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 915 void radeon_atombios_init_crtc(struct drm_device *dev, 916 struct radeon_crtc *radeon_crtc); 917 void radeon_legacy_init_crtc(struct drm_device *dev, 918 struct radeon_crtc *radeon_crtc); 919 920 void radeon_get_clock_info(struct drm_device *dev); 921 922 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 923 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 924 925 void radeon_enc_destroy(struct drm_encoder *encoder); 926 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 927 void radeon_combios_asic_init(struct drm_device *dev); 928 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 929 const struct drm_display_mode *mode, 930 struct drm_display_mode *adjusted_mode); 931 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 932 struct drm_display_mode *adjusted_mode); 933 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 934 935 /* legacy tv */ 936 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 937 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 938 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 939 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 940 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 941 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 942 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 943 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 944 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 945 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 946 struct drm_display_mode *mode, 947 struct drm_display_mode *adjusted_mode); 948 949 /* fmt blocks */ 950 void avivo_program_fmt(struct drm_encoder *encoder); 951 void dce3_program_fmt(struct drm_encoder *encoder); 952 void dce4_program_fmt(struct drm_encoder *encoder); 953 void dce8_program_fmt(struct drm_encoder *encoder); 954 955 /* fbdev layer */ 956 int radeon_fbdev_init(struct radeon_device *rdev); 957 void radeon_fbdev_fini(struct radeon_device *rdev); 958 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 959 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 960 void radeon_fbdev_restore_mode(struct radeon_device *rdev); 961 962 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 963 964 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); 965 966 void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector); 967 void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector); 968 969 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 970 971 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 972 973 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); 974 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); 975 #endif 976