1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_ASIC_H__ 29 #define __RADEON_ASIC_H__ 30 31 /* 32 * common functions 33 */ 34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 46 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 47 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 48 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 49 50 /* 51 * r100,rv100,rs100,rv200,rs200 52 */ 53 struct r100_mc_save { 54 u32 GENMO_WT; 55 u32 CRTC_EXT_CNTL; 56 u32 CRTC_GEN_CNTL; 57 u32 CRTC2_GEN_CNTL; 58 u32 CUR_OFFSET; 59 u32 CUR2_OFFSET; 60 }; 61 int r100_init(struct radeon_device *rdev); 62 void r100_fini(struct radeon_device *rdev); 63 int r100_suspend(struct radeon_device *rdev); 64 int r100_resume(struct radeon_device *rdev); 65 void r100_vga_set_state(struct radeon_device *rdev, bool state); 66 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 67 int r100_asic_reset(struct radeon_device *rdev); 68 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 69 void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 70 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 71 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 72 int r100_irq_set(struct radeon_device *rdev); 73 irqreturn_t r100_irq_process(struct radeon_device *rdev); 74 void r100_fence_ring_emit(struct radeon_device *rdev, 75 struct radeon_fence *fence); 76 void r100_semaphore_ring_emit(struct radeon_device *rdev, 77 struct radeon_ring *cp, 78 struct radeon_semaphore *semaphore, 79 bool emit_wait); 80 int r100_cs_parse(struct radeon_cs_parser *p); 81 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 82 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 83 int r100_copy_blit(struct radeon_device *rdev, 84 uint64_t src_offset, 85 uint64_t dst_offset, 86 unsigned num_gpu_pages, 87 struct radeon_fence **fence); 88 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 89 uint32_t tiling_flags, uint32_t pitch, 90 uint32_t offset, uint32_t obj_size); 91 void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 92 void r100_bandwidth_update(struct radeon_device *rdev); 93 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 94 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 95 void r100_hpd_init(struct radeon_device *rdev); 96 void r100_hpd_fini(struct radeon_device *rdev); 97 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 98 void r100_hpd_set_polarity(struct radeon_device *rdev, 99 enum radeon_hpd_id hpd); 100 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 101 int r100_debugfs_cp_init(struct radeon_device *rdev); 102 void r100_cp_disable(struct radeon_device *rdev); 103 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 104 void r100_cp_fini(struct radeon_device *rdev); 105 int r100_pci_gart_init(struct radeon_device *rdev); 106 void r100_pci_gart_fini(struct radeon_device *rdev); 107 int r100_pci_gart_enable(struct radeon_device *rdev); 108 void r100_pci_gart_disable(struct radeon_device *rdev); 109 int r100_debugfs_mc_info_init(struct radeon_device *rdev); 110 int r100_gui_wait_for_idle(struct radeon_device *rdev); 111 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 112 void r100_irq_disable(struct radeon_device *rdev); 113 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 114 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 115 void r100_vram_init_sizes(struct radeon_device *rdev); 116 int r100_cp_reset(struct radeon_device *rdev); 117 void r100_vga_render_disable(struct radeon_device *rdev); 118 void r100_restore_sanity(struct radeon_device *rdev); 119 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 120 struct radeon_cs_packet *pkt, 121 struct radeon_bo *robj); 122 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 123 struct radeon_cs_packet *pkt, 124 const unsigned *auth, unsigned n, 125 radeon_packet0_check_t check); 126 int r100_cs_packet_parse(struct radeon_cs_parser *p, 127 struct radeon_cs_packet *pkt, 128 unsigned idx); 129 void r100_enable_bm(struct radeon_device *rdev); 130 void r100_set_common_regs(struct radeon_device *rdev); 131 void r100_bm_disable(struct radeon_device *rdev); 132 extern bool r100_gui_idle(struct radeon_device *rdev); 133 extern void r100_pm_misc(struct radeon_device *rdev); 134 extern void r100_pm_prepare(struct radeon_device *rdev); 135 extern void r100_pm_finish(struct radeon_device *rdev); 136 extern void r100_pm_init_profile(struct radeon_device *rdev); 137 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 138 extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); 139 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 140 extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); 141 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 142 extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 143 144 /* 145 * r200,rv250,rs300,rv280 146 */ 147 extern int r200_copy_dma(struct radeon_device *rdev, 148 uint64_t src_offset, 149 uint64_t dst_offset, 150 unsigned num_gpu_pages, 151 struct radeon_fence **fence); 152 void r200_set_safe_registers(struct radeon_device *rdev); 153 154 /* 155 * r300,r350,rv350,rv380 156 */ 157 extern int r300_init(struct radeon_device *rdev); 158 extern void r300_fini(struct radeon_device *rdev); 159 extern int r300_suspend(struct radeon_device *rdev); 160 extern int r300_resume(struct radeon_device *rdev); 161 extern int r300_asic_reset(struct radeon_device *rdev); 162 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 163 extern void r300_fence_ring_emit(struct radeon_device *rdev, 164 struct radeon_fence *fence); 165 extern int r300_cs_parse(struct radeon_cs_parser *p); 166 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 167 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 168 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 169 extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 170 extern void r300_set_reg_safe(struct radeon_device *rdev); 171 extern void r300_mc_program(struct radeon_device *rdev); 172 extern void r300_mc_init(struct radeon_device *rdev); 173 extern void r300_clock_startup(struct radeon_device *rdev); 174 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 175 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 176 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 177 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 178 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 179 180 /* 181 * r420,r423,rv410 182 */ 183 extern int r420_init(struct radeon_device *rdev); 184 extern void r420_fini(struct radeon_device *rdev); 185 extern int r420_suspend(struct radeon_device *rdev); 186 extern int r420_resume(struct radeon_device *rdev); 187 extern void r420_pm_init_profile(struct radeon_device *rdev); 188 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 189 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 190 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 191 extern void r420_pipes_init(struct radeon_device *rdev); 192 193 /* 194 * rs400,rs480 195 */ 196 extern int rs400_init(struct radeon_device *rdev); 197 extern void rs400_fini(struct radeon_device *rdev); 198 extern int rs400_suspend(struct radeon_device *rdev); 199 extern int rs400_resume(struct radeon_device *rdev); 200 void rs400_gart_tlb_flush(struct radeon_device *rdev); 201 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 202 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 203 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 204 int rs400_gart_init(struct radeon_device *rdev); 205 int rs400_gart_enable(struct radeon_device *rdev); 206 void rs400_gart_adjust_size(struct radeon_device *rdev); 207 void rs400_gart_disable(struct radeon_device *rdev); 208 void rs400_gart_fini(struct radeon_device *rdev); 209 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 210 211 /* 212 * rs600. 213 */ 214 extern int rs600_asic_reset(struct radeon_device *rdev); 215 extern int rs600_init(struct radeon_device *rdev); 216 extern void rs600_fini(struct radeon_device *rdev); 217 extern int rs600_suspend(struct radeon_device *rdev); 218 extern int rs600_resume(struct radeon_device *rdev); 219 int rs600_irq_set(struct radeon_device *rdev); 220 irqreturn_t rs600_irq_process(struct radeon_device *rdev); 221 void rs600_irq_disable(struct radeon_device *rdev); 222 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 223 void rs600_gart_tlb_flush(struct radeon_device *rdev); 224 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 225 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 226 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 227 void rs600_bandwidth_update(struct radeon_device *rdev); 228 void rs600_hpd_init(struct radeon_device *rdev); 229 void rs600_hpd_fini(struct radeon_device *rdev); 230 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 231 void rs600_hpd_set_polarity(struct radeon_device *rdev, 232 enum radeon_hpd_id hpd); 233 extern void rs600_pm_misc(struct radeon_device *rdev); 234 extern void rs600_pm_prepare(struct radeon_device *rdev); 235 extern void rs600_pm_finish(struct radeon_device *rdev); 236 extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); 237 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 238 extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); 239 void rs600_set_safe_registers(struct radeon_device *rdev); 240 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 241 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 242 243 /* 244 * rs690,rs740 245 */ 246 int rs690_init(struct radeon_device *rdev); 247 void rs690_fini(struct radeon_device *rdev); 248 int rs690_resume(struct radeon_device *rdev); 249 int rs690_suspend(struct radeon_device *rdev); 250 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 251 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 252 void rs690_bandwidth_update(struct radeon_device *rdev); 253 void rs690_line_buffer_adjust(struct radeon_device *rdev, 254 struct drm_display_mode *mode1, 255 struct drm_display_mode *mode2); 256 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 257 258 /* 259 * rv515 260 */ 261 struct rv515_mc_save { 262 u32 vga_render_control; 263 u32 vga_hdp_control; 264 bool crtc_enabled[2]; 265 }; 266 267 int rv515_init(struct radeon_device *rdev); 268 void rv515_fini(struct radeon_device *rdev); 269 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 270 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 271 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 272 void rv515_bandwidth_update(struct radeon_device *rdev); 273 int rv515_resume(struct radeon_device *rdev); 274 int rv515_suspend(struct radeon_device *rdev); 275 void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 276 void rv515_vga_render_disable(struct radeon_device *rdev); 277 void rv515_set_safe_registers(struct radeon_device *rdev); 278 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 279 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 280 void rv515_clock_startup(struct radeon_device *rdev); 281 void rv515_debugfs(struct radeon_device *rdev); 282 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 283 284 /* 285 * r520,rv530,rv560,rv570,r580 286 */ 287 int r520_init(struct radeon_device *rdev); 288 int r520_resume(struct radeon_device *rdev); 289 int r520_mc_wait_for_idle(struct radeon_device *rdev); 290 291 /* 292 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 293 */ 294 int r600_init(struct radeon_device *rdev); 295 void r600_fini(struct radeon_device *rdev); 296 int r600_suspend(struct radeon_device *rdev); 297 int r600_resume(struct radeon_device *rdev); 298 void r600_vga_set_state(struct radeon_device *rdev, bool state); 299 int r600_wb_init(struct radeon_device *rdev); 300 void r600_wb_fini(struct radeon_device *rdev); 301 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 302 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 303 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 304 int r600_cs_parse(struct radeon_cs_parser *p); 305 int r600_dma_cs_parse(struct radeon_cs_parser *p); 306 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, 307 struct radeon_cs_reloc **cs_reloc); 308 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev); 309 void r600_fence_ring_emit(struct radeon_device *rdev, 310 struct radeon_fence *fence); 311 void r600_semaphore_ring_emit(struct radeon_device *rdev, 312 struct radeon_ring *cp, 313 struct radeon_semaphore *semaphore, 314 bool emit_wait); 315 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 316 struct radeon_fence *fence); 317 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 318 struct radeon_ring *ring, 319 struct radeon_semaphore *semaphore, 320 bool emit_wait); 321 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 322 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 323 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 324 int r600_asic_reset(struct radeon_device *rdev); 325 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 326 uint32_t tiling_flags, uint32_t pitch, 327 uint32_t offset, uint32_t obj_size); 328 void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 329 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 330 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 331 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 332 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 333 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 334 int r600_copy_cpdma(struct radeon_device *rdev, 335 uint64_t src_offset, uint64_t dst_offset, 336 unsigned num_gpu_pages, struct radeon_fence **fence); 337 int r600_copy_dma(struct radeon_device *rdev, 338 uint64_t src_offset, uint64_t dst_offset, 339 unsigned num_gpu_pages, struct radeon_fence **fence); 340 void r600_hpd_init(struct radeon_device *rdev); 341 void r600_hpd_fini(struct radeon_device *rdev); 342 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 343 void r600_hpd_set_polarity(struct radeon_device *rdev, 344 enum radeon_hpd_id hpd); 345 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 346 extern bool r600_gui_idle(struct radeon_device *rdev); 347 extern void r600_pm_misc(struct radeon_device *rdev); 348 extern void r600_pm_init_profile(struct radeon_device *rdev); 349 extern void rs780_pm_init_profile(struct radeon_device *rdev); 350 extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); 351 extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 352 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 353 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 354 extern int r600_get_pcie_lanes(struct radeon_device *rdev); 355 bool r600_card_posted(struct radeon_device *rdev); 356 void r600_cp_stop(struct radeon_device *rdev); 357 int r600_cp_start(struct radeon_device *rdev); 358 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 359 int r600_cp_resume(struct radeon_device *rdev); 360 void r600_cp_fini(struct radeon_device *rdev); 361 int r600_count_pipe_bits(uint32_t val); 362 int r600_mc_wait_for_idle(struct radeon_device *rdev); 363 int r600_pcie_gart_init(struct radeon_device *rdev); 364 void r600_scratch_init(struct radeon_device *rdev); 365 int r600_init_microcode(struct radeon_device *rdev); 366 void r600_fini_microcode(struct radeon_device *rdev); 367 /* r600 irq */ 368 irqreturn_t r600_irq_process(struct radeon_device *rdev); 369 int r600_irq_init(struct radeon_device *rdev); 370 void r600_irq_fini(struct radeon_device *rdev); 371 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 372 int r600_irq_set(struct radeon_device *rdev); 373 void r600_irq_suspend(struct radeon_device *rdev); 374 void r600_disable_interrupts(struct radeon_device *rdev); 375 void r600_rlc_stop(struct radeon_device *rdev); 376 /* r600 audio */ 377 int r600_audio_init(struct radeon_device *rdev); 378 struct r600_audio_pin r600_audio_status(struct radeon_device *rdev); 379 void r600_audio_fini(struct radeon_device *rdev); 380 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock); 381 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 382 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 383 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); 384 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 385 u32 r600_get_xclk(struct radeon_device *rdev); 386 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); 387 int rv6xx_get_temp(struct radeon_device *rdev); 388 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 389 int r600_dpm_pre_set_power_state(struct radeon_device *rdev); 390 void r600_dpm_post_set_power_state(struct radeon_device *rdev); 391 /* r600 dma */ 392 uint32_t r600_dma_get_rptr(struct radeon_device *rdev, 393 struct radeon_ring *ring); 394 uint32_t r600_dma_get_wptr(struct radeon_device *rdev, 395 struct radeon_ring *ring); 396 void r600_dma_set_wptr(struct radeon_device *rdev, 397 struct radeon_ring *ring); 398 /* rv6xx dpm */ 399 int rv6xx_dpm_init(struct radeon_device *rdev); 400 int rv6xx_dpm_enable(struct radeon_device *rdev); 401 void rv6xx_dpm_disable(struct radeon_device *rdev); 402 int rv6xx_dpm_set_power_state(struct radeon_device *rdev); 403 void rv6xx_setup_asic(struct radeon_device *rdev); 404 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev); 405 void rv6xx_dpm_fini(struct radeon_device *rdev); 406 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low); 407 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low); 408 void rv6xx_dpm_print_power_state(struct radeon_device *rdev, 409 struct radeon_ps *ps); 410 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 411 struct seq_file *m); 412 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, 413 enum radeon_dpm_forced_level level); 414 /* rs780 dpm */ 415 int rs780_dpm_init(struct radeon_device *rdev); 416 int rs780_dpm_enable(struct radeon_device *rdev); 417 void rs780_dpm_disable(struct radeon_device *rdev); 418 int rs780_dpm_set_power_state(struct radeon_device *rdev); 419 void rs780_dpm_setup_asic(struct radeon_device *rdev); 420 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev); 421 void rs780_dpm_fini(struct radeon_device *rdev); 422 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low); 423 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low); 424 void rs780_dpm_print_power_state(struct radeon_device *rdev, 425 struct radeon_ps *ps); 426 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 427 struct seq_file *m); 428 int rs780_dpm_force_performance_level(struct radeon_device *rdev, 429 enum radeon_dpm_forced_level level); 430 431 /* 432 * rv770,rv730,rv710,rv740 433 */ 434 int rv770_init(struct radeon_device *rdev); 435 void rv770_fini(struct radeon_device *rdev); 436 int rv770_suspend(struct radeon_device *rdev); 437 int rv770_resume(struct radeon_device *rdev); 438 void rv770_pm_misc(struct radeon_device *rdev); 439 u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 440 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 441 void r700_cp_stop(struct radeon_device *rdev); 442 void r700_cp_fini(struct radeon_device *rdev); 443 int rv770_copy_dma(struct radeon_device *rdev, 444 uint64_t src_offset, uint64_t dst_offset, 445 unsigned num_gpu_pages, 446 struct radeon_fence **fence); 447 u32 rv770_get_xclk(struct radeon_device *rdev); 448 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 449 int rv770_get_temp(struct radeon_device *rdev); 450 /* rv7xx pm */ 451 int rv770_dpm_init(struct radeon_device *rdev); 452 int rv770_dpm_enable(struct radeon_device *rdev); 453 void rv770_dpm_disable(struct radeon_device *rdev); 454 int rv770_dpm_set_power_state(struct radeon_device *rdev); 455 void rv770_dpm_setup_asic(struct radeon_device *rdev); 456 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev); 457 void rv770_dpm_fini(struct radeon_device *rdev); 458 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low); 459 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low); 460 void rv770_dpm_print_power_state(struct radeon_device *rdev, 461 struct radeon_ps *ps); 462 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 463 struct seq_file *m); 464 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev); 465 466 /* 467 * evergreen 468 */ 469 struct evergreen_mc_save { 470 u32 vga_render_control; 471 u32 vga_hdp_control; 472 bool crtc_enabled[RADEON_MAX_CRTCS]; 473 }; 474 475 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 476 int evergreen_init(struct radeon_device *rdev); 477 void evergreen_fini(struct radeon_device *rdev); 478 int evergreen_suspend(struct radeon_device *rdev); 479 int evergreen_resume(struct radeon_device *rdev); 480 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 481 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 482 int evergreen_asic_reset(struct radeon_device *rdev); 483 void evergreen_bandwidth_update(struct radeon_device *rdev); 484 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 485 void evergreen_hpd_init(struct radeon_device *rdev); 486 void evergreen_hpd_fini(struct radeon_device *rdev); 487 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 488 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 489 enum radeon_hpd_id hpd); 490 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 491 int evergreen_irq_set(struct radeon_device *rdev); 492 irqreturn_t evergreen_irq_process(struct radeon_device *rdev); 493 extern int evergreen_cs_parse(struct radeon_cs_parser *p); 494 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 495 extern void evergreen_pm_misc(struct radeon_device *rdev); 496 extern void evergreen_pm_prepare(struct radeon_device *rdev); 497 extern void evergreen_pm_finish(struct radeon_device *rdev); 498 extern void sumo_pm_init_profile(struct radeon_device *rdev); 499 extern void btc_pm_init_profile(struct radeon_device *rdev); 500 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 501 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 502 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 503 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 504 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 505 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 506 void evergreen_disable_interrupt_state(struct radeon_device *rdev); 507 int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 508 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 509 struct radeon_fence *fence); 510 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 511 struct radeon_ib *ib); 512 int evergreen_copy_dma(struct radeon_device *rdev, 513 uint64_t src_offset, uint64_t dst_offset, 514 unsigned num_gpu_pages, 515 struct radeon_fence **fence); 516 u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev); 517 void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 518 void evergreen_print_gpu_status_regs(struct radeon_device *rdev); 519 void evergreen_program_aspm(struct radeon_device *rdev); 520 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 521 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); 522 void sumo_rlc_fini(struct radeon_device *rdev); 523 int sumo_rlc_init(struct radeon_device *rdev); 524 int evergreen_rlc_resume(struct radeon_device *rdev); 525 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 526 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 527 void evergreen_mc_program(struct radeon_device *rdev); 528 int evergreen_mc_init(struct radeon_device *rdev); 529 void evergreen_irq_suspend(struct radeon_device *rdev); 530 bool evergreen_is_display_hung(struct radeon_device *rdev); 531 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); 532 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 533 int evergreen_get_temp(struct radeon_device *rdev); 534 int sumo_get_temp(struct radeon_device *rdev); 535 int tn_get_temp(struct radeon_device *rdev); 536 int cypress_dpm_init(struct radeon_device *rdev); 537 void cypress_dpm_setup_asic(struct radeon_device *rdev); 538 int cypress_dpm_enable(struct radeon_device *rdev); 539 void cypress_dpm_disable(struct radeon_device *rdev); 540 int cypress_dpm_set_power_state(struct radeon_device *rdev); 541 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev); 542 void cypress_dpm_fini(struct radeon_device *rdev); 543 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev); 544 int btc_dpm_init(struct radeon_device *rdev); 545 void btc_dpm_setup_asic(struct radeon_device *rdev); 546 int btc_dpm_enable(struct radeon_device *rdev); 547 void btc_dpm_disable(struct radeon_device *rdev); 548 int btc_dpm_pre_set_power_state(struct radeon_device *rdev); 549 int btc_dpm_set_power_state(struct radeon_device *rdev); 550 void btc_dpm_post_set_power_state(struct radeon_device *rdev); 551 void btc_dpm_fini(struct radeon_device *rdev); 552 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low); 553 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low); 554 bool btc_dpm_vblank_too_short(struct radeon_device *rdev); 555 int sumo_dpm_init(struct radeon_device *rdev); 556 int sumo_dpm_enable(struct radeon_device *rdev); 557 void sumo_dpm_disable(struct radeon_device *rdev); 558 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); 559 int sumo_dpm_set_power_state(struct radeon_device *rdev); 560 void sumo_dpm_post_set_power_state(struct radeon_device *rdev); 561 void sumo_dpm_setup_asic(struct radeon_device *rdev); 562 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev); 563 void sumo_dpm_fini(struct radeon_device *rdev); 564 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low); 565 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low); 566 void sumo_dpm_print_power_state(struct radeon_device *rdev, 567 struct radeon_ps *ps); 568 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 569 struct seq_file *m); 570 int sumo_dpm_force_performance_level(struct radeon_device *rdev, 571 enum radeon_dpm_forced_level level); 572 573 /* 574 * cayman 575 */ 576 void cayman_fence_ring_emit(struct radeon_device *rdev, 577 struct radeon_fence *fence); 578 void cayman_uvd_semaphore_emit(struct radeon_device *rdev, 579 struct radeon_ring *ring, 580 struct radeon_semaphore *semaphore, 581 bool emit_wait); 582 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 583 int cayman_init(struct radeon_device *rdev); 584 void cayman_fini(struct radeon_device *rdev); 585 int cayman_suspend(struct radeon_device *rdev); 586 int cayman_resume(struct radeon_device *rdev); 587 int cayman_asic_reset(struct radeon_device *rdev); 588 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 589 int cayman_vm_init(struct radeon_device *rdev); 590 void cayman_vm_fini(struct radeon_device *rdev); 591 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 592 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 593 void cayman_vm_set_page(struct radeon_device *rdev, 594 struct radeon_ib *ib, 595 uint64_t pe, 596 uint64_t addr, unsigned count, 597 uint32_t incr, uint32_t flags); 598 void cayman_vm_decode_fault(struct radeon_device *rdev, 599 u32 status, u32 addr); 600 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev); 601 void cayman_dma_vm_set_page(struct radeon_device *rdev, 602 struct radeon_ib *ib, 603 uint64_t pe, 604 uint64_t addr, unsigned count, 605 uint32_t incr, uint32_t flags); 606 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 607 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 608 void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 609 struct radeon_ib *ib); 610 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 611 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 612 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 613 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 614 int ring, u32 cp_int_cntl); 615 616 int ni_dpm_init(struct radeon_device *rdev); 617 void ni_dpm_setup_asic(struct radeon_device *rdev); 618 int ni_dpm_enable(struct radeon_device *rdev); 619 void ni_dpm_disable(struct radeon_device *rdev); 620 int ni_dpm_pre_set_power_state(struct radeon_device *rdev); 621 int ni_dpm_set_power_state(struct radeon_device *rdev); 622 void ni_dpm_post_set_power_state(struct radeon_device *rdev); 623 void ni_dpm_fini(struct radeon_device *rdev); 624 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); 625 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low); 626 void ni_dpm_print_power_state(struct radeon_device *rdev, 627 struct radeon_ps *ps); 628 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 629 struct seq_file *m); 630 int ni_dpm_force_performance_level(struct radeon_device *rdev, 631 enum radeon_dpm_forced_level level); 632 //bool ni_dpm_vblank_too_short(struct radeon_device *rdev); 633 int trinity_dpm_init(struct radeon_device *rdev); 634 int trinity_dpm_enable(struct radeon_device *rdev); 635 void trinity_dpm_disable(struct radeon_device *rdev); 636 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); 637 int trinity_dpm_set_power_state(struct radeon_device *rdev); 638 void trinity_dpm_post_set_power_state(struct radeon_device *rdev); 639 void trinity_dpm_setup_asic(struct radeon_device *rdev); 640 void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); 641 void trinity_dpm_fini(struct radeon_device *rdev); 642 u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); 643 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); 644 void trinity_dpm_print_power_state(struct radeon_device *rdev, 645 struct radeon_ps *ps); 646 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 647 struct seq_file *m); 648 int trinity_dpm_force_performance_level(struct radeon_device *rdev, 649 enum radeon_dpm_forced_level level); 650 void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 651 652 /* DCE6 - SI */ 653 void dce6_bandwidth_update(struct radeon_device *rdev); 654 int dce6_audio_init(struct radeon_device *rdev); 655 void dce6_audio_fini(struct radeon_device *rdev); 656 657 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder); 658 void dce6_afmt_select_pin(struct drm_encoder *encoder); 659 void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder); 660 661 /* 662 * si 663 */ 664 void si_fence_ring_emit(struct radeon_device *rdev, 665 struct radeon_fence *fence); 666 void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 667 int si_init(struct radeon_device *rdev); 668 void si_fini(struct radeon_device *rdev); 669 int si_suspend(struct radeon_device *rdev); 670 int si_resume(struct radeon_device *rdev); 671 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 672 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 673 int si_asic_reset(struct radeon_device *rdev); 674 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 675 int si_irq_set(struct radeon_device *rdev); 676 irqreturn_t si_irq_process(struct radeon_device *rdev); 677 int si_vm_init(struct radeon_device *rdev); 678 void si_vm_fini(struct radeon_device *rdev); 679 void si_vm_set_page(struct radeon_device *rdev, 680 struct radeon_ib *ib, 681 uint64_t pe, 682 uint64_t addr, unsigned count, 683 uint32_t incr, uint32_t flags); 684 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 685 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 686 int si_copy_dma(struct radeon_device *rdev, 687 uint64_t src_offset, uint64_t dst_offset, 688 unsigned num_gpu_pages, 689 struct radeon_fence **fence); 690 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 691 u32 si_get_xclk(struct radeon_device *rdev); 692 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode); 693 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock); 694 u32 si_get_csb_size(struct radeon_device *rdev); 695 void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); 696 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 697 u32 max_voltage_steps, 698 struct atom_voltage_table *voltage_table); 699 void si_dma_vm_set_page(struct radeon_device *rdev, 700 struct radeon_ib *ib, 701 uint64_t pe, 702 uint64_t addr, unsigned count, 703 uint32_t incr, uint32_t flags); 704 u32 si_gpu_check_soft_reset(struct radeon_device *rdev); 705 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 706 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 707 int si_get_temp(struct radeon_device *rdev); 708 void si_rlc_fini(struct radeon_device *rdev); 709 int si_rlc_init(struct radeon_device *rdev); 710 void si_rlc_reset(struct radeon_device *rdev); 711 void si_vram_gtt_location(struct radeon_device *rdev, 712 struct radeon_mc *mc); 713 void si_init_uvd_internal_cg(struct radeon_device *rdev); 714 void si_update_cg(struct radeon_device *rdev, 715 u32 block, bool enable); 716 int si_dpm_init(struct radeon_device *rdev); 717 void si_dpm_setup_asic(struct radeon_device *rdev); 718 int si_dpm_enable(struct radeon_device *rdev); 719 void si_dpm_disable(struct radeon_device *rdev); 720 int si_dpm_pre_set_power_state(struct radeon_device *rdev); 721 int si_dpm_set_power_state(struct radeon_device *rdev); 722 void si_dpm_post_set_power_state(struct radeon_device *rdev); 723 void si_dpm_fini(struct radeon_device *rdev); 724 void si_dpm_display_configuration_changed(struct radeon_device *rdev); 725 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 726 struct seq_file *m); 727 int si_dpm_force_performance_level(struct radeon_device *rdev, 728 enum radeon_dpm_forced_level level); 729 730 /* DCE8 - CIK */ 731 void dce8_bandwidth_update(struct radeon_device *rdev); 732 733 /* 734 * cik 735 */ 736 u32 cik_get_csb_size(struct radeon_device *rdev); 737 void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); 738 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); 739 u32 cik_get_xclk(struct radeon_device *rdev); 740 uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 741 void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 742 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 743 void cik_init_cp_pg_table(struct radeon_device *rdev); 744 void cik_update_cg(struct radeon_device *rdev, 745 u32 block, bool enable); 746 void cik_enter_rlc_safe_mode(struct radeon_device *rdev); 747 void cik_exit_rlc_safe_mode(struct radeon_device *rdev); 748 void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 749 struct radeon_fence *fence); 750 void cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 751 struct radeon_ring *ring, 752 struct radeon_semaphore *semaphore, 753 bool emit_wait); 754 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 755 int cik_copy_dma(struct radeon_device *rdev, 756 uint64_t src_offset, uint64_t dst_offset, 757 unsigned num_gpu_pages, 758 struct radeon_fence **fence); 759 int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 760 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 761 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 762 void cik_fence_gfx_ring_emit(struct radeon_device *rdev, 763 struct radeon_fence *fence); 764 void cik_fence_compute_ring_emit(struct radeon_device *rdev, 765 struct radeon_fence *fence); 766 void cik_semaphore_ring_emit(struct radeon_device *rdev, 767 struct radeon_ring *cp, 768 struct radeon_semaphore *semaphore, 769 bool emit_wait); 770 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); 771 int cik_init(struct radeon_device *rdev); 772 void cik_fini(struct radeon_device *rdev); 773 int cik_suspend(struct radeon_device *rdev); 774 int cik_resume(struct radeon_device *rdev); 775 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 776 int cik_asic_reset(struct radeon_device *rdev); 777 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 778 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 779 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 780 int cik_irq_set(struct radeon_device *rdev); 781 irqreturn_t cik_irq_process(struct radeon_device *rdev); 782 int cik_vm_init(struct radeon_device *rdev); 783 void cik_vm_fini(struct radeon_device *rdev); 784 void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 785 void cik_vm_set_page(struct radeon_device *rdev, 786 struct radeon_ib *ib, 787 uint64_t pe, 788 uint64_t addr, unsigned count, 789 uint32_t incr, uint32_t flags); 790 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 791 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 792 u32 cik_compute_ring_get_rptr(struct radeon_device *rdev, 793 struct radeon_ring *ring); 794 u32 cik_compute_ring_get_wptr(struct radeon_device *rdev, 795 struct radeon_ring *ring); 796 void cik_compute_ring_set_wptr(struct radeon_device *rdev, 797 struct radeon_ring *ring); 798 bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 799 void cik_fence_ring_emit(struct radeon_device *rdev, 800 struct radeon_fence *fence); 801 u32 cik_gpu_check_soft_reset(struct radeon_device *rdev); 802 void cik_sdma_enable(struct radeon_device *rdev, bool enable); 803 int cik_sdma_resume(struct radeon_device *rdev); 804 void cik_sdma_fini(struct radeon_device *rdev); 805 void cik_sdma_vm_set_page(struct radeon_device *rdev, 806 struct radeon_ib *ib, 807 uint64_t pe, 808 uint64_t addr, unsigned count, 809 uint32_t incr, uint32_t flags); 810 int ci_get_temp(struct radeon_device *rdev); 811 int kv_get_temp(struct radeon_device *rdev); 812 813 int ci_dpm_init(struct radeon_device *rdev); 814 int ci_dpm_enable(struct radeon_device *rdev); 815 void ci_dpm_disable(struct radeon_device *rdev); 816 int ci_dpm_pre_set_power_state(struct radeon_device *rdev); 817 int ci_dpm_set_power_state(struct radeon_device *rdev); 818 void ci_dpm_post_set_power_state(struct radeon_device *rdev); 819 void ci_dpm_setup_asic(struct radeon_device *rdev); 820 void ci_dpm_display_configuration_changed(struct radeon_device *rdev); 821 void ci_dpm_fini(struct radeon_device *rdev); 822 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low); 823 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low); 824 void ci_dpm_print_power_state(struct radeon_device *rdev, 825 struct radeon_ps *ps); 826 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 827 struct seq_file *m); 828 int ci_dpm_force_performance_level(struct radeon_device *rdev, 829 enum radeon_dpm_forced_level level); 830 bool ci_dpm_vblank_too_short(struct radeon_device *rdev); 831 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 832 833 int kv_dpm_init(struct radeon_device *rdev); 834 int kv_dpm_enable(struct radeon_device *rdev); 835 void kv_dpm_disable(struct radeon_device *rdev); 836 int kv_dpm_pre_set_power_state(struct radeon_device *rdev); 837 int kv_dpm_set_power_state(struct radeon_device *rdev); 838 void kv_dpm_post_set_power_state(struct radeon_device *rdev); 839 void kv_dpm_setup_asic(struct radeon_device *rdev); 840 void kv_dpm_display_configuration_changed(struct radeon_device *rdev); 841 void kv_dpm_fini(struct radeon_device *rdev); 842 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low); 843 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low); 844 void kv_dpm_print_power_state(struct radeon_device *rdev, 845 struct radeon_ps *ps); 846 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 847 struct seq_file *m); 848 int kv_dpm_force_performance_level(struct radeon_device *rdev, 849 enum radeon_dpm_forced_level level); 850 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 851 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 852 853 /* uvd v1.0 */ 854 uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, 855 struct radeon_ring *ring); 856 uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, 857 struct radeon_ring *ring); 858 void uvd_v1_0_set_wptr(struct radeon_device *rdev, 859 struct radeon_ring *ring); 860 861 int uvd_v1_0_init(struct radeon_device *rdev); 862 void uvd_v1_0_fini(struct radeon_device *rdev); 863 int uvd_v1_0_start(struct radeon_device *rdev); 864 void uvd_v1_0_stop(struct radeon_device *rdev); 865 866 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 867 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 868 void uvd_v1_0_semaphore_emit(struct radeon_device *rdev, 869 struct radeon_ring *ring, 870 struct radeon_semaphore *semaphore, 871 bool emit_wait); 872 void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 873 874 /* uvd v2.2 */ 875 int uvd_v2_2_resume(struct radeon_device *rdev); 876 void uvd_v2_2_fence_emit(struct radeon_device *rdev, 877 struct radeon_fence *fence); 878 879 /* uvd v3.1 */ 880 void uvd_v3_1_semaphore_emit(struct radeon_device *rdev, 881 struct radeon_ring *ring, 882 struct radeon_semaphore *semaphore, 883 bool emit_wait); 884 885 /* uvd v4.2 */ 886 int uvd_v4_2_resume(struct radeon_device *rdev); 887 888 #endif 889