157e252bfSMichael Neumann /* 257e252bfSMichael Neumann * Copyright 2011 Advanced Micro Devices, Inc. 357e252bfSMichael Neumann * 457e252bfSMichael Neumann * Permission is hereby granted, free of charge, to any person obtaining a 557e252bfSMichael Neumann * copy of this software and associated documentation files (the "Software"), 657e252bfSMichael Neumann * to deal in the Software without restriction, including without limitation 757e252bfSMichael Neumann * the rights to use, copy, modify, merge, publish, distribute, sublicense, 857e252bfSMichael Neumann * and/or sell copies of the Software, and to permit persons to whom the 957e252bfSMichael Neumann * Software is furnished to do so, subject to the following conditions: 1057e252bfSMichael Neumann * 1157e252bfSMichael Neumann * The above copyright notice and this permission notice shall be included in 1257e252bfSMichael Neumann * all copies or substantial portions of the Software. 1357e252bfSMichael Neumann * 1457e252bfSMichael Neumann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1557e252bfSMichael Neumann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1657e252bfSMichael Neumann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1757e252bfSMichael Neumann * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1857e252bfSMichael Neumann * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1957e252bfSMichael Neumann * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2057e252bfSMichael Neumann * OTHER DEALINGS IN THE SOFTWARE. 2157e252bfSMichael Neumann * 2257e252bfSMichael Neumann */ 2357e252bfSMichael Neumann #ifndef __R600_DPM_H__ 2457e252bfSMichael Neumann #define __R600_DPM_H__ 2557e252bfSMichael Neumann 2657e252bfSMichael Neumann #define R600_ASI_DFLT 10000 2757e252bfSMichael Neumann #define R600_BSP_DFLT 0x41EB 2857e252bfSMichael Neumann #define R600_BSU_DFLT 0x2 2957e252bfSMichael Neumann #define R600_AH_DFLT 5 3057e252bfSMichael Neumann #define R600_RLP_DFLT 25 3157e252bfSMichael Neumann #define R600_RMP_DFLT 65 3257e252bfSMichael Neumann #define R600_LHP_DFLT 40 3357e252bfSMichael Neumann #define R600_LMP_DFLT 15 3457e252bfSMichael Neumann #define R600_TD_DFLT 0 3557e252bfSMichael Neumann #define R600_UTC_DFLT_00 0x24 3657e252bfSMichael Neumann #define R600_UTC_DFLT_01 0x22 3757e252bfSMichael Neumann #define R600_UTC_DFLT_02 0x22 3857e252bfSMichael Neumann #define R600_UTC_DFLT_03 0x22 3957e252bfSMichael Neumann #define R600_UTC_DFLT_04 0x22 4057e252bfSMichael Neumann #define R600_UTC_DFLT_05 0x22 4157e252bfSMichael Neumann #define R600_UTC_DFLT_06 0x22 4257e252bfSMichael Neumann #define R600_UTC_DFLT_07 0x22 4357e252bfSMichael Neumann #define R600_UTC_DFLT_08 0x22 4457e252bfSMichael Neumann #define R600_UTC_DFLT_09 0x22 4557e252bfSMichael Neumann #define R600_UTC_DFLT_10 0x22 4657e252bfSMichael Neumann #define R600_UTC_DFLT_11 0x22 4757e252bfSMichael Neumann #define R600_UTC_DFLT_12 0x22 4857e252bfSMichael Neumann #define R600_UTC_DFLT_13 0x22 4957e252bfSMichael Neumann #define R600_UTC_DFLT_14 0x22 5057e252bfSMichael Neumann #define R600_DTC_DFLT_00 0x24 5157e252bfSMichael Neumann #define R600_DTC_DFLT_01 0x22 5257e252bfSMichael Neumann #define R600_DTC_DFLT_02 0x22 5357e252bfSMichael Neumann #define R600_DTC_DFLT_03 0x22 5457e252bfSMichael Neumann #define R600_DTC_DFLT_04 0x22 5557e252bfSMichael Neumann #define R600_DTC_DFLT_05 0x22 5657e252bfSMichael Neumann #define R600_DTC_DFLT_06 0x22 5757e252bfSMichael Neumann #define R600_DTC_DFLT_07 0x22 5857e252bfSMichael Neumann #define R600_DTC_DFLT_08 0x22 5957e252bfSMichael Neumann #define R600_DTC_DFLT_09 0x22 6057e252bfSMichael Neumann #define R600_DTC_DFLT_10 0x22 6157e252bfSMichael Neumann #define R600_DTC_DFLT_11 0x22 6257e252bfSMichael Neumann #define R600_DTC_DFLT_12 0x22 6357e252bfSMichael Neumann #define R600_DTC_DFLT_13 0x22 6457e252bfSMichael Neumann #define R600_DTC_DFLT_14 0x22 6557e252bfSMichael Neumann #define R600_VRC_DFLT 0x0000C003 6657e252bfSMichael Neumann #define R600_VOLTAGERESPONSETIME_DFLT 1000 6757e252bfSMichael Neumann #define R600_BACKBIASRESPONSETIME_DFLT 1000 6857e252bfSMichael Neumann #define R600_VRU_DFLT 0x3 6957e252bfSMichael Neumann #define R600_SPLLSTEPTIME_DFLT 0x1000 7057e252bfSMichael Neumann #define R600_SPLLSTEPUNIT_DFLT 0x3 7157e252bfSMichael Neumann #define R600_TPU_DFLT 0 7257e252bfSMichael Neumann #define R600_TPC_DFLT 0x200 7357e252bfSMichael Neumann #define R600_SSTU_DFLT 0 7457e252bfSMichael Neumann #define R600_SST_DFLT 0x00C8 7557e252bfSMichael Neumann #define R600_GICST_DFLT 0x200 7657e252bfSMichael Neumann #define R600_FCT_DFLT 0x0400 7757e252bfSMichael Neumann #define R600_FCTU_DFLT 0 7857e252bfSMichael Neumann #define R600_CTXCGTT3DRPHC_DFLT 0x20 7957e252bfSMichael Neumann #define R600_CTXCGTT3DRSDC_DFLT 0x40 8057e252bfSMichael Neumann #define R600_VDDC3DOORPHC_DFLT 0x100 8157e252bfSMichael Neumann #define R600_VDDC3DOORSDC_DFLT 0x7 8257e252bfSMichael Neumann #define R600_VDDC3DOORSU_DFLT 0 8357e252bfSMichael Neumann #define R600_MPLLLOCKTIME_DFLT 100 8457e252bfSMichael Neumann #define R600_MPLLRESETTIME_DFLT 150 8557e252bfSMichael Neumann #define R600_VCOSTEPPCT_DFLT 20 8657e252bfSMichael Neumann #define R600_ENDINGVCOSTEPPCT_DFLT 5 8757e252bfSMichael Neumann #define R600_REFERENCEDIVIDER_DFLT 4 8857e252bfSMichael Neumann 8957e252bfSMichael Neumann #define R600_PM_NUMBER_OF_TC 15 9057e252bfSMichael Neumann #define R600_PM_NUMBER_OF_SCLKS 20 9157e252bfSMichael Neumann #define R600_PM_NUMBER_OF_MCLKS 4 9257e252bfSMichael Neumann #define R600_PM_NUMBER_OF_VOLTAGE_LEVELS 4 9357e252bfSMichael Neumann #define R600_PM_NUMBER_OF_ACTIVITY_LEVELS 3 9457e252bfSMichael Neumann 9557e252bfSMichael Neumann /* XXX are these ok? */ 9657e252bfSMichael Neumann #define R600_TEMP_RANGE_MIN (90 * 1000) 9757e252bfSMichael Neumann #define R600_TEMP_RANGE_MAX (120 * 1000) 9857e252bfSMichael Neumann 99*7dcf36dcSFrançois Tigeot #define FDO_PWM_MODE_STATIC 1 100*7dcf36dcSFrançois Tigeot #define FDO_PWM_MODE_STATIC_RPM 5 101*7dcf36dcSFrançois Tigeot 10257e252bfSMichael Neumann enum r600_power_level { 10357e252bfSMichael Neumann R600_POWER_LEVEL_LOW = 0, 10457e252bfSMichael Neumann R600_POWER_LEVEL_MEDIUM = 1, 10557e252bfSMichael Neumann R600_POWER_LEVEL_HIGH = 2, 10657e252bfSMichael Neumann R600_POWER_LEVEL_CTXSW = 3, 10757e252bfSMichael Neumann }; 10857e252bfSMichael Neumann 10957e252bfSMichael Neumann enum r600_td { 11057e252bfSMichael Neumann R600_TD_AUTO, 11157e252bfSMichael Neumann R600_TD_UP, 11257e252bfSMichael Neumann R600_TD_DOWN, 11357e252bfSMichael Neumann }; 11457e252bfSMichael Neumann 11557e252bfSMichael Neumann enum r600_display_watermark { 11657e252bfSMichael Neumann R600_DISPLAY_WATERMARK_LOW = 0, 11757e252bfSMichael Neumann R600_DISPLAY_WATERMARK_HIGH = 1, 11857e252bfSMichael Neumann }; 11957e252bfSMichael Neumann 12057e252bfSMichael Neumann enum r600_display_gap 12157e252bfSMichael Neumann { 12257e252bfSMichael Neumann R600_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, 12357e252bfSMichael Neumann R600_PM_DISPLAY_GAP_VBLANK = 1, 12457e252bfSMichael Neumann R600_PM_DISPLAY_GAP_WATERMARK = 2, 12557e252bfSMichael Neumann R600_PM_DISPLAY_GAP_IGNORE = 3, 12657e252bfSMichael Neumann }; 12757e252bfSMichael Neumann 12857e252bfSMichael Neumann extern const u32 r600_utc[R600_PM_NUMBER_OF_TC]; 12957e252bfSMichael Neumann extern const u32 r600_dtc[R600_PM_NUMBER_OF_TC]; 13057e252bfSMichael Neumann 13157e252bfSMichael Neumann void r600_dpm_print_class_info(u32 class, u32 class2); 13257e252bfSMichael Neumann void r600_dpm_print_cap_info(u32 caps); 13357e252bfSMichael Neumann void r600_dpm_print_ps_status(struct radeon_device *rdev, 13457e252bfSMichael Neumann struct radeon_ps *rps); 13557e252bfSMichael Neumann u32 r600_dpm_get_vblank_time(struct radeon_device *rdev); 1364cd92098Szrj u32 r600_dpm_get_vrefresh(struct radeon_device *rdev); 13757e252bfSMichael Neumann bool r600_is_uvd_state(u32 class, u32 class2); 13857e252bfSMichael Neumann void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, 13957e252bfSMichael Neumann u32 *p, u32 *u); 14057e252bfSMichael Neumann int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th); 14157e252bfSMichael Neumann void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable); 14257e252bfSMichael Neumann void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable); 14357e252bfSMichael Neumann void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable); 14457e252bfSMichael Neumann void r600_enable_acpi_pm(struct radeon_device *rdev); 14557e252bfSMichael Neumann void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable); 14657e252bfSMichael Neumann bool r600_dynamicpm_enabled(struct radeon_device *rdev); 14757e252bfSMichael Neumann void r600_enable_sclk_control(struct radeon_device *rdev, bool enable); 14857e252bfSMichael Neumann void r600_enable_mclk_control(struct radeon_device *rdev, bool enable); 14957e252bfSMichael Neumann void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable); 15057e252bfSMichael Neumann void r600_wait_for_spll_change(struct radeon_device *rdev); 15157e252bfSMichael Neumann void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p); 15257e252bfSMichael Neumann void r600_set_at(struct radeon_device *rdev, 15357e252bfSMichael Neumann u32 l_to_m, u32 m_to_h, 15457e252bfSMichael Neumann u32 h_to_m, u32 m_to_l); 15557e252bfSMichael Neumann void r600_set_tc(struct radeon_device *rdev, u32 index, u32 u_t, u32 d_t); 15657e252bfSMichael Neumann void r600_select_td(struct radeon_device *rdev, enum r600_td td); 15757e252bfSMichael Neumann void r600_set_vrc(struct radeon_device *rdev, u32 vrv); 15857e252bfSMichael Neumann void r600_set_tpu(struct radeon_device *rdev, u32 u); 15957e252bfSMichael Neumann void r600_set_tpc(struct radeon_device *rdev, u32 c); 16057e252bfSMichael Neumann void r600_set_sstu(struct radeon_device *rdev, u32 u); 16157e252bfSMichael Neumann void r600_set_sst(struct radeon_device *rdev, u32 t); 16257e252bfSMichael Neumann void r600_set_git(struct radeon_device *rdev, u32 t); 16357e252bfSMichael Neumann void r600_set_fctu(struct radeon_device *rdev, u32 u); 16457e252bfSMichael Neumann void r600_set_fct(struct radeon_device *rdev, u32 t); 16557e252bfSMichael Neumann void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p); 16657e252bfSMichael Neumann void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s); 16757e252bfSMichael Neumann void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u); 16857e252bfSMichael Neumann void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p); 16957e252bfSMichael Neumann void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s); 17057e252bfSMichael Neumann void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time); 17157e252bfSMichael Neumann void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time); 17257e252bfSMichael Neumann void r600_engine_clock_entry_enable(struct radeon_device *rdev, 17357e252bfSMichael Neumann u32 index, bool enable); 17457e252bfSMichael Neumann void r600_engine_clock_entry_enable_pulse_skipping(struct radeon_device *rdev, 17557e252bfSMichael Neumann u32 index, bool enable); 17657e252bfSMichael Neumann void r600_engine_clock_entry_enable_post_divider(struct radeon_device *rdev, 17757e252bfSMichael Neumann u32 index, bool enable); 17857e252bfSMichael Neumann void r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev, 17957e252bfSMichael Neumann u32 index, u32 divider); 18057e252bfSMichael Neumann void r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev, 18157e252bfSMichael Neumann u32 index, u32 divider); 18257e252bfSMichael Neumann void r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev, 18357e252bfSMichael Neumann u32 index, u32 divider); 18457e252bfSMichael Neumann void r600_engine_clock_entry_set_step_time(struct radeon_device *rdev, 18557e252bfSMichael Neumann u32 index, u32 step_time); 18657e252bfSMichael Neumann void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u); 18757e252bfSMichael Neumann void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u); 18857e252bfSMichael Neumann void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt); 18957e252bfSMichael Neumann void r600_voltage_control_enable_pins(struct radeon_device *rdev, 19057e252bfSMichael Neumann u64 mask); 19157e252bfSMichael Neumann void r600_voltage_control_program_voltages(struct radeon_device *rdev, 19257e252bfSMichael Neumann enum r600_power_level index, u64 pins); 19357e252bfSMichael Neumann void r600_voltage_control_deactivate_static_control(struct radeon_device *rdev, 19457e252bfSMichael Neumann u64 mask); 19557e252bfSMichael Neumann void r600_power_level_enable(struct radeon_device *rdev, 19657e252bfSMichael Neumann enum r600_power_level index, bool enable); 19757e252bfSMichael Neumann void r600_power_level_set_voltage_index(struct radeon_device *rdev, 19857e252bfSMichael Neumann enum r600_power_level index, u32 voltage_index); 19957e252bfSMichael Neumann void r600_power_level_set_mem_clock_index(struct radeon_device *rdev, 20057e252bfSMichael Neumann enum r600_power_level index, u32 mem_clock_index); 20157e252bfSMichael Neumann void r600_power_level_set_eng_clock_index(struct radeon_device *rdev, 20257e252bfSMichael Neumann enum r600_power_level index, u32 eng_clock_index); 20357e252bfSMichael Neumann void r600_power_level_set_watermark_id(struct radeon_device *rdev, 20457e252bfSMichael Neumann enum r600_power_level index, 20557e252bfSMichael Neumann enum r600_display_watermark watermark_id); 20657e252bfSMichael Neumann void r600_power_level_set_pcie_gen2(struct radeon_device *rdev, 20757e252bfSMichael Neumann enum r600_power_level index, bool compatible); 20857e252bfSMichael Neumann enum r600_power_level r600_power_level_get_current_index(struct radeon_device *rdev); 20957e252bfSMichael Neumann enum r600_power_level r600_power_level_get_target_index(struct radeon_device *rdev); 21057e252bfSMichael Neumann void r600_power_level_set_enter_index(struct radeon_device *rdev, 21157e252bfSMichael Neumann enum r600_power_level index); 21257e252bfSMichael Neumann void r600_wait_for_power_level_unequal(struct radeon_device *rdev, 21357e252bfSMichael Neumann enum r600_power_level index); 21457e252bfSMichael Neumann void r600_wait_for_power_level(struct radeon_device *rdev, 21557e252bfSMichael Neumann enum r600_power_level index); 21657e252bfSMichael Neumann void r600_start_dpm(struct radeon_device *rdev); 21757e252bfSMichael Neumann void r600_stop_dpm(struct radeon_device *rdev); 21857e252bfSMichael Neumann 21957e252bfSMichael Neumann bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor); 22057e252bfSMichael Neumann 221c6f73aabSFrançois Tigeot int r600_get_platform_caps(struct radeon_device *rdev); 222c6f73aabSFrançois Tigeot 22357e252bfSMichael Neumann int r600_parse_extended_power_table(struct radeon_device *rdev); 22457e252bfSMichael Neumann void r600_free_extended_power_table(struct radeon_device *rdev); 22557e252bfSMichael Neumann 22657e252bfSMichael Neumann enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev, 22757e252bfSMichael Neumann u32 sys_mask, 22857e252bfSMichael Neumann enum radeon_pcie_gen asic_gen, 22957e252bfSMichael Neumann enum radeon_pcie_gen default_gen); 23057e252bfSMichael Neumann 2314cd92098Szrj u16 r600_get_pcie_lane_support(struct radeon_device *rdev, 2324cd92098Szrj u16 asic_lanes, 2334cd92098Szrj u16 default_lanes); 2344cd92098Szrj u8 r600_encode_pci_lane_width(u32 lanes); 2354cd92098Szrj 23657e252bfSMichael Neumann #endif 237