1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/r100.c 255573 2013-09-14 17:24:41Z dumbbell $ 29 */ 30 #include <drm/drmP.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "r100d.h" 36 #include "rs100d.h" 37 #include "rv200d.h" 38 #include "rv250d.h" 39 #include "atom.h" 40 41 #include <linux/firmware.h> 42 #include <linux/module.h> 43 44 #include "r100_reg_safe.h" 45 #include "rn50_reg_safe.h" 46 47 /* Firmware Names */ 48 #define FIRMWARE_R100 "radeonkmsfw_R100_cp" 49 #define FIRMWARE_R200 "radeonkmsfw_R200_cp" 50 #define FIRMWARE_R300 "radeonkmsfw_R300_cp" 51 #define FIRMWARE_R420 "radeonkmsfw_R420_cp" 52 #define FIRMWARE_RS690 "radeonkmsfw_RS690_cp" 53 #define FIRMWARE_RS600 "radeonkmsfw_RS600_cp" 54 #define FIRMWARE_R520 "radeonkmsfw_R520_cp" 55 56 MODULE_FIRMWARE(FIRMWARE_R100); 57 MODULE_FIRMWARE(FIRMWARE_R200); 58 MODULE_FIRMWARE(FIRMWARE_R300); 59 MODULE_FIRMWARE(FIRMWARE_R420); 60 MODULE_FIRMWARE(FIRMWARE_RS690); 61 MODULE_FIRMWARE(FIRMWARE_RS600); 62 MODULE_FIRMWARE(FIRMWARE_R520); 63 64 #include "r100_track.h" 65 66 /* This files gather functions specifics to: 67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 68 * and others in some cases. 69 */ 70 71 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) 72 { 73 if (crtc == 0) { 74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) 75 return true; 76 else 77 return false; 78 } else { 79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 80 return true; 81 else 82 return false; 83 } 84 } 85 86 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) 87 { 88 u32 vline1, vline2; 89 90 if (crtc == 0) { 91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 93 } else { 94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 96 } 97 if (vline1 != vline2) 98 return true; 99 else 100 return false; 101 } 102 103 /** 104 * r100_wait_for_vblank - vblank wait asic callback. 105 * 106 * @rdev: radeon_device pointer 107 * @crtc: crtc to wait for vblank on 108 * 109 * Wait for vblank on the requested crtc (r1xx-r4xx). 110 */ 111 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 112 { 113 unsigned i = 0; 114 115 if (crtc >= rdev->num_crtc) 116 return; 117 118 if (crtc == 0) { 119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) 120 return; 121 } else { 122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) 123 return; 124 } 125 126 /* depending on when we hit vblank, we may be close to active; if so, 127 * wait for another frame. 128 */ 129 while (r100_is_in_vblank(rdev, crtc)) { 130 if (i++ % 100 == 0) { 131 if (!r100_is_counter_moving(rdev, crtc)) 132 break; 133 } 134 } 135 136 while (!r100_is_in_vblank(rdev, crtc)) { 137 if (i++ % 100 == 0) { 138 if (!r100_is_counter_moving(rdev, crtc)) 139 break; 140 } 141 } 142 } 143 144 /** 145 * r100_page_flip - pageflip callback. 146 * 147 * @rdev: radeon_device pointer 148 * @crtc_id: crtc to cleanup pageflip on 149 * @crtc_base: new address of the crtc (GPU MC address) 150 * 151 * Does the actual pageflip (r1xx-r4xx). 152 * During vblank we take the crtc lock and wait for the update_pending 153 * bit to go high, when it does, we release the lock, and allow the 154 * double buffered update to take place. 155 */ 156 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) 157 { 158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 159 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 160 int i; 161 162 /* Lock the graphics update lock */ 163 /* update the scanout addresses */ 164 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 165 166 /* Wait for update_pending to go high. */ 167 for (i = 0; i < rdev->usec_timeout; i++) { 168 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 169 break; 170 udelay(1); 171 } 172 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 173 174 /* Unlock the lock, so double-buffering can take place inside vblank */ 175 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 176 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 177 178 } 179 180 /** 181 * r100_page_flip_pending - check if page flip is still pending 182 * 183 * @rdev: radeon_device pointer 184 * @crtc_id: crtc to check 185 * 186 * Check if the last pagefilp is still pending (r1xx-r4xx). 187 * Returns the current update pending status. 188 */ 189 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id) 190 { 191 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 192 193 /* Return current update_pending status: */ 194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & 195 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET); 196 } 197 198 /** 199 * r100_pm_get_dynpm_state - look up dynpm power state callback. 200 * 201 * @rdev: radeon_device pointer 202 * 203 * Look up the optimal power state based on the 204 * current state of the GPU (r1xx-r5xx). 205 * Used for dynpm only. 206 */ 207 void r100_pm_get_dynpm_state(struct radeon_device *rdev) 208 { 209 int i; 210 rdev->pm.dynpm_can_upclock = true; 211 rdev->pm.dynpm_can_downclock = true; 212 213 switch (rdev->pm.dynpm_planned_action) { 214 case DYNPM_ACTION_MINIMUM: 215 rdev->pm.requested_power_state_index = 0; 216 rdev->pm.dynpm_can_downclock = false; 217 break; 218 case DYNPM_ACTION_DOWNCLOCK: 219 if (rdev->pm.current_power_state_index == 0) { 220 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 221 rdev->pm.dynpm_can_downclock = false; 222 } else { 223 if (rdev->pm.active_crtc_count > 1) { 224 for (i = 0; i < rdev->pm.num_power_states; i++) { 225 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 226 continue; 227 else if (i >= rdev->pm.current_power_state_index) { 228 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 229 break; 230 } else { 231 rdev->pm.requested_power_state_index = i; 232 break; 233 } 234 } 235 } else 236 rdev->pm.requested_power_state_index = 237 rdev->pm.current_power_state_index - 1; 238 } 239 /* don't use the power state if crtcs are active and no display flag is set */ 240 if ((rdev->pm.active_crtc_count > 0) && 241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 242 RADEON_PM_MODE_NO_DISPLAY)) { 243 rdev->pm.requested_power_state_index++; 244 } 245 break; 246 case DYNPM_ACTION_UPCLOCK: 247 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 248 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 249 rdev->pm.dynpm_can_upclock = false; 250 } else { 251 if (rdev->pm.active_crtc_count > 1) { 252 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 253 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 254 continue; 255 else if (i <= rdev->pm.current_power_state_index) { 256 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 257 break; 258 } else { 259 rdev->pm.requested_power_state_index = i; 260 break; 261 } 262 } 263 } else 264 rdev->pm.requested_power_state_index = 265 rdev->pm.current_power_state_index + 1; 266 } 267 break; 268 case DYNPM_ACTION_DEFAULT: 269 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 270 rdev->pm.dynpm_can_upclock = false; 271 break; 272 case DYNPM_ACTION_NONE: 273 default: 274 DRM_ERROR("Requested mode for not defined action\n"); 275 return; 276 } 277 /* only one clock mode per power state */ 278 rdev->pm.requested_clock_mode_index = 0; 279 280 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 281 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 282 clock_info[rdev->pm.requested_clock_mode_index].sclk, 283 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 284 clock_info[rdev->pm.requested_clock_mode_index].mclk, 285 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 286 pcie_lanes); 287 } 288 289 /** 290 * r100_pm_init_profile - Initialize power profiles callback. 291 * 292 * @rdev: radeon_device pointer 293 * 294 * Initialize the power states used in profile mode 295 * (r1xx-r3xx). 296 * Used for profile mode only. 297 */ 298 void r100_pm_init_profile(struct radeon_device *rdev) 299 { 300 /* default */ 301 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 305 /* low sh */ 306 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 310 /* mid sh */ 311 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 315 /* high sh */ 316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 320 /* low mh */ 321 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 325 /* mid mh */ 326 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 330 /* high mh */ 331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 335 } 336 337 /** 338 * r100_pm_misc - set additional pm hw parameters callback. 339 * 340 * @rdev: radeon_device pointer 341 * 342 * Set non-clock parameters associated with a power state 343 * (voltage, pcie lanes, etc.) (r1xx-r4xx). 344 */ 345 void r100_pm_misc(struct radeon_device *rdev) 346 { 347 int requested_index = rdev->pm.requested_power_state_index; 348 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 349 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 350 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 351 352 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 353 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 354 tmp = RREG32(voltage->gpio.reg); 355 if (voltage->active_high) 356 tmp |= voltage->gpio.mask; 357 else 358 tmp &= ~(voltage->gpio.mask); 359 WREG32(voltage->gpio.reg, tmp); 360 if (voltage->delay) 361 udelay(voltage->delay); 362 } else { 363 tmp = RREG32(voltage->gpio.reg); 364 if (voltage->active_high) 365 tmp &= ~voltage->gpio.mask; 366 else 367 tmp |= voltage->gpio.mask; 368 WREG32(voltage->gpio.reg, tmp); 369 if (voltage->delay) 370 udelay(voltage->delay); 371 } 372 } 373 374 sclk_cntl = RREG32_PLL(SCLK_CNTL); 375 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 376 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 377 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 378 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 379 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 380 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 381 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 382 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 383 else 384 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 385 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 386 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 387 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 388 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 389 } else 390 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 391 392 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 393 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 394 if (voltage->delay) { 395 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 396 switch (voltage->delay) { 397 case 33: 398 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 399 break; 400 case 66: 401 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 402 break; 403 case 99: 404 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 405 break; 406 case 132: 407 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 408 break; 409 } 410 } else 411 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 412 } else 413 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 414 415 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 416 sclk_cntl &= ~FORCE_HDP; 417 else 418 sclk_cntl |= FORCE_HDP; 419 420 WREG32_PLL(SCLK_CNTL, sclk_cntl); 421 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 422 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 423 424 /* set pcie lanes */ 425 if ((rdev->flags & RADEON_IS_PCIE) && 426 !(rdev->flags & RADEON_IS_IGP) && 427 rdev->asic->pm.set_pcie_lanes && 428 (ps->pcie_lanes != 429 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 430 radeon_set_pcie_lanes(rdev, 431 ps->pcie_lanes); 432 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 433 } 434 } 435 436 /** 437 * r100_pm_prepare - pre-power state change callback. 438 * 439 * @rdev: radeon_device pointer 440 * 441 * Prepare for a power state change (r1xx-r4xx). 442 */ 443 void r100_pm_prepare(struct radeon_device *rdev) 444 { 445 struct drm_device *ddev = rdev->ddev; 446 struct drm_crtc *crtc; 447 struct radeon_crtc *radeon_crtc; 448 u32 tmp; 449 450 /* disable any active CRTCs */ 451 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 452 radeon_crtc = to_radeon_crtc(crtc); 453 if (radeon_crtc->enabled) { 454 if (radeon_crtc->crtc_id) { 455 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 456 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 457 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 458 } else { 459 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 460 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 461 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 462 } 463 } 464 } 465 } 466 467 /** 468 * r100_pm_finish - post-power state change callback. 469 * 470 * @rdev: radeon_device pointer 471 * 472 * Clean up after a power state change (r1xx-r4xx). 473 */ 474 void r100_pm_finish(struct radeon_device *rdev) 475 { 476 struct drm_device *ddev = rdev->ddev; 477 struct drm_crtc *crtc; 478 struct radeon_crtc *radeon_crtc; 479 u32 tmp; 480 481 /* enable any active CRTCs */ 482 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 483 radeon_crtc = to_radeon_crtc(crtc); 484 if (radeon_crtc->enabled) { 485 if (radeon_crtc->crtc_id) { 486 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 487 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 488 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 489 } else { 490 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 491 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 492 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 493 } 494 } 495 } 496 } 497 498 /** 499 * r100_gui_idle - gui idle callback. 500 * 501 * @rdev: radeon_device pointer 502 * 503 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). 504 * Returns true if idle, false if not. 505 */ 506 bool r100_gui_idle(struct radeon_device *rdev) 507 { 508 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 509 return false; 510 else 511 return true; 512 } 513 514 /* hpd for digital panel detect/disconnect */ 515 /** 516 * r100_hpd_sense - hpd sense callback. 517 * 518 * @rdev: radeon_device pointer 519 * @hpd: hpd (hotplug detect) pin 520 * 521 * Checks if a digital monitor is connected (r1xx-r4xx). 522 * Returns true if connected, false if not connected. 523 */ 524 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 525 { 526 bool connected = false; 527 528 switch (hpd) { 529 case RADEON_HPD_1: 530 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 531 connected = true; 532 break; 533 case RADEON_HPD_2: 534 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 535 connected = true; 536 break; 537 default: 538 break; 539 } 540 return connected; 541 } 542 543 /** 544 * r100_hpd_set_polarity - hpd set polarity callback. 545 * 546 * @rdev: radeon_device pointer 547 * @hpd: hpd (hotplug detect) pin 548 * 549 * Set the polarity of the hpd pin (r1xx-r4xx). 550 */ 551 void r100_hpd_set_polarity(struct radeon_device *rdev, 552 enum radeon_hpd_id hpd) 553 { 554 u32 tmp; 555 bool connected = r100_hpd_sense(rdev, hpd); 556 557 switch (hpd) { 558 case RADEON_HPD_1: 559 tmp = RREG32(RADEON_FP_GEN_CNTL); 560 if (connected) 561 tmp &= ~RADEON_FP_DETECT_INT_POL; 562 else 563 tmp |= RADEON_FP_DETECT_INT_POL; 564 WREG32(RADEON_FP_GEN_CNTL, tmp); 565 break; 566 case RADEON_HPD_2: 567 tmp = RREG32(RADEON_FP2_GEN_CNTL); 568 if (connected) 569 tmp &= ~RADEON_FP2_DETECT_INT_POL; 570 else 571 tmp |= RADEON_FP2_DETECT_INT_POL; 572 WREG32(RADEON_FP2_GEN_CNTL, tmp); 573 break; 574 default: 575 break; 576 } 577 } 578 579 /** 580 * r100_hpd_init - hpd setup callback. 581 * 582 * @rdev: radeon_device pointer 583 * 584 * Setup the hpd pins used by the card (r1xx-r4xx). 585 * Set the polarity, and enable the hpd interrupts. 586 */ 587 void r100_hpd_init(struct radeon_device *rdev) 588 { 589 struct drm_device *dev = rdev->ddev; 590 struct drm_connector *connector; 591 unsigned enable = 0; 592 593 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 594 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 595 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 596 enable |= 1 << radeon_connector->hpd.hpd; 597 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 598 } 599 radeon_irq_kms_enable_hpd(rdev, enable); 600 } 601 602 /** 603 * r100_hpd_fini - hpd tear down callback. 604 * 605 * @rdev: radeon_device pointer 606 * 607 * Tear down the hpd pins used by the card (r1xx-r4xx). 608 * Disable the hpd interrupts. 609 */ 610 void r100_hpd_fini(struct radeon_device *rdev) 611 { 612 struct drm_device *dev = rdev->ddev; 613 struct drm_connector *connector; 614 unsigned disable = 0; 615 616 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 617 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 618 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 619 disable |= 1 << radeon_connector->hpd.hpd; 620 } 621 radeon_irq_kms_disable_hpd(rdev, disable); 622 } 623 624 /* 625 * PCI GART 626 */ 627 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 628 { 629 /* TODO: can we do somethings here ? */ 630 /* It seems hw only cache one entry so we should discard this 631 * entry otherwise if first GPU GART read hit this entry it 632 * could end up in wrong address. */ 633 } 634 635 int r100_pci_gart_init(struct radeon_device *rdev) 636 { 637 int r; 638 639 if (rdev->gart.ptr) { 640 WARN(1, "R100 PCI GART already initialized\n"); 641 return 0; 642 } 643 /* Initialize common gart structure */ 644 r = radeon_gart_init(rdev); 645 if (r) 646 return r; 647 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 648 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 649 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 650 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 651 return radeon_gart_table_ram_alloc(rdev); 652 } 653 654 int r100_pci_gart_enable(struct radeon_device *rdev) 655 { 656 uint32_t tmp; 657 658 /* discard memory request outside of configured range */ 659 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 660 WREG32(RADEON_AIC_CNTL, tmp); 661 /* set address range for PCI address translate */ 662 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 663 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 664 /* set PCI GART page-table base address */ 665 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 666 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 667 WREG32(RADEON_AIC_CNTL, tmp); 668 r100_pci_gart_tlb_flush(rdev); 669 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", 670 (unsigned)(rdev->mc.gtt_size >> 20), 671 (unsigned long long)rdev->gart.table_addr); 672 rdev->gart.ready = true; 673 return 0; 674 } 675 676 void r100_pci_gart_disable(struct radeon_device *rdev) 677 { 678 uint32_t tmp; 679 680 /* discard memory request outside of configured range */ 681 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 682 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 683 WREG32(RADEON_AIC_LO_ADDR, 0); 684 WREG32(RADEON_AIC_HI_ADDR, 0); 685 } 686 687 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags) 688 { 689 return addr; 690 } 691 692 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 693 uint64_t entry) 694 { 695 u32 *gtt = rdev->gart.ptr; 696 gtt[i] = cpu_to_le32(lower_32_bits(entry)); 697 } 698 699 void r100_pci_gart_fini(struct radeon_device *rdev) 700 { 701 radeon_gart_fini(rdev); 702 r100_pci_gart_disable(rdev); 703 radeon_gart_table_ram_free(rdev); 704 } 705 706 int r100_irq_set(struct radeon_device *rdev) 707 { 708 uint32_t tmp = 0; 709 710 if (!rdev->irq.installed) { 711 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 712 WREG32(R_000040_GEN_INT_CNTL, 0); 713 return -EINVAL; 714 } 715 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 716 tmp |= RADEON_SW_INT_ENABLE; 717 } 718 if (rdev->irq.crtc_vblank_int[0] || 719 atomic_read(&rdev->irq.pflip[0])) { 720 tmp |= RADEON_CRTC_VBLANK_MASK; 721 } 722 if (rdev->irq.crtc_vblank_int[1] || 723 atomic_read(&rdev->irq.pflip[1])) { 724 tmp |= RADEON_CRTC2_VBLANK_MASK; 725 } 726 if (rdev->irq.hpd[0]) { 727 tmp |= RADEON_FP_DETECT_MASK; 728 } 729 if (rdev->irq.hpd[1]) { 730 tmp |= RADEON_FP2_DETECT_MASK; 731 } 732 WREG32(RADEON_GEN_INT_CNTL, tmp); 733 734 /* read back to post the write */ 735 RREG32(RADEON_GEN_INT_CNTL); 736 737 return 0; 738 } 739 740 void r100_irq_disable(struct radeon_device *rdev) 741 { 742 u32 tmp; 743 744 WREG32(R_000040_GEN_INT_CNTL, 0); 745 /* Wait and acknowledge irq */ 746 mdelay(1); 747 tmp = RREG32(R_000044_GEN_INT_STATUS); 748 WREG32(R_000044_GEN_INT_STATUS, tmp); 749 } 750 751 static uint32_t r100_irq_ack(struct radeon_device *rdev) 752 { 753 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 754 uint32_t irq_mask = RADEON_SW_INT_TEST | 755 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 756 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 757 758 if (irqs) { 759 WREG32(RADEON_GEN_INT_STATUS, irqs); 760 } 761 return irqs & irq_mask; 762 } 763 764 irqreturn_t r100_irq_process(struct radeon_device *rdev) 765 { 766 uint32_t status, msi_rearm; 767 bool queue_hotplug = false; 768 769 status = r100_irq_ack(rdev); 770 if (!status) { 771 return IRQ_NONE; 772 } 773 if (rdev->shutdown) { 774 return IRQ_NONE; 775 } 776 while (status) { 777 /* SW interrupt */ 778 if (status & RADEON_SW_INT_TEST) { 779 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 780 } 781 /* Vertical blank interrupts */ 782 if (status & RADEON_CRTC_VBLANK_STAT) { 783 if (rdev->irq.crtc_vblank_int[0]) { 784 drm_handle_vblank(rdev->ddev, 0); 785 rdev->pm.vblank_sync = true; 786 wake_up(&rdev->irq.vblank_queue); 787 } 788 if (atomic_read(&rdev->irq.pflip[0])) 789 radeon_crtc_handle_vblank(rdev, 0); 790 } 791 if (status & RADEON_CRTC2_VBLANK_STAT) { 792 if (rdev->irq.crtc_vblank_int[1]) { 793 drm_handle_vblank(rdev->ddev, 1); 794 rdev->pm.vblank_sync = true; 795 wake_up(&rdev->irq.vblank_queue); 796 } 797 if (atomic_read(&rdev->irq.pflip[1])) 798 radeon_crtc_handle_vblank(rdev, 1); 799 } 800 if (status & RADEON_FP_DETECT_STAT) { 801 queue_hotplug = true; 802 DRM_DEBUG("HPD1\n"); 803 } 804 if (status & RADEON_FP2_DETECT_STAT) { 805 queue_hotplug = true; 806 DRM_DEBUG("HPD2\n"); 807 } 808 status = r100_irq_ack(rdev); 809 } 810 if (queue_hotplug) 811 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); 812 if (rdev->msi_enabled) { 813 switch (rdev->family) { 814 case CHIP_RS400: 815 case CHIP_RS480: 816 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 817 WREG32(RADEON_AIC_CNTL, msi_rearm); 818 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 819 break; 820 default: 821 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 822 break; 823 } 824 } 825 return IRQ_HANDLED; 826 } 827 828 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 829 { 830 if (crtc == 0) 831 return RREG32(RADEON_CRTC_CRNT_FRAME); 832 else 833 return RREG32(RADEON_CRTC2_CRNT_FRAME); 834 } 835 836 /** 837 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer 838 * rdev: radeon device structure 839 * ring: ring buffer struct for emitting packets 840 */ 841 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring) 842 { 843 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 844 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 845 RADEON_HDP_READ_BUFFER_INVALIDATE); 846 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 847 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 848 } 849 850 /* Who ever call radeon_fence_emit should call ring_lock and ask 851 * for enough space (today caller are ib schedule and buffer move) */ 852 void r100_fence_ring_emit(struct radeon_device *rdev, 853 struct radeon_fence *fence) 854 { 855 struct radeon_ring *ring = &rdev->ring[fence->ring]; 856 857 /* We have to make sure that caches are flushed before 858 * CPU might read something from VRAM. */ 859 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 860 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 861 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 862 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 863 /* Wait until IDLE & CLEAN */ 864 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 865 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 866 r100_ring_hdp_flush(rdev, ring); 867 /* Emit fence sequence & fire IRQ */ 868 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 869 radeon_ring_write(ring, fence->seq); 870 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 871 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 872 } 873 874 bool r100_semaphore_ring_emit(struct radeon_device *rdev, 875 struct radeon_ring *ring, 876 struct radeon_semaphore *semaphore, 877 bool emit_wait) 878 { 879 /* Unused on older asics, since we don't have semaphores or multiple rings */ 880 BUG(); 881 return false; 882 } 883 884 int r100_copy_blit(struct radeon_device *rdev, 885 uint64_t src_offset, 886 uint64_t dst_offset, 887 unsigned num_gpu_pages, 888 struct radeon_fence **fence) 889 { 890 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 891 uint32_t cur_pages; 892 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 893 uint32_t pitch; 894 uint32_t stride_pixels; 895 unsigned ndw; 896 int num_loops; 897 int r = 0; 898 899 /* radeon limited to 16k stride */ 900 stride_bytes &= 0x3fff; 901 /* radeon pitch is /64 */ 902 pitch = stride_bytes / 64; 903 stride_pixels = stride_bytes / 4; 904 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 905 906 /* Ask for enough room for blit + flush + fence */ 907 ndw = 64 + (10 * num_loops); 908 r = radeon_ring_lock(rdev, ring, ndw); 909 if (r) { 910 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 911 return -EINVAL; 912 } 913 while (num_gpu_pages > 0) { 914 cur_pages = num_gpu_pages; 915 if (cur_pages > 8191) { 916 cur_pages = 8191; 917 } 918 num_gpu_pages -= cur_pages; 919 920 /* pages are in Y direction - height 921 page width in X direction - width */ 922 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 923 radeon_ring_write(ring, 924 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 925 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 926 RADEON_GMC_SRC_CLIPPING | 927 RADEON_GMC_DST_CLIPPING | 928 RADEON_GMC_BRUSH_NONE | 929 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 930 RADEON_GMC_SRC_DATATYPE_COLOR | 931 RADEON_ROP3_S | 932 RADEON_DP_SRC_SOURCE_MEMORY | 933 RADEON_GMC_CLR_CMP_CNTL_DIS | 934 RADEON_GMC_WR_MSK_DIS); 935 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); 936 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); 937 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 938 radeon_ring_write(ring, 0); 939 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 940 radeon_ring_write(ring, num_gpu_pages); 941 radeon_ring_write(ring, num_gpu_pages); 942 radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 943 } 944 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 945 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 946 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 947 radeon_ring_write(ring, 948 RADEON_WAIT_2D_IDLECLEAN | 949 RADEON_WAIT_HOST_IDLECLEAN | 950 RADEON_WAIT_DMA_GUI_IDLE); 951 if (fence) { 952 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); 953 if (r) { 954 radeon_ring_unlock_undo(rdev, ring); 955 return r; 956 } 957 } 958 radeon_ring_unlock_commit(rdev, ring, false); 959 return r; 960 } 961 962 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 963 { 964 unsigned i; 965 u32 tmp; 966 967 for (i = 0; i < rdev->usec_timeout; i++) { 968 tmp = RREG32(R_000E40_RBBM_STATUS); 969 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 970 return 0; 971 } 972 udelay(1); 973 } 974 return -1; 975 } 976 977 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 978 { 979 int r; 980 981 r = radeon_ring_lock(rdev, ring, 2); 982 if (r) { 983 return; 984 } 985 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 986 radeon_ring_write(ring, 987 RADEON_ISYNC_ANY2D_IDLE3D | 988 RADEON_ISYNC_ANY3D_IDLE2D | 989 RADEON_ISYNC_WAIT_IDLEGUI | 990 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 991 radeon_ring_unlock_commit(rdev, ring, false); 992 } 993 994 995 /* Load the microcode for the CP */ 996 static int r100_cp_init_microcode(struct radeon_device *rdev) 997 { 998 const char *fw_name = NULL; 999 int err; 1000 1001 DRM_DEBUG_KMS("\n"); 1002 1003 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 1004 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 1005 (rdev->family == CHIP_RS200)) { 1006 DRM_INFO("Loading R100 Microcode\n"); 1007 fw_name = FIRMWARE_R100; 1008 } else if ((rdev->family == CHIP_R200) || 1009 (rdev->family == CHIP_RV250) || 1010 (rdev->family == CHIP_RV280) || 1011 (rdev->family == CHIP_RS300)) { 1012 DRM_INFO("Loading R200 Microcode\n"); 1013 fw_name = FIRMWARE_R200; 1014 } else if ((rdev->family == CHIP_R300) || 1015 (rdev->family == CHIP_R350) || 1016 (rdev->family == CHIP_RV350) || 1017 (rdev->family == CHIP_RV380) || 1018 (rdev->family == CHIP_RS400) || 1019 (rdev->family == CHIP_RS480)) { 1020 DRM_INFO("Loading R300 Microcode\n"); 1021 fw_name = FIRMWARE_R300; 1022 } else if ((rdev->family == CHIP_R420) || 1023 (rdev->family == CHIP_R423) || 1024 (rdev->family == CHIP_RV410)) { 1025 DRM_INFO("Loading R400 Microcode\n"); 1026 fw_name = FIRMWARE_R420; 1027 } else if ((rdev->family == CHIP_RS690) || 1028 (rdev->family == CHIP_RS740)) { 1029 DRM_INFO("Loading RS690/RS740 Microcode\n"); 1030 fw_name = FIRMWARE_RS690; 1031 } else if (rdev->family == CHIP_RS600) { 1032 DRM_INFO("Loading RS600 Microcode\n"); 1033 fw_name = FIRMWARE_RS600; 1034 } else if ((rdev->family == CHIP_RV515) || 1035 (rdev->family == CHIP_R520) || 1036 (rdev->family == CHIP_RV530) || 1037 (rdev->family == CHIP_R580) || 1038 (rdev->family == CHIP_RV560) || 1039 (rdev->family == CHIP_RV570)) { 1040 DRM_INFO("Loading R500 Microcode\n"); 1041 fw_name = FIRMWARE_R520; 1042 } 1043 1044 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 1045 if (err) { 1046 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", 1047 fw_name); 1048 } else if (rdev->me_fw->datasize % 8) { 1049 printk(KERN_ERR 1050 "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 1051 rdev->me_fw->datasize, fw_name); 1052 err = -EINVAL; 1053 release_firmware(rdev->me_fw); 1054 rdev->me_fw = NULL; 1055 } 1056 return err; 1057 } 1058 1059 u32 r100_gfx_get_rptr(struct radeon_device *rdev, 1060 struct radeon_ring *ring) 1061 { 1062 u32 rptr; 1063 1064 if (rdev->wb.enabled) 1065 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 1066 else 1067 rptr = RREG32(RADEON_CP_RB_RPTR); 1068 1069 return rptr; 1070 } 1071 1072 u32 r100_gfx_get_wptr(struct radeon_device *rdev, 1073 struct radeon_ring *ring) 1074 { 1075 u32 wptr; 1076 1077 wptr = RREG32(RADEON_CP_RB_WPTR); 1078 1079 return wptr; 1080 } 1081 1082 void r100_gfx_set_wptr(struct radeon_device *rdev, 1083 struct radeon_ring *ring) 1084 { 1085 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1086 (void)RREG32(RADEON_CP_RB_WPTR); 1087 } 1088 1089 /** 1090 * r100_cp_fini_microcode - drop the firmware image reference 1091 * 1092 * @rdev: radeon_device pointer 1093 * 1094 * Drop the me firmware image reference. 1095 * Called at driver shutdown. 1096 */ 1097 static void r100_cp_fini_microcode (struct radeon_device *rdev) 1098 { 1099 release_firmware(rdev->me_fw); 1100 rdev->me_fw = NULL; 1101 } 1102 1103 static void r100_cp_load_microcode(struct radeon_device *rdev) 1104 { 1105 const __be32 *fw_data; 1106 int i, size; 1107 1108 if (r100_gui_wait_for_idle(rdev)) { 1109 printk(KERN_WARNING "Failed to wait GUI idle while " 1110 "programming pipes. Bad things might happen.\n"); 1111 } 1112 1113 if (rdev->me_fw) { 1114 size = rdev->me_fw->datasize / 4; 1115 fw_data = (const __be32 *)rdev->me_fw->data; 1116 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 1117 for (i = 0; i < size; i += 2) { 1118 WREG32(RADEON_CP_ME_RAM_DATAH, 1119 be32_to_cpup(&fw_data[i])); 1120 WREG32(RADEON_CP_ME_RAM_DATAL, 1121 be32_to_cpup(&fw_data[i + 1])); 1122 } 1123 } 1124 } 1125 1126 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1127 { 1128 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1129 unsigned rb_bufsz; 1130 unsigned rb_blksz; 1131 unsigned max_fetch; 1132 unsigned pre_write_timer; 1133 unsigned pre_write_limit; 1134 unsigned indirect2_start; 1135 unsigned indirect1_start; 1136 uint32_t tmp; 1137 int r; 1138 1139 if (r100_debugfs_cp_init(rdev)) { 1140 DRM_ERROR("Failed to register debugfs file for CP !\n"); 1141 } 1142 if (!rdev->me_fw) { 1143 r = r100_cp_init_microcode(rdev); 1144 if (r) { 1145 DRM_ERROR("Failed to load firmware!\n"); 1146 return r; 1147 } 1148 } 1149 1150 /* Align ring size */ 1151 rb_bufsz = order_base_2(ring_size / 8); 1152 ring_size = (1 << (rb_bufsz + 1)) * 4; 1153 r100_cp_load_microcode(rdev); 1154 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 1155 RADEON_CP_PACKET2); 1156 if (r) { 1157 return r; 1158 } 1159 /* Each time the cp read 1024 bytes (16 dword/quadword) update 1160 * the rptr copy in system ram */ 1161 rb_blksz = 9; 1162 /* cp will read 128bytes at a time (4 dwords) */ 1163 max_fetch = 1; 1164 ring->align_mask = 16 - 1; 1165 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1166 pre_write_timer = 64; 1167 /* Force CP_RB_WPTR write if written more than one time before the 1168 * delay expire 1169 */ 1170 pre_write_limit = 0; 1171 /* Setup the cp cache like this (cache size is 96 dwords) : 1172 * RING 0 to 15 1173 * INDIRECT1 16 to 79 1174 * INDIRECT2 80 to 95 1175 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1176 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1177 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1178 * Idea being that most of the gpu cmd will be through indirect1 buffer 1179 * so it gets the bigger cache. 1180 */ 1181 indirect2_start = 80; 1182 indirect1_start = 16; 1183 /* cp setup */ 1184 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1185 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1186 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1187 REG_SET(RADEON_MAX_FETCH, max_fetch)); 1188 #ifdef __BIG_ENDIAN 1189 tmp |= RADEON_BUF_SWAP_32BIT; 1190 #endif 1191 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1192 1193 /* Set ring address */ 1194 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1195 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1196 /* Force read & write ptr to 0 */ 1197 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1198 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1199 ring->wptr = 0; 1200 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1201 1202 /* set the wb address whether it's enabled or not */ 1203 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1204 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1205 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1206 1207 if (rdev->wb.enabled) 1208 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1209 else { 1210 tmp |= RADEON_RB_NO_UPDATE; 1211 WREG32(R_000770_SCRATCH_UMSK, 0); 1212 } 1213 1214 WREG32(RADEON_CP_RB_CNTL, tmp); 1215 udelay(10); 1216 /* Set cp mode to bus mastering & enable cp*/ 1217 WREG32(RADEON_CP_CSQ_MODE, 1218 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1219 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1220 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1221 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1222 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1223 1224 /* at this point everything should be setup correctly to enable master */ 1225 pci_enable_busmaster(rdev->dev->bsddev); 1226 1227 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1228 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1229 if (r) { 1230 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1231 return r; 1232 } 1233 ring->ready = true; 1234 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1235 1236 if (!ring->rptr_save_reg /* not resuming from suspend */ 1237 && radeon_ring_supports_scratch_reg(rdev, ring)) { 1238 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 1239 if (r) { 1240 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 1241 ring->rptr_save_reg = 0; 1242 } 1243 } 1244 return 0; 1245 } 1246 1247 void r100_cp_fini(struct radeon_device *rdev) 1248 { 1249 if (r100_cp_wait_for_idle(rdev)) { 1250 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1251 } 1252 /* Disable ring */ 1253 r100_cp_disable(rdev); 1254 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); 1255 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1256 DRM_INFO("radeon: cp finalized\n"); 1257 } 1258 1259 void r100_cp_disable(struct radeon_device *rdev) 1260 { 1261 /* Disable ring */ 1262 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1263 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1264 WREG32(RADEON_CP_CSQ_MODE, 0); 1265 WREG32(RADEON_CP_CSQ_CNTL, 0); 1266 WREG32(R_000770_SCRATCH_UMSK, 0); 1267 if (r100_gui_wait_for_idle(rdev)) { 1268 printk(KERN_WARNING "Failed to wait GUI idle while " 1269 "programming pipes. Bad things might happen.\n"); 1270 } 1271 } 1272 1273 /* 1274 * CS functions 1275 */ 1276 int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 1277 struct radeon_cs_packet *pkt, 1278 unsigned idx, 1279 unsigned reg) 1280 { 1281 int r; 1282 u32 tile_flags = 0; 1283 u32 tmp; 1284 struct radeon_bo_list *reloc; 1285 u32 value; 1286 1287 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1288 if (r) { 1289 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1290 idx, reg); 1291 radeon_cs_dump_packet(p, pkt); 1292 return r; 1293 } 1294 1295 value = radeon_get_ib_value(p, idx); 1296 tmp = value & 0x003fffff; 1297 tmp += (((u32)reloc->gpu_offset) >> 10); 1298 1299 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1300 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1301 tile_flags |= RADEON_DST_TILE_MACRO; 1302 if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1303 if (reg == RADEON_SRC_PITCH_OFFSET) { 1304 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1305 radeon_cs_dump_packet(p, pkt); 1306 return -EINVAL; 1307 } 1308 tile_flags |= RADEON_DST_TILE_MICRO; 1309 } 1310 1311 tmp |= tile_flags; 1312 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; 1313 } else 1314 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; 1315 return 0; 1316 } 1317 1318 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 1319 struct radeon_cs_packet *pkt, 1320 int idx) 1321 { 1322 unsigned c, i; 1323 struct radeon_bo_list *reloc; 1324 struct r100_cs_track *track; 1325 int r = 0; 1326 volatile uint32_t *ib; 1327 u32 idx_value; 1328 1329 ib = p->ib.ptr; 1330 track = (struct r100_cs_track *)p->track; 1331 c = radeon_get_ib_value(p, idx++) & 0x1F; 1332 if (c > 16) { 1333 DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 1334 pkt->opcode); 1335 radeon_cs_dump_packet(p, pkt); 1336 return -EINVAL; 1337 } 1338 track->num_arrays = c; 1339 for (i = 0; i < (c - 1); i+=2, idx+=3) { 1340 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1341 if (r) { 1342 DRM_ERROR("No reloc for packet3 %d\n", 1343 pkt->opcode); 1344 radeon_cs_dump_packet(p, pkt); 1345 return r; 1346 } 1347 idx_value = radeon_get_ib_value(p, idx); 1348 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1349 1350 track->arrays[i + 0].esize = idx_value >> 8; 1351 track->arrays[i + 0].robj = reloc->robj; 1352 track->arrays[i + 0].esize &= 0x7F; 1353 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1354 if (r) { 1355 DRM_ERROR("No reloc for packet3 %d\n", 1356 pkt->opcode); 1357 radeon_cs_dump_packet(p, pkt); 1358 return r; 1359 } 1360 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); 1361 track->arrays[i + 1].robj = reloc->robj; 1362 track->arrays[i + 1].esize = idx_value >> 24; 1363 track->arrays[i + 1].esize &= 0x7F; 1364 } 1365 if (c & 1) { 1366 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1367 if (r) { 1368 DRM_ERROR("No reloc for packet3 %d\n", 1369 pkt->opcode); 1370 radeon_cs_dump_packet(p, pkt); 1371 return r; 1372 } 1373 idx_value = radeon_get_ib_value(p, idx); 1374 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1375 track->arrays[i + 0].robj = reloc->robj; 1376 track->arrays[i + 0].esize = idx_value >> 8; 1377 track->arrays[i + 0].esize &= 0x7F; 1378 } 1379 return r; 1380 } 1381 1382 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1383 struct radeon_cs_packet *pkt, 1384 const unsigned *auth, unsigned n, 1385 radeon_packet0_check_t check) 1386 { 1387 unsigned reg; 1388 unsigned i, j, m; 1389 unsigned idx; 1390 int r; 1391 1392 idx = pkt->idx + 1; 1393 reg = pkt->reg; 1394 /* Check that register fall into register range 1395 * determined by the number of entry (n) in the 1396 * safe register bitmap. 1397 */ 1398 if (pkt->one_reg_wr) { 1399 if ((reg >> 7) > n) { 1400 return -EINVAL; 1401 } 1402 } else { 1403 if (((reg + (pkt->count << 2)) >> 7) > n) { 1404 return -EINVAL; 1405 } 1406 } 1407 for (i = 0; i <= pkt->count; i++, idx++) { 1408 j = (reg >> 7); 1409 m = 1 << ((reg >> 2) & 31); 1410 if (auth[j] & m) { 1411 r = check(p, pkt, idx, reg); 1412 if (r) { 1413 return r; 1414 } 1415 } 1416 if (pkt->one_reg_wr) { 1417 if (!(auth[j] & m)) { 1418 break; 1419 } 1420 } else { 1421 reg += 4; 1422 } 1423 } 1424 return 0; 1425 } 1426 1427 /** 1428 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1429 * @parser: parser structure holding parsing context. 1430 * 1431 * Userspace sends a special sequence for VLINE waits. 1432 * PACKET0 - VLINE_START_END + value 1433 * PACKET0 - WAIT_UNTIL +_value 1434 * RELOC (P3) - crtc_id in reloc. 1435 * 1436 * This function parses this and relocates the VLINE START END 1437 * and WAIT UNTIL packets to the correct crtc. 1438 * It also detects a switched off crtc and nulls out the 1439 * wait in that case. 1440 */ 1441 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1442 { 1443 struct drm_crtc *crtc; 1444 struct radeon_crtc *radeon_crtc; 1445 struct radeon_cs_packet p3reloc, waitreloc; 1446 int crtc_id; 1447 int r; 1448 uint32_t header, h_idx, reg; 1449 volatile uint32_t *ib; 1450 1451 ib = p->ib.ptr; 1452 1453 /* parse the wait until */ 1454 r = radeon_cs_packet_parse(p, &waitreloc, p->idx); 1455 if (r) 1456 return r; 1457 1458 /* check its a wait until and only 1 count */ 1459 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1460 waitreloc.count != 0) { 1461 DRM_ERROR("vline wait had illegal wait until segment\n"); 1462 return -EINVAL; 1463 } 1464 1465 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1466 DRM_ERROR("vline wait had illegal wait until\n"); 1467 return -EINVAL; 1468 } 1469 1470 /* jump over the NOP */ 1471 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1472 if (r) 1473 return r; 1474 1475 h_idx = p->idx - 2; 1476 p->idx += waitreloc.count + 2; 1477 p->idx += p3reloc.count + 2; 1478 1479 header = radeon_get_ib_value(p, h_idx); 1480 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1481 reg = R100_CP_PACKET0_GET_REG(header); 1482 crtc = drm_crtc_find(p->rdev->ddev, crtc_id); 1483 if (!crtc) { 1484 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1485 return -ENOENT; 1486 } 1487 radeon_crtc = to_radeon_crtc(crtc); 1488 crtc_id = radeon_crtc->crtc_id; 1489 1490 if (!crtc->enabled) { 1491 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1492 ib[h_idx + 2] = PACKET2(0); 1493 ib[h_idx + 3] = PACKET2(0); 1494 } else if (crtc_id == 1) { 1495 switch (reg) { 1496 case AVIVO_D1MODE_VLINE_START_END: 1497 header &= ~R300_CP_PACKET0_REG_MASK; 1498 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1499 break; 1500 case RADEON_CRTC_GUI_TRIG_VLINE: 1501 header &= ~R300_CP_PACKET0_REG_MASK; 1502 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1503 break; 1504 default: 1505 DRM_ERROR("unknown crtc reloc\n"); 1506 return -EINVAL; 1507 } 1508 ib[h_idx] = header; 1509 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1510 } 1511 1512 return 0; 1513 } 1514 1515 static int r100_get_vtx_size(uint32_t vtx_fmt) 1516 { 1517 int vtx_size; 1518 vtx_size = 2; 1519 /* ordered according to bits in spec */ 1520 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1521 vtx_size++; 1522 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1523 vtx_size += 3; 1524 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1525 vtx_size++; 1526 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1527 vtx_size++; 1528 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1529 vtx_size += 3; 1530 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1531 vtx_size++; 1532 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1533 vtx_size++; 1534 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1535 vtx_size += 2; 1536 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1537 vtx_size += 2; 1538 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1539 vtx_size++; 1540 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1541 vtx_size += 2; 1542 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1543 vtx_size++; 1544 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1545 vtx_size += 2; 1546 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1547 vtx_size++; 1548 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1549 vtx_size++; 1550 /* blend weight */ 1551 if (vtx_fmt & (0x7 << 15)) 1552 vtx_size += (vtx_fmt >> 15) & 0x7; 1553 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1554 vtx_size += 3; 1555 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1556 vtx_size += 2; 1557 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1558 vtx_size++; 1559 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1560 vtx_size++; 1561 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1562 vtx_size++; 1563 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1564 vtx_size++; 1565 return vtx_size; 1566 } 1567 1568 static int r100_packet0_check(struct radeon_cs_parser *p, 1569 struct radeon_cs_packet *pkt, 1570 unsigned idx, unsigned reg) 1571 { 1572 struct radeon_bo_list *reloc; 1573 struct r100_cs_track *track; 1574 volatile uint32_t *ib; 1575 uint32_t tmp; 1576 int r; 1577 int i, face; 1578 u32 tile_flags = 0; 1579 u32 idx_value; 1580 1581 ib = p->ib.ptr; 1582 track = (struct r100_cs_track *)p->track; 1583 1584 idx_value = radeon_get_ib_value(p, idx); 1585 1586 switch (reg) { 1587 case RADEON_CRTC_GUI_TRIG_VLINE: 1588 r = r100_cs_packet_parse_vline(p); 1589 if (r) { 1590 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1591 idx, reg); 1592 radeon_cs_dump_packet(p, pkt); 1593 return r; 1594 } 1595 break; 1596 /* FIXME: only allow PACKET3 blit? easier to check for out of 1597 * range access */ 1598 case RADEON_DST_PITCH_OFFSET: 1599 case RADEON_SRC_PITCH_OFFSET: 1600 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1601 if (r) 1602 return r; 1603 break; 1604 case RADEON_RB3D_DEPTHOFFSET: 1605 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1606 if (r) { 1607 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1608 idx, reg); 1609 radeon_cs_dump_packet(p, pkt); 1610 return r; 1611 } 1612 track->zb.robj = reloc->robj; 1613 track->zb.offset = idx_value; 1614 track->zb_dirty = true; 1615 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1616 break; 1617 case RADEON_RB3D_COLOROFFSET: 1618 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1619 if (r) { 1620 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1621 idx, reg); 1622 radeon_cs_dump_packet(p, pkt); 1623 return r; 1624 } 1625 track->cb[0].robj = reloc->robj; 1626 track->cb[0].offset = idx_value; 1627 track->cb_dirty = true; 1628 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1629 break; 1630 case RADEON_PP_TXOFFSET_0: 1631 case RADEON_PP_TXOFFSET_1: 1632 case RADEON_PP_TXOFFSET_2: 1633 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1634 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1635 if (r) { 1636 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1637 idx, reg); 1638 radeon_cs_dump_packet(p, pkt); 1639 return r; 1640 } 1641 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1642 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1643 tile_flags |= RADEON_TXO_MACRO_TILE; 1644 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1645 tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1646 1647 tmp = idx_value & ~(0x7 << 2); 1648 tmp |= tile_flags; 1649 ib[idx] = tmp + ((u32)reloc->gpu_offset); 1650 } else 1651 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1652 track->textures[i].robj = reloc->robj; 1653 track->tex_dirty = true; 1654 break; 1655 case RADEON_PP_CUBIC_OFFSET_T0_0: 1656 case RADEON_PP_CUBIC_OFFSET_T0_1: 1657 case RADEON_PP_CUBIC_OFFSET_T0_2: 1658 case RADEON_PP_CUBIC_OFFSET_T0_3: 1659 case RADEON_PP_CUBIC_OFFSET_T0_4: 1660 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1661 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1662 if (r) { 1663 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1664 idx, reg); 1665 radeon_cs_dump_packet(p, pkt); 1666 return r; 1667 } 1668 track->textures[0].cube_info[i].offset = idx_value; 1669 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1670 track->textures[0].cube_info[i].robj = reloc->robj; 1671 track->tex_dirty = true; 1672 break; 1673 case RADEON_PP_CUBIC_OFFSET_T1_0: 1674 case RADEON_PP_CUBIC_OFFSET_T1_1: 1675 case RADEON_PP_CUBIC_OFFSET_T1_2: 1676 case RADEON_PP_CUBIC_OFFSET_T1_3: 1677 case RADEON_PP_CUBIC_OFFSET_T1_4: 1678 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1679 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1680 if (r) { 1681 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1682 idx, reg); 1683 radeon_cs_dump_packet(p, pkt); 1684 return r; 1685 } 1686 track->textures[1].cube_info[i].offset = idx_value; 1687 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1688 track->textures[1].cube_info[i].robj = reloc->robj; 1689 track->tex_dirty = true; 1690 break; 1691 case RADEON_PP_CUBIC_OFFSET_T2_0: 1692 case RADEON_PP_CUBIC_OFFSET_T2_1: 1693 case RADEON_PP_CUBIC_OFFSET_T2_2: 1694 case RADEON_PP_CUBIC_OFFSET_T2_3: 1695 case RADEON_PP_CUBIC_OFFSET_T2_4: 1696 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1697 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1698 if (r) { 1699 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1700 idx, reg); 1701 radeon_cs_dump_packet(p, pkt); 1702 return r; 1703 } 1704 track->textures[2].cube_info[i].offset = idx_value; 1705 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1706 track->textures[2].cube_info[i].robj = reloc->robj; 1707 track->tex_dirty = true; 1708 break; 1709 case RADEON_RE_WIDTH_HEIGHT: 1710 track->maxy = ((idx_value >> 16) & 0x7FF); 1711 track->cb_dirty = true; 1712 track->zb_dirty = true; 1713 break; 1714 case RADEON_RB3D_COLORPITCH: 1715 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1716 if (r) { 1717 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1718 idx, reg); 1719 radeon_cs_dump_packet(p, pkt); 1720 return r; 1721 } 1722 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1723 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1724 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1725 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1726 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1727 1728 tmp = idx_value & ~(0x7 << 16); 1729 tmp |= tile_flags; 1730 ib[idx] = tmp; 1731 } else 1732 ib[idx] = idx_value; 1733 1734 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1735 track->cb_dirty = true; 1736 break; 1737 case RADEON_RB3D_DEPTHPITCH: 1738 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1739 track->zb_dirty = true; 1740 break; 1741 case RADEON_RB3D_CNTL: 1742 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1743 case 7: 1744 case 8: 1745 case 9: 1746 case 11: 1747 case 12: 1748 track->cb[0].cpp = 1; 1749 break; 1750 case 3: 1751 case 4: 1752 case 15: 1753 track->cb[0].cpp = 2; 1754 break; 1755 case 6: 1756 track->cb[0].cpp = 4; 1757 break; 1758 default: 1759 DRM_ERROR("Invalid color buffer format (%d) !\n", 1760 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1761 return -EINVAL; 1762 } 1763 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1764 track->cb_dirty = true; 1765 track->zb_dirty = true; 1766 break; 1767 case RADEON_RB3D_ZSTENCILCNTL: 1768 switch (idx_value & 0xf) { 1769 case 0: 1770 track->zb.cpp = 2; 1771 break; 1772 case 2: 1773 case 3: 1774 case 4: 1775 case 5: 1776 case 9: 1777 case 11: 1778 track->zb.cpp = 4; 1779 break; 1780 default: 1781 break; 1782 } 1783 track->zb_dirty = true; 1784 break; 1785 case RADEON_RB3D_ZPASS_ADDR: 1786 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1787 if (r) { 1788 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1789 idx, reg); 1790 radeon_cs_dump_packet(p, pkt); 1791 return r; 1792 } 1793 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1794 break; 1795 case RADEON_PP_CNTL: 1796 { 1797 uint32_t temp = idx_value >> 4; 1798 for (i = 0; i < track->num_texture; i++) 1799 track->textures[i].enabled = !!(temp & (1 << i)); 1800 track->tex_dirty = true; 1801 } 1802 break; 1803 case RADEON_SE_VF_CNTL: 1804 track->vap_vf_cntl = idx_value; 1805 break; 1806 case RADEON_SE_VTX_FMT: 1807 track->vtx_size = r100_get_vtx_size(idx_value); 1808 break; 1809 case RADEON_PP_TEX_SIZE_0: 1810 case RADEON_PP_TEX_SIZE_1: 1811 case RADEON_PP_TEX_SIZE_2: 1812 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1813 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1814 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1815 track->tex_dirty = true; 1816 break; 1817 case RADEON_PP_TEX_PITCH_0: 1818 case RADEON_PP_TEX_PITCH_1: 1819 case RADEON_PP_TEX_PITCH_2: 1820 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1821 track->textures[i].pitch = idx_value + 32; 1822 track->tex_dirty = true; 1823 break; 1824 case RADEON_PP_TXFILTER_0: 1825 case RADEON_PP_TXFILTER_1: 1826 case RADEON_PP_TXFILTER_2: 1827 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1828 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1829 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1830 tmp = (idx_value >> 23) & 0x7; 1831 if (tmp == 2 || tmp == 6) 1832 track->textures[i].roundup_w = false; 1833 tmp = (idx_value >> 27) & 0x7; 1834 if (tmp == 2 || tmp == 6) 1835 track->textures[i].roundup_h = false; 1836 track->tex_dirty = true; 1837 break; 1838 case RADEON_PP_TXFORMAT_0: 1839 case RADEON_PP_TXFORMAT_1: 1840 case RADEON_PP_TXFORMAT_2: 1841 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1842 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1843 track->textures[i].use_pitch = 1; 1844 } else { 1845 track->textures[i].use_pitch = 0; 1846 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1847 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1848 } 1849 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1850 track->textures[i].tex_coord_type = 2; 1851 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1852 case RADEON_TXFORMAT_I8: 1853 case RADEON_TXFORMAT_RGB332: 1854 case RADEON_TXFORMAT_Y8: 1855 track->textures[i].cpp = 1; 1856 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1857 break; 1858 case RADEON_TXFORMAT_AI88: 1859 case RADEON_TXFORMAT_ARGB1555: 1860 case RADEON_TXFORMAT_RGB565: 1861 case RADEON_TXFORMAT_ARGB4444: 1862 case RADEON_TXFORMAT_VYUY422: 1863 case RADEON_TXFORMAT_YVYU422: 1864 case RADEON_TXFORMAT_SHADOW16: 1865 case RADEON_TXFORMAT_LDUDV655: 1866 case RADEON_TXFORMAT_DUDV88: 1867 track->textures[i].cpp = 2; 1868 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1869 break; 1870 case RADEON_TXFORMAT_ARGB8888: 1871 case RADEON_TXFORMAT_RGBA8888: 1872 case RADEON_TXFORMAT_SHADOW32: 1873 case RADEON_TXFORMAT_LDUDUV8888: 1874 track->textures[i].cpp = 4; 1875 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1876 break; 1877 case RADEON_TXFORMAT_DXT1: 1878 track->textures[i].cpp = 1; 1879 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1880 break; 1881 case RADEON_TXFORMAT_DXT23: 1882 case RADEON_TXFORMAT_DXT45: 1883 track->textures[i].cpp = 1; 1884 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1885 break; 1886 } 1887 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1888 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1889 track->tex_dirty = true; 1890 break; 1891 case RADEON_PP_CUBIC_FACES_0: 1892 case RADEON_PP_CUBIC_FACES_1: 1893 case RADEON_PP_CUBIC_FACES_2: 1894 tmp = idx_value; 1895 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1896 for (face = 0; face < 4; face++) { 1897 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1898 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1899 } 1900 track->tex_dirty = true; 1901 break; 1902 default: 1903 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1904 reg, idx); 1905 return -EINVAL; 1906 } 1907 return 0; 1908 } 1909 1910 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1911 struct radeon_cs_packet *pkt, 1912 struct radeon_bo *robj) 1913 { 1914 unsigned idx; 1915 u32 value; 1916 idx = pkt->idx + 1; 1917 value = radeon_get_ib_value(p, idx + 2); 1918 if ((value + 1) > radeon_bo_size(robj)) { 1919 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1920 "(need %u have %lu) !\n", 1921 value + 1, 1922 radeon_bo_size(robj)); 1923 return -EINVAL; 1924 } 1925 return 0; 1926 } 1927 1928 static int r100_packet3_check(struct radeon_cs_parser *p, 1929 struct radeon_cs_packet *pkt) 1930 { 1931 struct radeon_bo_list *reloc; 1932 struct r100_cs_track *track; 1933 unsigned idx; 1934 volatile uint32_t *ib; 1935 int r; 1936 1937 ib = p->ib.ptr; 1938 idx = pkt->idx + 1; 1939 track = (struct r100_cs_track *)p->track; 1940 switch (pkt->opcode) { 1941 case PACKET3_3D_LOAD_VBPNTR: 1942 r = r100_packet3_load_vbpntr(p, pkt, idx); 1943 if (r) 1944 return r; 1945 break; 1946 case PACKET3_INDX_BUFFER: 1947 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1948 if (r) { 1949 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1950 radeon_cs_dump_packet(p, pkt); 1951 return r; 1952 } 1953 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); 1954 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1955 if (r) { 1956 return r; 1957 } 1958 break; 1959 case 0x23: 1960 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1961 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1962 if (r) { 1963 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1964 radeon_cs_dump_packet(p, pkt); 1965 return r; 1966 } 1967 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); 1968 track->num_arrays = 1; 1969 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1970 1971 track->arrays[0].robj = reloc->robj; 1972 track->arrays[0].esize = track->vtx_size; 1973 1974 track->max_indx = radeon_get_ib_value(p, idx+1); 1975 1976 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1977 track->immd_dwords = pkt->count - 1; 1978 r = r100_cs_track_check(p->rdev, track); 1979 if (r) 1980 return r; 1981 break; 1982 case PACKET3_3D_DRAW_IMMD: 1983 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1984 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1985 return -EINVAL; 1986 } 1987 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1988 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1989 track->immd_dwords = pkt->count - 1; 1990 r = r100_cs_track_check(p->rdev, track); 1991 if (r) 1992 return r; 1993 break; 1994 /* triggers drawing using in-packet vertex data */ 1995 case PACKET3_3D_DRAW_IMMD_2: 1996 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1997 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1998 return -EINVAL; 1999 } 2000 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2001 track->immd_dwords = pkt->count; 2002 r = r100_cs_track_check(p->rdev, track); 2003 if (r) 2004 return r; 2005 break; 2006 /* triggers drawing using in-packet vertex data */ 2007 case PACKET3_3D_DRAW_VBUF_2: 2008 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2009 r = r100_cs_track_check(p->rdev, track); 2010 if (r) 2011 return r; 2012 break; 2013 /* triggers drawing of vertex buffers setup elsewhere */ 2014 case PACKET3_3D_DRAW_INDX_2: 2015 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2016 r = r100_cs_track_check(p->rdev, track); 2017 if (r) 2018 return r; 2019 break; 2020 /* triggers drawing using indices to vertex buffer */ 2021 case PACKET3_3D_DRAW_VBUF: 2022 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2023 r = r100_cs_track_check(p->rdev, track); 2024 if (r) 2025 return r; 2026 break; 2027 /* triggers drawing of vertex buffers setup elsewhere */ 2028 case PACKET3_3D_DRAW_INDX: 2029 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2030 r = r100_cs_track_check(p->rdev, track); 2031 if (r) 2032 return r; 2033 break; 2034 /* triggers drawing using indices to vertex buffer */ 2035 case PACKET3_3D_CLEAR_HIZ: 2036 case PACKET3_3D_CLEAR_ZMASK: 2037 if (p->rdev->hyperz_filp != p->filp) 2038 return -EINVAL; 2039 break; 2040 case PACKET3_NOP: 2041 break; 2042 default: 2043 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2044 return -EINVAL; 2045 } 2046 return 0; 2047 } 2048 2049 int r100_cs_parse(struct radeon_cs_parser *p) 2050 { 2051 struct radeon_cs_packet pkt; 2052 struct r100_cs_track *track; 2053 int r; 2054 2055 track = kzalloc(sizeof(*track), GFP_KERNEL); 2056 if (!track) 2057 return -ENOMEM; 2058 r100_cs_track_clear(p->rdev, track); 2059 p->track = track; 2060 do { 2061 r = radeon_cs_packet_parse(p, &pkt, p->idx); 2062 if (r) { 2063 return r; 2064 } 2065 p->idx += pkt.count + 2; 2066 switch (pkt.type) { 2067 case RADEON_PACKET_TYPE0: 2068 if (p->rdev->family >= CHIP_R200) 2069 r = r100_cs_parse_packet0(p, &pkt, 2070 p->rdev->config.r100.reg_safe_bm, 2071 p->rdev->config.r100.reg_safe_bm_size, 2072 &r200_packet0_check); 2073 else 2074 r = r100_cs_parse_packet0(p, &pkt, 2075 p->rdev->config.r100.reg_safe_bm, 2076 p->rdev->config.r100.reg_safe_bm_size, 2077 &r100_packet0_check); 2078 break; 2079 case RADEON_PACKET_TYPE2: 2080 break; 2081 case RADEON_PACKET_TYPE3: 2082 r = r100_packet3_check(p, &pkt); 2083 break; 2084 default: 2085 DRM_ERROR("Unknown packet type %d !\n", 2086 pkt.type); 2087 return -EINVAL; 2088 } 2089 if (r) 2090 return r; 2091 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 2092 return 0; 2093 } 2094 2095 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2096 { 2097 DRM_ERROR("pitch %d\n", t->pitch); 2098 DRM_ERROR("use_pitch %d\n", t->use_pitch); 2099 DRM_ERROR("width %d\n", t->width); 2100 DRM_ERROR("width_11 %d\n", t->width_11); 2101 DRM_ERROR("height %d\n", t->height); 2102 DRM_ERROR("height_11 %d\n", t->height_11); 2103 DRM_ERROR("num levels %d\n", t->num_levels); 2104 DRM_ERROR("depth %d\n", t->txdepth); 2105 DRM_ERROR("bpp %d\n", t->cpp); 2106 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2107 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2108 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2109 DRM_ERROR("compress format %d\n", t->compress_format); 2110 } 2111 2112 static int r100_track_compress_size(int compress_format, int w, int h) 2113 { 2114 int block_width, block_height, block_bytes; 2115 int wblocks, hblocks; 2116 int min_wblocks; 2117 int sz; 2118 2119 block_width = 4; 2120 block_height = 4; 2121 2122 switch (compress_format) { 2123 case R100_TRACK_COMP_DXT1: 2124 block_bytes = 8; 2125 min_wblocks = 4; 2126 break; 2127 default: 2128 case R100_TRACK_COMP_DXT35: 2129 block_bytes = 16; 2130 min_wblocks = 2; 2131 break; 2132 } 2133 2134 hblocks = (h + block_height - 1) / block_height; 2135 wblocks = (w + block_width - 1) / block_width; 2136 if (wblocks < min_wblocks) 2137 wblocks = min_wblocks; 2138 sz = wblocks * hblocks * block_bytes; 2139 return sz; 2140 } 2141 2142 static int r100_cs_track_cube(struct radeon_device *rdev, 2143 struct r100_cs_track *track, unsigned idx) 2144 { 2145 unsigned face, w, h; 2146 struct radeon_bo *cube_robj; 2147 unsigned long size; 2148 unsigned compress_format = track->textures[idx].compress_format; 2149 2150 for (face = 0; face < 5; face++) { 2151 cube_robj = track->textures[idx].cube_info[face].robj; 2152 w = track->textures[idx].cube_info[face].width; 2153 h = track->textures[idx].cube_info[face].height; 2154 2155 if (compress_format) { 2156 size = r100_track_compress_size(compress_format, w, h); 2157 } else 2158 size = w * h; 2159 size *= track->textures[idx].cpp; 2160 2161 size += track->textures[idx].cube_info[face].offset; 2162 2163 if (size > radeon_bo_size(cube_robj)) { 2164 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 2165 size, radeon_bo_size(cube_robj)); 2166 r100_cs_track_texture_print(&track->textures[idx]); 2167 return -1; 2168 } 2169 } 2170 return 0; 2171 } 2172 2173 static int r100_cs_track_texture_check(struct radeon_device *rdev, 2174 struct r100_cs_track *track) 2175 { 2176 struct radeon_bo *robj; 2177 unsigned long size; 2178 unsigned u, i, w, h, d; 2179 int ret; 2180 2181 for (u = 0; u < track->num_texture; u++) { 2182 if (!track->textures[u].enabled) 2183 continue; 2184 if (track->textures[u].lookup_disable) 2185 continue; 2186 robj = track->textures[u].robj; 2187 if (robj == NULL) { 2188 DRM_ERROR("No texture bound to unit %u\n", u); 2189 return -EINVAL; 2190 } 2191 size = 0; 2192 for (i = 0; i <= track->textures[u].num_levels; i++) { 2193 if (track->textures[u].use_pitch) { 2194 if (rdev->family < CHIP_R300) 2195 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 2196 else 2197 w = track->textures[u].pitch / (1 << i); 2198 } else { 2199 w = track->textures[u].width; 2200 if (rdev->family >= CHIP_RV515) 2201 w |= track->textures[u].width_11; 2202 w = w / (1 << i); 2203 if (track->textures[u].roundup_w) 2204 w = roundup_pow_of_two(w); 2205 } 2206 h = track->textures[u].height; 2207 if (rdev->family >= CHIP_RV515) 2208 h |= track->textures[u].height_11; 2209 h = h / (1 << i); 2210 if (track->textures[u].roundup_h) 2211 h = roundup_pow_of_two(h); 2212 if (track->textures[u].tex_coord_type == 1) { 2213 d = (1 << track->textures[u].txdepth) / (1 << i); 2214 if (!d) 2215 d = 1; 2216 } else { 2217 d = 1; 2218 } 2219 if (track->textures[u].compress_format) { 2220 2221 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 2222 /* compressed textures are block based */ 2223 } else 2224 size += w * h * d; 2225 } 2226 size *= track->textures[u].cpp; 2227 2228 switch (track->textures[u].tex_coord_type) { 2229 case 0: 2230 case 1: 2231 break; 2232 case 2: 2233 if (track->separate_cube) { 2234 ret = r100_cs_track_cube(rdev, track, u); 2235 if (ret) 2236 return ret; 2237 } else 2238 size *= 6; 2239 break; 2240 default: 2241 DRM_ERROR("Invalid texture coordinate type %u for unit " 2242 "%u\n", track->textures[u].tex_coord_type, u); 2243 return -EINVAL; 2244 } 2245 if (size > radeon_bo_size(robj)) { 2246 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 2247 "%lu\n", u, size, radeon_bo_size(robj)); 2248 r100_cs_track_texture_print(&track->textures[u]); 2249 return -EINVAL; 2250 } 2251 } 2252 return 0; 2253 } 2254 2255 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 2256 { 2257 unsigned i; 2258 unsigned long size; 2259 unsigned prim_walk; 2260 unsigned nverts; 2261 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 2262 2263 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 2264 !track->blend_read_enable) 2265 num_cb = 0; 2266 2267 for (i = 0; i < num_cb; i++) { 2268 if (track->cb[i].robj == NULL) { 2269 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2270 return -EINVAL; 2271 } 2272 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2273 size += track->cb[i].offset; 2274 if (size > radeon_bo_size(track->cb[i].robj)) { 2275 DRM_ERROR("[drm] Buffer too small for color buffer %d " 2276 "(need %lu have %lu) !\n", i, size, 2277 radeon_bo_size(track->cb[i].robj)); 2278 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 2279 i, track->cb[i].pitch, track->cb[i].cpp, 2280 track->cb[i].offset, track->maxy); 2281 return -EINVAL; 2282 } 2283 } 2284 track->cb_dirty = false; 2285 2286 if (track->zb_dirty && track->z_enabled) { 2287 if (track->zb.robj == NULL) { 2288 DRM_ERROR("[drm] No buffer for z buffer !\n"); 2289 return -EINVAL; 2290 } 2291 size = track->zb.pitch * track->zb.cpp * track->maxy; 2292 size += track->zb.offset; 2293 if (size > radeon_bo_size(track->zb.robj)) { 2294 DRM_ERROR("[drm] Buffer too small for z buffer " 2295 "(need %lu have %lu) !\n", size, 2296 radeon_bo_size(track->zb.robj)); 2297 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 2298 track->zb.pitch, track->zb.cpp, 2299 track->zb.offset, track->maxy); 2300 return -EINVAL; 2301 } 2302 } 2303 track->zb_dirty = false; 2304 2305 if (track->aa_dirty && track->aaresolve) { 2306 if (track->aa.robj == NULL) { 2307 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 2308 return -EINVAL; 2309 } 2310 /* I believe the format comes from colorbuffer0. */ 2311 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 2312 size += track->aa.offset; 2313 if (size > radeon_bo_size(track->aa.robj)) { 2314 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 2315 "(need %lu have %lu) !\n", i, size, 2316 radeon_bo_size(track->aa.robj)); 2317 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 2318 i, track->aa.pitch, track->cb[0].cpp, 2319 track->aa.offset, track->maxy); 2320 return -EINVAL; 2321 } 2322 } 2323 track->aa_dirty = false; 2324 2325 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 2326 if (track->vap_vf_cntl & (1 << 14)) { 2327 nverts = track->vap_alt_nverts; 2328 } else { 2329 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 2330 } 2331 switch (prim_walk) { 2332 case 1: 2333 for (i = 0; i < track->num_arrays; i++) { 2334 size = track->arrays[i].esize * track->max_indx * 4; 2335 if (track->arrays[i].robj == NULL) { 2336 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2337 "bound\n", prim_walk, i); 2338 return -EINVAL; 2339 } 2340 if (size > radeon_bo_size(track->arrays[i].robj)) { 2341 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2342 "need %lu dwords have %lu dwords\n", 2343 prim_walk, i, size >> 2, 2344 radeon_bo_size(track->arrays[i].robj) 2345 >> 2); 2346 DRM_ERROR("Max indices %u\n", track->max_indx); 2347 return -EINVAL; 2348 } 2349 } 2350 break; 2351 case 2: 2352 for (i = 0; i < track->num_arrays; i++) { 2353 size = track->arrays[i].esize * (nverts - 1) * 4; 2354 if (track->arrays[i].robj == NULL) { 2355 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2356 "bound\n", prim_walk, i); 2357 return -EINVAL; 2358 } 2359 if (size > radeon_bo_size(track->arrays[i].robj)) { 2360 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2361 "need %lu dwords have %lu dwords\n", 2362 prim_walk, i, size >> 2, 2363 radeon_bo_size(track->arrays[i].robj) 2364 >> 2); 2365 return -EINVAL; 2366 } 2367 } 2368 break; 2369 case 3: 2370 size = track->vtx_size * nverts; 2371 if (size != track->immd_dwords) { 2372 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 2373 track->immd_dwords, size); 2374 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2375 nverts, track->vtx_size); 2376 return -EINVAL; 2377 } 2378 break; 2379 default: 2380 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2381 prim_walk); 2382 return -EINVAL; 2383 } 2384 2385 if (track->tex_dirty) { 2386 track->tex_dirty = false; 2387 return r100_cs_track_texture_check(rdev, track); 2388 } 2389 return 0; 2390 } 2391 2392 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 2393 { 2394 unsigned i, face; 2395 2396 track->cb_dirty = true; 2397 track->zb_dirty = true; 2398 track->tex_dirty = true; 2399 track->aa_dirty = true; 2400 2401 if (rdev->family < CHIP_R300) { 2402 track->num_cb = 1; 2403 if (rdev->family <= CHIP_RS200) 2404 track->num_texture = 3; 2405 else 2406 track->num_texture = 6; 2407 track->maxy = 2048; 2408 track->separate_cube = 1; 2409 } else { 2410 track->num_cb = 4; 2411 track->num_texture = 16; 2412 track->maxy = 4096; 2413 track->separate_cube = 0; 2414 track->aaresolve = false; 2415 track->aa.robj = NULL; 2416 } 2417 2418 for (i = 0; i < track->num_cb; i++) { 2419 track->cb[i].robj = NULL; 2420 track->cb[i].pitch = 8192; 2421 track->cb[i].cpp = 16; 2422 track->cb[i].offset = 0; 2423 } 2424 track->z_enabled = true; 2425 track->zb.robj = NULL; 2426 track->zb.pitch = 8192; 2427 track->zb.cpp = 4; 2428 track->zb.offset = 0; 2429 track->vtx_size = 0x7F; 2430 track->immd_dwords = 0xFFFFFFFFUL; 2431 track->num_arrays = 11; 2432 track->max_indx = 0x00FFFFFFUL; 2433 for (i = 0; i < track->num_arrays; i++) { 2434 track->arrays[i].robj = NULL; 2435 track->arrays[i].esize = 0x7F; 2436 } 2437 for (i = 0; i < track->num_texture; i++) { 2438 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 2439 track->textures[i].pitch = 16536; 2440 track->textures[i].width = 16536; 2441 track->textures[i].height = 16536; 2442 track->textures[i].width_11 = 1 << 11; 2443 track->textures[i].height_11 = 1 << 11; 2444 track->textures[i].num_levels = 12; 2445 if (rdev->family <= CHIP_RS200) { 2446 track->textures[i].tex_coord_type = 0; 2447 track->textures[i].txdepth = 0; 2448 } else { 2449 track->textures[i].txdepth = 16; 2450 track->textures[i].tex_coord_type = 1; 2451 } 2452 track->textures[i].cpp = 64; 2453 track->textures[i].robj = NULL; 2454 /* CS IB emission code makes sure texture unit are disabled */ 2455 track->textures[i].enabled = false; 2456 track->textures[i].lookup_disable = false; 2457 track->textures[i].roundup_w = true; 2458 track->textures[i].roundup_h = true; 2459 if (track->separate_cube) 2460 for (face = 0; face < 5; face++) { 2461 track->textures[i].cube_info[face].robj = NULL; 2462 track->textures[i].cube_info[face].width = 16536; 2463 track->textures[i].cube_info[face].height = 16536; 2464 track->textures[i].cube_info[face].offset = 0; 2465 } 2466 } 2467 } 2468 2469 /* 2470 * Global GPU functions 2471 */ 2472 static void r100_errata(struct radeon_device *rdev) 2473 { 2474 rdev->pll_errata = 0; 2475 2476 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2477 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2478 } 2479 2480 if (rdev->family == CHIP_RV100 || 2481 rdev->family == CHIP_RS100 || 2482 rdev->family == CHIP_RS200) { 2483 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2484 } 2485 } 2486 2487 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2488 { 2489 unsigned i; 2490 uint32_t tmp; 2491 2492 for (i = 0; i < rdev->usec_timeout; i++) { 2493 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2494 if (tmp >= n) { 2495 return 0; 2496 } 2497 DRM_UDELAY(1); 2498 } 2499 return -1; 2500 } 2501 2502 int r100_gui_wait_for_idle(struct radeon_device *rdev) 2503 { 2504 unsigned i; 2505 uint32_t tmp; 2506 2507 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 2508 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" 2509 " Bad things might happen.\n"); 2510 } 2511 for (i = 0; i < rdev->usec_timeout; i++) { 2512 tmp = RREG32(RADEON_RBBM_STATUS); 2513 if (!(tmp & RADEON_RBBM_ACTIVE)) { 2514 return 0; 2515 } 2516 DRM_UDELAY(1); 2517 } 2518 return -1; 2519 } 2520 2521 int r100_mc_wait_for_idle(struct radeon_device *rdev) 2522 { 2523 unsigned i; 2524 uint32_t tmp; 2525 2526 for (i = 0; i < rdev->usec_timeout; i++) { 2527 /* read MC_STATUS */ 2528 tmp = RREG32(RADEON_MC_STATUS); 2529 if (tmp & RADEON_MC_IDLE) { 2530 return 0; 2531 } 2532 DRM_UDELAY(1); 2533 } 2534 return -1; 2535 } 2536 2537 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2538 { 2539 u32 rbbm_status; 2540 2541 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2542 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2543 radeon_ring_lockup_update(rdev, ring); 2544 return false; 2545 } 2546 return radeon_ring_test_lockup(rdev, ring); 2547 } 2548 2549 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 2550 void r100_enable_bm(struct radeon_device *rdev) 2551 { 2552 uint32_t tmp; 2553 /* Enable bus mastering */ 2554 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 2555 WREG32(RADEON_BUS_CNTL, tmp); 2556 } 2557 2558 void r100_bm_disable(struct radeon_device *rdev) 2559 { 2560 u32 tmp; 2561 2562 /* disable bus mastering */ 2563 tmp = RREG32(R_000030_BUS_CNTL); 2564 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2565 mdelay(1); 2566 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2567 mdelay(1); 2568 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2569 tmp = RREG32(RADEON_BUS_CNTL); 2570 mdelay(1); 2571 pci_disable_busmaster(rdev->dev->bsddev); 2572 mdelay(1); 2573 } 2574 2575 int r100_asic_reset(struct radeon_device *rdev, bool hard) 2576 { 2577 struct r100_mc_save save; 2578 u32 status, tmp; 2579 int ret = 0; 2580 2581 status = RREG32(R_000E40_RBBM_STATUS); 2582 if (!G_000E40_GUI_ACTIVE(status)) { 2583 return 0; 2584 } 2585 r100_mc_stop(rdev, &save); 2586 status = RREG32(R_000E40_RBBM_STATUS); 2587 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2588 /* stop CP */ 2589 WREG32(RADEON_CP_CSQ_CNTL, 0); 2590 tmp = RREG32(RADEON_CP_RB_CNTL); 2591 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2592 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2593 WREG32(RADEON_CP_RB_WPTR, 0); 2594 WREG32(RADEON_CP_RB_CNTL, tmp); 2595 /* save PCI state */ 2596 pci_save_state(device_get_parent(rdev->dev->bsddev)); 2597 /* disable bus mastering */ 2598 r100_bm_disable(rdev); 2599 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2600 S_0000F0_SOFT_RESET_RE(1) | 2601 S_0000F0_SOFT_RESET_PP(1) | 2602 S_0000F0_SOFT_RESET_RB(1)); 2603 RREG32(R_0000F0_RBBM_SOFT_RESET); 2604 mdelay(500); 2605 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2606 mdelay(1); 2607 status = RREG32(R_000E40_RBBM_STATUS); 2608 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2609 /* reset CP */ 2610 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2611 RREG32(R_0000F0_RBBM_SOFT_RESET); 2612 mdelay(500); 2613 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2614 mdelay(1); 2615 status = RREG32(R_000E40_RBBM_STATUS); 2616 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2617 /* restore PCI & busmastering */ 2618 pci_restore_state(device_get_parent(rdev->dev->bsddev)); 2619 r100_enable_bm(rdev); 2620 /* Check if GPU is idle */ 2621 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2622 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2623 dev_err(rdev->dev, "failed to reset GPU\n"); 2624 ret = -1; 2625 } else 2626 dev_info(rdev->dev, "GPU reset succeed\n"); 2627 r100_mc_resume(rdev, &save); 2628 return ret; 2629 } 2630 2631 void r100_set_common_regs(struct radeon_device *rdev) 2632 { 2633 struct drm_device *dev = rdev->ddev; 2634 bool force_dac2 = false; 2635 u32 tmp; 2636 2637 /* set these so they don't interfere with anything */ 2638 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2639 WREG32(RADEON_SUBPIC_CNTL, 0); 2640 WREG32(RADEON_VIPH_CONTROL, 0); 2641 WREG32(RADEON_I2C_CNTL_1, 0); 2642 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2643 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2644 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2645 2646 /* always set up dac2 on rn50 and some rv100 as lots 2647 * of servers seem to wire it up to a VGA port but 2648 * don't report it in the bios connector 2649 * table. 2650 */ 2651 switch (dev->pdev->device) { 2652 /* RN50 */ 2653 case 0x515e: 2654 case 0x5969: 2655 force_dac2 = true; 2656 break; 2657 /* RV100*/ 2658 case 0x5159: 2659 case 0x515a: 2660 /* DELL triple head servers */ 2661 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2662 ((dev->pdev->subsystem_device == 0x016c) || 2663 (dev->pdev->subsystem_device == 0x016d) || 2664 (dev->pdev->subsystem_device == 0x016e) || 2665 (dev->pdev->subsystem_device == 0x016f) || 2666 (dev->pdev->subsystem_device == 0x0170) || 2667 (dev->pdev->subsystem_device == 0x017d) || 2668 (dev->pdev->subsystem_device == 0x017e) || 2669 (dev->pdev->subsystem_device == 0x0183) || 2670 (dev->pdev->subsystem_device == 0x018a) || 2671 (dev->pdev->subsystem_device == 0x019a))) 2672 force_dac2 = true; 2673 break; 2674 } 2675 2676 if (force_dac2) { 2677 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2678 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2679 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2680 2681 /* For CRT on DAC2, don't turn it on if BIOS didn't 2682 enable it, even it's detected. 2683 */ 2684 2685 /* force it to crtc0 */ 2686 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2687 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2688 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2689 2690 /* set up the TV DAC */ 2691 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2692 RADEON_TV_DAC_STD_MASK | 2693 RADEON_TV_DAC_RDACPD | 2694 RADEON_TV_DAC_GDACPD | 2695 RADEON_TV_DAC_BDACPD | 2696 RADEON_TV_DAC_BGADJ_MASK | 2697 RADEON_TV_DAC_DACADJ_MASK); 2698 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2699 RADEON_TV_DAC_NHOLD | 2700 RADEON_TV_DAC_STD_PS2 | 2701 (0x58 << 16)); 2702 2703 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2704 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2705 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2706 } 2707 2708 /* switch PM block to ACPI mode */ 2709 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2710 tmp &= ~RADEON_PM_MODE_SEL; 2711 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2712 2713 } 2714 2715 /* 2716 * VRAM info 2717 */ 2718 static void r100_vram_get_type(struct radeon_device *rdev) 2719 { 2720 uint32_t tmp; 2721 2722 rdev->mc.vram_is_ddr = false; 2723 if (rdev->flags & RADEON_IS_IGP) 2724 rdev->mc.vram_is_ddr = true; 2725 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2726 rdev->mc.vram_is_ddr = true; 2727 if ((rdev->family == CHIP_RV100) || 2728 (rdev->family == CHIP_RS100) || 2729 (rdev->family == CHIP_RS200)) { 2730 tmp = RREG32(RADEON_MEM_CNTL); 2731 if (tmp & RV100_HALF_MODE) { 2732 rdev->mc.vram_width = 32; 2733 } else { 2734 rdev->mc.vram_width = 64; 2735 } 2736 if (rdev->flags & RADEON_SINGLE_CRTC) { 2737 rdev->mc.vram_width /= 4; 2738 rdev->mc.vram_is_ddr = true; 2739 } 2740 } else if (rdev->family <= CHIP_RV280) { 2741 tmp = RREG32(RADEON_MEM_CNTL); 2742 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2743 rdev->mc.vram_width = 128; 2744 } else { 2745 rdev->mc.vram_width = 64; 2746 } 2747 } else { 2748 /* newer IGPs */ 2749 rdev->mc.vram_width = 128; 2750 } 2751 } 2752 2753 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2754 { 2755 u32 aper_size; 2756 u8 byte; 2757 2758 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2759 2760 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2761 * that is has the 2nd generation multifunction PCI interface 2762 */ 2763 if (rdev->family == CHIP_RV280 || 2764 rdev->family >= CHIP_RV350) { 2765 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2766 ~RADEON_HDP_APER_CNTL); 2767 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2768 return aper_size * 2; 2769 } 2770 2771 /* Older cards have all sorts of funny issues to deal with. First 2772 * check if it's a multifunction card by reading the PCI config 2773 * header type... Limit those to one aperture size 2774 */ 2775 byte = pci_read_config(rdev->dev->bsddev, 0xe, 1); 2776 if (byte & 0x80) { 2777 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2778 DRM_INFO("Limiting VRAM to one aperture\n"); 2779 return aper_size; 2780 } 2781 2782 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2783 * have set it up. We don't write this as it's broken on some ASICs but 2784 * we expect the BIOS to have done the right thing (might be too optimistic...) 2785 */ 2786 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2787 return aper_size * 2; 2788 return aper_size; 2789 } 2790 2791 void r100_vram_init_sizes(struct radeon_device *rdev) 2792 { 2793 u64 config_aper_size; 2794 2795 /* work out accessible VRAM */ 2796 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2797 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2798 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2799 /* FIXME we don't use the second aperture yet when we could use it */ 2800 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2801 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2802 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2803 if (rdev->flags & RADEON_IS_IGP) { 2804 uint32_t tom; 2805 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2806 tom = RREG32(RADEON_NB_TOM); 2807 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2808 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2809 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2810 } else { 2811 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2812 /* Some production boards of m6 will report 0 2813 * if it's 8 MB 2814 */ 2815 if (rdev->mc.real_vram_size == 0) { 2816 rdev->mc.real_vram_size = 8192 * 1024; 2817 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2818 } 2819 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2820 * Novell bug 204882 + along with lots of ubuntu ones 2821 */ 2822 if (rdev->mc.aper_size > config_aper_size) 2823 config_aper_size = rdev->mc.aper_size; 2824 2825 if (config_aper_size > rdev->mc.real_vram_size) 2826 rdev->mc.mc_vram_size = config_aper_size; 2827 else 2828 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2829 } 2830 } 2831 2832 void r100_vga_set_state(struct radeon_device *rdev, bool state) 2833 { 2834 uint32_t temp; 2835 2836 temp = RREG32(RADEON_CONFIG_CNTL); 2837 if (state == false) { 2838 temp &= ~RADEON_CFG_VGA_RAM_EN; 2839 temp |= RADEON_CFG_VGA_IO_DIS; 2840 } else { 2841 temp &= ~RADEON_CFG_VGA_IO_DIS; 2842 } 2843 WREG32(RADEON_CONFIG_CNTL, temp); 2844 } 2845 2846 static void r100_mc_init(struct radeon_device *rdev) 2847 { 2848 u64 base; 2849 2850 r100_vram_get_type(rdev); 2851 r100_vram_init_sizes(rdev); 2852 base = rdev->mc.aper_base; 2853 if (rdev->flags & RADEON_IS_IGP) 2854 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2855 radeon_vram_location(rdev, &rdev->mc, base); 2856 rdev->mc.gtt_base_align = 0; 2857 if (!(rdev->flags & RADEON_IS_AGP)) 2858 radeon_gtt_location(rdev, &rdev->mc); 2859 radeon_update_bandwidth_info(rdev); 2860 } 2861 2862 2863 /* 2864 * Indirect registers accessor 2865 */ 2866 void r100_pll_errata_after_index(struct radeon_device *rdev) 2867 { 2868 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2869 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2870 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2871 } 2872 } 2873 2874 static void r100_pll_errata_after_data(struct radeon_device *rdev) 2875 { 2876 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2877 * or the chip could hang on a subsequent access 2878 */ 2879 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2880 mdelay(5); 2881 } 2882 2883 /* This function is required to workaround a hardware bug in some (all?) 2884 * revisions of the R300. This workaround should be called after every 2885 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2886 * may not be correct. 2887 */ 2888 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2889 uint32_t save, tmp; 2890 2891 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2892 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2893 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2894 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2895 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2896 } 2897 } 2898 2899 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2900 { 2901 unsigned long flags; 2902 uint32_t data; 2903 2904 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2905 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2906 r100_pll_errata_after_index(rdev); 2907 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2908 r100_pll_errata_after_data(rdev); 2909 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2910 return data; 2911 } 2912 2913 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2914 { 2915 unsigned long flags; 2916 2917 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2918 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2919 r100_pll_errata_after_index(rdev); 2920 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2921 r100_pll_errata_after_data(rdev); 2922 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2923 } 2924 2925 static void r100_set_safe_registers(struct radeon_device *rdev) 2926 { 2927 if (ASIC_IS_RN50(rdev)) { 2928 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2929 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2930 } else if (rdev->family < CHIP_R200) { 2931 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2932 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2933 } else { 2934 r200_set_safe_registers(rdev); 2935 } 2936 } 2937 2938 /* 2939 * Debugfs info 2940 */ 2941 #if defined(CONFIG_DEBUG_FS) 2942 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2943 { 2944 struct drm_info_node *node = (struct drm_info_node *) m->private; 2945 struct drm_device *dev = node->minor->dev; 2946 struct radeon_device *rdev = dev->dev_private; 2947 uint32_t reg, value; 2948 unsigned i; 2949 2950 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2951 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2952 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2953 for (i = 0; i < 64; i++) { 2954 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2955 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2956 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2957 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2958 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2959 } 2960 return 0; 2961 } 2962 2963 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2964 { 2965 struct drm_info_node *node = (struct drm_info_node *) m->private; 2966 struct drm_device *dev = node->minor->dev; 2967 struct radeon_device *rdev = dev->dev_private; 2968 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2969 uint32_t rdp, wdp; 2970 unsigned count, i, j; 2971 2972 radeon_ring_free_size(rdev, ring); 2973 rdp = RREG32(RADEON_CP_RB_RPTR); 2974 wdp = RREG32(RADEON_CP_RB_WPTR); 2975 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 2976 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2977 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2978 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2979 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 2980 seq_printf(m, "%u dwords in ring\n", count); 2981 if (ring->ready) { 2982 for (j = 0; j <= count; j++) { 2983 i = (rdp + j) & ring->ptr_mask; 2984 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 2985 } 2986 } 2987 return 0; 2988 } 2989 2990 2991 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2992 { 2993 struct drm_info_node *node = (struct drm_info_node *) m->private; 2994 struct drm_device *dev = node->minor->dev; 2995 struct radeon_device *rdev = dev->dev_private; 2996 uint32_t csq_stat, csq2_stat, tmp; 2997 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2998 unsigned i; 2999 3000 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 3001 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 3002 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 3003 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 3004 r_rptr = (csq_stat >> 0) & 0x3ff; 3005 r_wptr = (csq_stat >> 10) & 0x3ff; 3006 ib1_rptr = (csq_stat >> 20) & 0x3ff; 3007 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 3008 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 3009 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 3010 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 3011 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 3012 seq_printf(m, "Ring rptr %u\n", r_rptr); 3013 seq_printf(m, "Ring wptr %u\n", r_wptr); 3014 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 3015 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 3016 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 3017 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 3018 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 3019 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 3020 seq_printf(m, "Ring fifo:\n"); 3021 for (i = 0; i < 256; i++) { 3022 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3023 tmp = RREG32(RADEON_CP_CSQ_DATA); 3024 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 3025 } 3026 seq_printf(m, "Indirect1 fifo:\n"); 3027 for (i = 256; i <= 512; i++) { 3028 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3029 tmp = RREG32(RADEON_CP_CSQ_DATA); 3030 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 3031 } 3032 seq_printf(m, "Indirect2 fifo:\n"); 3033 for (i = 640; i < ib1_wptr; i++) { 3034 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3035 tmp = RREG32(RADEON_CP_CSQ_DATA); 3036 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 3037 } 3038 return 0; 3039 } 3040 3041 static int r100_debugfs_mc_info(struct seq_file *m, void *data) 3042 { 3043 struct drm_info_node *node = (struct drm_info_node *) m->private; 3044 struct drm_device *dev = node->minor->dev; 3045 struct radeon_device *rdev = dev->dev_private; 3046 uint32_t tmp; 3047 3048 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 3049 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 3050 tmp = RREG32(RADEON_MC_FB_LOCATION); 3051 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 3052 tmp = RREG32(RADEON_BUS_CNTL); 3053 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 3054 tmp = RREG32(RADEON_MC_AGP_LOCATION); 3055 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 3056 tmp = RREG32(RADEON_AGP_BASE); 3057 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 3058 tmp = RREG32(RADEON_HOST_PATH_CNTL); 3059 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 3060 tmp = RREG32(0x01D0); 3061 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 3062 tmp = RREG32(RADEON_AIC_LO_ADDR); 3063 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 3064 tmp = RREG32(RADEON_AIC_HI_ADDR); 3065 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 3066 tmp = RREG32(0x01E4); 3067 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 3068 return 0; 3069 } 3070 3071 static struct drm_info_list r100_debugfs_rbbm_list[] = { 3072 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 3073 }; 3074 3075 static struct drm_info_list r100_debugfs_cp_list[] = { 3076 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 3077 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 3078 }; 3079 3080 static struct drm_info_list r100_debugfs_mc_info_list[] = { 3081 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 3082 }; 3083 #endif 3084 3085 int r100_debugfs_rbbm_init(struct radeon_device *rdev) 3086 { 3087 #if defined(CONFIG_DEBUG_FS) 3088 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 3089 #else 3090 return 0; 3091 #endif 3092 } 3093 3094 int r100_debugfs_cp_init(struct radeon_device *rdev) 3095 { 3096 #if defined(CONFIG_DEBUG_FS) 3097 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 3098 #else 3099 return 0; 3100 #endif 3101 } 3102 3103 int r100_debugfs_mc_info_init(struct radeon_device *rdev) 3104 { 3105 #if defined(CONFIG_DEBUG_FS) 3106 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 3107 #else 3108 return 0; 3109 #endif 3110 } 3111 3112 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 3113 uint32_t tiling_flags, uint32_t pitch, 3114 uint32_t offset, uint32_t obj_size) 3115 { 3116 int surf_index = reg * 16; 3117 int flags = 0; 3118 3119 if (rdev->family <= CHIP_RS200) { 3120 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3121 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3122 flags |= RADEON_SURF_TILE_COLOR_BOTH; 3123 if (tiling_flags & RADEON_TILING_MACRO) 3124 flags |= RADEON_SURF_TILE_COLOR_MACRO; 3125 /* setting pitch to 0 disables tiling */ 3126 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3127 == 0) 3128 pitch = 0; 3129 } else if (rdev->family <= CHIP_RV280) { 3130 if (tiling_flags & (RADEON_TILING_MACRO)) 3131 flags |= R200_SURF_TILE_COLOR_MACRO; 3132 if (tiling_flags & RADEON_TILING_MICRO) 3133 flags |= R200_SURF_TILE_COLOR_MICRO; 3134 } else { 3135 if (tiling_flags & RADEON_TILING_MACRO) 3136 flags |= R300_SURF_TILE_MACRO; 3137 if (tiling_flags & RADEON_TILING_MICRO) 3138 flags |= R300_SURF_TILE_MICRO; 3139 } 3140 3141 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 3142 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 3143 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 3144 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 3145 3146 /* r100/r200 divide by 16 */ 3147 if (rdev->family < CHIP_R300) 3148 flags |= pitch / 16; 3149 else 3150 flags |= pitch / 8; 3151 3152 3153 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 3154 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 3155 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 3156 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 3157 return 0; 3158 } 3159 3160 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 3161 { 3162 int surf_index = reg * 16; 3163 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 3164 } 3165 3166 void r100_bandwidth_update(struct radeon_device *rdev) 3167 { 3168 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 3169 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 3170 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; 3171 fixed20_12 crit_point_ff = {0}; 3172 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 3173 fixed20_12 memtcas_ff[8] = { 3174 dfixed_init(1), 3175 dfixed_init(2), 3176 dfixed_init(3), 3177 dfixed_init(0), 3178 dfixed_init_half(1), 3179 dfixed_init_half(2), 3180 dfixed_init(0), 3181 }; 3182 fixed20_12 memtcas_rs480_ff[8] = { 3183 dfixed_init(0), 3184 dfixed_init(1), 3185 dfixed_init(2), 3186 dfixed_init(3), 3187 dfixed_init(0), 3188 dfixed_init_half(1), 3189 dfixed_init_half(2), 3190 dfixed_init_half(3), 3191 }; 3192 fixed20_12 memtcas2_ff[8] = { 3193 dfixed_init(0), 3194 dfixed_init(1), 3195 dfixed_init(2), 3196 dfixed_init(3), 3197 dfixed_init(4), 3198 dfixed_init(5), 3199 dfixed_init(6), 3200 dfixed_init(7), 3201 }; 3202 fixed20_12 memtrbs[8] = { 3203 dfixed_init(1), 3204 dfixed_init_half(1), 3205 dfixed_init(2), 3206 dfixed_init_half(2), 3207 dfixed_init(3), 3208 dfixed_init_half(3), 3209 dfixed_init(4), 3210 dfixed_init_half(4) 3211 }; 3212 fixed20_12 memtrbs_r4xx[8] = { 3213 dfixed_init(4), 3214 dfixed_init(5), 3215 dfixed_init(6), 3216 dfixed_init(7), 3217 dfixed_init(8), 3218 dfixed_init(9), 3219 dfixed_init(10), 3220 dfixed_init(11) 3221 }; 3222 fixed20_12 min_mem_eff; 3223 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 3224 fixed20_12 cur_latency_mclk, cur_latency_sclk; 3225 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0}, 3226 disp_drain_rate2, read_return_rate; 3227 fixed20_12 time_disp1_drop_priority; 3228 int c; 3229 int cur_size = 16; /* in octawords */ 3230 int critical_point = 0, critical_point2; 3231 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 3232 int stop_req, max_stop_req; 3233 struct drm_display_mode *mode1 = NULL; 3234 struct drm_display_mode *mode2 = NULL; 3235 uint32_t pixel_bytes1 = 0; 3236 uint32_t pixel_bytes2 = 0; 3237 3238 /* Guess line buffer size to be 8192 pixels */ 3239 u32 lb_size = 8192; 3240 3241 if (!rdev->mode_info.mode_config_initialized) 3242 return; 3243 3244 radeon_update_display_priority(rdev); 3245 3246 if (rdev->mode_info.crtcs[0]->base.enabled) { 3247 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 3248 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8; 3249 } 3250 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3251 if (rdev->mode_info.crtcs[1]->base.enabled) { 3252 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 3253 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8; 3254 } 3255 } 3256 3257 min_mem_eff.full = dfixed_const_8(0); 3258 /* get modes */ 3259 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 3260 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 3261 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 3262 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 3263 /* check crtc enables */ 3264 if (mode2) 3265 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 3266 if (mode1) 3267 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 3268 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 3269 } 3270 3271 /* 3272 * determine is there is enough bw for current mode 3273 */ 3274 sclk_ff = rdev->pm.sclk; 3275 mclk_ff = rdev->pm.mclk; 3276 3277 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 3278 temp_ff.full = dfixed_const(temp); 3279 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 3280 3281 pix_clk.full = 0; 3282 pix_clk2.full = 0; 3283 peak_disp_bw.full = 0; 3284 if (mode1) { 3285 temp_ff.full = dfixed_const(1000); 3286 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 3287 pix_clk.full = dfixed_div(pix_clk, temp_ff); 3288 temp_ff.full = dfixed_const(pixel_bytes1); 3289 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 3290 } 3291 if (mode2) { 3292 temp_ff.full = dfixed_const(1000); 3293 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 3294 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 3295 temp_ff.full = dfixed_const(pixel_bytes2); 3296 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 3297 } 3298 3299 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 3300 if (peak_disp_bw.full >= mem_bw.full) { 3301 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 3302 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 3303 } 3304 3305 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 3306 temp = RREG32(RADEON_MEM_TIMING_CNTL); 3307 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 3308 mem_trcd = ((temp >> 2) & 0x3) + 1; 3309 mem_trp = ((temp & 0x3)) + 1; 3310 mem_tras = ((temp & 0x70) >> 4) + 1; 3311 } else if (rdev->family == CHIP_R300 || 3312 rdev->family == CHIP_R350) { /* r300, r350 */ 3313 mem_trcd = (temp & 0x7) + 1; 3314 mem_trp = ((temp >> 8) & 0x7) + 1; 3315 mem_tras = ((temp >> 11) & 0xf) + 4; 3316 } else if (rdev->family == CHIP_RV350 || 3317 rdev->family <= CHIP_RV380) { 3318 /* rv3x0 */ 3319 mem_trcd = (temp & 0x7) + 3; 3320 mem_trp = ((temp >> 8) & 0x7) + 3; 3321 mem_tras = ((temp >> 11) & 0xf) + 6; 3322 } else if (rdev->family == CHIP_R420 || 3323 rdev->family == CHIP_R423 || 3324 rdev->family == CHIP_RV410) { 3325 /* r4xx */ 3326 mem_trcd = (temp & 0xf) + 3; 3327 if (mem_trcd > 15) 3328 mem_trcd = 15; 3329 mem_trp = ((temp >> 8) & 0xf) + 3; 3330 if (mem_trp > 15) 3331 mem_trp = 15; 3332 mem_tras = ((temp >> 12) & 0x1f) + 6; 3333 if (mem_tras > 31) 3334 mem_tras = 31; 3335 } else { /* RV200, R200 */ 3336 mem_trcd = (temp & 0x7) + 1; 3337 mem_trp = ((temp >> 8) & 0x7) + 1; 3338 mem_tras = ((temp >> 12) & 0xf) + 4; 3339 } 3340 /* convert to FF */ 3341 trcd_ff.full = dfixed_const(mem_trcd); 3342 trp_ff.full = dfixed_const(mem_trp); 3343 tras_ff.full = dfixed_const(mem_tras); 3344 3345 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 3346 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3347 data = (temp & (7 << 20)) >> 20; 3348 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 3349 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 3350 tcas_ff = memtcas_rs480_ff[data]; 3351 else 3352 tcas_ff = memtcas_ff[data]; 3353 } else 3354 tcas_ff = memtcas2_ff[data]; 3355 3356 if (rdev->family == CHIP_RS400 || 3357 rdev->family == CHIP_RS480) { 3358 /* extra cas latency stored in bits 23-25 0-4 clocks */ 3359 data = (temp >> 23) & 0x7; 3360 if (data < 5) 3361 tcas_ff.full += dfixed_const(data); 3362 } 3363 3364 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 3365 /* on the R300, Tcas is included in Trbs. 3366 */ 3367 temp = RREG32(RADEON_MEM_CNTL); 3368 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 3369 if (data == 1) { 3370 if (R300_MEM_USE_CD_CH_ONLY & temp) { 3371 temp = RREG32(R300_MC_IND_INDEX); 3372 temp &= ~R300_MC_IND_ADDR_MASK; 3373 temp |= R300_MC_READ_CNTL_CD_mcind; 3374 WREG32(R300_MC_IND_INDEX, temp); 3375 temp = RREG32(R300_MC_IND_DATA); 3376 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 3377 } else { 3378 temp = RREG32(R300_MC_READ_CNTL_AB); 3379 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3380 } 3381 } else { 3382 temp = RREG32(R300_MC_READ_CNTL_AB); 3383 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3384 } 3385 if (rdev->family == CHIP_RV410 || 3386 rdev->family == CHIP_R420 || 3387 rdev->family == CHIP_R423) 3388 trbs_ff = memtrbs_r4xx[data]; 3389 else 3390 trbs_ff = memtrbs[data]; 3391 tcas_ff.full += trbs_ff.full; 3392 } 3393 3394 sclk_eff_ff.full = sclk_ff.full; 3395 3396 if (rdev->flags & RADEON_IS_AGP) { 3397 fixed20_12 agpmode_ff; 3398 agpmode_ff.full = dfixed_const(radeon_agpmode); 3399 temp_ff.full = dfixed_const_666(16); 3400 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3401 } 3402 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3403 3404 if (ASIC_IS_R300(rdev)) { 3405 sclk_delay_ff.full = dfixed_const(250); 3406 } else { 3407 if ((rdev->family == CHIP_RV100) || 3408 rdev->flags & RADEON_IS_IGP) { 3409 if (rdev->mc.vram_is_ddr) 3410 sclk_delay_ff.full = dfixed_const(41); 3411 else 3412 sclk_delay_ff.full = dfixed_const(33); 3413 } else { 3414 if (rdev->mc.vram_width == 128) 3415 sclk_delay_ff.full = dfixed_const(57); 3416 else 3417 sclk_delay_ff.full = dfixed_const(41); 3418 } 3419 } 3420 3421 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3422 3423 if (rdev->mc.vram_is_ddr) { 3424 if (rdev->mc.vram_width == 32) { 3425 k1.full = dfixed_const(40); 3426 c = 3; 3427 } else { 3428 k1.full = dfixed_const(20); 3429 c = 1; 3430 } 3431 } else { 3432 k1.full = dfixed_const(40); 3433 c = 3; 3434 } 3435 3436 temp_ff.full = dfixed_const(2); 3437 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 3438 temp_ff.full = dfixed_const(c); 3439 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 3440 temp_ff.full = dfixed_const(4); 3441 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 3442 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3443 mc_latency_mclk.full += k1.full; 3444 3445 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 3446 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3447 3448 /* 3449 HW cursor time assuming worst case of full size colour cursor. 3450 */ 3451 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3452 temp_ff.full += trcd_ff.full; 3453 if (temp_ff.full < tras_ff.full) 3454 temp_ff.full = tras_ff.full; 3455 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3456 3457 temp_ff.full = dfixed_const(cur_size); 3458 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3459 /* 3460 Find the total latency for the display data. 3461 */ 3462 disp_latency_overhead.full = dfixed_const(8); 3463 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3464 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3465 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3466 3467 if (mc_latency_mclk.full > mc_latency_sclk.full) 3468 disp_latency.full = mc_latency_mclk.full; 3469 else 3470 disp_latency.full = mc_latency_sclk.full; 3471 3472 /* setup Max GRPH_STOP_REQ default value */ 3473 if (ASIC_IS_RV100(rdev)) 3474 max_stop_req = 0x5c; 3475 else 3476 max_stop_req = 0x7c; 3477 3478 if (mode1) { 3479 /* CRTC1 3480 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3481 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3482 */ 3483 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3484 3485 if (stop_req > max_stop_req) 3486 stop_req = max_stop_req; 3487 3488 /* 3489 Find the drain rate of the display buffer. 3490 */ 3491 temp_ff.full = dfixed_const((16/pixel_bytes1)); 3492 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3493 3494 /* 3495 Find the critical point of the display buffer. 3496 */ 3497 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 3498 crit_point_ff.full += dfixed_const_half(0); 3499 3500 critical_point = dfixed_trunc(crit_point_ff); 3501 3502 if (rdev->disp_priority == 2) { 3503 critical_point = 0; 3504 } 3505 3506 /* 3507 The critical point should never be above max_stop_req-4. Setting 3508 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3509 */ 3510 if (max_stop_req - critical_point < 4) 3511 critical_point = 0; 3512 3513 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3514 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3515 critical_point = 0x10; 3516 } 3517 3518 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3519 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3520 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3521 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3522 if ((rdev->family == CHIP_R350) && 3523 (stop_req > 0x15)) { 3524 stop_req -= 0x10; 3525 } 3526 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3527 temp |= RADEON_GRPH_BUFFER_SIZE; 3528 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3529 RADEON_GRPH_CRITICAL_AT_SOF | 3530 RADEON_GRPH_STOP_CNTL); 3531 /* 3532 Write the result into the register. 3533 */ 3534 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3535 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3536 3537 #if 0 3538 if ((rdev->family == CHIP_RS400) || 3539 (rdev->family == CHIP_RS480)) { 3540 /* attempt to program RS400 disp regs correctly ??? */ 3541 temp = RREG32(RS400_DISP1_REG_CNTL); 3542 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3543 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3544 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3545 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3546 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3547 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3548 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3549 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3550 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3551 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3552 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3553 } 3554 #endif 3555 3556 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3557 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3558 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3559 } 3560 3561 if (mode2) { 3562 u32 grph2_cntl; 3563 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3564 3565 if (stop_req > max_stop_req) 3566 stop_req = max_stop_req; 3567 3568 /* 3569 Find the drain rate of the display buffer. 3570 */ 3571 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3572 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3573 3574 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3575 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3576 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3577 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3578 if ((rdev->family == CHIP_R350) && 3579 (stop_req > 0x15)) { 3580 stop_req -= 0x10; 3581 } 3582 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3583 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3584 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3585 RADEON_GRPH_CRITICAL_AT_SOF | 3586 RADEON_GRPH_STOP_CNTL); 3587 3588 if ((rdev->family == CHIP_RS100) || 3589 (rdev->family == CHIP_RS200)) 3590 critical_point2 = 0; 3591 else { 3592 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3593 temp_ff.full = dfixed_const(temp); 3594 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3595 if (sclk_ff.full < temp_ff.full) 3596 temp_ff.full = sclk_ff.full; 3597 3598 read_return_rate.full = temp_ff.full; 3599 3600 if (mode1) { 3601 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3602 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3603 } else { 3604 time_disp1_drop_priority.full = 0; 3605 } 3606 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3607 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3608 crit_point_ff.full += dfixed_const_half(0); 3609 3610 critical_point2 = dfixed_trunc(crit_point_ff); 3611 3612 if (rdev->disp_priority == 2) { 3613 critical_point2 = 0; 3614 } 3615 3616 if (max_stop_req - critical_point2 < 4) 3617 critical_point2 = 0; 3618 3619 } 3620 3621 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3622 /* some R300 cards have problem with this set to 0 */ 3623 critical_point2 = 0x10; 3624 } 3625 3626 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3627 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3628 3629 if ((rdev->family == CHIP_RS400) || 3630 (rdev->family == CHIP_RS480)) { 3631 #if 0 3632 /* attempt to program RS400 disp2 regs correctly ??? */ 3633 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3634 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3635 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3636 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3637 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3638 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3639 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3640 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3641 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3642 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3643 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3644 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3645 #endif 3646 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3647 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3648 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3649 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3650 } 3651 3652 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3653 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3654 } 3655 3656 /* Save number of lines the linebuffer leads before the scanout */ 3657 if (mode1) 3658 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 3659 3660 if (mode2) 3661 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 3662 } 3663 3664 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 3665 { 3666 uint32_t scratch; 3667 uint32_t tmp = 0; 3668 unsigned i; 3669 int r; 3670 3671 r = radeon_scratch_get(rdev, &scratch); 3672 if (r) { 3673 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3674 return r; 3675 } 3676 WREG32(scratch, 0xCAFEDEAD); 3677 r = radeon_ring_lock(rdev, ring, 2); 3678 if (r) { 3679 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3680 radeon_scratch_free(rdev, scratch); 3681 return r; 3682 } 3683 radeon_ring_write(ring, PACKET0(scratch, 0)); 3684 radeon_ring_write(ring, 0xDEADBEEF); 3685 radeon_ring_unlock_commit(rdev, ring, false); 3686 for (i = 0; i < rdev->usec_timeout; i++) { 3687 tmp = RREG32(scratch); 3688 if (tmp == 0xDEADBEEF) { 3689 break; 3690 } 3691 DRM_UDELAY(1); 3692 } 3693 if (i < rdev->usec_timeout) { 3694 DRM_INFO("ring test succeeded in %d usecs\n", i); 3695 } else { 3696 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3697 scratch, tmp); 3698 r = -EINVAL; 3699 } 3700 radeon_scratch_free(rdev, scratch); 3701 return r; 3702 } 3703 3704 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3705 { 3706 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3707 3708 if (ring->rptr_save_reg) { 3709 u32 next_rptr = ring->wptr + 2 + 3; 3710 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); 3711 radeon_ring_write(ring, next_rptr); 3712 } 3713 3714 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3715 radeon_ring_write(ring, ib->gpu_addr); 3716 radeon_ring_write(ring, ib->length_dw); 3717 } 3718 3719 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3720 { 3721 struct radeon_ib ib; 3722 uint32_t scratch; 3723 uint32_t tmp = 0; 3724 unsigned i; 3725 int r; 3726 3727 r = radeon_scratch_get(rdev, &scratch); 3728 if (r) { 3729 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3730 return r; 3731 } 3732 WREG32(scratch, 0xCAFEDEAD); 3733 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); 3734 if (r) { 3735 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3736 goto free_scratch; 3737 } 3738 ib.ptr[0] = PACKET0(scratch, 0); 3739 ib.ptr[1] = 0xDEADBEEF; 3740 ib.ptr[2] = PACKET2(0); 3741 ib.ptr[3] = PACKET2(0); 3742 ib.ptr[4] = PACKET2(0); 3743 ib.ptr[5] = PACKET2(0); 3744 ib.ptr[6] = PACKET2(0); 3745 ib.ptr[7] = PACKET2(0); 3746 ib.length_dw = 8; 3747 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3748 if (r) { 3749 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3750 goto free_ib; 3751 } 3752 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies( 3753 RADEON_USEC_IB_TEST_TIMEOUT)); 3754 if (r < 0) { 3755 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3756 goto free_ib; 3757 } else if (r == 0) { 3758 DRM_ERROR("radeon: fence wait timed out.\n"); 3759 #if 0 3760 r = -ETIMEDOUT; 3761 goto free_ib; 3762 #endif 3763 } 3764 r = 0; 3765 for (i = 0; i < rdev->usec_timeout; i++) { 3766 tmp = RREG32(scratch); 3767 if (tmp == 0xDEADBEEF) { 3768 break; 3769 } 3770 DRM_UDELAY(1); 3771 } 3772 if (i < rdev->usec_timeout) { 3773 DRM_INFO("ib test succeeded in %u usecs\n", i); 3774 } else { 3775 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3776 scratch, tmp); 3777 r = -EINVAL; 3778 } 3779 free_ib: 3780 radeon_ib_free(rdev, &ib); 3781 free_scratch: 3782 radeon_scratch_free(rdev, scratch); 3783 return r; 3784 } 3785 3786 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3787 { 3788 /* Shutdown CP we shouldn't need to do that but better be safe than 3789 * sorry 3790 */ 3791 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3792 WREG32(R_000740_CP_CSQ_CNTL, 0); 3793 3794 /* Save few CRTC registers */ 3795 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3796 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3797 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3798 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3799 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3800 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3801 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3802 } 3803 3804 /* Disable VGA aperture access */ 3805 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3806 /* Disable cursor, overlay, crtc */ 3807 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3808 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3809 S_000054_CRTC_DISPLAY_DIS(1)); 3810 WREG32(R_000050_CRTC_GEN_CNTL, 3811 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3812 S_000050_CRTC_DISP_REQ_EN_B(1)); 3813 WREG32(R_000420_OV0_SCALE_CNTL, 3814 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3815 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3816 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3817 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3818 S_000360_CUR2_LOCK(1)); 3819 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3820 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3821 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3822 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3823 WREG32(R_000360_CUR2_OFFSET, 3824 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3825 } 3826 } 3827 3828 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3829 { 3830 /* Update base address for crtc */ 3831 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3832 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3833 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3834 } 3835 /* Restore CRTC registers */ 3836 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3837 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3838 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3839 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3840 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3841 } 3842 } 3843 3844 void r100_vga_render_disable(struct radeon_device *rdev) 3845 { 3846 u32 tmp; 3847 3848 tmp = RREG8(R_0003C2_GENMO_WT); 3849 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3850 } 3851 3852 static void r100_debugfs(struct radeon_device *rdev) 3853 { 3854 int r; 3855 3856 r = r100_debugfs_mc_info_init(rdev); 3857 if (r) 3858 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3859 } 3860 3861 static void r100_mc_program(struct radeon_device *rdev) 3862 { 3863 struct r100_mc_save save; 3864 3865 /* Stops all mc clients */ 3866 r100_mc_stop(rdev, &save); 3867 if (rdev->flags & RADEON_IS_AGP) { 3868 WREG32(R_00014C_MC_AGP_LOCATION, 3869 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3870 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3871 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3872 if (rdev->family > CHIP_RV200) 3873 WREG32(R_00015C_AGP_BASE_2, 3874 upper_32_bits(rdev->mc.agp_base) & 0xff); 3875 } else { 3876 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3877 WREG32(R_000170_AGP_BASE, 0); 3878 if (rdev->family > CHIP_RV200) 3879 WREG32(R_00015C_AGP_BASE_2, 0); 3880 } 3881 /* Wait for mc idle */ 3882 if (r100_mc_wait_for_idle(rdev)) 3883 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3884 /* Program MC, should be a 32bits limited address space */ 3885 WREG32(R_000148_MC_FB_LOCATION, 3886 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3887 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3888 r100_mc_resume(rdev, &save); 3889 } 3890 3891 static void r100_clock_startup(struct radeon_device *rdev) 3892 { 3893 u32 tmp; 3894 3895 if (radeon_dynclks != -1 && radeon_dynclks) 3896 radeon_legacy_set_clock_gating(rdev, 1); 3897 /* We need to force on some of the block */ 3898 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3899 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3900 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3901 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3902 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3903 } 3904 3905 static int r100_startup(struct radeon_device *rdev) 3906 { 3907 int r; 3908 3909 /* set common regs */ 3910 r100_set_common_regs(rdev); 3911 /* program mc */ 3912 r100_mc_program(rdev); 3913 /* Resume clock */ 3914 r100_clock_startup(rdev); 3915 /* Initialize GART (initialize after TTM so we can allocate 3916 * memory through TTM but finalize after TTM) */ 3917 r100_enable_bm(rdev); 3918 if (rdev->flags & RADEON_IS_PCI) { 3919 r = r100_pci_gart_enable(rdev); 3920 if (r) 3921 return r; 3922 } 3923 3924 /* allocate wb buffer */ 3925 r = radeon_wb_init(rdev); 3926 if (r) 3927 return r; 3928 3929 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3930 if (r) { 3931 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3932 return r; 3933 } 3934 3935 /* Enable IRQ */ 3936 if (!rdev->irq.installed) { 3937 r = radeon_irq_kms_init(rdev); 3938 if (r) 3939 return r; 3940 } 3941 3942 r100_irq_set(rdev); 3943 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3944 /* 1M ring buffer */ 3945 r = r100_cp_init(rdev, 1024 * 1024); 3946 if (r) { 3947 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3948 return r; 3949 } 3950 3951 r = radeon_ib_pool_init(rdev); 3952 if (r) { 3953 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3954 return r; 3955 } 3956 3957 return 0; 3958 } 3959 3960 int r100_resume(struct radeon_device *rdev) 3961 { 3962 int r; 3963 3964 /* Make sur GART are not working */ 3965 if (rdev->flags & RADEON_IS_PCI) 3966 r100_pci_gart_disable(rdev); 3967 /* Resume clock before doing reset */ 3968 r100_clock_startup(rdev); 3969 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3970 if (radeon_asic_reset(rdev)) { 3971 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3972 RREG32(R_000E40_RBBM_STATUS), 3973 RREG32(R_0007C0_CP_STAT)); 3974 } 3975 /* post */ 3976 radeon_combios_asic_init(rdev->ddev); 3977 /* Resume clock after posting */ 3978 r100_clock_startup(rdev); 3979 /* Initialize surface registers */ 3980 radeon_surface_init(rdev); 3981 3982 rdev->accel_working = true; 3983 r = r100_startup(rdev); 3984 if (r) { 3985 rdev->accel_working = false; 3986 } 3987 return r; 3988 } 3989 3990 int r100_suspend(struct radeon_device *rdev) 3991 { 3992 radeon_pm_suspend(rdev); 3993 r100_cp_disable(rdev); 3994 radeon_wb_disable(rdev); 3995 r100_irq_disable(rdev); 3996 if (rdev->flags & RADEON_IS_PCI) 3997 r100_pci_gart_disable(rdev); 3998 return 0; 3999 } 4000 4001 void r100_fini(struct radeon_device *rdev) 4002 { 4003 radeon_pm_fini(rdev); 4004 r100_cp_fini(rdev); 4005 radeon_wb_fini(rdev); 4006 radeon_ib_pool_fini(rdev); 4007 radeon_gem_fini(rdev); 4008 if (rdev->flags & RADEON_IS_PCI) 4009 r100_pci_gart_fini(rdev); 4010 radeon_agp_fini(rdev); 4011 radeon_irq_kms_fini(rdev); 4012 radeon_fence_driver_fini(rdev); 4013 radeon_bo_fini(rdev); 4014 radeon_atombios_fini(rdev); 4015 r100_cp_fini_microcode(rdev); 4016 kfree(rdev->bios); 4017 rdev->bios = NULL; 4018 } 4019 4020 /* 4021 * Due to how kexec works, it can leave the hw fully initialised when it 4022 * boots the new kernel. However doing our init sequence with the CP and 4023 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 4024 * do some quick sanity checks and restore sane values to avoid this 4025 * problem. 4026 */ 4027 void r100_restore_sanity(struct radeon_device *rdev) 4028 { 4029 u32 tmp; 4030 4031 tmp = RREG32(RADEON_CP_CSQ_CNTL); 4032 if (tmp) { 4033 WREG32(RADEON_CP_CSQ_CNTL, 0); 4034 } 4035 tmp = RREG32(RADEON_CP_RB_CNTL); 4036 if (tmp) { 4037 WREG32(RADEON_CP_RB_CNTL, 0); 4038 } 4039 tmp = RREG32(RADEON_SCRATCH_UMSK); 4040 if (tmp) { 4041 WREG32(RADEON_SCRATCH_UMSK, 0); 4042 } 4043 } 4044 4045 int r100_init(struct radeon_device *rdev) 4046 { 4047 int r; 4048 4049 /* Register debugfs file specific to this group of asics */ 4050 r100_debugfs(rdev); 4051 /* Disable VGA */ 4052 r100_vga_render_disable(rdev); 4053 /* Initialize scratch registers */ 4054 radeon_scratch_init(rdev); 4055 /* Initialize surface registers */ 4056 radeon_surface_init(rdev); 4057 /* sanity check some register to avoid hangs like after kexec */ 4058 r100_restore_sanity(rdev); 4059 /* TODO: disable VGA need to use VGA request */ 4060 /* BIOS*/ 4061 if (!radeon_get_bios(rdev)) { 4062 if (ASIC_IS_AVIVO(rdev)) 4063 return -EINVAL; 4064 } 4065 if (rdev->is_atom_bios) { 4066 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 4067 return -EINVAL; 4068 } else { 4069 r = radeon_combios_init(rdev); 4070 if (r) 4071 return r; 4072 } 4073 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4074 if (radeon_asic_reset(rdev)) { 4075 dev_warn(rdev->dev, 4076 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4077 RREG32(R_000E40_RBBM_STATUS), 4078 RREG32(R_0007C0_CP_STAT)); 4079 } 4080 /* check if cards are posted or not */ 4081 if (radeon_boot_test_post_card(rdev) == false) 4082 return -EINVAL; 4083 /* Set asic errata */ 4084 r100_errata(rdev); 4085 /* Initialize clocks */ 4086 radeon_get_clock_info(rdev->ddev); 4087 /* initialize AGP */ 4088 if (rdev->flags & RADEON_IS_AGP) { 4089 r = radeon_agp_init(rdev); 4090 if (r) { 4091 radeon_agp_disable(rdev); 4092 } 4093 } 4094 /* initialize VRAM */ 4095 r100_mc_init(rdev); 4096 /* Fence driver */ 4097 r = radeon_fence_driver_init(rdev); 4098 if (r) 4099 return r; 4100 /* Memory manager */ 4101 r = radeon_bo_init(rdev); 4102 if (r) 4103 return r; 4104 if (rdev->flags & RADEON_IS_PCI) { 4105 r = r100_pci_gart_init(rdev); 4106 if (r) 4107 return r; 4108 } 4109 r100_set_safe_registers(rdev); 4110 4111 /* Initialize power management */ 4112 radeon_pm_init(rdev); 4113 4114 rdev->accel_working = true; 4115 r = r100_startup(rdev); 4116 if (r) { 4117 /* Somethings want wront with the accel init stop accel */ 4118 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4119 r100_cp_fini(rdev); 4120 radeon_wb_fini(rdev); 4121 radeon_ib_pool_fini(rdev); 4122 radeon_irq_kms_fini(rdev); 4123 if (rdev->flags & RADEON_IS_PCI) 4124 r100_pci_gart_fini(rdev); 4125 rdev->accel_working = false; 4126 } 4127 return 0; 4128 } 4129 4130 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 4131 bool always_indirect) 4132 { 4133 unsigned long flags; 4134 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 4135 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 4136 return bus_read_4(rdev->rmmio, reg); 4137 else { 4138 uint32_t ret; 4139 4140 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4141 bus_write_4(rdev->rmmio, RADEON_MM_INDEX, reg); 4142 ret = bus_read_4(rdev->rmmio, RADEON_MM_DATA); 4143 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4144 4145 return ret; 4146 } 4147 } 4148 4149 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 4150 bool always_indirect) 4151 { 4152 unsigned long flags; 4153 4154 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 4155 bus_write_4(rdev->rmmio, reg, v); 4156 else { 4157 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4158 bus_write_4(rdev->rmmio, RADEON_MM_INDEX, reg); 4159 bus_write_4(rdev->rmmio, RADEON_MM_DATA, v); 4160 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4161 } 4162 } 4163 4164 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 4165 { 4166 if (reg < rdev->rio_mem_size) 4167 return bus_read_4(rdev->rio_mem, reg); 4168 else { 4169 /* XXX No locking? -- dumbbell@ */ 4170 bus_write_4(rdev->rio_mem, RADEON_MM_INDEX, reg); 4171 return bus_read_4(rdev->rio_mem, RADEON_MM_DATA); 4172 } 4173 } 4174 4175 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 4176 { 4177 if (reg < rdev->rio_mem_size) 4178 bus_write_4(rdev->rio_mem, reg, v); 4179 else { 4180 /* XXX No locking? -- dumbbell@ */ 4181 bus_write_4(rdev->rio_mem, RADEON_MM_INDEX, reg); 4182 bus_write_4(rdev->rio_mem, RADEON_MM_DATA, v); 4183 } 4184 } 4185