1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/r100.c 255573 2013-09-14 17:24:41Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include <uapi_drm/radeon_drm.h> 33 #include "radeon_reg.h" 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "r100d.h" 37 #include "rs100d.h" 38 #include "rv200d.h" 39 #include "rv250d.h" 40 #include "atom.h" 41 42 #include "r100_reg_safe.h" 43 #include "rn50_reg_safe.h" 44 45 /* Firmware Names */ 46 #define FIRMWARE_R100 "radeonkmsfw_R100_cp" 47 #define FIRMWARE_R200 "radeonkmsfw_R200_cp" 48 #define FIRMWARE_R300 "radeonkmsfw_R300_cp" 49 #define FIRMWARE_R420 "radeonkmsfw_R420_cp" 50 #define FIRMWARE_RS690 "radeonkmsfw_RS690_cp" 51 #define FIRMWARE_RS600 "radeonkmsfw_RS600_cp" 52 #define FIRMWARE_R520 "radeonkmsfw_R520_cp" 53 54 #include "r100_track.h" 55 56 /* This files gather functions specifics to: 57 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 58 * and others in some cases. 59 */ 60 61 /** 62 * r100_wait_for_vblank - vblank wait asic callback. 63 * 64 * @rdev: radeon_device pointer 65 * @crtc: crtc to wait for vblank on 66 * 67 * Wait for vblank on the requested crtc (r1xx-r4xx). 68 */ 69 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 70 { 71 int i; 72 73 if (crtc >= rdev->num_crtc) 74 return; 75 76 if (crtc == 0) { 77 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) { 78 for (i = 0; i < rdev->usec_timeout; i++) { 79 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)) 80 break; 81 DRM_UDELAY(1); 82 } 83 for (i = 0; i < rdev->usec_timeout; i++) { 84 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) 85 break; 86 DRM_UDELAY(1); 87 } 88 } 89 } else { 90 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) { 91 for (i = 0; i < rdev->usec_timeout; i++) { 92 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)) 93 break; 94 DRM_UDELAY(1); 95 } 96 for (i = 0; i < rdev->usec_timeout; i++) { 97 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 98 break; 99 DRM_UDELAY(1); 100 } 101 } 102 } 103 } 104 105 /** 106 * r100_pre_page_flip - pre-pageflip callback. 107 * 108 * @rdev: radeon_device pointer 109 * @crtc: crtc to prepare for pageflip on 110 * 111 * Pre-pageflip callback (r1xx-r4xx). 112 * Enables the pageflip irq (vblank irq). 113 */ 114 void r100_pre_page_flip(struct radeon_device *rdev, int crtc) 115 { 116 /* enable the pflip int */ 117 radeon_irq_kms_pflip_irq_get(rdev, crtc); 118 } 119 120 /** 121 * r100_post_page_flip - pos-pageflip callback. 122 * 123 * @rdev: radeon_device pointer 124 * @crtc: crtc to cleanup pageflip on 125 * 126 * Post-pageflip callback (r1xx-r4xx). 127 * Disables the pageflip irq (vblank irq). 128 */ 129 void r100_post_page_flip(struct radeon_device *rdev, int crtc) 130 { 131 /* disable the pflip int */ 132 radeon_irq_kms_pflip_irq_put(rdev, crtc); 133 } 134 135 /** 136 * r100_page_flip - pageflip callback. 137 * 138 * @rdev: radeon_device pointer 139 * @crtc_id: crtc to cleanup pageflip on 140 * @crtc_base: new address of the crtc (GPU MC address) 141 * 142 * Does the actual pageflip (r1xx-r4xx). 143 * During vblank we take the crtc lock and wait for the update_pending 144 * bit to go high, when it does, we release the lock, and allow the 145 * double buffered update to take place. 146 * Returns the current update pending status. 147 */ 148 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 149 { 150 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 151 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 152 int i; 153 154 /* Lock the graphics update lock */ 155 /* update the scanout addresses */ 156 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 157 158 /* Wait for update_pending to go high. */ 159 for (i = 0; i < rdev->usec_timeout; i++) { 160 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 161 break; 162 DRM_UDELAY(1); 163 } 164 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 165 166 /* Unlock the lock, so double-buffering can take place inside vblank */ 167 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 168 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 169 170 /* Return current update_pending status: */ 171 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; 172 } 173 174 /** 175 * r100_pm_get_dynpm_state - look up dynpm power state callback. 176 * 177 * @rdev: radeon_device pointer 178 * 179 * Look up the optimal power state based on the 180 * current state of the GPU (r1xx-r5xx). 181 * Used for dynpm only. 182 */ 183 void r100_pm_get_dynpm_state(struct radeon_device *rdev) 184 { 185 int i; 186 rdev->pm.dynpm_can_upclock = true; 187 rdev->pm.dynpm_can_downclock = true; 188 189 switch (rdev->pm.dynpm_planned_action) { 190 case DYNPM_ACTION_MINIMUM: 191 rdev->pm.requested_power_state_index = 0; 192 rdev->pm.dynpm_can_downclock = false; 193 break; 194 case DYNPM_ACTION_DOWNCLOCK: 195 if (rdev->pm.current_power_state_index == 0) { 196 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 197 rdev->pm.dynpm_can_downclock = false; 198 } else { 199 if (rdev->pm.active_crtc_count > 1) { 200 for (i = 0; i < rdev->pm.num_power_states; i++) { 201 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 202 continue; 203 else if (i >= rdev->pm.current_power_state_index) { 204 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 205 break; 206 } else { 207 rdev->pm.requested_power_state_index = i; 208 break; 209 } 210 } 211 } else 212 rdev->pm.requested_power_state_index = 213 rdev->pm.current_power_state_index - 1; 214 } 215 /* don't use the power state if crtcs are active and no display flag is set */ 216 if ((rdev->pm.active_crtc_count > 0) && 217 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 218 RADEON_PM_MODE_NO_DISPLAY)) { 219 rdev->pm.requested_power_state_index++; 220 } 221 break; 222 case DYNPM_ACTION_UPCLOCK: 223 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 224 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 225 rdev->pm.dynpm_can_upclock = false; 226 } else { 227 if (rdev->pm.active_crtc_count > 1) { 228 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 229 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 230 continue; 231 else if (i <= rdev->pm.current_power_state_index) { 232 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 233 break; 234 } else { 235 rdev->pm.requested_power_state_index = i; 236 break; 237 } 238 } 239 } else 240 rdev->pm.requested_power_state_index = 241 rdev->pm.current_power_state_index + 1; 242 } 243 break; 244 case DYNPM_ACTION_DEFAULT: 245 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 246 rdev->pm.dynpm_can_upclock = false; 247 break; 248 case DYNPM_ACTION_NONE: 249 default: 250 DRM_ERROR("Requested mode for not defined action\n"); 251 return; 252 } 253 /* only one clock mode per power state */ 254 rdev->pm.requested_clock_mode_index = 0; 255 256 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 257 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 258 clock_info[rdev->pm.requested_clock_mode_index].sclk, 259 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 260 clock_info[rdev->pm.requested_clock_mode_index].mclk, 261 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 262 pcie_lanes); 263 } 264 265 /** 266 * r100_pm_init_profile - Initialize power profiles callback. 267 * 268 * @rdev: radeon_device pointer 269 * 270 * Initialize the power states used in profile mode 271 * (r1xx-r3xx). 272 * Used for profile mode only. 273 */ 274 void r100_pm_init_profile(struct radeon_device *rdev) 275 { 276 /* default */ 277 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 278 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 279 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 280 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 281 /* low sh */ 282 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 283 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 284 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 285 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 286 /* mid sh */ 287 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 288 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 289 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 290 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 291 /* high sh */ 292 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 293 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 294 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 295 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 296 /* low mh */ 297 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 298 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 299 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 300 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 301 /* mid mh */ 302 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 303 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 304 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 305 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 306 /* high mh */ 307 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 308 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 309 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 310 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 311 } 312 313 /** 314 * r100_pm_misc - set additional pm hw parameters callback. 315 * 316 * @rdev: radeon_device pointer 317 * 318 * Set non-clock parameters associated with a power state 319 * (voltage, pcie lanes, etc.) (r1xx-r4xx). 320 */ 321 void r100_pm_misc(struct radeon_device *rdev) 322 { 323 int requested_index = rdev->pm.requested_power_state_index; 324 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 325 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 326 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 327 328 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 329 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 330 tmp = RREG32(voltage->gpio.reg); 331 if (voltage->active_high) 332 tmp |= voltage->gpio.mask; 333 else 334 tmp &= ~(voltage->gpio.mask); 335 WREG32(voltage->gpio.reg, tmp); 336 if (voltage->delay) 337 DRM_UDELAY(voltage->delay); 338 } else { 339 tmp = RREG32(voltage->gpio.reg); 340 if (voltage->active_high) 341 tmp &= ~voltage->gpio.mask; 342 else 343 tmp |= voltage->gpio.mask; 344 WREG32(voltage->gpio.reg, tmp); 345 if (voltage->delay) 346 DRM_UDELAY(voltage->delay); 347 } 348 } 349 350 sclk_cntl = RREG32_PLL(SCLK_CNTL); 351 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 352 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 353 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 354 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 355 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 356 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 357 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 358 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 359 else 360 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 361 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 362 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 363 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 364 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 365 } else 366 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 367 368 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 369 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 370 if (voltage->delay) { 371 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 372 switch (voltage->delay) { 373 case 33: 374 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 375 break; 376 case 66: 377 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 378 break; 379 case 99: 380 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 381 break; 382 case 132: 383 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 384 break; 385 } 386 } else 387 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 388 } else 389 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 390 391 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 392 sclk_cntl &= ~FORCE_HDP; 393 else 394 sclk_cntl |= FORCE_HDP; 395 396 WREG32_PLL(SCLK_CNTL, sclk_cntl); 397 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 398 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 399 400 /* set pcie lanes */ 401 if ((rdev->flags & RADEON_IS_PCIE) && 402 !(rdev->flags & RADEON_IS_IGP) && 403 rdev->asic->pm.set_pcie_lanes && 404 (ps->pcie_lanes != 405 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 406 radeon_set_pcie_lanes(rdev, 407 ps->pcie_lanes); 408 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 409 } 410 } 411 412 /** 413 * r100_pm_prepare - pre-power state change callback. 414 * 415 * @rdev: radeon_device pointer 416 * 417 * Prepare for a power state change (r1xx-r4xx). 418 */ 419 void r100_pm_prepare(struct radeon_device *rdev) 420 { 421 struct drm_device *ddev = rdev->ddev; 422 struct drm_crtc *crtc; 423 struct radeon_crtc *radeon_crtc; 424 u32 tmp; 425 426 /* disable any active CRTCs */ 427 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 428 radeon_crtc = to_radeon_crtc(crtc); 429 if (radeon_crtc->enabled) { 430 if (radeon_crtc->crtc_id) { 431 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 432 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 433 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 434 } else { 435 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 436 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 437 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 438 } 439 } 440 } 441 } 442 443 /** 444 * r100_pm_finish - post-power state change callback. 445 * 446 * @rdev: radeon_device pointer 447 * 448 * Clean up after a power state change (r1xx-r4xx). 449 */ 450 void r100_pm_finish(struct radeon_device *rdev) 451 { 452 struct drm_device *ddev = rdev->ddev; 453 struct drm_crtc *crtc; 454 struct radeon_crtc *radeon_crtc; 455 u32 tmp; 456 457 /* enable any active CRTCs */ 458 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 459 radeon_crtc = to_radeon_crtc(crtc); 460 if (radeon_crtc->enabled) { 461 if (radeon_crtc->crtc_id) { 462 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 463 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 464 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 465 } else { 466 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 467 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 468 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 469 } 470 } 471 } 472 } 473 474 /** 475 * r100_gui_idle - gui idle callback. 476 * 477 * @rdev: radeon_device pointer 478 * 479 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). 480 * Returns true if idle, false if not. 481 */ 482 bool r100_gui_idle(struct radeon_device *rdev) 483 { 484 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 485 return false; 486 else 487 return true; 488 } 489 490 /* hpd for digital panel detect/disconnect */ 491 /** 492 * r100_hpd_sense - hpd sense callback. 493 * 494 * @rdev: radeon_device pointer 495 * @hpd: hpd (hotplug detect) pin 496 * 497 * Checks if a digital monitor is connected (r1xx-r4xx). 498 * Returns true if connected, false if not connected. 499 */ 500 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 501 { 502 bool connected = false; 503 504 switch (hpd) { 505 case RADEON_HPD_1: 506 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 507 connected = true; 508 break; 509 case RADEON_HPD_2: 510 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 511 connected = true; 512 break; 513 default: 514 break; 515 } 516 return connected; 517 } 518 519 /** 520 * r100_hpd_set_polarity - hpd set polarity callback. 521 * 522 * @rdev: radeon_device pointer 523 * @hpd: hpd (hotplug detect) pin 524 * 525 * Set the polarity of the hpd pin (r1xx-r4xx). 526 */ 527 void r100_hpd_set_polarity(struct radeon_device *rdev, 528 enum radeon_hpd_id hpd) 529 { 530 u32 tmp; 531 bool connected = r100_hpd_sense(rdev, hpd); 532 533 switch (hpd) { 534 case RADEON_HPD_1: 535 tmp = RREG32(RADEON_FP_GEN_CNTL); 536 if (connected) 537 tmp &= ~RADEON_FP_DETECT_INT_POL; 538 else 539 tmp |= RADEON_FP_DETECT_INT_POL; 540 WREG32(RADEON_FP_GEN_CNTL, tmp); 541 break; 542 case RADEON_HPD_2: 543 tmp = RREG32(RADEON_FP2_GEN_CNTL); 544 if (connected) 545 tmp &= ~RADEON_FP2_DETECT_INT_POL; 546 else 547 tmp |= RADEON_FP2_DETECT_INT_POL; 548 WREG32(RADEON_FP2_GEN_CNTL, tmp); 549 break; 550 default: 551 break; 552 } 553 } 554 555 /** 556 * r100_hpd_init - hpd setup callback. 557 * 558 * @rdev: radeon_device pointer 559 * 560 * Setup the hpd pins used by the card (r1xx-r4xx). 561 * Set the polarity, and enable the hpd interrupts. 562 */ 563 void r100_hpd_init(struct radeon_device *rdev) 564 { 565 struct drm_device *dev = rdev->ddev; 566 struct drm_connector *connector; 567 unsigned enable = 0; 568 569 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 570 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 571 enable |= 1 << radeon_connector->hpd.hpd; 572 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 573 } 574 radeon_irq_kms_enable_hpd(rdev, enable); 575 } 576 577 /** 578 * r100_hpd_fini - hpd tear down callback. 579 * 580 * @rdev: radeon_device pointer 581 * 582 * Tear down the hpd pins used by the card (r1xx-r4xx). 583 * Disable the hpd interrupts. 584 */ 585 void r100_hpd_fini(struct radeon_device *rdev) 586 { 587 struct drm_device *dev = rdev->ddev; 588 struct drm_connector *connector; 589 unsigned disable = 0; 590 591 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 592 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 593 disable |= 1 << radeon_connector->hpd.hpd; 594 } 595 radeon_irq_kms_disable_hpd(rdev, disable); 596 } 597 598 /* 599 * PCI GART 600 */ 601 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 602 { 603 /* TODO: can we do somethings here ? */ 604 /* It seems hw only cache one entry so we should discard this 605 * entry otherwise if first GPU GART read hit this entry it 606 * could end up in wrong address. */ 607 } 608 609 int r100_pci_gart_init(struct radeon_device *rdev) 610 { 611 int r; 612 613 if (rdev->gart.ptr) { 614 DRM_ERROR("R100 PCI GART already initialized\n"); 615 return 0; 616 } 617 /* Initialize common gart structure */ 618 r = radeon_gart_init(rdev); 619 if (r) 620 return r; 621 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 622 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 623 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 624 return radeon_gart_table_ram_alloc(rdev); 625 } 626 627 int r100_pci_gart_enable(struct radeon_device *rdev) 628 { 629 uint32_t tmp; 630 631 radeon_gart_restore(rdev); 632 /* discard memory request outside of configured range */ 633 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 634 WREG32(RADEON_AIC_CNTL, tmp); 635 /* set address range for PCI address translate */ 636 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 637 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 638 /* set PCI GART page-table base address */ 639 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 640 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 641 WREG32(RADEON_AIC_CNTL, tmp); 642 r100_pci_gart_tlb_flush(rdev); 643 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", 644 (unsigned)(rdev->mc.gtt_size >> 20), 645 (unsigned long long)rdev->gart.table_addr); 646 rdev->gart.ready = true; 647 return 0; 648 } 649 650 void r100_pci_gart_disable(struct radeon_device *rdev) 651 { 652 uint32_t tmp; 653 654 /* discard memory request outside of configured range */ 655 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 656 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 657 WREG32(RADEON_AIC_LO_ADDR, 0); 658 WREG32(RADEON_AIC_HI_ADDR, 0); 659 } 660 661 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 662 { 663 u32 *gtt = rdev->gart.ptr; 664 665 if (i < 0 || i > rdev->gart.num_gpu_pages) { 666 return -EINVAL; 667 } 668 gtt[i] = cpu_to_le32(lower_32_bits(addr)); 669 return 0; 670 } 671 672 void r100_pci_gart_fini(struct radeon_device *rdev) 673 { 674 radeon_gart_fini(rdev); 675 r100_pci_gart_disable(rdev); 676 radeon_gart_table_ram_free(rdev); 677 } 678 679 int r100_irq_set(struct radeon_device *rdev) 680 { 681 uint32_t tmp = 0; 682 683 if (!rdev->irq.installed) { 684 DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n"); 685 WREG32(R_000040_GEN_INT_CNTL, 0); 686 return -EINVAL; 687 } 688 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 689 tmp |= RADEON_SW_INT_ENABLE; 690 } 691 if (rdev->irq.crtc_vblank_int[0] || 692 atomic_read(&rdev->irq.pflip[0])) { 693 tmp |= RADEON_CRTC_VBLANK_MASK; 694 } 695 if (rdev->irq.crtc_vblank_int[1] || 696 atomic_read(&rdev->irq.pflip[1])) { 697 tmp |= RADEON_CRTC2_VBLANK_MASK; 698 } 699 if (rdev->irq.hpd[0]) { 700 tmp |= RADEON_FP_DETECT_MASK; 701 } 702 if (rdev->irq.hpd[1]) { 703 tmp |= RADEON_FP2_DETECT_MASK; 704 } 705 WREG32(RADEON_GEN_INT_CNTL, tmp); 706 return 0; 707 } 708 709 void r100_irq_disable(struct radeon_device *rdev) 710 { 711 u32 tmp; 712 713 WREG32(R_000040_GEN_INT_CNTL, 0); 714 /* Wait and acknowledge irq */ 715 DRM_MDELAY(1); 716 tmp = RREG32(R_000044_GEN_INT_STATUS); 717 WREG32(R_000044_GEN_INT_STATUS, tmp); 718 } 719 720 static uint32_t r100_irq_ack(struct radeon_device *rdev) 721 { 722 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 723 uint32_t irq_mask = RADEON_SW_INT_TEST | 724 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 725 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 726 727 if (irqs) { 728 WREG32(RADEON_GEN_INT_STATUS, irqs); 729 } 730 return irqs & irq_mask; 731 } 732 733 irqreturn_t r100_irq_process(struct radeon_device *rdev) 734 { 735 uint32_t status, msi_rearm; 736 bool queue_hotplug = false; 737 738 status = r100_irq_ack(rdev); 739 if (!status) { 740 return IRQ_NONE; 741 } 742 if (rdev->shutdown) { 743 return IRQ_NONE; 744 } 745 while (status) { 746 /* SW interrupt */ 747 if (status & RADEON_SW_INT_TEST) { 748 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 749 } 750 /* Vertical blank interrupts */ 751 if (status & RADEON_CRTC_VBLANK_STAT) { 752 if (rdev->irq.crtc_vblank_int[0]) { 753 drm_handle_vblank(rdev->ddev, 0); 754 rdev->pm.vblank_sync = true; 755 DRM_WAKEUP(&rdev->irq.vblank_queue); 756 } 757 if (atomic_read(&rdev->irq.pflip[0])) 758 radeon_crtc_handle_flip(rdev, 0); 759 } 760 if (status & RADEON_CRTC2_VBLANK_STAT) { 761 if (rdev->irq.crtc_vblank_int[1]) { 762 drm_handle_vblank(rdev->ddev, 1); 763 rdev->pm.vblank_sync = true; 764 DRM_WAKEUP(&rdev->irq.vblank_queue); 765 } 766 if (atomic_read(&rdev->irq.pflip[1])) 767 radeon_crtc_handle_flip(rdev, 1); 768 } 769 if (status & RADEON_FP_DETECT_STAT) { 770 queue_hotplug = true; 771 DRM_DEBUG("HPD1\n"); 772 } 773 if (status & RADEON_FP2_DETECT_STAT) { 774 queue_hotplug = true; 775 DRM_DEBUG("HPD2\n"); 776 } 777 status = r100_irq_ack(rdev); 778 } 779 if (queue_hotplug) 780 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); 781 if (rdev->msi_enabled) { 782 switch (rdev->family) { 783 case CHIP_RS400: 784 case CHIP_RS480: 785 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 786 WREG32(RADEON_AIC_CNTL, msi_rearm); 787 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 788 break; 789 default: 790 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 791 break; 792 } 793 } 794 return IRQ_HANDLED; 795 } 796 797 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 798 { 799 if (crtc == 0) 800 return RREG32(RADEON_CRTC_CRNT_FRAME); 801 else 802 return RREG32(RADEON_CRTC2_CRNT_FRAME); 803 } 804 805 /* Who ever call radeon_fence_emit should call ring_lock and ask 806 * for enough space (today caller are ib schedule and buffer move) */ 807 void r100_fence_ring_emit(struct radeon_device *rdev, 808 struct radeon_fence *fence) 809 { 810 struct radeon_ring *ring = &rdev->ring[fence->ring]; 811 812 /* We have to make sure that caches are flushed before 813 * CPU might read something from VRAM. */ 814 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 815 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 816 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 817 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 818 /* Wait until IDLE & CLEAN */ 819 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 820 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 821 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 822 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 823 RADEON_HDP_READ_BUFFER_INVALIDATE); 824 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 825 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 826 /* Emit fence sequence & fire IRQ */ 827 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 828 radeon_ring_write(ring, fence->seq); 829 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 830 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 831 } 832 833 void r100_semaphore_ring_emit(struct radeon_device *rdev, 834 struct radeon_ring *ring, 835 struct radeon_semaphore *semaphore, 836 bool emit_wait) 837 { 838 /* Unused on older asics, since we don't have semaphores or multiple rings */ 839 panic("%s: Unused on older asics", __func__); 840 } 841 842 int r100_copy_blit(struct radeon_device *rdev, 843 uint64_t src_offset, 844 uint64_t dst_offset, 845 unsigned num_gpu_pages, 846 struct radeon_fence **fence) 847 { 848 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 849 uint32_t cur_pages; 850 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 851 uint32_t pitch; 852 uint32_t stride_pixels; 853 unsigned ndw; 854 int num_loops; 855 int r = 0; 856 857 /* radeon limited to 16k stride */ 858 stride_bytes &= 0x3fff; 859 /* radeon pitch is /64 */ 860 pitch = stride_bytes / 64; 861 stride_pixels = stride_bytes / 4; 862 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 863 864 /* Ask for enough room for blit + flush + fence */ 865 ndw = 64 + (10 * num_loops); 866 r = radeon_ring_lock(rdev, ring, ndw); 867 if (r) { 868 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 869 return -EINVAL; 870 } 871 while (num_gpu_pages > 0) { 872 cur_pages = num_gpu_pages; 873 if (cur_pages > 8191) { 874 cur_pages = 8191; 875 } 876 num_gpu_pages -= cur_pages; 877 878 /* pages are in Y direction - height 879 page width in X direction - width */ 880 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 881 radeon_ring_write(ring, 882 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 883 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 884 RADEON_GMC_SRC_CLIPPING | 885 RADEON_GMC_DST_CLIPPING | 886 RADEON_GMC_BRUSH_NONE | 887 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 888 RADEON_GMC_SRC_DATATYPE_COLOR | 889 RADEON_ROP3_S | 890 RADEON_DP_SRC_SOURCE_MEMORY | 891 RADEON_GMC_CLR_CMP_CNTL_DIS | 892 RADEON_GMC_WR_MSK_DIS); 893 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); 894 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); 895 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 896 radeon_ring_write(ring, 0); 897 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 898 radeon_ring_write(ring, num_gpu_pages); 899 radeon_ring_write(ring, num_gpu_pages); 900 radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 901 } 902 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 903 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 904 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 905 radeon_ring_write(ring, 906 RADEON_WAIT_2D_IDLECLEAN | 907 RADEON_WAIT_HOST_IDLECLEAN | 908 RADEON_WAIT_DMA_GUI_IDLE); 909 if (fence) { 910 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); 911 } 912 radeon_ring_unlock_commit(rdev, ring); 913 return r; 914 } 915 916 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 917 { 918 unsigned i; 919 u32 tmp; 920 921 for (i = 0; i < rdev->usec_timeout; i++) { 922 tmp = RREG32(R_000E40_RBBM_STATUS); 923 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 924 return 0; 925 } 926 DRM_UDELAY(1); 927 } 928 return -1; 929 } 930 931 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 932 { 933 int r; 934 935 r = radeon_ring_lock(rdev, ring, 2); 936 if (r) { 937 return; 938 } 939 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 940 radeon_ring_write(ring, 941 RADEON_ISYNC_ANY2D_IDLE3D | 942 RADEON_ISYNC_ANY3D_IDLE2D | 943 RADEON_ISYNC_WAIT_IDLEGUI | 944 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 945 radeon_ring_unlock_commit(rdev, ring); 946 } 947 948 949 /* Load the microcode for the CP */ 950 static int r100_cp_init_microcode(struct radeon_device *rdev) 951 { 952 const char *fw_name = NULL; 953 int err; 954 955 DRM_DEBUG_KMS("\n"); 956 957 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 958 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 959 (rdev->family == CHIP_RS200)) { 960 DRM_INFO("Loading R100 Microcode\n"); 961 fw_name = FIRMWARE_R100; 962 } else if ((rdev->family == CHIP_R200) || 963 (rdev->family == CHIP_RV250) || 964 (rdev->family == CHIP_RV280) || 965 (rdev->family == CHIP_RS300)) { 966 DRM_INFO("Loading R200 Microcode\n"); 967 fw_name = FIRMWARE_R200; 968 } else if ((rdev->family == CHIP_R300) || 969 (rdev->family == CHIP_R350) || 970 (rdev->family == CHIP_RV350) || 971 (rdev->family == CHIP_RV380) || 972 (rdev->family == CHIP_RS400) || 973 (rdev->family == CHIP_RS480)) { 974 DRM_INFO("Loading R300 Microcode\n"); 975 fw_name = FIRMWARE_R300; 976 } else if ((rdev->family == CHIP_R420) || 977 (rdev->family == CHIP_R423) || 978 (rdev->family == CHIP_RV410)) { 979 DRM_INFO("Loading R400 Microcode\n"); 980 fw_name = FIRMWARE_R420; 981 } else if ((rdev->family == CHIP_RS690) || 982 (rdev->family == CHIP_RS740)) { 983 DRM_INFO("Loading RS690/RS740 Microcode\n"); 984 fw_name = FIRMWARE_RS690; 985 } else if (rdev->family == CHIP_RS600) { 986 DRM_INFO("Loading RS600 Microcode\n"); 987 fw_name = FIRMWARE_RS600; 988 } else if ((rdev->family == CHIP_RV515) || 989 (rdev->family == CHIP_R520) || 990 (rdev->family == CHIP_RV530) || 991 (rdev->family == CHIP_R580) || 992 (rdev->family == CHIP_RV560) || 993 (rdev->family == CHIP_RV570)) { 994 DRM_INFO("Loading R500 Microcode\n"); 995 fw_name = FIRMWARE_R520; 996 } 997 998 err = 0; 999 rdev->me_fw = firmware_get(fw_name); 1000 if (rdev->me_fw == NULL) { 1001 DRM_ERROR("radeon_cp: Failed to load firmware \"%s\"\n", 1002 fw_name); 1003 err = -ENOENT; 1004 } else if (rdev->me_fw->datasize % 8) { 1005 DRM_ERROR( 1006 "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 1007 rdev->me_fw->datasize, fw_name); 1008 err = -EINVAL; 1009 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD); 1010 rdev->me_fw = NULL; 1011 } 1012 return err; 1013 } 1014 1015 /** 1016 * r100_cp_fini_microcode - drop the firmware image reference 1017 * 1018 * @rdev: radeon_device pointer 1019 * 1020 * Drop the me firmware image reference. 1021 * Called at driver shutdown. 1022 */ 1023 static void r100_cp_fini_microcode (struct radeon_device *rdev) 1024 { 1025 1026 if (rdev->me_fw != NULL) { 1027 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD); 1028 rdev->me_fw = NULL; 1029 } 1030 } 1031 1032 static void r100_cp_load_microcode(struct radeon_device *rdev) 1033 { 1034 const __be32 *fw_data; 1035 int i, size; 1036 1037 if (r100_gui_wait_for_idle(rdev)) { 1038 DRM_ERROR("Failed to wait GUI idle while " 1039 "programming pipes. Bad things might happen.\n"); 1040 } 1041 1042 if (rdev->me_fw) { 1043 size = rdev->me_fw->datasize / 4; 1044 fw_data = (const __be32 *)rdev->me_fw->data; 1045 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 1046 for (i = 0; i < size; i += 2) { 1047 WREG32(RADEON_CP_ME_RAM_DATAH, 1048 be32_to_cpup(&fw_data[i])); 1049 WREG32(RADEON_CP_ME_RAM_DATAL, 1050 be32_to_cpup(&fw_data[i + 1])); 1051 } 1052 } 1053 } 1054 1055 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1056 { 1057 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1058 unsigned rb_bufsz; 1059 unsigned rb_blksz; 1060 unsigned max_fetch; 1061 unsigned pre_write_timer; 1062 unsigned pre_write_limit; 1063 unsigned indirect2_start; 1064 unsigned indirect1_start; 1065 uint32_t tmp; 1066 int r; 1067 1068 if (r100_debugfs_cp_init(rdev)) { 1069 DRM_ERROR("Failed to register debugfs file for CP !\n"); 1070 } 1071 if (!rdev->me_fw) { 1072 r = r100_cp_init_microcode(rdev); 1073 if (r) { 1074 DRM_ERROR("Failed to load firmware!\n"); 1075 return r; 1076 } 1077 } 1078 1079 /* Align ring size */ 1080 rb_bufsz = drm_order(ring_size / 8); 1081 ring_size = (1 << (rb_bufsz + 1)) * 4; 1082 r100_cp_load_microcode(rdev); 1083 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 1084 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR, 1085 0, 0x7fffff, RADEON_CP_PACKET2); 1086 if (r) { 1087 return r; 1088 } 1089 /* Each time the cp read 1024 bytes (16 dword/quadword) update 1090 * the rptr copy in system ram */ 1091 rb_blksz = 9; 1092 /* cp will read 128bytes at a time (4 dwords) */ 1093 max_fetch = 1; 1094 ring->align_mask = 16 - 1; 1095 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1096 pre_write_timer = 64; 1097 /* Force CP_RB_WPTR write if written more than one time before the 1098 * delay expire 1099 */ 1100 pre_write_limit = 0; 1101 /* Setup the cp cache like this (cache size is 96 dwords) : 1102 * RING 0 to 15 1103 * INDIRECT1 16 to 79 1104 * INDIRECT2 80 to 95 1105 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1106 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1107 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1108 * Idea being that most of the gpu cmd will be through indirect1 buffer 1109 * so it gets the bigger cache. 1110 */ 1111 indirect2_start = 80; 1112 indirect1_start = 16; 1113 /* cp setup */ 1114 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1115 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1116 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1117 REG_SET(RADEON_MAX_FETCH, max_fetch)); 1118 #ifdef __BIG_ENDIAN 1119 tmp |= RADEON_BUF_SWAP_32BIT; 1120 #endif 1121 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1122 1123 /* Set ring address */ 1124 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1125 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1126 /* Force read & write ptr to 0 */ 1127 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1128 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1129 ring->wptr = 0; 1130 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1131 1132 /* set the wb address whether it's enabled or not */ 1133 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1134 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1135 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1136 1137 if (rdev->wb.enabled) 1138 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1139 else { 1140 tmp |= RADEON_RB_NO_UPDATE; 1141 WREG32(R_000770_SCRATCH_UMSK, 0); 1142 } 1143 1144 WREG32(RADEON_CP_RB_CNTL, tmp); 1145 DRM_UDELAY(10); 1146 ring->rptr = RREG32(RADEON_CP_RB_RPTR); 1147 /* Set cp mode to bus mastering & enable cp*/ 1148 WREG32(RADEON_CP_CSQ_MODE, 1149 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1150 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1151 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1152 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1153 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1154 1155 /* at this point everything should be setup correctly to enable master */ 1156 pci_enable_busmaster(rdev->dev); 1157 1158 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1159 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1160 if (r) { 1161 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1162 return r; 1163 } 1164 ring->ready = true; 1165 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1166 1167 if (!ring->rptr_save_reg /* not resuming from suspend */ 1168 && radeon_ring_supports_scratch_reg(rdev, ring)) { 1169 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 1170 if (r) { 1171 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 1172 ring->rptr_save_reg = 0; 1173 } 1174 } 1175 return 0; 1176 } 1177 1178 void r100_cp_fini(struct radeon_device *rdev) 1179 { 1180 if (r100_cp_wait_for_idle(rdev)) { 1181 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1182 } 1183 /* Disable ring */ 1184 r100_cp_disable(rdev); 1185 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); 1186 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1187 DRM_INFO("radeon: cp finalized\n"); 1188 } 1189 1190 void r100_cp_disable(struct radeon_device *rdev) 1191 { 1192 /* Disable ring */ 1193 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1194 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1195 WREG32(RADEON_CP_CSQ_MODE, 0); 1196 WREG32(RADEON_CP_CSQ_CNTL, 0); 1197 WREG32(R_000770_SCRATCH_UMSK, 0); 1198 if (r100_gui_wait_for_idle(rdev)) { 1199 DRM_ERROR("Failed to wait GUI idle while " 1200 "programming pipes. Bad things might happen.\n"); 1201 } 1202 } 1203 1204 /* 1205 * CS functions 1206 */ 1207 int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 1208 struct radeon_cs_packet *pkt, 1209 unsigned idx, 1210 unsigned reg) 1211 { 1212 int r; 1213 u32 tile_flags = 0; 1214 u32 tmp; 1215 struct radeon_cs_reloc *reloc; 1216 u32 value; 1217 1218 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1219 if (r) { 1220 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1221 idx, reg); 1222 radeon_cs_dump_packet(p, pkt); 1223 return r; 1224 } 1225 1226 value = radeon_get_ib_value(p, idx); 1227 tmp = value & 0x003fffff; 1228 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 1229 1230 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1231 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1232 tile_flags |= RADEON_DST_TILE_MACRO; 1233 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 1234 if (reg == RADEON_SRC_PITCH_OFFSET) { 1235 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1236 radeon_cs_dump_packet(p, pkt); 1237 return -EINVAL; 1238 } 1239 tile_flags |= RADEON_DST_TILE_MICRO; 1240 } 1241 1242 tmp |= tile_flags; 1243 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; 1244 } else 1245 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; 1246 return 0; 1247 } 1248 1249 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 1250 struct radeon_cs_packet *pkt, 1251 int idx) 1252 { 1253 unsigned c, i; 1254 struct radeon_cs_reloc *reloc; 1255 struct r100_cs_track *track; 1256 int r = 0; 1257 volatile uint32_t *ib; 1258 u32 idx_value; 1259 1260 ib = p->ib.ptr; 1261 track = (struct r100_cs_track *)p->track; 1262 c = radeon_get_ib_value(p, idx++) & 0x1F; 1263 if (c > 16) { 1264 DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 1265 pkt->opcode); 1266 radeon_cs_dump_packet(p, pkt); 1267 return -EINVAL; 1268 } 1269 track->num_arrays = c; 1270 for (i = 0; i < (c - 1); i+=2, idx+=3) { 1271 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1272 if (r) { 1273 DRM_ERROR("No reloc for packet3 %d\n", 1274 pkt->opcode); 1275 radeon_cs_dump_packet(p, pkt); 1276 return r; 1277 } 1278 idx_value = radeon_get_ib_value(p, idx); 1279 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1280 1281 track->arrays[i + 0].esize = idx_value >> 8; 1282 track->arrays[i + 0].robj = reloc->robj; 1283 track->arrays[i + 0].esize &= 0x7F; 1284 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1285 if (r) { 1286 DRM_ERROR("No reloc for packet3 %d\n", 1287 pkt->opcode); 1288 radeon_cs_dump_packet(p, pkt); 1289 return r; 1290 } 1291 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); 1292 track->arrays[i + 1].robj = reloc->robj; 1293 track->arrays[i + 1].esize = idx_value >> 24; 1294 track->arrays[i + 1].esize &= 0x7F; 1295 } 1296 if (c & 1) { 1297 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1298 if (r) { 1299 DRM_ERROR("No reloc for packet3 %d\n", 1300 pkt->opcode); 1301 radeon_cs_dump_packet(p, pkt); 1302 return r; 1303 } 1304 idx_value = radeon_get_ib_value(p, idx); 1305 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1306 track->arrays[i + 0].robj = reloc->robj; 1307 track->arrays[i + 0].esize = idx_value >> 8; 1308 track->arrays[i + 0].esize &= 0x7F; 1309 } 1310 return r; 1311 } 1312 1313 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1314 struct radeon_cs_packet *pkt, 1315 const unsigned *auth, unsigned n, 1316 radeon_packet0_check_t check) 1317 { 1318 unsigned reg; 1319 unsigned i, j, m; 1320 unsigned idx; 1321 int r; 1322 1323 idx = pkt->idx + 1; 1324 reg = pkt->reg; 1325 /* Check that register fall into register range 1326 * determined by the number of entry (n) in the 1327 * safe register bitmap. 1328 */ 1329 if (pkt->one_reg_wr) { 1330 if ((reg >> 7) > n) { 1331 return -EINVAL; 1332 } 1333 } else { 1334 if (((reg + (pkt->count << 2)) >> 7) > n) { 1335 return -EINVAL; 1336 } 1337 } 1338 for (i = 0; i <= pkt->count; i++, idx++) { 1339 j = (reg >> 7); 1340 m = 1 << ((reg >> 2) & 31); 1341 if (auth[j] & m) { 1342 r = check(p, pkt, idx, reg); 1343 if (r) { 1344 return r; 1345 } 1346 } 1347 if (pkt->one_reg_wr) { 1348 if (!(auth[j] & m)) { 1349 break; 1350 } 1351 } else { 1352 reg += 4; 1353 } 1354 } 1355 return 0; 1356 } 1357 1358 /** 1359 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1360 * @parser: parser structure holding parsing context. 1361 * 1362 * Userspace sends a special sequence for VLINE waits. 1363 * PACKET0 - VLINE_START_END + value 1364 * PACKET0 - WAIT_UNTIL +_value 1365 * RELOC (P3) - crtc_id in reloc. 1366 * 1367 * This function parses this and relocates the VLINE START END 1368 * and WAIT UNTIL packets to the correct crtc. 1369 * It also detects a switched off crtc and nulls out the 1370 * wait in that case. 1371 */ 1372 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1373 { 1374 struct drm_mode_object *obj; 1375 struct drm_crtc *crtc; 1376 struct radeon_crtc *radeon_crtc; 1377 struct radeon_cs_packet p3reloc, waitreloc; 1378 int crtc_id; 1379 int r; 1380 uint32_t header, h_idx, reg; 1381 volatile uint32_t *ib; 1382 1383 ib = p->ib.ptr; 1384 1385 /* parse the wait until */ 1386 r = radeon_cs_packet_parse(p, &waitreloc, p->idx); 1387 if (r) 1388 return r; 1389 1390 /* check its a wait until and only 1 count */ 1391 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1392 waitreloc.count != 0) { 1393 DRM_ERROR("vline wait had illegal wait until segment\n"); 1394 return -EINVAL; 1395 } 1396 1397 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1398 DRM_ERROR("vline wait had illegal wait until\n"); 1399 return -EINVAL; 1400 } 1401 1402 /* jump over the NOP */ 1403 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1404 if (r) 1405 return r; 1406 1407 h_idx = p->idx - 2; 1408 p->idx += waitreloc.count + 2; 1409 p->idx += p3reloc.count + 2; 1410 1411 header = radeon_get_ib_value(p, h_idx); 1412 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1413 reg = R100_CP_PACKET0_GET_REG(header); 1414 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1415 if (!obj) { 1416 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1417 return -EINVAL; 1418 } 1419 crtc = obj_to_crtc(obj); 1420 radeon_crtc = to_radeon_crtc(crtc); 1421 crtc_id = radeon_crtc->crtc_id; 1422 1423 if (!crtc->enabled) { 1424 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1425 ib[h_idx + 2] = PACKET2(0); 1426 ib[h_idx + 3] = PACKET2(0); 1427 } else if (crtc_id == 1) { 1428 switch (reg) { 1429 case AVIVO_D1MODE_VLINE_START_END: 1430 header &= ~R300_CP_PACKET0_REG_MASK; 1431 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1432 break; 1433 case RADEON_CRTC_GUI_TRIG_VLINE: 1434 header &= ~R300_CP_PACKET0_REG_MASK; 1435 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1436 break; 1437 default: 1438 DRM_ERROR("unknown crtc reloc\n"); 1439 return -EINVAL; 1440 } 1441 ib[h_idx] = header; 1442 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1443 } 1444 1445 return 0; 1446 } 1447 1448 static int r100_get_vtx_size(uint32_t vtx_fmt) 1449 { 1450 int vtx_size; 1451 vtx_size = 2; 1452 /* ordered according to bits in spec */ 1453 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1454 vtx_size++; 1455 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1456 vtx_size += 3; 1457 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1458 vtx_size++; 1459 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1460 vtx_size++; 1461 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1462 vtx_size += 3; 1463 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1464 vtx_size++; 1465 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1466 vtx_size++; 1467 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1468 vtx_size += 2; 1469 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1470 vtx_size += 2; 1471 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1472 vtx_size++; 1473 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1474 vtx_size += 2; 1475 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1476 vtx_size++; 1477 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1478 vtx_size += 2; 1479 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1480 vtx_size++; 1481 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1482 vtx_size++; 1483 /* blend weight */ 1484 if (vtx_fmt & (0x7 << 15)) 1485 vtx_size += (vtx_fmt >> 15) & 0x7; 1486 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1487 vtx_size += 3; 1488 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1489 vtx_size += 2; 1490 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1491 vtx_size++; 1492 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1493 vtx_size++; 1494 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1495 vtx_size++; 1496 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1497 vtx_size++; 1498 return vtx_size; 1499 } 1500 1501 static int r100_packet0_check(struct radeon_cs_parser *p, 1502 struct radeon_cs_packet *pkt, 1503 unsigned idx, unsigned reg) 1504 { 1505 struct radeon_cs_reloc *reloc; 1506 struct r100_cs_track *track; 1507 volatile uint32_t *ib; 1508 uint32_t tmp; 1509 int r; 1510 int i, face; 1511 u32 tile_flags = 0; 1512 u32 idx_value; 1513 1514 ib = p->ib.ptr; 1515 track = (struct r100_cs_track *)p->track; 1516 1517 idx_value = radeon_get_ib_value(p, idx); 1518 1519 switch (reg) { 1520 case RADEON_CRTC_GUI_TRIG_VLINE: 1521 r = r100_cs_packet_parse_vline(p); 1522 if (r) { 1523 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1524 idx, reg); 1525 radeon_cs_dump_packet(p, pkt); 1526 return r; 1527 } 1528 break; 1529 /* FIXME: only allow PACKET3 blit? easier to check for out of 1530 * range access */ 1531 case RADEON_DST_PITCH_OFFSET: 1532 case RADEON_SRC_PITCH_OFFSET: 1533 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1534 if (r) 1535 return r; 1536 break; 1537 case RADEON_RB3D_DEPTHOFFSET: 1538 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1539 if (r) { 1540 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1541 idx, reg); 1542 radeon_cs_dump_packet(p, pkt); 1543 return r; 1544 } 1545 track->zb.robj = reloc->robj; 1546 track->zb.offset = idx_value; 1547 track->zb_dirty = true; 1548 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1549 break; 1550 case RADEON_RB3D_COLOROFFSET: 1551 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1552 if (r) { 1553 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1554 idx, reg); 1555 radeon_cs_dump_packet(p, pkt); 1556 return r; 1557 } 1558 track->cb[0].robj = reloc->robj; 1559 track->cb[0].offset = idx_value; 1560 track->cb_dirty = true; 1561 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1562 break; 1563 case RADEON_PP_TXOFFSET_0: 1564 case RADEON_PP_TXOFFSET_1: 1565 case RADEON_PP_TXOFFSET_2: 1566 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1567 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1568 if (r) { 1569 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1570 idx, reg); 1571 radeon_cs_dump_packet(p, pkt); 1572 return r; 1573 } 1574 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1575 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1576 tile_flags |= RADEON_TXO_MACRO_TILE; 1577 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1578 tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1579 1580 tmp = idx_value & ~(0x7 << 2); 1581 tmp |= tile_flags; 1582 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); 1583 } else 1584 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1585 track->textures[i].robj = reloc->robj; 1586 track->tex_dirty = true; 1587 break; 1588 case RADEON_PP_CUBIC_OFFSET_T0_0: 1589 case RADEON_PP_CUBIC_OFFSET_T0_1: 1590 case RADEON_PP_CUBIC_OFFSET_T0_2: 1591 case RADEON_PP_CUBIC_OFFSET_T0_3: 1592 case RADEON_PP_CUBIC_OFFSET_T0_4: 1593 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1594 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1595 if (r) { 1596 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1597 idx, reg); 1598 radeon_cs_dump_packet(p, pkt); 1599 return r; 1600 } 1601 track->textures[0].cube_info[i].offset = idx_value; 1602 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1603 track->textures[0].cube_info[i].robj = reloc->robj; 1604 track->tex_dirty = true; 1605 break; 1606 case RADEON_PP_CUBIC_OFFSET_T1_0: 1607 case RADEON_PP_CUBIC_OFFSET_T1_1: 1608 case RADEON_PP_CUBIC_OFFSET_T1_2: 1609 case RADEON_PP_CUBIC_OFFSET_T1_3: 1610 case RADEON_PP_CUBIC_OFFSET_T1_4: 1611 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1612 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1613 if (r) { 1614 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1615 idx, reg); 1616 radeon_cs_dump_packet(p, pkt); 1617 return r; 1618 } 1619 track->textures[1].cube_info[i].offset = idx_value; 1620 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1621 track->textures[1].cube_info[i].robj = reloc->robj; 1622 track->tex_dirty = true; 1623 break; 1624 case RADEON_PP_CUBIC_OFFSET_T2_0: 1625 case RADEON_PP_CUBIC_OFFSET_T2_1: 1626 case RADEON_PP_CUBIC_OFFSET_T2_2: 1627 case RADEON_PP_CUBIC_OFFSET_T2_3: 1628 case RADEON_PP_CUBIC_OFFSET_T2_4: 1629 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1630 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1631 if (r) { 1632 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1633 idx, reg); 1634 radeon_cs_dump_packet(p, pkt); 1635 return r; 1636 } 1637 track->textures[2].cube_info[i].offset = idx_value; 1638 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1639 track->textures[2].cube_info[i].robj = reloc->robj; 1640 track->tex_dirty = true; 1641 break; 1642 case RADEON_RE_WIDTH_HEIGHT: 1643 track->maxy = ((idx_value >> 16) & 0x7FF); 1644 track->cb_dirty = true; 1645 track->zb_dirty = true; 1646 break; 1647 case RADEON_RB3D_COLORPITCH: 1648 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1649 if (r) { 1650 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1651 idx, reg); 1652 radeon_cs_dump_packet(p, pkt); 1653 return r; 1654 } 1655 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1656 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1657 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1658 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1659 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1660 1661 tmp = idx_value & ~(0x7 << 16); 1662 tmp |= tile_flags; 1663 ib[idx] = tmp; 1664 } else 1665 ib[idx] = idx_value; 1666 1667 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1668 track->cb_dirty = true; 1669 break; 1670 case RADEON_RB3D_DEPTHPITCH: 1671 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1672 track->zb_dirty = true; 1673 break; 1674 case RADEON_RB3D_CNTL: 1675 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1676 case 7: 1677 case 8: 1678 case 9: 1679 case 11: 1680 case 12: 1681 track->cb[0].cpp = 1; 1682 break; 1683 case 3: 1684 case 4: 1685 case 15: 1686 track->cb[0].cpp = 2; 1687 break; 1688 case 6: 1689 track->cb[0].cpp = 4; 1690 break; 1691 default: 1692 DRM_ERROR("Invalid color buffer format (%d) !\n", 1693 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1694 return -EINVAL; 1695 } 1696 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1697 track->cb_dirty = true; 1698 track->zb_dirty = true; 1699 break; 1700 case RADEON_RB3D_ZSTENCILCNTL: 1701 switch (idx_value & 0xf) { 1702 case 0: 1703 track->zb.cpp = 2; 1704 break; 1705 case 2: 1706 case 3: 1707 case 4: 1708 case 5: 1709 case 9: 1710 case 11: 1711 track->zb.cpp = 4; 1712 break; 1713 default: 1714 break; 1715 } 1716 track->zb_dirty = true; 1717 break; 1718 case RADEON_RB3D_ZPASS_ADDR: 1719 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1720 if (r) { 1721 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1722 idx, reg); 1723 radeon_cs_dump_packet(p, pkt); 1724 return r; 1725 } 1726 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1727 break; 1728 case RADEON_PP_CNTL: 1729 { 1730 uint32_t temp = idx_value >> 4; 1731 for (i = 0; i < track->num_texture; i++) 1732 track->textures[i].enabled = !!(temp & (1 << i)); 1733 track->tex_dirty = true; 1734 } 1735 break; 1736 case RADEON_SE_VF_CNTL: 1737 track->vap_vf_cntl = idx_value; 1738 break; 1739 case RADEON_SE_VTX_FMT: 1740 track->vtx_size = r100_get_vtx_size(idx_value); 1741 break; 1742 case RADEON_PP_TEX_SIZE_0: 1743 case RADEON_PP_TEX_SIZE_1: 1744 case RADEON_PP_TEX_SIZE_2: 1745 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1746 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1747 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1748 track->tex_dirty = true; 1749 break; 1750 case RADEON_PP_TEX_PITCH_0: 1751 case RADEON_PP_TEX_PITCH_1: 1752 case RADEON_PP_TEX_PITCH_2: 1753 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1754 track->textures[i].pitch = idx_value + 32; 1755 track->tex_dirty = true; 1756 break; 1757 case RADEON_PP_TXFILTER_0: 1758 case RADEON_PP_TXFILTER_1: 1759 case RADEON_PP_TXFILTER_2: 1760 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1761 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1762 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1763 tmp = (idx_value >> 23) & 0x7; 1764 if (tmp == 2 || tmp == 6) 1765 track->textures[i].roundup_w = false; 1766 tmp = (idx_value >> 27) & 0x7; 1767 if (tmp == 2 || tmp == 6) 1768 track->textures[i].roundup_h = false; 1769 track->tex_dirty = true; 1770 break; 1771 case RADEON_PP_TXFORMAT_0: 1772 case RADEON_PP_TXFORMAT_1: 1773 case RADEON_PP_TXFORMAT_2: 1774 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1775 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1776 track->textures[i].use_pitch = 1; 1777 } else { 1778 track->textures[i].use_pitch = 0; 1779 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1780 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1781 } 1782 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1783 track->textures[i].tex_coord_type = 2; 1784 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1785 case RADEON_TXFORMAT_I8: 1786 case RADEON_TXFORMAT_RGB332: 1787 case RADEON_TXFORMAT_Y8: 1788 track->textures[i].cpp = 1; 1789 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1790 break; 1791 case RADEON_TXFORMAT_AI88: 1792 case RADEON_TXFORMAT_ARGB1555: 1793 case RADEON_TXFORMAT_RGB565: 1794 case RADEON_TXFORMAT_ARGB4444: 1795 case RADEON_TXFORMAT_VYUY422: 1796 case RADEON_TXFORMAT_YVYU422: 1797 case RADEON_TXFORMAT_SHADOW16: 1798 case RADEON_TXFORMAT_LDUDV655: 1799 case RADEON_TXFORMAT_DUDV88: 1800 track->textures[i].cpp = 2; 1801 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1802 break; 1803 case RADEON_TXFORMAT_ARGB8888: 1804 case RADEON_TXFORMAT_RGBA8888: 1805 case RADEON_TXFORMAT_SHADOW32: 1806 case RADEON_TXFORMAT_LDUDUV8888: 1807 track->textures[i].cpp = 4; 1808 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1809 break; 1810 case RADEON_TXFORMAT_DXT1: 1811 track->textures[i].cpp = 1; 1812 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1813 break; 1814 case RADEON_TXFORMAT_DXT23: 1815 case RADEON_TXFORMAT_DXT45: 1816 track->textures[i].cpp = 1; 1817 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1818 break; 1819 } 1820 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1821 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1822 track->tex_dirty = true; 1823 break; 1824 case RADEON_PP_CUBIC_FACES_0: 1825 case RADEON_PP_CUBIC_FACES_1: 1826 case RADEON_PP_CUBIC_FACES_2: 1827 tmp = idx_value; 1828 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1829 for (face = 0; face < 4; face++) { 1830 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1831 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1832 } 1833 track->tex_dirty = true; 1834 break; 1835 default: 1836 DRM_ERROR("Forbidden register 0x%04X in cs at %d\n", 1837 reg, idx); 1838 return -EINVAL; 1839 } 1840 return 0; 1841 } 1842 1843 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1844 struct radeon_cs_packet *pkt, 1845 struct radeon_bo *robj) 1846 { 1847 unsigned idx; 1848 u32 value; 1849 idx = pkt->idx + 1; 1850 value = radeon_get_ib_value(p, idx + 2); 1851 if ((value + 1) > radeon_bo_size(robj)) { 1852 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1853 "(need %u have %lu) !\n", 1854 value + 1, 1855 radeon_bo_size(robj)); 1856 return -EINVAL; 1857 } 1858 return 0; 1859 } 1860 1861 static int r100_packet3_check(struct radeon_cs_parser *p, 1862 struct radeon_cs_packet *pkt) 1863 { 1864 struct radeon_cs_reloc *reloc; 1865 struct r100_cs_track *track; 1866 unsigned idx; 1867 volatile uint32_t *ib; 1868 int r; 1869 1870 ib = p->ib.ptr; 1871 idx = pkt->idx + 1; 1872 track = (struct r100_cs_track *)p->track; 1873 switch (pkt->opcode) { 1874 case PACKET3_3D_LOAD_VBPNTR: 1875 r = r100_packet3_load_vbpntr(p, pkt, idx); 1876 if (r) 1877 return r; 1878 break; 1879 case PACKET3_INDX_BUFFER: 1880 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1881 if (r) { 1882 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1883 radeon_cs_dump_packet(p, pkt); 1884 return r; 1885 } 1886 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 1887 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1888 if (r) { 1889 return r; 1890 } 1891 break; 1892 case 0x23: 1893 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1894 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1895 if (r) { 1896 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1897 radeon_cs_dump_packet(p, pkt); 1898 return r; 1899 } 1900 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 1901 track->num_arrays = 1; 1902 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1903 1904 track->arrays[0].robj = reloc->robj; 1905 track->arrays[0].esize = track->vtx_size; 1906 1907 track->max_indx = radeon_get_ib_value(p, idx+1); 1908 1909 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1910 track->immd_dwords = pkt->count - 1; 1911 r = r100_cs_track_check(p->rdev, track); 1912 if (r) 1913 return r; 1914 break; 1915 case PACKET3_3D_DRAW_IMMD: 1916 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1917 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1918 return -EINVAL; 1919 } 1920 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1921 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1922 track->immd_dwords = pkt->count - 1; 1923 r = r100_cs_track_check(p->rdev, track); 1924 if (r) 1925 return r; 1926 break; 1927 /* triggers drawing using in-packet vertex data */ 1928 case PACKET3_3D_DRAW_IMMD_2: 1929 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1930 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1931 return -EINVAL; 1932 } 1933 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1934 track->immd_dwords = pkt->count; 1935 r = r100_cs_track_check(p->rdev, track); 1936 if (r) 1937 return r; 1938 break; 1939 /* triggers drawing using in-packet vertex data */ 1940 case PACKET3_3D_DRAW_VBUF_2: 1941 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1942 r = r100_cs_track_check(p->rdev, track); 1943 if (r) 1944 return r; 1945 break; 1946 /* triggers drawing of vertex buffers setup elsewhere */ 1947 case PACKET3_3D_DRAW_INDX_2: 1948 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1949 r = r100_cs_track_check(p->rdev, track); 1950 if (r) 1951 return r; 1952 break; 1953 /* triggers drawing using indices to vertex buffer */ 1954 case PACKET3_3D_DRAW_VBUF: 1955 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1956 r = r100_cs_track_check(p->rdev, track); 1957 if (r) 1958 return r; 1959 break; 1960 /* triggers drawing of vertex buffers setup elsewhere */ 1961 case PACKET3_3D_DRAW_INDX: 1962 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1963 r = r100_cs_track_check(p->rdev, track); 1964 if (r) 1965 return r; 1966 break; 1967 /* triggers drawing using indices to vertex buffer */ 1968 case PACKET3_3D_CLEAR_HIZ: 1969 case PACKET3_3D_CLEAR_ZMASK: 1970 if (p->rdev->hyperz_filp != p->filp) 1971 return -EINVAL; 1972 break; 1973 case PACKET3_NOP: 1974 break; 1975 default: 1976 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1977 return -EINVAL; 1978 } 1979 return 0; 1980 } 1981 1982 int r100_cs_parse(struct radeon_cs_parser *p) 1983 { 1984 struct radeon_cs_packet pkt; 1985 struct r100_cs_track *track; 1986 int r; 1987 1988 track = kmalloc(sizeof(*track), M_DRM, M_ZERO | M_WAITOK); 1989 if (!track) 1990 return -ENOMEM; 1991 r100_cs_track_clear(p->rdev, track); 1992 p->track = track; 1993 do { 1994 r = radeon_cs_packet_parse(p, &pkt, p->idx); 1995 if (r) { 1996 drm_free(p->track, M_DRM); 1997 p->track = NULL; 1998 return r; 1999 } 2000 p->idx += pkt.count + 2; 2001 switch (pkt.type) { 2002 case RADEON_PACKET_TYPE0: 2003 if (p->rdev->family >= CHIP_R200) 2004 r = r100_cs_parse_packet0(p, &pkt, 2005 p->rdev->config.r100.reg_safe_bm, 2006 p->rdev->config.r100.reg_safe_bm_size, 2007 &r200_packet0_check); 2008 else 2009 r = r100_cs_parse_packet0(p, &pkt, 2010 p->rdev->config.r100.reg_safe_bm, 2011 p->rdev->config.r100.reg_safe_bm_size, 2012 &r100_packet0_check); 2013 break; 2014 case RADEON_PACKET_TYPE2: 2015 break; 2016 case RADEON_PACKET_TYPE3: 2017 r = r100_packet3_check(p, &pkt); 2018 break; 2019 default: 2020 DRM_ERROR("Unknown packet type %d !\n", 2021 pkt.type); 2022 drm_free(p->track, M_DRM); 2023 p->track = NULL; 2024 return -EINVAL; 2025 } 2026 if (r) { 2027 drm_free(p->track, M_DRM); 2028 p->track = NULL; 2029 return r; 2030 } 2031 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 2032 drm_free(p->track, M_DRM); 2033 p->track = NULL; 2034 return 0; 2035 } 2036 2037 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2038 { 2039 DRM_ERROR("pitch %d\n", t->pitch); 2040 DRM_ERROR("use_pitch %d\n", t->use_pitch); 2041 DRM_ERROR("width %d\n", t->width); 2042 DRM_ERROR("width_11 %d\n", t->width_11); 2043 DRM_ERROR("height %d\n", t->height); 2044 DRM_ERROR("height_11 %d\n", t->height_11); 2045 DRM_ERROR("num levels %d\n", t->num_levels); 2046 DRM_ERROR("depth %d\n", t->txdepth); 2047 DRM_ERROR("bpp %d\n", t->cpp); 2048 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2049 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2050 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2051 DRM_ERROR("compress format %d\n", t->compress_format); 2052 } 2053 2054 static int r100_track_compress_size(int compress_format, int w, int h) 2055 { 2056 int block_width, block_height, block_bytes; 2057 int wblocks, hblocks; 2058 int min_wblocks; 2059 int sz; 2060 2061 block_width = 4; 2062 block_height = 4; 2063 2064 switch (compress_format) { 2065 case R100_TRACK_COMP_DXT1: 2066 block_bytes = 8; 2067 min_wblocks = 4; 2068 break; 2069 default: 2070 case R100_TRACK_COMP_DXT35: 2071 block_bytes = 16; 2072 min_wblocks = 2; 2073 break; 2074 } 2075 2076 hblocks = (h + block_height - 1) / block_height; 2077 wblocks = (w + block_width - 1) / block_width; 2078 if (wblocks < min_wblocks) 2079 wblocks = min_wblocks; 2080 sz = wblocks * hblocks * block_bytes; 2081 return sz; 2082 } 2083 2084 static int r100_cs_track_cube(struct radeon_device *rdev, 2085 struct r100_cs_track *track, unsigned idx) 2086 { 2087 unsigned face, w, h; 2088 struct radeon_bo *cube_robj; 2089 unsigned long size; 2090 unsigned compress_format = track->textures[idx].compress_format; 2091 2092 for (face = 0; face < 5; face++) { 2093 cube_robj = track->textures[idx].cube_info[face].robj; 2094 w = track->textures[idx].cube_info[face].width; 2095 h = track->textures[idx].cube_info[face].height; 2096 2097 if (compress_format) { 2098 size = r100_track_compress_size(compress_format, w, h); 2099 } else 2100 size = w * h; 2101 size *= track->textures[idx].cpp; 2102 2103 size += track->textures[idx].cube_info[face].offset; 2104 2105 if (size > radeon_bo_size(cube_robj)) { 2106 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 2107 size, radeon_bo_size(cube_robj)); 2108 r100_cs_track_texture_print(&track->textures[idx]); 2109 return -1; 2110 } 2111 } 2112 return 0; 2113 } 2114 2115 static int r100_cs_track_texture_check(struct radeon_device *rdev, 2116 struct r100_cs_track *track) 2117 { 2118 struct radeon_bo *robj; 2119 unsigned long size; 2120 unsigned u, i, w, h, d; 2121 int ret; 2122 2123 for (u = 0; u < track->num_texture; u++) { 2124 if (!track->textures[u].enabled) 2125 continue; 2126 if (track->textures[u].lookup_disable) 2127 continue; 2128 robj = track->textures[u].robj; 2129 if (robj == NULL) { 2130 DRM_ERROR("No texture bound to unit %u\n", u); 2131 return -EINVAL; 2132 } 2133 size = 0; 2134 for (i = 0; i <= track->textures[u].num_levels; i++) { 2135 if (track->textures[u].use_pitch) { 2136 if (rdev->family < CHIP_R300) 2137 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 2138 else 2139 w = track->textures[u].pitch / (1 << i); 2140 } else { 2141 w = track->textures[u].width; 2142 if (rdev->family >= CHIP_RV515) 2143 w |= track->textures[u].width_11; 2144 w = w / (1 << i); 2145 if (track->textures[u].roundup_w) 2146 w = roundup_pow_of_two(w); 2147 } 2148 h = track->textures[u].height; 2149 if (rdev->family >= CHIP_RV515) 2150 h |= track->textures[u].height_11; 2151 h = h / (1 << i); 2152 if (track->textures[u].roundup_h) 2153 h = roundup_pow_of_two(h); 2154 if (track->textures[u].tex_coord_type == 1) { 2155 d = (1 << track->textures[u].txdepth) / (1 << i); 2156 if (!d) 2157 d = 1; 2158 } else { 2159 d = 1; 2160 } 2161 if (track->textures[u].compress_format) { 2162 2163 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 2164 /* compressed textures are block based */ 2165 } else 2166 size += w * h * d; 2167 } 2168 size *= track->textures[u].cpp; 2169 2170 switch (track->textures[u].tex_coord_type) { 2171 case 0: 2172 case 1: 2173 break; 2174 case 2: 2175 if (track->separate_cube) { 2176 ret = r100_cs_track_cube(rdev, track, u); 2177 if (ret) 2178 return ret; 2179 } else 2180 size *= 6; 2181 break; 2182 default: 2183 DRM_ERROR("Invalid texture coordinate type %u for unit " 2184 "%u\n", track->textures[u].tex_coord_type, u); 2185 return -EINVAL; 2186 } 2187 if (size > radeon_bo_size(robj)) { 2188 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 2189 "%lu\n", u, size, radeon_bo_size(robj)); 2190 r100_cs_track_texture_print(&track->textures[u]); 2191 return -EINVAL; 2192 } 2193 } 2194 return 0; 2195 } 2196 2197 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 2198 { 2199 unsigned i; 2200 unsigned long size; 2201 unsigned prim_walk; 2202 unsigned nverts; 2203 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 2204 2205 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 2206 !track->blend_read_enable) 2207 num_cb = 0; 2208 2209 for (i = 0; i < num_cb; i++) { 2210 if (track->cb[i].robj == NULL) { 2211 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2212 return -EINVAL; 2213 } 2214 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2215 size += track->cb[i].offset; 2216 if (size > radeon_bo_size(track->cb[i].robj)) { 2217 DRM_ERROR("[drm] Buffer too small for color buffer %d " 2218 "(need %lu have %lu) !\n", i, size, 2219 radeon_bo_size(track->cb[i].robj)); 2220 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 2221 i, track->cb[i].pitch, track->cb[i].cpp, 2222 track->cb[i].offset, track->maxy); 2223 return -EINVAL; 2224 } 2225 } 2226 track->cb_dirty = false; 2227 2228 if (track->zb_dirty && track->z_enabled) { 2229 if (track->zb.robj == NULL) { 2230 DRM_ERROR("[drm] No buffer for z buffer !\n"); 2231 return -EINVAL; 2232 } 2233 size = track->zb.pitch * track->zb.cpp * track->maxy; 2234 size += track->zb.offset; 2235 if (size > radeon_bo_size(track->zb.robj)) { 2236 DRM_ERROR("[drm] Buffer too small for z buffer " 2237 "(need %lu have %lu) !\n", size, 2238 radeon_bo_size(track->zb.robj)); 2239 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 2240 track->zb.pitch, track->zb.cpp, 2241 track->zb.offset, track->maxy); 2242 return -EINVAL; 2243 } 2244 } 2245 track->zb_dirty = false; 2246 2247 if (track->aa_dirty && track->aaresolve) { 2248 if (track->aa.robj == NULL) { 2249 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 2250 return -EINVAL; 2251 } 2252 /* I believe the format comes from colorbuffer0. */ 2253 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 2254 size += track->aa.offset; 2255 if (size > radeon_bo_size(track->aa.robj)) { 2256 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 2257 "(need %lu have %lu) !\n", i, size, 2258 radeon_bo_size(track->aa.robj)); 2259 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 2260 i, track->aa.pitch, track->cb[0].cpp, 2261 track->aa.offset, track->maxy); 2262 return -EINVAL; 2263 } 2264 } 2265 track->aa_dirty = false; 2266 2267 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 2268 if (track->vap_vf_cntl & (1 << 14)) { 2269 nverts = track->vap_alt_nverts; 2270 } else { 2271 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 2272 } 2273 switch (prim_walk) { 2274 case 1: 2275 for (i = 0; i < track->num_arrays; i++) { 2276 size = track->arrays[i].esize * track->max_indx * 4; 2277 if (track->arrays[i].robj == NULL) { 2278 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2279 "bound\n", prim_walk, i); 2280 return -EINVAL; 2281 } 2282 if (size > radeon_bo_size(track->arrays[i].robj)) { 2283 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2284 "need %lu dwords have %lu dwords\n", 2285 prim_walk, i, size >> 2, 2286 radeon_bo_size(track->arrays[i].robj) 2287 >> 2); 2288 DRM_ERROR("Max indices %u\n", track->max_indx); 2289 return -EINVAL; 2290 } 2291 } 2292 break; 2293 case 2: 2294 for (i = 0; i < track->num_arrays; i++) { 2295 size = track->arrays[i].esize * (nverts - 1) * 4; 2296 if (track->arrays[i].robj == NULL) { 2297 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2298 "bound\n", prim_walk, i); 2299 return -EINVAL; 2300 } 2301 if (size > radeon_bo_size(track->arrays[i].robj)) { 2302 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2303 "need %lu dwords have %lu dwords\n", 2304 prim_walk, i, size >> 2, 2305 radeon_bo_size(track->arrays[i].robj) 2306 >> 2); 2307 return -EINVAL; 2308 } 2309 } 2310 break; 2311 case 3: 2312 size = track->vtx_size * nverts; 2313 if (size != track->immd_dwords) { 2314 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 2315 track->immd_dwords, size); 2316 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2317 nverts, track->vtx_size); 2318 return -EINVAL; 2319 } 2320 break; 2321 default: 2322 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2323 prim_walk); 2324 return -EINVAL; 2325 } 2326 2327 if (track->tex_dirty) { 2328 track->tex_dirty = false; 2329 return r100_cs_track_texture_check(rdev, track); 2330 } 2331 return 0; 2332 } 2333 2334 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 2335 { 2336 unsigned i, face; 2337 2338 track->cb_dirty = true; 2339 track->zb_dirty = true; 2340 track->tex_dirty = true; 2341 track->aa_dirty = true; 2342 2343 if (rdev->family < CHIP_R300) { 2344 track->num_cb = 1; 2345 if (rdev->family <= CHIP_RS200) 2346 track->num_texture = 3; 2347 else 2348 track->num_texture = 6; 2349 track->maxy = 2048; 2350 track->separate_cube = 1; 2351 } else { 2352 track->num_cb = 4; 2353 track->num_texture = 16; 2354 track->maxy = 4096; 2355 track->separate_cube = 0; 2356 track->aaresolve = false; 2357 track->aa.robj = NULL; 2358 } 2359 2360 for (i = 0; i < track->num_cb; i++) { 2361 track->cb[i].robj = NULL; 2362 track->cb[i].pitch = 8192; 2363 track->cb[i].cpp = 16; 2364 track->cb[i].offset = 0; 2365 } 2366 track->z_enabled = true; 2367 track->zb.robj = NULL; 2368 track->zb.pitch = 8192; 2369 track->zb.cpp = 4; 2370 track->zb.offset = 0; 2371 track->vtx_size = 0x7F; 2372 track->immd_dwords = 0xFFFFFFFFUL; 2373 track->num_arrays = 11; 2374 track->max_indx = 0x00FFFFFFUL; 2375 for (i = 0; i < track->num_arrays; i++) { 2376 track->arrays[i].robj = NULL; 2377 track->arrays[i].esize = 0x7F; 2378 } 2379 for (i = 0; i < track->num_texture; i++) { 2380 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 2381 track->textures[i].pitch = 16536; 2382 track->textures[i].width = 16536; 2383 track->textures[i].height = 16536; 2384 track->textures[i].width_11 = 1 << 11; 2385 track->textures[i].height_11 = 1 << 11; 2386 track->textures[i].num_levels = 12; 2387 if (rdev->family <= CHIP_RS200) { 2388 track->textures[i].tex_coord_type = 0; 2389 track->textures[i].txdepth = 0; 2390 } else { 2391 track->textures[i].txdepth = 16; 2392 track->textures[i].tex_coord_type = 1; 2393 } 2394 track->textures[i].cpp = 64; 2395 track->textures[i].robj = NULL; 2396 /* CS IB emission code makes sure texture unit are disabled */ 2397 track->textures[i].enabled = false; 2398 track->textures[i].lookup_disable = false; 2399 track->textures[i].roundup_w = true; 2400 track->textures[i].roundup_h = true; 2401 if (track->separate_cube) 2402 for (face = 0; face < 5; face++) { 2403 track->textures[i].cube_info[face].robj = NULL; 2404 track->textures[i].cube_info[face].width = 16536; 2405 track->textures[i].cube_info[face].height = 16536; 2406 track->textures[i].cube_info[face].offset = 0; 2407 } 2408 } 2409 } 2410 2411 /* 2412 * Global GPU functions 2413 */ 2414 static void r100_errata(struct radeon_device *rdev) 2415 { 2416 rdev->pll_errata = 0; 2417 2418 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2419 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2420 } 2421 2422 if (rdev->family == CHIP_RV100 || 2423 rdev->family == CHIP_RS100 || 2424 rdev->family == CHIP_RS200) { 2425 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2426 } 2427 } 2428 2429 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2430 { 2431 unsigned i; 2432 uint32_t tmp; 2433 2434 for (i = 0; i < rdev->usec_timeout; i++) { 2435 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2436 if (tmp >= n) { 2437 return 0; 2438 } 2439 DRM_UDELAY(1); 2440 } 2441 return -1; 2442 } 2443 2444 int r100_gui_wait_for_idle(struct radeon_device *rdev) 2445 { 2446 unsigned i; 2447 uint32_t tmp; 2448 2449 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 2450 DRM_ERROR("radeon: wait for empty RBBM fifo failed !" 2451 " Bad things might happen.\n"); 2452 } 2453 for (i = 0; i < rdev->usec_timeout; i++) { 2454 tmp = RREG32(RADEON_RBBM_STATUS); 2455 if (!(tmp & RADEON_RBBM_ACTIVE)) { 2456 return 0; 2457 } 2458 DRM_UDELAY(1); 2459 } 2460 return -1; 2461 } 2462 2463 int r100_mc_wait_for_idle(struct radeon_device *rdev) 2464 { 2465 unsigned i; 2466 uint32_t tmp; 2467 2468 for (i = 0; i < rdev->usec_timeout; i++) { 2469 /* read MC_STATUS */ 2470 tmp = RREG32(RADEON_MC_STATUS); 2471 if (tmp & RADEON_MC_IDLE) { 2472 return 0; 2473 } 2474 DRM_UDELAY(1); 2475 } 2476 return -1; 2477 } 2478 2479 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2480 { 2481 u32 rbbm_status; 2482 2483 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2484 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2485 radeon_ring_lockup_update(ring); 2486 return false; 2487 } 2488 /* force CP activities */ 2489 radeon_ring_force_activity(rdev, ring); 2490 return radeon_ring_test_lockup(rdev, ring); 2491 } 2492 2493 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 2494 void r100_enable_bm(struct radeon_device *rdev) 2495 { 2496 uint32_t tmp; 2497 /* Enable bus mastering */ 2498 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 2499 WREG32(RADEON_BUS_CNTL, tmp); 2500 } 2501 2502 void r100_bm_disable(struct radeon_device *rdev) 2503 { 2504 u32 tmp; 2505 2506 /* disable bus mastering */ 2507 tmp = RREG32(R_000030_BUS_CNTL); 2508 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2509 DRM_MDELAY(1); 2510 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2511 DRM_MDELAY(1); 2512 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2513 tmp = RREG32(RADEON_BUS_CNTL); 2514 DRM_MDELAY(1); 2515 pci_disable_busmaster(rdev->dev); 2516 DRM_MDELAY(1); 2517 } 2518 2519 int r100_asic_reset(struct radeon_device *rdev) 2520 { 2521 struct r100_mc_save save; 2522 u32 status, tmp; 2523 int ret = 0; 2524 2525 status = RREG32(R_000E40_RBBM_STATUS); 2526 if (!G_000E40_GUI_ACTIVE(status)) { 2527 return 0; 2528 } 2529 r100_mc_stop(rdev, &save); 2530 status = RREG32(R_000E40_RBBM_STATUS); 2531 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2532 /* stop CP */ 2533 WREG32(RADEON_CP_CSQ_CNTL, 0); 2534 tmp = RREG32(RADEON_CP_RB_CNTL); 2535 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2536 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2537 WREG32(RADEON_CP_RB_WPTR, 0); 2538 WREG32(RADEON_CP_RB_CNTL, tmp); 2539 /* save PCI state */ 2540 pci_save_state(device_get_parent(rdev->dev)); 2541 /* disable bus mastering */ 2542 r100_bm_disable(rdev); 2543 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2544 S_0000F0_SOFT_RESET_RE(1) | 2545 S_0000F0_SOFT_RESET_PP(1) | 2546 S_0000F0_SOFT_RESET_RB(1)); 2547 RREG32(R_0000F0_RBBM_SOFT_RESET); 2548 DRM_MDELAY(500); 2549 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2550 DRM_MDELAY(1); 2551 status = RREG32(R_000E40_RBBM_STATUS); 2552 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2553 /* reset CP */ 2554 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2555 RREG32(R_0000F0_RBBM_SOFT_RESET); 2556 DRM_MDELAY(500); 2557 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2558 DRM_MDELAY(1); 2559 status = RREG32(R_000E40_RBBM_STATUS); 2560 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2561 /* restore PCI & busmastering */ 2562 pci_restore_state(device_get_parent(rdev->dev)); 2563 r100_enable_bm(rdev); 2564 /* Check if GPU is idle */ 2565 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2566 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2567 dev_err(rdev->dev, "failed to reset GPU\n"); 2568 ret = -1; 2569 } else 2570 dev_info(rdev->dev, "GPU reset succeed\n"); 2571 r100_mc_resume(rdev, &save); 2572 return ret; 2573 } 2574 2575 void r100_set_common_regs(struct radeon_device *rdev) 2576 { 2577 struct drm_device *dev = rdev->ddev; 2578 bool force_dac2 = false; 2579 u32 tmp; 2580 2581 /* set these so they don't interfere with anything */ 2582 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2583 WREG32(RADEON_SUBPIC_CNTL, 0); 2584 WREG32(RADEON_VIPH_CONTROL, 0); 2585 WREG32(RADEON_I2C_CNTL_1, 0); 2586 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2587 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2588 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2589 2590 /* always set up dac2 on rn50 and some rv100 as lots 2591 * of servers seem to wire it up to a VGA port but 2592 * don't report it in the bios connector 2593 * table. 2594 */ 2595 switch (dev->pci_device) { 2596 /* RN50 */ 2597 case 0x515e: 2598 case 0x5969: 2599 force_dac2 = true; 2600 break; 2601 /* RV100*/ 2602 case 0x5159: 2603 case 0x515a: 2604 /* DELL triple head servers */ 2605 if ((dev->pci_subvendor == 0x1028 /* DELL */) && 2606 ((dev->pci_subdevice == 0x016c) || 2607 (dev->pci_subdevice == 0x016d) || 2608 (dev->pci_subdevice == 0x016e) || 2609 (dev->pci_subdevice == 0x016f) || 2610 (dev->pci_subdevice == 0x0170) || 2611 (dev->pci_subdevice == 0x017d) || 2612 (dev->pci_subdevice == 0x017e) || 2613 (dev->pci_subdevice == 0x0183) || 2614 (dev->pci_subdevice == 0x018a) || 2615 (dev->pci_subdevice == 0x019a))) 2616 force_dac2 = true; 2617 break; 2618 } 2619 2620 if (force_dac2) { 2621 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2622 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2623 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2624 2625 /* For CRT on DAC2, don't turn it on if BIOS didn't 2626 enable it, even it's detected. 2627 */ 2628 2629 /* force it to crtc0 */ 2630 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2631 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2632 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2633 2634 /* set up the TV DAC */ 2635 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2636 RADEON_TV_DAC_STD_MASK | 2637 RADEON_TV_DAC_RDACPD | 2638 RADEON_TV_DAC_GDACPD | 2639 RADEON_TV_DAC_BDACPD | 2640 RADEON_TV_DAC_BGADJ_MASK | 2641 RADEON_TV_DAC_DACADJ_MASK); 2642 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2643 RADEON_TV_DAC_NHOLD | 2644 RADEON_TV_DAC_STD_PS2 | 2645 (0x58 << 16)); 2646 2647 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2648 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2649 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2650 } 2651 2652 /* switch PM block to ACPI mode */ 2653 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2654 tmp &= ~RADEON_PM_MODE_SEL; 2655 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2656 2657 } 2658 2659 /* 2660 * VRAM info 2661 */ 2662 static void r100_vram_get_type(struct radeon_device *rdev) 2663 { 2664 uint32_t tmp; 2665 2666 rdev->mc.vram_is_ddr = false; 2667 if (rdev->flags & RADEON_IS_IGP) 2668 rdev->mc.vram_is_ddr = true; 2669 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2670 rdev->mc.vram_is_ddr = true; 2671 if ((rdev->family == CHIP_RV100) || 2672 (rdev->family == CHIP_RS100) || 2673 (rdev->family == CHIP_RS200)) { 2674 tmp = RREG32(RADEON_MEM_CNTL); 2675 if (tmp & RV100_HALF_MODE) { 2676 rdev->mc.vram_width = 32; 2677 } else { 2678 rdev->mc.vram_width = 64; 2679 } 2680 if (rdev->flags & RADEON_SINGLE_CRTC) { 2681 rdev->mc.vram_width /= 4; 2682 rdev->mc.vram_is_ddr = true; 2683 } 2684 } else if (rdev->family <= CHIP_RV280) { 2685 tmp = RREG32(RADEON_MEM_CNTL); 2686 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2687 rdev->mc.vram_width = 128; 2688 } else { 2689 rdev->mc.vram_width = 64; 2690 } 2691 } else { 2692 /* newer IGPs */ 2693 rdev->mc.vram_width = 128; 2694 } 2695 } 2696 2697 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2698 { 2699 u32 aper_size; 2700 u8 byte; 2701 2702 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2703 2704 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2705 * that is has the 2nd generation multifunction PCI interface 2706 */ 2707 if (rdev->family == CHIP_RV280 || 2708 rdev->family >= CHIP_RV350) { 2709 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2710 ~RADEON_HDP_APER_CNTL); 2711 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2712 return aper_size * 2; 2713 } 2714 2715 /* Older cards have all sorts of funny issues to deal with. First 2716 * check if it's a multifunction card by reading the PCI config 2717 * header type... Limit those to one aperture size 2718 */ 2719 byte = pci_read_config(rdev->dev, 0xe, 1); 2720 if (byte & 0x80) { 2721 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2722 DRM_INFO("Limiting VRAM to one aperture\n"); 2723 return aper_size; 2724 } 2725 2726 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2727 * have set it up. We don't write this as it's broken on some ASICs but 2728 * we expect the BIOS to have done the right thing (might be too optimistic...) 2729 */ 2730 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2731 return aper_size * 2; 2732 return aper_size; 2733 } 2734 2735 void r100_vram_init_sizes(struct radeon_device *rdev) 2736 { 2737 u64 config_aper_size; 2738 2739 /* work out accessible VRAM */ 2740 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 2741 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 2742 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2743 /* FIXME we don't use the second aperture yet when we could use it */ 2744 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2745 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2746 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2747 if (rdev->flags & RADEON_IS_IGP) { 2748 uint32_t tom; 2749 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2750 tom = RREG32(RADEON_NB_TOM); 2751 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2752 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2753 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2754 } else { 2755 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2756 /* Some production boards of m6 will report 0 2757 * if it's 8 MB 2758 */ 2759 if (rdev->mc.real_vram_size == 0) { 2760 rdev->mc.real_vram_size = 8192 * 1024; 2761 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2762 } 2763 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2764 * Novell bug 204882 + along with lots of ubuntu ones 2765 */ 2766 if (rdev->mc.aper_size > config_aper_size) 2767 config_aper_size = rdev->mc.aper_size; 2768 2769 if (config_aper_size > rdev->mc.real_vram_size) 2770 rdev->mc.mc_vram_size = config_aper_size; 2771 else 2772 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2773 } 2774 } 2775 2776 void r100_vga_set_state(struct radeon_device *rdev, bool state) 2777 { 2778 uint32_t temp; 2779 2780 temp = RREG32(RADEON_CONFIG_CNTL); 2781 if (state == false) { 2782 temp &= ~RADEON_CFG_VGA_RAM_EN; 2783 temp |= RADEON_CFG_VGA_IO_DIS; 2784 } else { 2785 temp &= ~RADEON_CFG_VGA_IO_DIS; 2786 } 2787 WREG32(RADEON_CONFIG_CNTL, temp); 2788 } 2789 2790 static void r100_mc_init(struct radeon_device *rdev) 2791 { 2792 u64 base; 2793 2794 r100_vram_get_type(rdev); 2795 r100_vram_init_sizes(rdev); 2796 base = rdev->mc.aper_base; 2797 if (rdev->flags & RADEON_IS_IGP) 2798 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2799 radeon_vram_location(rdev, &rdev->mc, base); 2800 rdev->mc.gtt_base_align = 0; 2801 if (!(rdev->flags & RADEON_IS_AGP)) 2802 radeon_gtt_location(rdev, &rdev->mc); 2803 radeon_update_bandwidth_info(rdev); 2804 } 2805 2806 2807 /* 2808 * Indirect registers accessor 2809 */ 2810 void r100_pll_errata_after_index(struct radeon_device *rdev) 2811 { 2812 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2813 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2814 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2815 } 2816 } 2817 2818 static void r100_pll_errata_after_data(struct radeon_device *rdev) 2819 { 2820 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2821 * or the chip could hang on a subsequent access 2822 */ 2823 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2824 DRM_MDELAY(5); 2825 } 2826 2827 /* This function is required to workaround a hardware bug in some (all?) 2828 * revisions of the R300. This workaround should be called after every 2829 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2830 * may not be correct. 2831 */ 2832 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2833 uint32_t save, tmp; 2834 2835 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2836 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2837 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2838 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2839 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2840 } 2841 } 2842 2843 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2844 { 2845 uint32_t data; 2846 2847 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2848 r100_pll_errata_after_index(rdev); 2849 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2850 r100_pll_errata_after_data(rdev); 2851 return data; 2852 } 2853 2854 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2855 { 2856 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2857 r100_pll_errata_after_index(rdev); 2858 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2859 r100_pll_errata_after_data(rdev); 2860 } 2861 2862 static void r100_set_safe_registers(struct radeon_device *rdev) 2863 { 2864 if (ASIC_IS_RN50(rdev)) { 2865 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2866 rdev->config.r100.reg_safe_bm_size = DRM_ARRAY_SIZE(rn50_reg_safe_bm); 2867 } else if (rdev->family < CHIP_R200) { 2868 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2869 rdev->config.r100.reg_safe_bm_size = DRM_ARRAY_SIZE(r100_reg_safe_bm); 2870 } else { 2871 r200_set_safe_registers(rdev); 2872 } 2873 } 2874 2875 /* 2876 * Debugfs info 2877 */ 2878 #if defined(CONFIG_DEBUG_FS) 2879 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2880 { 2881 struct drm_info_node *node = (struct drm_info_node *) m->private; 2882 struct drm_device *dev = node->minor->dev; 2883 struct radeon_device *rdev = dev->dev_private; 2884 uint32_t reg, value; 2885 unsigned i; 2886 2887 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2888 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2889 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2890 for (i = 0; i < 64; i++) { 2891 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2892 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2893 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2894 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2895 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2896 } 2897 return 0; 2898 } 2899 2900 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2901 { 2902 struct drm_info_node *node = (struct drm_info_node *) m->private; 2903 struct drm_device *dev = node->minor->dev; 2904 struct radeon_device *rdev = dev->dev_private; 2905 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2906 uint32_t rdp, wdp; 2907 unsigned count, i, j; 2908 2909 radeon_ring_free_size(rdev, ring); 2910 rdp = RREG32(RADEON_CP_RB_RPTR); 2911 wdp = RREG32(RADEON_CP_RB_WPTR); 2912 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 2913 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2914 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2915 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2916 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 2917 seq_printf(m, "%u dwords in ring\n", count); 2918 for (j = 0; j <= count; j++) { 2919 i = (rdp + j) & ring->ptr_mask; 2920 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 2921 } 2922 return 0; 2923 } 2924 2925 2926 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2927 { 2928 struct drm_info_node *node = (struct drm_info_node *) m->private; 2929 struct drm_device *dev = node->minor->dev; 2930 struct radeon_device *rdev = dev->dev_private; 2931 uint32_t csq_stat, csq2_stat, tmp; 2932 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2933 unsigned i; 2934 2935 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2936 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2937 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2938 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2939 r_rptr = (csq_stat >> 0) & 0x3ff; 2940 r_wptr = (csq_stat >> 10) & 0x3ff; 2941 ib1_rptr = (csq_stat >> 20) & 0x3ff; 2942 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2943 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2944 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2945 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2946 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2947 seq_printf(m, "Ring rptr %u\n", r_rptr); 2948 seq_printf(m, "Ring wptr %u\n", r_wptr); 2949 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 2950 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2951 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 2952 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 2953 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 2954 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 2955 seq_printf(m, "Ring fifo:\n"); 2956 for (i = 0; i < 256; i++) { 2957 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2958 tmp = RREG32(RADEON_CP_CSQ_DATA); 2959 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 2960 } 2961 seq_printf(m, "Indirect1 fifo:\n"); 2962 for (i = 256; i <= 512; i++) { 2963 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2964 tmp = RREG32(RADEON_CP_CSQ_DATA); 2965 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 2966 } 2967 seq_printf(m, "Indirect2 fifo:\n"); 2968 for (i = 640; i < ib1_wptr; i++) { 2969 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2970 tmp = RREG32(RADEON_CP_CSQ_DATA); 2971 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 2972 } 2973 return 0; 2974 } 2975 2976 static int r100_debugfs_mc_info(struct seq_file *m, void *data) 2977 { 2978 struct drm_info_node *node = (struct drm_info_node *) m->private; 2979 struct drm_device *dev = node->minor->dev; 2980 struct radeon_device *rdev = dev->dev_private; 2981 uint32_t tmp; 2982 2983 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 2984 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 2985 tmp = RREG32(RADEON_MC_FB_LOCATION); 2986 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 2987 tmp = RREG32(RADEON_BUS_CNTL); 2988 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 2989 tmp = RREG32(RADEON_MC_AGP_LOCATION); 2990 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 2991 tmp = RREG32(RADEON_AGP_BASE); 2992 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 2993 tmp = RREG32(RADEON_HOST_PATH_CNTL); 2994 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 2995 tmp = RREG32(0x01D0); 2996 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 2997 tmp = RREG32(RADEON_AIC_LO_ADDR); 2998 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 2999 tmp = RREG32(RADEON_AIC_HI_ADDR); 3000 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 3001 tmp = RREG32(0x01E4); 3002 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 3003 return 0; 3004 } 3005 3006 static struct drm_info_list r100_debugfs_rbbm_list[] = { 3007 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 3008 }; 3009 3010 static struct drm_info_list r100_debugfs_cp_list[] = { 3011 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 3012 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 3013 }; 3014 3015 static struct drm_info_list r100_debugfs_mc_info_list[] = { 3016 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 3017 }; 3018 #endif 3019 3020 int r100_debugfs_rbbm_init(struct radeon_device *rdev) 3021 { 3022 #if defined(CONFIG_DEBUG_FS) 3023 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 3024 #else 3025 return 0; 3026 #endif 3027 } 3028 3029 int r100_debugfs_cp_init(struct radeon_device *rdev) 3030 { 3031 #if defined(CONFIG_DEBUG_FS) 3032 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 3033 #else 3034 return 0; 3035 #endif 3036 } 3037 3038 int r100_debugfs_mc_info_init(struct radeon_device *rdev) 3039 { 3040 #if defined(CONFIG_DEBUG_FS) 3041 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 3042 #else 3043 return 0; 3044 #endif 3045 } 3046 3047 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 3048 uint32_t tiling_flags, uint32_t pitch, 3049 uint32_t offset, uint32_t obj_size) 3050 { 3051 int surf_index = reg * 16; 3052 int flags = 0; 3053 3054 if (rdev->family <= CHIP_RS200) { 3055 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3056 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3057 flags |= RADEON_SURF_TILE_COLOR_BOTH; 3058 if (tiling_flags & RADEON_TILING_MACRO) 3059 flags |= RADEON_SURF_TILE_COLOR_MACRO; 3060 } else if (rdev->family <= CHIP_RV280) { 3061 if (tiling_flags & (RADEON_TILING_MACRO)) 3062 flags |= R200_SURF_TILE_COLOR_MACRO; 3063 if (tiling_flags & RADEON_TILING_MICRO) 3064 flags |= R200_SURF_TILE_COLOR_MICRO; 3065 } else { 3066 if (tiling_flags & RADEON_TILING_MACRO) 3067 flags |= R300_SURF_TILE_MACRO; 3068 if (tiling_flags & RADEON_TILING_MICRO) 3069 flags |= R300_SURF_TILE_MICRO; 3070 } 3071 3072 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 3073 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 3074 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 3075 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 3076 3077 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */ 3078 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) { 3079 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) 3080 if (ASIC_IS_RN50(rdev)) 3081 pitch /= 16; 3082 } 3083 3084 /* r100/r200 divide by 16 */ 3085 if (rdev->family < CHIP_R300) 3086 flags |= pitch / 16; 3087 else 3088 flags |= pitch / 8; 3089 3090 3091 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 3092 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 3093 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 3094 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 3095 return 0; 3096 } 3097 3098 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 3099 { 3100 int surf_index = reg * 16; 3101 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 3102 } 3103 3104 void r100_bandwidth_update(struct radeon_device *rdev) 3105 { 3106 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 3107 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 3108 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; 3109 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 3110 fixed20_12 memtcas_ff[8] = { 3111 dfixed_init(1), 3112 dfixed_init(2), 3113 dfixed_init(3), 3114 dfixed_init(0), 3115 dfixed_init_half(1), 3116 dfixed_init_half(2), 3117 dfixed_init(0), 3118 }; 3119 fixed20_12 memtcas_rs480_ff[8] = { 3120 dfixed_init(0), 3121 dfixed_init(1), 3122 dfixed_init(2), 3123 dfixed_init(3), 3124 dfixed_init(0), 3125 dfixed_init_half(1), 3126 dfixed_init_half(2), 3127 dfixed_init_half(3), 3128 }; 3129 fixed20_12 memtcas2_ff[8] = { 3130 dfixed_init(0), 3131 dfixed_init(1), 3132 dfixed_init(2), 3133 dfixed_init(3), 3134 dfixed_init(4), 3135 dfixed_init(5), 3136 dfixed_init(6), 3137 dfixed_init(7), 3138 }; 3139 fixed20_12 memtrbs[8] = { 3140 dfixed_init(1), 3141 dfixed_init_half(1), 3142 dfixed_init(2), 3143 dfixed_init_half(2), 3144 dfixed_init(3), 3145 dfixed_init_half(3), 3146 dfixed_init(4), 3147 dfixed_init_half(4) 3148 }; 3149 fixed20_12 memtrbs_r4xx[8] = { 3150 dfixed_init(4), 3151 dfixed_init(5), 3152 dfixed_init(6), 3153 dfixed_init(7), 3154 dfixed_init(8), 3155 dfixed_init(9), 3156 dfixed_init(10), 3157 dfixed_init(11) 3158 }; 3159 fixed20_12 min_mem_eff; 3160 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 3161 fixed20_12 cur_latency_mclk, cur_latency_sclk; 3162 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, 3163 disp_drain_rate2, read_return_rate; 3164 fixed20_12 time_disp1_drop_priority; 3165 int c; 3166 int cur_size = 16; /* in octawords */ 3167 int critical_point = 0, critical_point2; 3168 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 3169 int stop_req, max_stop_req; 3170 struct drm_display_mode *mode1 = NULL; 3171 struct drm_display_mode *mode2 = NULL; 3172 uint32_t pixel_bytes1 = 0; 3173 uint32_t pixel_bytes2 = 0; 3174 3175 radeon_update_display_priority(rdev); 3176 3177 if (rdev->mode_info.crtcs[0]->base.enabled) { 3178 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 3179 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 3180 } 3181 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3182 if (rdev->mode_info.crtcs[1]->base.enabled) { 3183 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 3184 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; 3185 } 3186 } 3187 3188 min_mem_eff.full = dfixed_const_8(0); 3189 /* get modes */ 3190 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 3191 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 3192 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 3193 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 3194 /* check crtc enables */ 3195 if (mode2) 3196 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 3197 if (mode1) 3198 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 3199 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 3200 } 3201 3202 /* 3203 * determine is there is enough bw for current mode 3204 */ 3205 sclk_ff = rdev->pm.sclk; 3206 mclk_ff = rdev->pm.mclk; 3207 3208 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 3209 temp_ff.full = dfixed_const(temp); 3210 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 3211 3212 pix_clk.full = 0; 3213 pix_clk2.full = 0; 3214 peak_disp_bw.full = 0; 3215 if (mode1) { 3216 temp_ff.full = dfixed_const(1000); 3217 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 3218 pix_clk.full = dfixed_div(pix_clk, temp_ff); 3219 temp_ff.full = dfixed_const(pixel_bytes1); 3220 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 3221 } 3222 if (mode2) { 3223 temp_ff.full = dfixed_const(1000); 3224 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 3225 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 3226 temp_ff.full = dfixed_const(pixel_bytes2); 3227 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 3228 } 3229 3230 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 3231 if (peak_disp_bw.full >= mem_bw.full) { 3232 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 3233 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 3234 } 3235 3236 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 3237 temp = RREG32(RADEON_MEM_TIMING_CNTL); 3238 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 3239 mem_trcd = ((temp >> 2) & 0x3) + 1; 3240 mem_trp = ((temp & 0x3)) + 1; 3241 mem_tras = ((temp & 0x70) >> 4) + 1; 3242 } else if (rdev->family == CHIP_R300 || 3243 rdev->family == CHIP_R350) { /* r300, r350 */ 3244 mem_trcd = (temp & 0x7) + 1; 3245 mem_trp = ((temp >> 8) & 0x7) + 1; 3246 mem_tras = ((temp >> 11) & 0xf) + 4; 3247 } else if (rdev->family == CHIP_RV350 || 3248 rdev->family <= CHIP_RV380) { 3249 /* rv3x0 */ 3250 mem_trcd = (temp & 0x7) + 3; 3251 mem_trp = ((temp >> 8) & 0x7) + 3; 3252 mem_tras = ((temp >> 11) & 0xf) + 6; 3253 } else if (rdev->family == CHIP_R420 || 3254 rdev->family == CHIP_R423 || 3255 rdev->family == CHIP_RV410) { 3256 /* r4xx */ 3257 mem_trcd = (temp & 0xf) + 3; 3258 if (mem_trcd > 15) 3259 mem_trcd = 15; 3260 mem_trp = ((temp >> 8) & 0xf) + 3; 3261 if (mem_trp > 15) 3262 mem_trp = 15; 3263 mem_tras = ((temp >> 12) & 0x1f) + 6; 3264 if (mem_tras > 31) 3265 mem_tras = 31; 3266 } else { /* RV200, R200 */ 3267 mem_trcd = (temp & 0x7) + 1; 3268 mem_trp = ((temp >> 8) & 0x7) + 1; 3269 mem_tras = ((temp >> 12) & 0xf) + 4; 3270 } 3271 /* convert to FF */ 3272 trcd_ff.full = dfixed_const(mem_trcd); 3273 trp_ff.full = dfixed_const(mem_trp); 3274 tras_ff.full = dfixed_const(mem_tras); 3275 3276 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 3277 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3278 data = (temp & (7 << 20)) >> 20; 3279 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 3280 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 3281 tcas_ff = memtcas_rs480_ff[data]; 3282 else 3283 tcas_ff = memtcas_ff[data]; 3284 } else 3285 tcas_ff = memtcas2_ff[data]; 3286 3287 if (rdev->family == CHIP_RS400 || 3288 rdev->family == CHIP_RS480) { 3289 /* extra cas latency stored in bits 23-25 0-4 clocks */ 3290 data = (temp >> 23) & 0x7; 3291 if (data < 5) 3292 tcas_ff.full += dfixed_const(data); 3293 } 3294 3295 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 3296 /* on the R300, Tcas is included in Trbs. 3297 */ 3298 temp = RREG32(RADEON_MEM_CNTL); 3299 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 3300 if (data == 1) { 3301 if (R300_MEM_USE_CD_CH_ONLY & temp) { 3302 temp = RREG32(R300_MC_IND_INDEX); 3303 temp &= ~R300_MC_IND_ADDR_MASK; 3304 temp |= R300_MC_READ_CNTL_CD_mcind; 3305 WREG32(R300_MC_IND_INDEX, temp); 3306 temp = RREG32(R300_MC_IND_DATA); 3307 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 3308 } else { 3309 temp = RREG32(R300_MC_READ_CNTL_AB); 3310 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3311 } 3312 } else { 3313 temp = RREG32(R300_MC_READ_CNTL_AB); 3314 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3315 } 3316 if (rdev->family == CHIP_RV410 || 3317 rdev->family == CHIP_R420 || 3318 rdev->family == CHIP_R423) 3319 trbs_ff = memtrbs_r4xx[data]; 3320 else 3321 trbs_ff = memtrbs[data]; 3322 tcas_ff.full += trbs_ff.full; 3323 } 3324 3325 sclk_eff_ff.full = sclk_ff.full; 3326 3327 if (rdev->flags & RADEON_IS_AGP) { 3328 fixed20_12 agpmode_ff; 3329 agpmode_ff.full = dfixed_const(radeon_agpmode); 3330 temp_ff.full = dfixed_const_666(16); 3331 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3332 } 3333 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3334 3335 if (ASIC_IS_R300(rdev)) { 3336 sclk_delay_ff.full = dfixed_const(250); 3337 } else { 3338 if ((rdev->family == CHIP_RV100) || 3339 rdev->flags & RADEON_IS_IGP) { 3340 if (rdev->mc.vram_is_ddr) 3341 sclk_delay_ff.full = dfixed_const(41); 3342 else 3343 sclk_delay_ff.full = dfixed_const(33); 3344 } else { 3345 if (rdev->mc.vram_width == 128) 3346 sclk_delay_ff.full = dfixed_const(57); 3347 else 3348 sclk_delay_ff.full = dfixed_const(41); 3349 } 3350 } 3351 3352 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3353 3354 if (rdev->mc.vram_is_ddr) { 3355 if (rdev->mc.vram_width == 32) { 3356 k1.full = dfixed_const(40); 3357 c = 3; 3358 } else { 3359 k1.full = dfixed_const(20); 3360 c = 1; 3361 } 3362 } else { 3363 k1.full = dfixed_const(40); 3364 c = 3; 3365 } 3366 3367 temp_ff.full = dfixed_const(2); 3368 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 3369 temp_ff.full = dfixed_const(c); 3370 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 3371 temp_ff.full = dfixed_const(4); 3372 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 3373 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3374 mc_latency_mclk.full += k1.full; 3375 3376 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 3377 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3378 3379 /* 3380 HW cursor time assuming worst case of full size colour cursor. 3381 */ 3382 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3383 temp_ff.full += trcd_ff.full; 3384 if (temp_ff.full < tras_ff.full) 3385 temp_ff.full = tras_ff.full; 3386 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3387 3388 temp_ff.full = dfixed_const(cur_size); 3389 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3390 /* 3391 Find the total latency for the display data. 3392 */ 3393 disp_latency_overhead.full = dfixed_const(8); 3394 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3395 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3396 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3397 3398 if (mc_latency_mclk.full > mc_latency_sclk.full) 3399 disp_latency.full = mc_latency_mclk.full; 3400 else 3401 disp_latency.full = mc_latency_sclk.full; 3402 3403 /* setup Max GRPH_STOP_REQ default value */ 3404 if (ASIC_IS_RV100(rdev)) 3405 max_stop_req = 0x5c; 3406 else 3407 max_stop_req = 0x7c; 3408 3409 if (mode1) { 3410 /* CRTC1 3411 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3412 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3413 */ 3414 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3415 3416 if (stop_req > max_stop_req) 3417 stop_req = max_stop_req; 3418 3419 /* 3420 Find the drain rate of the display buffer. 3421 */ 3422 temp_ff.full = dfixed_const((16/pixel_bytes1)); 3423 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3424 3425 /* 3426 Find the critical point of the display buffer. 3427 */ 3428 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 3429 crit_point_ff.full += dfixed_const_half(0); 3430 3431 critical_point = dfixed_trunc(crit_point_ff); 3432 3433 if (rdev->disp_priority == 2) { 3434 critical_point = 0; 3435 } 3436 3437 /* 3438 The critical point should never be above max_stop_req-4. Setting 3439 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3440 */ 3441 if (max_stop_req - critical_point < 4) 3442 critical_point = 0; 3443 3444 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3445 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3446 critical_point = 0x10; 3447 } 3448 3449 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3450 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3451 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3452 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3453 if ((rdev->family == CHIP_R350) && 3454 (stop_req > 0x15)) { 3455 stop_req -= 0x10; 3456 } 3457 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3458 temp |= RADEON_GRPH_BUFFER_SIZE; 3459 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3460 RADEON_GRPH_CRITICAL_AT_SOF | 3461 RADEON_GRPH_STOP_CNTL); 3462 /* 3463 Write the result into the register. 3464 */ 3465 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3466 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3467 3468 #if 0 3469 if ((rdev->family == CHIP_RS400) || 3470 (rdev->family == CHIP_RS480)) { 3471 /* attempt to program RS400 disp regs correctly ??? */ 3472 temp = RREG32(RS400_DISP1_REG_CNTL); 3473 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3474 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3475 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3476 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3477 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3478 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3479 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3480 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3481 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3482 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3483 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3484 } 3485 #endif 3486 3487 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3488 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3489 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3490 } 3491 3492 if (mode2) { 3493 u32 grph2_cntl; 3494 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3495 3496 if (stop_req > max_stop_req) 3497 stop_req = max_stop_req; 3498 3499 /* 3500 Find the drain rate of the display buffer. 3501 */ 3502 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3503 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3504 3505 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3506 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3507 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3508 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3509 if ((rdev->family == CHIP_R350) && 3510 (stop_req > 0x15)) { 3511 stop_req -= 0x10; 3512 } 3513 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3514 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3515 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3516 RADEON_GRPH_CRITICAL_AT_SOF | 3517 RADEON_GRPH_STOP_CNTL); 3518 3519 if ((rdev->family == CHIP_RS100) || 3520 (rdev->family == CHIP_RS200)) 3521 critical_point2 = 0; 3522 else { 3523 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3524 temp_ff.full = dfixed_const(temp); 3525 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3526 if (sclk_ff.full < temp_ff.full) 3527 temp_ff.full = sclk_ff.full; 3528 3529 read_return_rate.full = temp_ff.full; 3530 3531 if (mode1) { 3532 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3533 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3534 } else { 3535 time_disp1_drop_priority.full = 0; 3536 } 3537 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3538 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3539 crit_point_ff.full += dfixed_const_half(0); 3540 3541 critical_point2 = dfixed_trunc(crit_point_ff); 3542 3543 if (rdev->disp_priority == 2) { 3544 critical_point2 = 0; 3545 } 3546 3547 if (max_stop_req - critical_point2 < 4) 3548 critical_point2 = 0; 3549 3550 } 3551 3552 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3553 /* some R300 cards have problem with this set to 0 */ 3554 critical_point2 = 0x10; 3555 } 3556 3557 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3558 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3559 3560 if ((rdev->family == CHIP_RS400) || 3561 (rdev->family == CHIP_RS480)) { 3562 #if 0 3563 /* attempt to program RS400 disp2 regs correctly ??? */ 3564 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3565 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3566 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3567 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3568 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3569 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3570 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3571 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3572 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3573 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3574 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3575 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3576 #endif 3577 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3578 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3579 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3580 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3581 } 3582 3583 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3584 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3585 } 3586 } 3587 3588 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 3589 { 3590 uint32_t scratch; 3591 uint32_t tmp = 0; 3592 unsigned i; 3593 int r; 3594 3595 r = radeon_scratch_get(rdev, &scratch); 3596 if (r) { 3597 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3598 return r; 3599 } 3600 WREG32(scratch, 0xCAFEDEAD); 3601 r = radeon_ring_lock(rdev, ring, 2); 3602 if (r) { 3603 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3604 radeon_scratch_free(rdev, scratch); 3605 return r; 3606 } 3607 radeon_ring_write(ring, PACKET0(scratch, 0)); 3608 radeon_ring_write(ring, 0xDEADBEEF); 3609 radeon_ring_unlock_commit(rdev, ring); 3610 for (i = 0; i < rdev->usec_timeout; i++) { 3611 tmp = RREG32(scratch); 3612 if (tmp == 0xDEADBEEF) { 3613 break; 3614 } 3615 DRM_UDELAY(1); 3616 } 3617 if (i < rdev->usec_timeout) { 3618 DRM_INFO("ring test succeeded in %d usecs\n", i); 3619 } else { 3620 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3621 scratch, tmp); 3622 r = -EINVAL; 3623 } 3624 radeon_scratch_free(rdev, scratch); 3625 return r; 3626 } 3627 3628 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3629 { 3630 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3631 3632 if (ring->rptr_save_reg) { 3633 u32 next_rptr = ring->wptr + 2 + 3; 3634 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); 3635 radeon_ring_write(ring, next_rptr); 3636 } 3637 3638 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3639 radeon_ring_write(ring, ib->gpu_addr); 3640 radeon_ring_write(ring, ib->length_dw); 3641 } 3642 3643 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3644 { 3645 struct radeon_ib ib; 3646 uint32_t scratch; 3647 uint32_t tmp = 0; 3648 unsigned i; 3649 int r; 3650 3651 r = radeon_scratch_get(rdev, &scratch); 3652 if (r) { 3653 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3654 return r; 3655 } 3656 WREG32(scratch, 0xCAFEDEAD); 3657 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); 3658 if (r) { 3659 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3660 goto free_scratch; 3661 } 3662 ib.ptr[0] = PACKET0(scratch, 0); 3663 ib.ptr[1] = 0xDEADBEEF; 3664 ib.ptr[2] = PACKET2(0); 3665 ib.ptr[3] = PACKET2(0); 3666 ib.ptr[4] = PACKET2(0); 3667 ib.ptr[5] = PACKET2(0); 3668 ib.ptr[6] = PACKET2(0); 3669 ib.ptr[7] = PACKET2(0); 3670 ib.length_dw = 8; 3671 r = radeon_ib_schedule(rdev, &ib, NULL); 3672 if (r) { 3673 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3674 goto free_ib; 3675 } 3676 r = radeon_fence_wait(ib.fence, false); 3677 if (r) { 3678 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3679 goto free_ib; 3680 } 3681 for (i = 0; i < rdev->usec_timeout; i++) { 3682 tmp = RREG32(scratch); 3683 if (tmp == 0xDEADBEEF) { 3684 break; 3685 } 3686 DRM_UDELAY(1); 3687 } 3688 if (i < rdev->usec_timeout) { 3689 DRM_INFO("ib test succeeded in %u usecs\n", i); 3690 } else { 3691 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3692 scratch, tmp); 3693 r = -EINVAL; 3694 } 3695 free_ib: 3696 radeon_ib_free(rdev, &ib); 3697 free_scratch: 3698 radeon_scratch_free(rdev, scratch); 3699 return r; 3700 } 3701 3702 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3703 { 3704 /* Shutdown CP we shouldn't need to do that but better be safe than 3705 * sorry 3706 */ 3707 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3708 WREG32(R_000740_CP_CSQ_CNTL, 0); 3709 3710 /* Save few CRTC registers */ 3711 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3712 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3713 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3714 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3715 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3716 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3717 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3718 } 3719 3720 /* Disable VGA aperture access */ 3721 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3722 /* Disable cursor, overlay, crtc */ 3723 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3724 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3725 S_000054_CRTC_DISPLAY_DIS(1)); 3726 WREG32(R_000050_CRTC_GEN_CNTL, 3727 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3728 S_000050_CRTC_DISP_REQ_EN_B(1)); 3729 WREG32(R_000420_OV0_SCALE_CNTL, 3730 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3731 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3732 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3733 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3734 S_000360_CUR2_LOCK(1)); 3735 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3736 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3737 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3738 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3739 WREG32(R_000360_CUR2_OFFSET, 3740 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3741 } 3742 } 3743 3744 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3745 { 3746 /* Update base address for crtc */ 3747 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3748 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3749 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3750 } 3751 /* Restore CRTC registers */ 3752 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3753 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3754 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3755 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3756 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3757 } 3758 } 3759 3760 void r100_vga_render_disable(struct radeon_device *rdev) 3761 { 3762 u32 tmp; 3763 3764 tmp = RREG8(R_0003C2_GENMO_WT); 3765 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3766 } 3767 3768 static void r100_debugfs(struct radeon_device *rdev) 3769 { 3770 int r; 3771 3772 r = r100_debugfs_mc_info_init(rdev); 3773 if (r) 3774 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3775 } 3776 3777 static void r100_mc_program(struct radeon_device *rdev) 3778 { 3779 struct r100_mc_save save; 3780 3781 /* Stops all mc clients */ 3782 r100_mc_stop(rdev, &save); 3783 if (rdev->flags & RADEON_IS_AGP) { 3784 WREG32(R_00014C_MC_AGP_LOCATION, 3785 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3786 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3787 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3788 if (rdev->family > CHIP_RV200) 3789 WREG32(R_00015C_AGP_BASE_2, 3790 upper_32_bits(rdev->mc.agp_base) & 0xff); 3791 } else { 3792 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3793 WREG32(R_000170_AGP_BASE, 0); 3794 if (rdev->family > CHIP_RV200) 3795 WREG32(R_00015C_AGP_BASE_2, 0); 3796 } 3797 /* Wait for mc idle */ 3798 if (r100_mc_wait_for_idle(rdev)) 3799 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3800 /* Program MC, should be a 32bits limited address space */ 3801 WREG32(R_000148_MC_FB_LOCATION, 3802 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3803 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3804 r100_mc_resume(rdev, &save); 3805 } 3806 3807 static void r100_clock_startup(struct radeon_device *rdev) 3808 { 3809 u32 tmp; 3810 3811 if (radeon_dynclks != -1 && radeon_dynclks) 3812 radeon_legacy_set_clock_gating(rdev, 1); 3813 /* We need to force on some of the block */ 3814 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3815 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3816 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3817 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3818 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3819 } 3820 3821 static int r100_startup(struct radeon_device *rdev) 3822 { 3823 int r; 3824 3825 /* set common regs */ 3826 r100_set_common_regs(rdev); 3827 /* program mc */ 3828 r100_mc_program(rdev); 3829 /* Resume clock */ 3830 r100_clock_startup(rdev); 3831 /* Initialize GART (initialize after TTM so we can allocate 3832 * memory through TTM but finalize after TTM) */ 3833 r100_enable_bm(rdev); 3834 if (rdev->flags & RADEON_IS_PCI) { 3835 r = r100_pci_gart_enable(rdev); 3836 if (r) 3837 return r; 3838 } 3839 3840 /* allocate wb buffer */ 3841 r = radeon_wb_init(rdev); 3842 if (r) 3843 return r; 3844 3845 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3846 if (r) { 3847 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3848 return r; 3849 } 3850 3851 /* Enable IRQ */ 3852 r100_irq_set(rdev); 3853 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3854 /* 1M ring buffer */ 3855 r = r100_cp_init(rdev, 1024 * 1024); 3856 if (r) { 3857 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3858 return r; 3859 } 3860 3861 r = radeon_ib_pool_init(rdev); 3862 if (r) { 3863 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3864 return r; 3865 } 3866 3867 return 0; 3868 } 3869 3870 int r100_resume(struct radeon_device *rdev) 3871 { 3872 int r; 3873 3874 /* Make sur GART are not working */ 3875 if (rdev->flags & RADEON_IS_PCI) 3876 r100_pci_gart_disable(rdev); 3877 /* Resume clock before doing reset */ 3878 r100_clock_startup(rdev); 3879 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3880 if (radeon_asic_reset(rdev)) { 3881 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3882 RREG32(R_000E40_RBBM_STATUS), 3883 RREG32(R_0007C0_CP_STAT)); 3884 } 3885 /* post */ 3886 radeon_combios_asic_init(rdev->ddev); 3887 /* Resume clock after posting */ 3888 r100_clock_startup(rdev); 3889 /* Initialize surface registers */ 3890 radeon_surface_init(rdev); 3891 3892 rdev->accel_working = true; 3893 r = r100_startup(rdev); 3894 if (r) { 3895 rdev->accel_working = false; 3896 } 3897 return r; 3898 } 3899 3900 int r100_suspend(struct radeon_device *rdev) 3901 { 3902 r100_cp_disable(rdev); 3903 radeon_wb_disable(rdev); 3904 r100_irq_disable(rdev); 3905 if (rdev->flags & RADEON_IS_PCI) 3906 r100_pci_gart_disable(rdev); 3907 return 0; 3908 } 3909 3910 void r100_fini(struct radeon_device *rdev) 3911 { 3912 r100_cp_fini(rdev); 3913 radeon_wb_fini(rdev); 3914 radeon_ib_pool_fini(rdev); 3915 radeon_gem_fini(rdev); 3916 if (rdev->flags & RADEON_IS_PCI) 3917 r100_pci_gart_fini(rdev); 3918 radeon_agp_fini(rdev); 3919 radeon_irq_kms_fini(rdev); 3920 radeon_fence_driver_fini(rdev); 3921 radeon_bo_fini(rdev); 3922 radeon_atombios_fini(rdev); 3923 r100_cp_fini_microcode(rdev); 3924 drm_free(rdev->bios, M_DRM); 3925 rdev->bios = NULL; 3926 } 3927 3928 /* 3929 * Due to how kexec works, it can leave the hw fully initialised when it 3930 * boots the new kernel. However doing our init sequence with the CP and 3931 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 3932 * do some quick sanity checks and restore sane values to avoid this 3933 * problem. 3934 */ 3935 void r100_restore_sanity(struct radeon_device *rdev) 3936 { 3937 u32 tmp; 3938 3939 tmp = RREG32(RADEON_CP_CSQ_CNTL); 3940 if (tmp) { 3941 WREG32(RADEON_CP_CSQ_CNTL, 0); 3942 } 3943 tmp = RREG32(RADEON_CP_RB_CNTL); 3944 if (tmp) { 3945 WREG32(RADEON_CP_RB_CNTL, 0); 3946 } 3947 tmp = RREG32(RADEON_SCRATCH_UMSK); 3948 if (tmp) { 3949 WREG32(RADEON_SCRATCH_UMSK, 0); 3950 } 3951 } 3952 3953 int r100_init(struct radeon_device *rdev) 3954 { 3955 int r; 3956 3957 /* Register debugfs file specific to this group of asics */ 3958 r100_debugfs(rdev); 3959 /* Disable VGA */ 3960 r100_vga_render_disable(rdev); 3961 /* Initialize scratch registers */ 3962 radeon_scratch_init(rdev); 3963 /* Initialize surface registers */ 3964 radeon_surface_init(rdev); 3965 /* sanity check some register to avoid hangs like after kexec */ 3966 r100_restore_sanity(rdev); 3967 /* TODO: disable VGA need to use VGA request */ 3968 /* BIOS*/ 3969 if (!radeon_get_bios(rdev)) { 3970 if (ASIC_IS_AVIVO(rdev)) 3971 return -EINVAL; 3972 } 3973 if (rdev->is_atom_bios) { 3974 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 3975 return -EINVAL; 3976 } else { 3977 r = radeon_combios_init(rdev); 3978 if (r) 3979 return r; 3980 } 3981 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3982 if (radeon_asic_reset(rdev)) { 3983 dev_warn(rdev->dev, 3984 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3985 RREG32(R_000E40_RBBM_STATUS), 3986 RREG32(R_0007C0_CP_STAT)); 3987 } 3988 /* check if cards are posted or not */ 3989 if (radeon_boot_test_post_card(rdev) == false) 3990 return -EINVAL; 3991 /* Set asic errata */ 3992 r100_errata(rdev); 3993 /* Initialize clocks */ 3994 radeon_get_clock_info(rdev->ddev); 3995 /* initialize AGP */ 3996 if (rdev->flags & RADEON_IS_AGP) { 3997 r = radeon_agp_init(rdev); 3998 if (r) { 3999 radeon_agp_disable(rdev); 4000 } 4001 } 4002 /* initialize VRAM */ 4003 r100_mc_init(rdev); 4004 /* Fence driver */ 4005 r = radeon_fence_driver_init(rdev); 4006 if (r) 4007 return r; 4008 r = radeon_irq_kms_init(rdev); 4009 if (r) 4010 return r; 4011 /* Memory manager */ 4012 r = radeon_bo_init(rdev); 4013 if (r) 4014 return r; 4015 if (rdev->flags & RADEON_IS_PCI) { 4016 r = r100_pci_gart_init(rdev); 4017 if (r) 4018 return r; 4019 } 4020 r100_set_safe_registers(rdev); 4021 4022 rdev->accel_working = true; 4023 r = r100_startup(rdev); 4024 if (r) { 4025 /* Somethings want wront with the accel init stop accel */ 4026 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4027 r100_cp_fini(rdev); 4028 radeon_wb_fini(rdev); 4029 radeon_ib_pool_fini(rdev); 4030 radeon_irq_kms_fini(rdev); 4031 if (rdev->flags & RADEON_IS_PCI) 4032 r100_pci_gart_fini(rdev); 4033 rdev->accel_working = false; 4034 } 4035 return 0; 4036 } 4037 4038 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 4039 bool always_indirect) 4040 { 4041 if (reg < rdev->rmmio_size && !always_indirect) 4042 return bus_read_4(rdev->rmmio, reg); 4043 else { 4044 uint32_t ret; 4045 4046 spin_lock(&rdev->mmio_idx_lock); 4047 bus_write_4(rdev->rmmio, RADEON_MM_INDEX, reg); 4048 ret = bus_read_4(rdev->rmmio, RADEON_MM_DATA); 4049 spin_unlock(&rdev->mmio_idx_lock); 4050 4051 return ret; 4052 } 4053 } 4054 4055 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 4056 bool always_indirect) 4057 { 4058 if (reg < rdev->rmmio_size && !always_indirect) 4059 bus_write_4(rdev->rmmio, reg, v); 4060 else { 4061 spin_lock(&rdev->mmio_idx_lock); 4062 bus_write_4(rdev->rmmio, RADEON_MM_INDEX, reg); 4063 bus_write_4(rdev->rmmio, RADEON_MM_DATA, v); 4064 spin_unlock(&rdev->mmio_idx_lock); 4065 } 4066 } 4067 4068 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 4069 { 4070 if (reg < rdev->rio_mem_size) 4071 return bus_read_4(rdev->rio_mem, reg); 4072 else { 4073 /* XXX No locking? -- dumbbell@ */ 4074 bus_write_4(rdev->rio_mem, RADEON_MM_INDEX, reg); 4075 return bus_read_4(rdev->rio_mem, RADEON_MM_DATA); 4076 } 4077 } 4078 4079 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 4080 { 4081 if (reg < rdev->rio_mem_size) 4082 bus_write_4(rdev->rio_mem, reg, v); 4083 else { 4084 /* XXX No locking? -- dumbbell@ */ 4085 bus_write_4(rdev->rio_mem, RADEON_MM_INDEX, reg); 4086 bus_write_4(rdev->rio_mem, RADEON_MM_DATA, v); 4087 } 4088 } 4089