1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <drm/drmP.h> 27 #include "radeon.h" 28 #include "radeon_asic.h" 29 #include "radeon_audio.h" 30 #include <uapi_drm/radeon_drm.h> 31 #include "nid.h" 32 #include "atom.h" 33 #include "ni_reg.h" 34 #include "cayman_blit_shaders.h" 35 #include "radeon_ucode.h" 36 #include "clearstate_cayman.h" 37 38 /* 39 * Indirect registers accessor 40 */ 41 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 42 { 43 unsigned long flags; 44 u32 r; 45 46 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 47 WREG32(TN_SMC_IND_INDEX_0, (reg)); 48 r = RREG32(TN_SMC_IND_DATA_0); 49 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 50 return r; 51 } 52 53 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 54 { 55 unsigned long flags; 56 57 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 58 WREG32(TN_SMC_IND_INDEX_0, (reg)); 59 WREG32(TN_SMC_IND_DATA_0, (v)); 60 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 61 } 62 63 static const u32 tn_rlc_save_restore_register_list[] = 64 { 65 0x98fc, 66 0x98f0, 67 0x9834, 68 0x9838, 69 0x9870, 70 0x9874, 71 0x8a14, 72 0x8b24, 73 0x8bcc, 74 0x8b10, 75 0x8c30, 76 0x8d00, 77 0x8d04, 78 0x8c00, 79 0x8c04, 80 0x8c10, 81 0x8c14, 82 0x8d8c, 83 0x8cf0, 84 0x8e38, 85 0x9508, 86 0x9688, 87 0x9608, 88 0x960c, 89 0x9610, 90 0x9614, 91 0x88c4, 92 0x8978, 93 0x88d4, 94 0x900c, 95 0x9100, 96 0x913c, 97 0x90e8, 98 0x9354, 99 0xa008, 100 0x98f8, 101 0x9148, 102 0x914c, 103 0x3f94, 104 0x98f4, 105 0x9b7c, 106 0x3f8c, 107 0x8950, 108 0x8954, 109 0x8a18, 110 0x8b28, 111 0x9144, 112 0x3f90, 113 0x915c, 114 0x9160, 115 0x9178, 116 0x917c, 117 0x9180, 118 0x918c, 119 0x9190, 120 0x9194, 121 0x9198, 122 0x919c, 123 0x91a8, 124 0x91ac, 125 0x91b0, 126 0x91b4, 127 0x91b8, 128 0x91c4, 129 0x91c8, 130 0x91cc, 131 0x91d0, 132 0x91d4, 133 0x91e0, 134 0x91e4, 135 0x91ec, 136 0x91f0, 137 0x91f4, 138 0x9200, 139 0x9204, 140 0x929c, 141 0x8030, 142 0x9150, 143 0x9a60, 144 0x920c, 145 0x9210, 146 0x9228, 147 0x922c, 148 0x9244, 149 0x9248, 150 0x91e8, 151 0x9294, 152 0x9208, 153 0x9224, 154 0x9240, 155 0x9220, 156 0x923c, 157 0x9258, 158 0x9744, 159 0xa200, 160 0xa204, 161 0xa208, 162 0xa20c, 163 0x8d58, 164 0x9030, 165 0x9034, 166 0x9038, 167 0x903c, 168 0x9040, 169 0x9654, 170 0x897c, 171 0xa210, 172 0xa214, 173 0x9868, 174 0xa02c, 175 0x9664, 176 0x9698, 177 0x949c, 178 0x8e10, 179 0x8e18, 180 0x8c50, 181 0x8c58, 182 0x8c60, 183 0x8c68, 184 0x89b4, 185 0x9830, 186 0x802c, 187 }; 188 189 /* Firmware Names */ 190 MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); 191 MODULE_FIRMWARE("radeon/BARTS_me.bin"); 192 MODULE_FIRMWARE("radeon/BARTS_mc.bin"); 193 MODULE_FIRMWARE("radeon/BARTS_smc.bin"); 194 MODULE_FIRMWARE("radeon/BTC_rlc.bin"); 195 MODULE_FIRMWARE("radeon/TURKS_pfp.bin"); 196 MODULE_FIRMWARE("radeon/TURKS_me.bin"); 197 MODULE_FIRMWARE("radeon/TURKS_mc.bin"); 198 MODULE_FIRMWARE("radeon/TURKS_smc.bin"); 199 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin"); 200 MODULE_FIRMWARE("radeon/CAICOS_me.bin"); 201 MODULE_FIRMWARE("radeon/CAICOS_mc.bin"); 202 MODULE_FIRMWARE("radeon/CAICOS_smc.bin"); 203 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); 204 MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); 205 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); 206 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); 207 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin"); 208 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin"); 209 MODULE_FIRMWARE("radeon/ARUBA_me.bin"); 210 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin"); 211 212 213 static const u32 cayman_golden_registers2[] = 214 { 215 0x3e5c, 0xffffffff, 0x00000000, 216 0x3e48, 0xffffffff, 0x00000000, 217 0x3e4c, 0xffffffff, 0x00000000, 218 0x3e64, 0xffffffff, 0x00000000, 219 0x3e50, 0xffffffff, 0x00000000, 220 0x3e60, 0xffffffff, 0x00000000 221 }; 222 223 static const u32 cayman_golden_registers[] = 224 { 225 0x5eb4, 0xffffffff, 0x00000002, 226 0x5e78, 0x8f311ff1, 0x001000f0, 227 0x3f90, 0xffff0000, 0xff000000, 228 0x9148, 0xffff0000, 0xff000000, 229 0x3f94, 0xffff0000, 0xff000000, 230 0x914c, 0xffff0000, 0xff000000, 231 0xc78, 0x00000080, 0x00000080, 232 0xbd4, 0x70073777, 0x00011003, 233 0xd02c, 0xbfffff1f, 0x08421000, 234 0xd0b8, 0x73773777, 0x02011003, 235 0x5bc0, 0x00200000, 0x50100000, 236 0x98f8, 0x33773777, 0x02011003, 237 0x98fc, 0xffffffff, 0x76541032, 238 0x7030, 0x31000311, 0x00000011, 239 0x2f48, 0x33773777, 0x42010001, 240 0x6b28, 0x00000010, 0x00000012, 241 0x7728, 0x00000010, 0x00000012, 242 0x10328, 0x00000010, 0x00000012, 243 0x10f28, 0x00000010, 0x00000012, 244 0x11b28, 0x00000010, 0x00000012, 245 0x12728, 0x00000010, 0x00000012, 246 0x240c, 0x000007ff, 0x00000000, 247 0x8a14, 0xf000001f, 0x00000007, 248 0x8b24, 0x3fff3fff, 0x00ff0fff, 249 0x8b10, 0x0000ff0f, 0x00000000, 250 0x28a4c, 0x07ffffff, 0x06000000, 251 0x10c, 0x00000001, 0x00010003, 252 0xa02c, 0xffffffff, 0x0000009b, 253 0x913c, 0x0000010f, 0x01000100, 254 0x8c04, 0xf8ff00ff, 0x40600060, 255 0x28350, 0x00000f01, 0x00000000, 256 0x9508, 0x3700001f, 0x00000002, 257 0x960c, 0xffffffff, 0x54763210, 258 0x88c4, 0x001f3ae3, 0x00000082, 259 0x88d0, 0xffffffff, 0x0f40df40, 260 0x88d4, 0x0000001f, 0x00000010, 261 0x8974, 0xffffffff, 0x00000000 262 }; 263 264 static const u32 dvst_golden_registers2[] = 265 { 266 0x8f8, 0xffffffff, 0, 267 0x8fc, 0x00380000, 0, 268 0x8f8, 0xffffffff, 1, 269 0x8fc, 0x0e000000, 0 270 }; 271 272 static const u32 dvst_golden_registers[] = 273 { 274 0x690, 0x3fff3fff, 0x20c00033, 275 0x918c, 0x0fff0fff, 0x00010006, 276 0x91a8, 0x0fff0fff, 0x00010006, 277 0x9150, 0xffffdfff, 0x6e944040, 278 0x917c, 0x0fff0fff, 0x00030002, 279 0x9198, 0x0fff0fff, 0x00030002, 280 0x915c, 0x0fff0fff, 0x00010000, 281 0x3f90, 0xffff0001, 0xff000000, 282 0x9178, 0x0fff0fff, 0x00070000, 283 0x9194, 0x0fff0fff, 0x00070000, 284 0x9148, 0xffff0001, 0xff000000, 285 0x9190, 0x0fff0fff, 0x00090008, 286 0x91ac, 0x0fff0fff, 0x00090008, 287 0x3f94, 0xffff0000, 0xff000000, 288 0x914c, 0xffff0000, 0xff000000, 289 0x929c, 0x00000fff, 0x00000001, 290 0x55e4, 0xff607fff, 0xfc000100, 291 0x8a18, 0xff000fff, 0x00000100, 292 0x8b28, 0xff000fff, 0x00000100, 293 0x9144, 0xfffc0fff, 0x00000100, 294 0x6ed8, 0x00010101, 0x00010000, 295 0x9830, 0xffffffff, 0x00000000, 296 0x9834, 0xf00fffff, 0x00000400, 297 0x9838, 0xfffffffe, 0x00000000, 298 0xd0c0, 0xff000fff, 0x00000100, 299 0xd02c, 0xbfffff1f, 0x08421000, 300 0xd0b8, 0x73773777, 0x12010001, 301 0x5bb0, 0x000000f0, 0x00000070, 302 0x98f8, 0x73773777, 0x12010001, 303 0x98fc, 0xffffffff, 0x00000010, 304 0x9b7c, 0x00ff0000, 0x00fc0000, 305 0x8030, 0x00001f0f, 0x0000100a, 306 0x2f48, 0x73773777, 0x12010001, 307 0x2408, 0x00030000, 0x000c007f, 308 0x8a14, 0xf000003f, 0x00000007, 309 0x8b24, 0x3fff3fff, 0x00ff0fff, 310 0x8b10, 0x0000ff0f, 0x00000000, 311 0x28a4c, 0x07ffffff, 0x06000000, 312 0x4d8, 0x00000fff, 0x00000100, 313 0xa008, 0xffffffff, 0x00010000, 314 0x913c, 0xffff03ff, 0x01000100, 315 0x8c00, 0x000000ff, 0x00000003, 316 0x8c04, 0xf8ff00ff, 0x40600060, 317 0x8cf0, 0x1fff1fff, 0x08e00410, 318 0x28350, 0x00000f01, 0x00000000, 319 0x9508, 0xf700071f, 0x00000002, 320 0x960c, 0xffffffff, 0x54763210, 321 0x20ef8, 0x01ff01ff, 0x00000002, 322 0x20e98, 0xfffffbff, 0x00200000, 323 0x2015c, 0xffffffff, 0x00000f40, 324 0x88c4, 0x001f3ae3, 0x00000082, 325 0x8978, 0x3fffffff, 0x04050140, 326 0x88d4, 0x0000001f, 0x00000010, 327 0x8974, 0xffffffff, 0x00000000 328 }; 329 330 static const u32 scrapper_golden_registers[] = 331 { 332 0x690, 0x3fff3fff, 0x20c00033, 333 0x918c, 0x0fff0fff, 0x00010006, 334 0x918c, 0x0fff0fff, 0x00010006, 335 0x91a8, 0x0fff0fff, 0x00010006, 336 0x91a8, 0x0fff0fff, 0x00010006, 337 0x9150, 0xffffdfff, 0x6e944040, 338 0x9150, 0xffffdfff, 0x6e944040, 339 0x917c, 0x0fff0fff, 0x00030002, 340 0x917c, 0x0fff0fff, 0x00030002, 341 0x9198, 0x0fff0fff, 0x00030002, 342 0x9198, 0x0fff0fff, 0x00030002, 343 0x915c, 0x0fff0fff, 0x00010000, 344 0x915c, 0x0fff0fff, 0x00010000, 345 0x3f90, 0xffff0001, 0xff000000, 346 0x3f90, 0xffff0001, 0xff000000, 347 0x9178, 0x0fff0fff, 0x00070000, 348 0x9178, 0x0fff0fff, 0x00070000, 349 0x9194, 0x0fff0fff, 0x00070000, 350 0x9194, 0x0fff0fff, 0x00070000, 351 0x9148, 0xffff0001, 0xff000000, 352 0x9148, 0xffff0001, 0xff000000, 353 0x9190, 0x0fff0fff, 0x00090008, 354 0x9190, 0x0fff0fff, 0x00090008, 355 0x91ac, 0x0fff0fff, 0x00090008, 356 0x91ac, 0x0fff0fff, 0x00090008, 357 0x3f94, 0xffff0000, 0xff000000, 358 0x3f94, 0xffff0000, 0xff000000, 359 0x914c, 0xffff0000, 0xff000000, 360 0x914c, 0xffff0000, 0xff000000, 361 0x929c, 0x00000fff, 0x00000001, 362 0x929c, 0x00000fff, 0x00000001, 363 0x55e4, 0xff607fff, 0xfc000100, 364 0x8a18, 0xff000fff, 0x00000100, 365 0x8a18, 0xff000fff, 0x00000100, 366 0x8b28, 0xff000fff, 0x00000100, 367 0x8b28, 0xff000fff, 0x00000100, 368 0x9144, 0xfffc0fff, 0x00000100, 369 0x9144, 0xfffc0fff, 0x00000100, 370 0x6ed8, 0x00010101, 0x00010000, 371 0x9830, 0xffffffff, 0x00000000, 372 0x9830, 0xffffffff, 0x00000000, 373 0x9834, 0xf00fffff, 0x00000400, 374 0x9834, 0xf00fffff, 0x00000400, 375 0x9838, 0xfffffffe, 0x00000000, 376 0x9838, 0xfffffffe, 0x00000000, 377 0xd0c0, 0xff000fff, 0x00000100, 378 0xd02c, 0xbfffff1f, 0x08421000, 379 0xd02c, 0xbfffff1f, 0x08421000, 380 0xd0b8, 0x73773777, 0x12010001, 381 0xd0b8, 0x73773777, 0x12010001, 382 0x5bb0, 0x000000f0, 0x00000070, 383 0x98f8, 0x73773777, 0x12010001, 384 0x98f8, 0x73773777, 0x12010001, 385 0x98fc, 0xffffffff, 0x00000010, 386 0x98fc, 0xffffffff, 0x00000010, 387 0x9b7c, 0x00ff0000, 0x00fc0000, 388 0x9b7c, 0x00ff0000, 0x00fc0000, 389 0x8030, 0x00001f0f, 0x0000100a, 390 0x8030, 0x00001f0f, 0x0000100a, 391 0x2f48, 0x73773777, 0x12010001, 392 0x2f48, 0x73773777, 0x12010001, 393 0x2408, 0x00030000, 0x000c007f, 394 0x8a14, 0xf000003f, 0x00000007, 395 0x8a14, 0xf000003f, 0x00000007, 396 0x8b24, 0x3fff3fff, 0x00ff0fff, 397 0x8b24, 0x3fff3fff, 0x00ff0fff, 398 0x8b10, 0x0000ff0f, 0x00000000, 399 0x8b10, 0x0000ff0f, 0x00000000, 400 0x28a4c, 0x07ffffff, 0x06000000, 401 0x28a4c, 0x07ffffff, 0x06000000, 402 0x4d8, 0x00000fff, 0x00000100, 403 0x4d8, 0x00000fff, 0x00000100, 404 0xa008, 0xffffffff, 0x00010000, 405 0xa008, 0xffffffff, 0x00010000, 406 0x913c, 0xffff03ff, 0x01000100, 407 0x913c, 0xffff03ff, 0x01000100, 408 0x90e8, 0x001fffff, 0x010400c0, 409 0x8c00, 0x000000ff, 0x00000003, 410 0x8c00, 0x000000ff, 0x00000003, 411 0x8c04, 0xf8ff00ff, 0x40600060, 412 0x8c04, 0xf8ff00ff, 0x40600060, 413 0x8c30, 0x0000000f, 0x00040005, 414 0x8cf0, 0x1fff1fff, 0x08e00410, 415 0x8cf0, 0x1fff1fff, 0x08e00410, 416 0x900c, 0x00ffffff, 0x0017071f, 417 0x28350, 0x00000f01, 0x00000000, 418 0x28350, 0x00000f01, 0x00000000, 419 0x9508, 0xf700071f, 0x00000002, 420 0x9508, 0xf700071f, 0x00000002, 421 0x9688, 0x00300000, 0x0017000f, 422 0x960c, 0xffffffff, 0x54763210, 423 0x960c, 0xffffffff, 0x54763210, 424 0x20ef8, 0x01ff01ff, 0x00000002, 425 0x20e98, 0xfffffbff, 0x00200000, 426 0x2015c, 0xffffffff, 0x00000f40, 427 0x88c4, 0x001f3ae3, 0x00000082, 428 0x88c4, 0x001f3ae3, 0x00000082, 429 0x8978, 0x3fffffff, 0x04050140, 430 0x8978, 0x3fffffff, 0x04050140, 431 0x88d4, 0x0000001f, 0x00000010, 432 0x88d4, 0x0000001f, 0x00000010, 433 0x8974, 0xffffffff, 0x00000000, 434 0x8974, 0xffffffff, 0x00000000 435 }; 436 437 static void ni_init_golden_registers(struct radeon_device *rdev) 438 { 439 switch (rdev->family) { 440 case CHIP_CAYMAN: 441 radeon_program_register_sequence(rdev, 442 cayman_golden_registers, 443 (const u32)ARRAY_SIZE(cayman_golden_registers)); 444 radeon_program_register_sequence(rdev, 445 cayman_golden_registers2, 446 (const u32)ARRAY_SIZE(cayman_golden_registers2)); 447 break; 448 case CHIP_ARUBA: 449 if ((rdev->pdev->device == 0x9900) || 450 (rdev->pdev->device == 0x9901) || 451 (rdev->pdev->device == 0x9903) || 452 (rdev->pdev->device == 0x9904) || 453 (rdev->pdev->device == 0x9905) || 454 (rdev->pdev->device == 0x9906) || 455 (rdev->pdev->device == 0x9907) || 456 (rdev->pdev->device == 0x9908) || 457 (rdev->pdev->device == 0x9909) || 458 (rdev->pdev->device == 0x990A) || 459 (rdev->pdev->device == 0x990B) || 460 (rdev->pdev->device == 0x990C) || 461 (rdev->pdev->device == 0x990D) || 462 (rdev->pdev->device == 0x990E) || 463 (rdev->pdev->device == 0x990F) || 464 (rdev->pdev->device == 0x9910) || 465 (rdev->pdev->device == 0x9913) || 466 (rdev->pdev->device == 0x9917) || 467 (rdev->pdev->device == 0x9918)) { 468 radeon_program_register_sequence(rdev, 469 dvst_golden_registers, 470 (const u32)ARRAY_SIZE(dvst_golden_registers)); 471 radeon_program_register_sequence(rdev, 472 dvst_golden_registers2, 473 (const u32)ARRAY_SIZE(dvst_golden_registers2)); 474 } else { 475 radeon_program_register_sequence(rdev, 476 scrapper_golden_registers, 477 (const u32)ARRAY_SIZE(scrapper_golden_registers)); 478 radeon_program_register_sequence(rdev, 479 dvst_golden_registers2, 480 (const u32)ARRAY_SIZE(dvst_golden_registers2)); 481 } 482 break; 483 default: 484 break; 485 } 486 } 487 488 #define BTC_IO_MC_REGS_SIZE 29 489 490 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 491 {0x00000077, 0xff010100}, 492 {0x00000078, 0x00000000}, 493 {0x00000079, 0x00001434}, 494 {0x0000007a, 0xcc08ec08}, 495 {0x0000007b, 0x00040000}, 496 {0x0000007c, 0x000080c0}, 497 {0x0000007d, 0x09000000}, 498 {0x0000007e, 0x00210404}, 499 {0x00000081, 0x08a8e800}, 500 {0x00000082, 0x00030444}, 501 {0x00000083, 0x00000000}, 502 {0x00000085, 0x00000001}, 503 {0x00000086, 0x00000002}, 504 {0x00000087, 0x48490000}, 505 {0x00000088, 0x20244647}, 506 {0x00000089, 0x00000005}, 507 {0x0000008b, 0x66030000}, 508 {0x0000008c, 0x00006603}, 509 {0x0000008d, 0x00000100}, 510 {0x0000008f, 0x00001c0a}, 511 {0x00000090, 0xff000001}, 512 {0x00000094, 0x00101101}, 513 {0x00000095, 0x00000fff}, 514 {0x00000096, 0x00116fff}, 515 {0x00000097, 0x60010000}, 516 {0x00000098, 0x10010000}, 517 {0x00000099, 0x00006000}, 518 {0x0000009a, 0x00001000}, 519 {0x0000009f, 0x00946a00} 520 }; 521 522 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 523 {0x00000077, 0xff010100}, 524 {0x00000078, 0x00000000}, 525 {0x00000079, 0x00001434}, 526 {0x0000007a, 0xcc08ec08}, 527 {0x0000007b, 0x00040000}, 528 {0x0000007c, 0x000080c0}, 529 {0x0000007d, 0x09000000}, 530 {0x0000007e, 0x00210404}, 531 {0x00000081, 0x08a8e800}, 532 {0x00000082, 0x00030444}, 533 {0x00000083, 0x00000000}, 534 {0x00000085, 0x00000001}, 535 {0x00000086, 0x00000002}, 536 {0x00000087, 0x48490000}, 537 {0x00000088, 0x20244647}, 538 {0x00000089, 0x00000005}, 539 {0x0000008b, 0x66030000}, 540 {0x0000008c, 0x00006603}, 541 {0x0000008d, 0x00000100}, 542 {0x0000008f, 0x00001c0a}, 543 {0x00000090, 0xff000001}, 544 {0x00000094, 0x00101101}, 545 {0x00000095, 0x00000fff}, 546 {0x00000096, 0x00116fff}, 547 {0x00000097, 0x60010000}, 548 {0x00000098, 0x10010000}, 549 {0x00000099, 0x00006000}, 550 {0x0000009a, 0x00001000}, 551 {0x0000009f, 0x00936a00} 552 }; 553 554 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 555 {0x00000077, 0xff010100}, 556 {0x00000078, 0x00000000}, 557 {0x00000079, 0x00001434}, 558 {0x0000007a, 0xcc08ec08}, 559 {0x0000007b, 0x00040000}, 560 {0x0000007c, 0x000080c0}, 561 {0x0000007d, 0x09000000}, 562 {0x0000007e, 0x00210404}, 563 {0x00000081, 0x08a8e800}, 564 {0x00000082, 0x00030444}, 565 {0x00000083, 0x00000000}, 566 {0x00000085, 0x00000001}, 567 {0x00000086, 0x00000002}, 568 {0x00000087, 0x48490000}, 569 {0x00000088, 0x20244647}, 570 {0x00000089, 0x00000005}, 571 {0x0000008b, 0x66030000}, 572 {0x0000008c, 0x00006603}, 573 {0x0000008d, 0x00000100}, 574 {0x0000008f, 0x00001c0a}, 575 {0x00000090, 0xff000001}, 576 {0x00000094, 0x00101101}, 577 {0x00000095, 0x00000fff}, 578 {0x00000096, 0x00116fff}, 579 {0x00000097, 0x60010000}, 580 {0x00000098, 0x10010000}, 581 {0x00000099, 0x00006000}, 582 {0x0000009a, 0x00001000}, 583 {0x0000009f, 0x00916a00} 584 }; 585 586 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 587 {0x00000077, 0xff010100}, 588 {0x00000078, 0x00000000}, 589 {0x00000079, 0x00001434}, 590 {0x0000007a, 0xcc08ec08}, 591 {0x0000007b, 0x00040000}, 592 {0x0000007c, 0x000080c0}, 593 {0x0000007d, 0x09000000}, 594 {0x0000007e, 0x00210404}, 595 {0x00000081, 0x08a8e800}, 596 {0x00000082, 0x00030444}, 597 {0x00000083, 0x00000000}, 598 {0x00000085, 0x00000001}, 599 {0x00000086, 0x00000002}, 600 {0x00000087, 0x48490000}, 601 {0x00000088, 0x20244647}, 602 {0x00000089, 0x00000005}, 603 {0x0000008b, 0x66030000}, 604 {0x0000008c, 0x00006603}, 605 {0x0000008d, 0x00000100}, 606 {0x0000008f, 0x00001c0a}, 607 {0x00000090, 0xff000001}, 608 {0x00000094, 0x00101101}, 609 {0x00000095, 0x00000fff}, 610 {0x00000096, 0x00116fff}, 611 {0x00000097, 0x60010000}, 612 {0x00000098, 0x10010000}, 613 {0x00000099, 0x00006000}, 614 {0x0000009a, 0x00001000}, 615 {0x0000009f, 0x00976b00} 616 }; 617 618 int ni_mc_load_microcode(struct radeon_device *rdev) 619 { 620 const __be32 *fw_data; 621 u32 mem_type, running, blackout = 0; 622 u32 *io_mc_regs; 623 int i, ucode_size, regs_size; 624 625 if (!rdev->mc_fw) 626 return -EINVAL; 627 628 switch (rdev->family) { 629 case CHIP_BARTS: 630 io_mc_regs = (u32 *)&barts_io_mc_regs; 631 ucode_size = BTC_MC_UCODE_SIZE; 632 regs_size = BTC_IO_MC_REGS_SIZE; 633 break; 634 case CHIP_TURKS: 635 io_mc_regs = (u32 *)&turks_io_mc_regs; 636 ucode_size = BTC_MC_UCODE_SIZE; 637 regs_size = BTC_IO_MC_REGS_SIZE; 638 break; 639 case CHIP_CAICOS: 640 default: 641 io_mc_regs = (u32 *)&caicos_io_mc_regs; 642 ucode_size = BTC_MC_UCODE_SIZE; 643 regs_size = BTC_IO_MC_REGS_SIZE; 644 break; 645 case CHIP_CAYMAN: 646 io_mc_regs = (u32 *)&cayman_io_mc_regs; 647 ucode_size = CAYMAN_MC_UCODE_SIZE; 648 regs_size = BTC_IO_MC_REGS_SIZE; 649 break; 650 } 651 652 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; 653 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 654 655 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) { 656 if (running) { 657 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 658 WREG32(MC_SHARED_BLACKOUT_CNTL, 1); 659 } 660 661 /* reset the engine and set to writable */ 662 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 663 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 664 665 /* load mc io regs */ 666 for (i = 0; i < regs_size; i++) { 667 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); 668 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); 669 } 670 /* load the MC ucode */ 671 fw_data = (const __be32 *)rdev->mc_fw->data; 672 for (i = 0; i < ucode_size; i++) 673 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); 674 675 /* put the engine back into the active state */ 676 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 677 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); 678 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); 679 680 /* wait for training to complete */ 681 for (i = 0; i < rdev->usec_timeout; i++) { 682 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) 683 break; 684 udelay(1); 685 } 686 687 if (running) 688 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); 689 } 690 691 return 0; 692 } 693 694 int ni_init_microcode(struct radeon_device *rdev) 695 { 696 const char *chip_name; 697 const char *rlc_chip_name; 698 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size; 699 size_t smc_req_size = 0; 700 char fw_name[30]; 701 int err; 702 703 DRM_DEBUG("\n"); 704 705 switch (rdev->family) { 706 case CHIP_BARTS: 707 chip_name = "BARTS"; 708 rlc_chip_name = "BTC"; 709 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 710 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 711 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 712 mc_req_size = BTC_MC_UCODE_SIZE * 4; 713 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4); 714 break; 715 case CHIP_TURKS: 716 chip_name = "TURKS"; 717 rlc_chip_name = "BTC"; 718 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 719 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 720 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 721 mc_req_size = BTC_MC_UCODE_SIZE * 4; 722 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4); 723 break; 724 case CHIP_CAICOS: 725 chip_name = "CAICOS"; 726 rlc_chip_name = "BTC"; 727 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 728 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 729 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 730 mc_req_size = BTC_MC_UCODE_SIZE * 4; 731 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4); 732 break; 733 case CHIP_CAYMAN: 734 chip_name = "CAYMAN"; 735 rlc_chip_name = "CAYMAN"; 736 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; 737 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; 738 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; 739 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; 740 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4); 741 break; 742 case CHIP_ARUBA: 743 chip_name = "ARUBA"; 744 rlc_chip_name = "ARUBA"; 745 /* pfp/me same size as CAYMAN */ 746 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; 747 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; 748 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4; 749 mc_req_size = 0; 750 break; 751 default: BUG(); 752 } 753 754 DRM_INFO("Loading %s Microcode\n", chip_name); 755 756 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name); 757 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 758 if (err) 759 goto out; 760 if (rdev->pfp_fw->datasize != pfp_req_size) { 761 printk(KERN_ERR 762 "ni_pfp: Bogus length %zu in firmware \"%s\"\n", 763 rdev->pfp_fw->datasize, fw_name); 764 err = -EINVAL; 765 goto out; 766 } 767 768 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name); 769 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 770 if (err) 771 goto out; 772 if (rdev->me_fw->datasize != me_req_size) { 773 printk(KERN_ERR 774 "ni_me: Bogus length %zu in firmware \"%s\"\n", 775 rdev->me_fw->datasize, fw_name); 776 err = -EINVAL; 777 } 778 779 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", 780 rlc_chip_name); 781 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 782 if (err) 783 goto out; 784 if (rdev->rlc_fw->datasize != rlc_req_size) { 785 printk(KERN_ERR 786 "ni_rlc: Bogus length %zu in firmware \"%s\"\n", 787 rdev->rlc_fw->datasize, fw_name); 788 err = -EINVAL; 789 } 790 791 /* no MC ucode on TN */ 792 if (!(rdev->flags & RADEON_IS_IGP)) { 793 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mc", chip_name); 794 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); 795 if (err) 796 goto out; 797 if (rdev->mc_fw->datasize != mc_req_size) { 798 printk(KERN_ERR 799 "ni_mc: Bogus length %zu in firmware \"%s\"\n", 800 rdev->mc_fw->datasize, fw_name); 801 err = -EINVAL; 802 } 803 } 804 805 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) { 806 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", chip_name); 807 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 808 if (err) { 809 printk(KERN_ERR 810 "smc: error loading firmware \"%s\"\n", 811 fw_name); 812 release_firmware(rdev->smc_fw); 813 rdev->smc_fw = NULL; 814 err = 0; 815 } else if (rdev->smc_fw->datasize != smc_req_size) { 816 printk(KERN_ERR 817 "ni_smc: Bogus length %zu in firmware \"%s\"\n", 818 rdev->smc_fw->datasize, fw_name); 819 err = -EINVAL; 820 } 821 } 822 823 out: 824 if (err) { 825 if (err != -EINVAL) 826 printk(KERN_ERR 827 "ni_cp: Failed to load firmware \"%s\"\n", 828 fw_name); 829 release_firmware(rdev->pfp_fw); 830 rdev->pfp_fw = NULL; 831 release_firmware(rdev->me_fw); 832 rdev->me_fw = NULL; 833 release_firmware(rdev->rlc_fw); 834 rdev->rlc_fw = NULL; 835 release_firmware(rdev->mc_fw); 836 rdev->mc_fw = NULL; 837 release_firmware(rdev->smc_fw); 838 rdev->smc_fw = NULL; 839 } 840 return err; 841 } 842 843 /** 844 * ni_fini_microcode - drop the firmwares image references 845 * 846 * @rdev: radeon_device pointer 847 * 848 * Drop the pfp, me, mc and rlc firmwares image references. 849 * Called at driver shutdown. 850 */ 851 void ni_fini_microcode(struct radeon_device *rdev) 852 { 853 release_firmware(rdev->pfp_fw); 854 rdev->pfp_fw = NULL; 855 release_firmware(rdev->me_fw); 856 rdev->me_fw = NULL; 857 release_firmware(rdev->rlc_fw); 858 rdev->rlc_fw = NULL; 859 release_firmware(rdev->mc_fw); 860 rdev->mc_fw = NULL; 861 release_firmware(rdev->smc_fw); 862 rdev->smc_fw = NULL; 863 } 864 865 /** 866 * cayman_get_allowed_info_register - fetch the register for the info ioctl 867 * 868 * @rdev: radeon_device pointer 869 * @reg: register offset in bytes 870 * @val: register value 871 * 872 * Returns 0 for success or -EINVAL for an invalid register 873 * 874 */ 875 int cayman_get_allowed_info_register(struct radeon_device *rdev, 876 u32 reg, u32 *val) 877 { 878 switch (reg) { 879 case GRBM_STATUS: 880 case GRBM_STATUS_SE0: 881 case GRBM_STATUS_SE1: 882 case SRBM_STATUS: 883 case SRBM_STATUS2: 884 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): 885 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): 886 case UVD_STATUS: 887 *val = RREG32(reg); 888 return 0; 889 default: 890 return -EINVAL; 891 } 892 } 893 894 int tn_get_temp(struct radeon_device *rdev) 895 { 896 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; 897 int actual_temp = (temp / 8) - 49; 898 899 return actual_temp * 1000; 900 } 901 902 /* 903 * Core functions 904 */ 905 static void cayman_gpu_init(struct radeon_device *rdev) 906 { 907 u32 gb_addr_config = 0; 908 u32 mc_shared_chmap, mc_arb_ramcfg; 909 u32 cgts_tcc_disable; 910 u32 sx_debug_1; 911 u32 smx_dc_ctl0; 912 u32 cgts_sm_ctrl_reg; 913 u32 hdp_host_path_cntl; 914 u32 tmp; 915 u32 disabled_rb_mask; 916 int i, j; 917 918 switch (rdev->family) { 919 case CHIP_CAYMAN: 920 rdev->config.cayman.max_shader_engines = 2; 921 rdev->config.cayman.max_pipes_per_simd = 4; 922 rdev->config.cayman.max_tile_pipes = 8; 923 rdev->config.cayman.max_simds_per_se = 12; 924 rdev->config.cayman.max_backends_per_se = 4; 925 rdev->config.cayman.max_texture_channel_caches = 8; 926 rdev->config.cayman.max_gprs = 256; 927 rdev->config.cayman.max_threads = 256; 928 rdev->config.cayman.max_gs_threads = 32; 929 rdev->config.cayman.max_stack_entries = 512; 930 rdev->config.cayman.sx_num_of_sets = 8; 931 rdev->config.cayman.sx_max_export_size = 256; 932 rdev->config.cayman.sx_max_export_pos_size = 64; 933 rdev->config.cayman.sx_max_export_smx_size = 192; 934 rdev->config.cayman.max_hw_contexts = 8; 935 rdev->config.cayman.sq_num_cf_insts = 2; 936 937 rdev->config.cayman.sc_prim_fifo_size = 0x100; 938 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 939 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 940 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN; 941 break; 942 case CHIP_ARUBA: 943 default: 944 rdev->config.cayman.max_shader_engines = 1; 945 rdev->config.cayman.max_pipes_per_simd = 4; 946 rdev->config.cayman.max_tile_pipes = 2; 947 if ((rdev->pdev->device == 0x9900) || 948 (rdev->pdev->device == 0x9901) || 949 (rdev->pdev->device == 0x9905) || 950 (rdev->pdev->device == 0x9906) || 951 (rdev->pdev->device == 0x9907) || 952 (rdev->pdev->device == 0x9908) || 953 (rdev->pdev->device == 0x9909) || 954 (rdev->pdev->device == 0x990B) || 955 (rdev->pdev->device == 0x990C) || 956 (rdev->pdev->device == 0x990F) || 957 (rdev->pdev->device == 0x9910) || 958 (rdev->pdev->device == 0x9917) || 959 (rdev->pdev->device == 0x9999) || 960 (rdev->pdev->device == 0x999C)) { 961 rdev->config.cayman.max_simds_per_se = 6; 962 rdev->config.cayman.max_backends_per_se = 2; 963 rdev->config.cayman.max_hw_contexts = 8; 964 rdev->config.cayman.sx_max_export_size = 256; 965 rdev->config.cayman.sx_max_export_pos_size = 64; 966 rdev->config.cayman.sx_max_export_smx_size = 192; 967 } else if ((rdev->pdev->device == 0x9903) || 968 (rdev->pdev->device == 0x9904) || 969 (rdev->pdev->device == 0x990A) || 970 (rdev->pdev->device == 0x990D) || 971 (rdev->pdev->device == 0x990E) || 972 (rdev->pdev->device == 0x9913) || 973 (rdev->pdev->device == 0x9918) || 974 (rdev->pdev->device == 0x999D)) { 975 rdev->config.cayman.max_simds_per_se = 4; 976 rdev->config.cayman.max_backends_per_se = 2; 977 rdev->config.cayman.max_hw_contexts = 8; 978 rdev->config.cayman.sx_max_export_size = 256; 979 rdev->config.cayman.sx_max_export_pos_size = 64; 980 rdev->config.cayman.sx_max_export_smx_size = 192; 981 } else if ((rdev->pdev->device == 0x9919) || 982 (rdev->pdev->device == 0x9990) || 983 (rdev->pdev->device == 0x9991) || 984 (rdev->pdev->device == 0x9994) || 985 (rdev->pdev->device == 0x9995) || 986 (rdev->pdev->device == 0x9996) || 987 (rdev->pdev->device == 0x999A) || 988 (rdev->pdev->device == 0x99A0)) { 989 rdev->config.cayman.max_simds_per_se = 3; 990 rdev->config.cayman.max_backends_per_se = 1; 991 rdev->config.cayman.max_hw_contexts = 4; 992 rdev->config.cayman.sx_max_export_size = 128; 993 rdev->config.cayman.sx_max_export_pos_size = 32; 994 rdev->config.cayman.sx_max_export_smx_size = 96; 995 } else { 996 rdev->config.cayman.max_simds_per_se = 2; 997 rdev->config.cayman.max_backends_per_se = 1; 998 rdev->config.cayman.max_hw_contexts = 4; 999 rdev->config.cayman.sx_max_export_size = 128; 1000 rdev->config.cayman.sx_max_export_pos_size = 32; 1001 rdev->config.cayman.sx_max_export_smx_size = 96; 1002 } 1003 rdev->config.cayman.max_texture_channel_caches = 2; 1004 rdev->config.cayman.max_gprs = 256; 1005 rdev->config.cayman.max_threads = 256; 1006 rdev->config.cayman.max_gs_threads = 32; 1007 rdev->config.cayman.max_stack_entries = 512; 1008 rdev->config.cayman.sx_num_of_sets = 8; 1009 rdev->config.cayman.sq_num_cf_insts = 2; 1010 1011 rdev->config.cayman.sc_prim_fifo_size = 0x40; 1012 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; 1013 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; 1014 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN; 1015 break; 1016 } 1017 1018 /* Initialize HDP */ 1019 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1020 WREG32((0x2c14 + j), 0x00000000); 1021 WREG32((0x2c18 + j), 0x00000000); 1022 WREG32((0x2c1c + j), 0x00000000); 1023 WREG32((0x2c20 + j), 0x00000000); 1024 WREG32((0x2c24 + j), 0x00000000); 1025 } 1026 1027 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1028 WREG32(SRBM_INT_CNTL, 0x1); 1029 WREG32(SRBM_INT_ACK, 0x1); 1030 1031 evergreen_fix_pci_max_read_req_size(rdev); 1032 1033 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1034 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1035 1036 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 1037 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1038 if (rdev->config.cayman.mem_row_size_in_kb > 4) 1039 rdev->config.cayman.mem_row_size_in_kb = 4; 1040 /* XXX use MC settings? */ 1041 rdev->config.cayman.shader_engine_tile_size = 32; 1042 rdev->config.cayman.num_gpus = 1; 1043 rdev->config.cayman.multi_gpu_tile_size = 64; 1044 1045 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; 1046 rdev->config.cayman.num_tile_pipes = (1 << tmp); 1047 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; 1048 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; 1049 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; 1050 rdev->config.cayman.num_shader_engines = tmp + 1; 1051 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; 1052 rdev->config.cayman.num_gpus = tmp + 1; 1053 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; 1054 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; 1055 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; 1056 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; 1057 1058 1059 /* setup tiling info dword. gb_addr_config is not adequate since it does 1060 * not have bank info, so create a custom tiling dword. 1061 * bits 3:0 num_pipes 1062 * bits 7:4 num_banks 1063 * bits 11:8 group_size 1064 * bits 15:12 row_size 1065 */ 1066 rdev->config.cayman.tile_config = 0; 1067 switch (rdev->config.cayman.num_tile_pipes) { 1068 case 1: 1069 default: 1070 rdev->config.cayman.tile_config |= (0 << 0); 1071 break; 1072 case 2: 1073 rdev->config.cayman.tile_config |= (1 << 0); 1074 break; 1075 case 4: 1076 rdev->config.cayman.tile_config |= (2 << 0); 1077 break; 1078 case 8: 1079 rdev->config.cayman.tile_config |= (3 << 0); 1080 break; 1081 } 1082 1083 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ 1084 if (rdev->flags & RADEON_IS_IGP) 1085 rdev->config.cayman.tile_config |= 1 << 4; 1086 else { 1087 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { 1088 case 0: /* four banks */ 1089 rdev->config.cayman.tile_config |= 0 << 4; 1090 break; 1091 case 1: /* eight banks */ 1092 rdev->config.cayman.tile_config |= 1 << 4; 1093 break; 1094 case 2: /* sixteen banks */ 1095 default: 1096 rdev->config.cayman.tile_config |= 2 << 4; 1097 break; 1098 } 1099 } 1100 rdev->config.cayman.tile_config |= 1101 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 1102 rdev->config.cayman.tile_config |= 1103 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 1104 1105 tmp = 0; 1106 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) { 1107 u32 rb_disable_bitmap; 1108 1109 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1110 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1111 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; 1112 tmp <<= 4; 1113 tmp |= rb_disable_bitmap; 1114 } 1115 /* enabled rb are just the one not disabled :) */ 1116 disabled_rb_mask = tmp; 1117 tmp = 0; 1118 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++) 1119 tmp |= (1 << i); 1120 /* if all the backends are disabled, fix it up here */ 1121 if ((disabled_rb_mask & tmp) == tmp) { 1122 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++) 1123 disabled_rb_mask &= ~(1 << i); 1124 } 1125 1126 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) { 1127 u32 simd_disable_bitmap; 1128 1129 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1130 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1131 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; 1132 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se; 1133 tmp <<= 16; 1134 tmp |= simd_disable_bitmap; 1135 } 1136 rdev->config.cayman.active_simds = hweight32(~tmp); 1137 1138 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 1139 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 1140 1141 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1142 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1143 if (ASIC_IS_DCE6(rdev)) 1144 WREG32(DMIF_ADDR_CALC, gb_addr_config); 1145 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1146 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1147 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1148 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); 1149 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1150 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1151 1152 if ((rdev->config.cayman.max_backends_per_se == 1) && 1153 (rdev->flags & RADEON_IS_IGP)) { 1154 if ((disabled_rb_mask & 3) == 2) { 1155 /* RB1 disabled, RB0 enabled */ 1156 tmp = 0x00000000; 1157 } else { 1158 /* RB0 disabled, RB1 enabled */ 1159 tmp = 0x11111111; 1160 } 1161 } else { 1162 tmp = gb_addr_config & NUM_PIPES_MASK; 1163 tmp = r6xx_remap_render_backend(rdev, tmp, 1164 rdev->config.cayman.max_backends_per_se * 1165 rdev->config.cayman.max_shader_engines, 1166 CAYMAN_MAX_BACKENDS, disabled_rb_mask); 1167 } 1168 WREG32(GB_BACKEND_MAP, tmp); 1169 1170 cgts_tcc_disable = 0xffff0000; 1171 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) 1172 cgts_tcc_disable &= ~(1 << (16 + i)); 1173 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); 1174 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); 1175 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); 1176 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); 1177 1178 /* reprogram the shader complex */ 1179 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG); 1180 for (i = 0; i < 16; i++) 1181 WREG32(CGTS_SM_CTRL_REG, OVERRIDE); 1182 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); 1183 1184 /* set HW defaults for 3D engine */ 1185 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); 1186 1187 sx_debug_1 = RREG32(SX_DEBUG_1); 1188 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 1189 WREG32(SX_DEBUG_1, sx_debug_1); 1190 1191 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 1192 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); 1193 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); 1194 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 1195 1196 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); 1197 1198 /* need to be explicitly zero-ed */ 1199 WREG32(VGT_OFFCHIP_LDS_BASE, 0); 1200 WREG32(SQ_LSTMP_RING_BASE, 0); 1201 WREG32(SQ_HSTMP_RING_BASE, 0); 1202 WREG32(SQ_ESTMP_RING_BASE, 0); 1203 WREG32(SQ_GSTMP_RING_BASE, 0); 1204 WREG32(SQ_VSTMP_RING_BASE, 0); 1205 WREG32(SQ_PSTMP_RING_BASE, 0); 1206 1207 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO); 1208 1209 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) | 1210 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | 1211 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); 1212 1213 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | 1214 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | 1215 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); 1216 1217 1218 WREG32(VGT_NUM_INSTANCES, 1); 1219 1220 WREG32(CP_PERFMON_CNTL, 0); 1221 1222 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | 1223 FETCH_FIFO_HIWATER(0x4) | 1224 DONE_FIFO_HIWATER(0xe0) | 1225 ALU_UPDATE_FIFO_HIWATER(0x8))); 1226 1227 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4)); 1228 WREG32(SQ_CONFIG, (VC_ENABLE | 1229 EXPORT_SRC_C | 1230 GFX_PRIO(0) | 1231 CS1_PRIO(0) | 1232 CS2_PRIO(1))); 1233 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE); 1234 1235 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1236 FORCE_EOV_MAX_REZ_CNT(255))); 1237 1238 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | 1239 AUTO_INVLD_EN(ES_AND_GS_AUTO)); 1240 1241 WREG32(VGT_GS_VERTEX_REUSE, 16); 1242 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1243 1244 WREG32(CB_PERF_CTR0_SEL_0, 0); 1245 WREG32(CB_PERF_CTR0_SEL_1, 0); 1246 WREG32(CB_PERF_CTR1_SEL_0, 0); 1247 WREG32(CB_PERF_CTR1_SEL_1, 0); 1248 WREG32(CB_PERF_CTR2_SEL_0, 0); 1249 WREG32(CB_PERF_CTR2_SEL_1, 0); 1250 WREG32(CB_PERF_CTR3_SEL_0, 0); 1251 WREG32(CB_PERF_CTR3_SEL_1, 0); 1252 1253 tmp = RREG32(HDP_MISC_CNTL); 1254 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 1255 WREG32(HDP_MISC_CNTL, tmp); 1256 1257 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1258 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1259 1260 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 1261 1262 udelay(50); 1263 1264 /* set clockgating golden values on TN */ 1265 if (rdev->family == CHIP_ARUBA) { 1266 tmp = RREG32_CG(CG_CGTT_LOCAL_0); 1267 tmp &= ~0x00380000; 1268 WREG32_CG(CG_CGTT_LOCAL_0, tmp); 1269 tmp = RREG32_CG(CG_CGTT_LOCAL_1); 1270 tmp &= ~0x0e000000; 1271 WREG32_CG(CG_CGTT_LOCAL_1, tmp); 1272 } 1273 } 1274 1275 /* 1276 * GART 1277 */ 1278 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) 1279 { 1280 /* flush hdp cache */ 1281 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1282 1283 /* bits 0-7 are the VM contexts0-7 */ 1284 WREG32(VM_INVALIDATE_REQUEST, 1); 1285 } 1286 1287 static int cayman_pcie_gart_enable(struct radeon_device *rdev) 1288 { 1289 int i, r; 1290 1291 if (rdev->gart.robj == NULL) { 1292 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1293 return -EINVAL; 1294 } 1295 r = radeon_gart_table_vram_pin(rdev); 1296 if (r) 1297 return r; 1298 /* Setup TLB control */ 1299 WREG32(MC_VM_MX_L1_TLB_CNTL, 1300 (0xA << 7) | 1301 ENABLE_L1_TLB | 1302 ENABLE_L1_FRAGMENT_PROCESSING | 1303 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1304 ENABLE_ADVANCED_DRIVER_MODEL | 1305 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 1306 /* Setup L2 cache */ 1307 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | 1308 ENABLE_L2_FRAGMENT_PROCESSING | 1309 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1310 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 1311 EFFECTIVE_L2_QUEUE_SIZE(7) | 1312 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 1313 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); 1314 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 1315 BANK_SELECT(6) | 1316 L2_CACHE_BIGK_FRAGMENT_SIZE(6)); 1317 /* setup context0 */ 1318 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1319 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1320 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1321 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1322 (u32)(rdev->dummy_page.addr >> 12)); 1323 WREG32(VM_CONTEXT0_CNTL2, 0); 1324 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1325 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1326 1327 WREG32(0x15D4, 0); 1328 WREG32(0x15D8, 0); 1329 WREG32(0x15DC, 0); 1330 1331 /* empty context1-7 */ 1332 /* Assign the pt base to something valid for now; the pts used for 1333 * the VMs are determined by the application and setup and assigned 1334 * on the fly in the vm part of radeon_gart.c 1335 */ 1336 for (i = 1; i < 8; i++) { 1337 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); 1338 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 1339 rdev->vm_manager.max_pfn - 1); 1340 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 1341 rdev->vm_manager.saved_table_addr[i]); 1342 } 1343 1344 /* enable context1-7 */ 1345 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 1346 (u32)(rdev->dummy_page.addr >> 12)); 1347 WREG32(VM_CONTEXT1_CNTL2, 4); 1348 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | 1349 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) | 1350 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 1351 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | 1352 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 1353 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | 1354 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | 1355 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | 1356 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | 1357 VALID_PROTECTION_FAULT_ENABLE_DEFAULT | 1358 READ_PROTECTION_FAULT_ENABLE_INTERRUPT | 1359 READ_PROTECTION_FAULT_ENABLE_DEFAULT | 1360 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | 1361 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); 1362 1363 cayman_pcie_gart_tlb_flush(rdev); 1364 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1365 (unsigned)(rdev->mc.gtt_size >> 20), 1366 (unsigned long long)rdev->gart.table_addr); 1367 rdev->gart.ready = true; 1368 return 0; 1369 } 1370 1371 static void cayman_pcie_gart_disable(struct radeon_device *rdev) 1372 { 1373 unsigned i; 1374 1375 for (i = 1; i < 8; ++i) { 1376 rdev->vm_manager.saved_table_addr[i] = RREG32( 1377 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2)); 1378 } 1379 1380 /* Disable all tables */ 1381 WREG32(VM_CONTEXT0_CNTL, 0); 1382 WREG32(VM_CONTEXT1_CNTL, 0); 1383 /* Setup TLB control */ 1384 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | 1385 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1386 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 1387 /* Setup L2 cache */ 1388 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1389 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 1390 EFFECTIVE_L2_QUEUE_SIZE(7) | 1391 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 1392 WREG32(VM_L2_CNTL2, 0); 1393 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 1394 L2_CACHE_BIGK_FRAGMENT_SIZE(6)); 1395 radeon_gart_table_vram_unpin(rdev); 1396 } 1397 1398 static void cayman_pcie_gart_fini(struct radeon_device *rdev) 1399 { 1400 cayman_pcie_gart_disable(rdev); 1401 radeon_gart_table_vram_free(rdev); 1402 radeon_gart_fini(rdev); 1403 } 1404 1405 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 1406 int ring, u32 cp_int_cntl) 1407 { 1408 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3; 1409 1410 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3)); 1411 WREG32(CP_INT_CNTL, cp_int_cntl); 1412 } 1413 1414 /* 1415 * CP. 1416 */ 1417 void cayman_fence_ring_emit(struct radeon_device *rdev, 1418 struct radeon_fence *fence) 1419 { 1420 struct radeon_ring *ring = &rdev->ring[fence->ring]; 1421 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 1422 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | 1423 PACKET3_SH_ACTION_ENA; 1424 1425 /* flush read cache over gart for this vmid */ 1426 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1427 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); 1428 radeon_ring_write(ring, 0xFFFFFFFF); 1429 radeon_ring_write(ring, 0); 1430 radeon_ring_write(ring, 10); /* poll interval */ 1431 /* EVENT_WRITE_EOP - flush caches, send int */ 1432 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1433 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 1434 radeon_ring_write(ring, lower_32_bits(addr)); 1435 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 1436 radeon_ring_write(ring, fence->seq); 1437 radeon_ring_write(ring, 0); 1438 } 1439 1440 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1441 { 1442 struct radeon_ring *ring = &rdev->ring[ib->ring]; 1443 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | 1444 PACKET3_SH_ACTION_ENA; 1445 1446 /* set to DX10/11 mode */ 1447 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); 1448 radeon_ring_write(ring, 1); 1449 1450 if (ring->rptr_save_reg) { 1451 uint32_t next_rptr = ring->wptr + 3 + 4 + 8; 1452 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1453 radeon_ring_write(ring, ((ring->rptr_save_reg - 1454 PACKET3_SET_CONFIG_REG_START) >> 2)); 1455 radeon_ring_write(ring, next_rptr); 1456 } 1457 1458 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1459 radeon_ring_write(ring, 1460 #ifdef __BIG_ENDIAN 1461 (2 << 0) | 1462 #endif 1463 (ib->gpu_addr & 0xFFFFFFFC)); 1464 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 1465 radeon_ring_write(ring, ib->length_dw | 1466 (ib->vm ? (ib->vm->id << 24) : 0)); 1467 1468 /* flush read cache over gart for this vmid */ 1469 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1470 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); 1471 radeon_ring_write(ring, 0xFFFFFFFF); 1472 radeon_ring_write(ring, 0); 1473 radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */ 1474 } 1475 1476 static void cayman_cp_enable(struct radeon_device *rdev, bool enable) 1477 { 1478 if (enable) 1479 WREG32(CP_ME_CNTL, 0); 1480 else { 1481 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 1482 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1483 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 1484 WREG32(SCRATCH_UMSK, 0); 1485 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1486 } 1487 } 1488 1489 u32 cayman_gfx_get_rptr(struct radeon_device *rdev, 1490 struct radeon_ring *ring) 1491 { 1492 u32 rptr; 1493 1494 if (rdev->wb.enabled) 1495 rptr = rdev->wb.wb[ring->rptr_offs/4]; 1496 else { 1497 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) 1498 rptr = RREG32(CP_RB0_RPTR); 1499 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) 1500 rptr = RREG32(CP_RB1_RPTR); 1501 else 1502 rptr = RREG32(CP_RB2_RPTR); 1503 } 1504 1505 return rptr; 1506 } 1507 1508 u32 cayman_gfx_get_wptr(struct radeon_device *rdev, 1509 struct radeon_ring *ring) 1510 { 1511 u32 wptr; 1512 1513 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) 1514 wptr = RREG32(CP_RB0_WPTR); 1515 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) 1516 wptr = RREG32(CP_RB1_WPTR); 1517 else 1518 wptr = RREG32(CP_RB2_WPTR); 1519 1520 return wptr; 1521 } 1522 1523 void cayman_gfx_set_wptr(struct radeon_device *rdev, 1524 struct radeon_ring *ring) 1525 { 1526 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) { 1527 WREG32(CP_RB0_WPTR, ring->wptr); 1528 (void)RREG32(CP_RB0_WPTR); 1529 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) { 1530 WREG32(CP_RB1_WPTR, ring->wptr); 1531 (void)RREG32(CP_RB1_WPTR); 1532 } else { 1533 WREG32(CP_RB2_WPTR, ring->wptr); 1534 (void)RREG32(CP_RB2_WPTR); 1535 } 1536 } 1537 1538 static int cayman_cp_load_microcode(struct radeon_device *rdev) 1539 { 1540 const __be32 *fw_data; 1541 int i; 1542 1543 if (!rdev->me_fw || !rdev->pfp_fw) 1544 return -EINVAL; 1545 1546 cayman_cp_enable(rdev, false); 1547 1548 fw_data = (const __be32 *)rdev->pfp_fw->data; 1549 WREG32(CP_PFP_UCODE_ADDR, 0); 1550 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++) 1551 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1552 WREG32(CP_PFP_UCODE_ADDR, 0); 1553 1554 fw_data = (const __be32 *)rdev->me_fw->data; 1555 WREG32(CP_ME_RAM_WADDR, 0); 1556 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++) 1557 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1558 1559 WREG32(CP_PFP_UCODE_ADDR, 0); 1560 WREG32(CP_ME_RAM_WADDR, 0); 1561 WREG32(CP_ME_RAM_RADDR, 0); 1562 return 0; 1563 } 1564 1565 static int cayman_cp_start(struct radeon_device *rdev) 1566 { 1567 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1568 int r, i; 1569 1570 r = radeon_ring_lock(rdev, ring, 7); 1571 if (r) { 1572 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1573 return r; 1574 } 1575 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1576 radeon_ring_write(ring, 0x1); 1577 radeon_ring_write(ring, 0x0); 1578 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); 1579 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1580 radeon_ring_write(ring, 0); 1581 radeon_ring_write(ring, 0); 1582 radeon_ring_unlock_commit(rdev, ring, false); 1583 1584 cayman_cp_enable(rdev, true); 1585 1586 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); 1587 if (r) { 1588 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1589 return r; 1590 } 1591 1592 /* setup clear context state */ 1593 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1594 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1595 1596 for (i = 0; i < cayman_default_size; i++) 1597 radeon_ring_write(ring, cayman_default_state[i]); 1598 1599 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1600 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1601 1602 /* set clear context state */ 1603 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1604 radeon_ring_write(ring, 0); 1605 1606 /* SQ_VTX_BASE_VTX_LOC */ 1607 radeon_ring_write(ring, 0xc0026f00); 1608 radeon_ring_write(ring, 0x00000000); 1609 radeon_ring_write(ring, 0x00000000); 1610 radeon_ring_write(ring, 0x00000000); 1611 1612 /* Clear consts */ 1613 radeon_ring_write(ring, 0xc0036f00); 1614 radeon_ring_write(ring, 0x00000bc4); 1615 radeon_ring_write(ring, 0xffffffff); 1616 radeon_ring_write(ring, 0xffffffff); 1617 radeon_ring_write(ring, 0xffffffff); 1618 1619 radeon_ring_write(ring, 0xc0026900); 1620 radeon_ring_write(ring, 0x00000316); 1621 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1622 radeon_ring_write(ring, 0x00000010); /* */ 1623 1624 radeon_ring_unlock_commit(rdev, ring, false); 1625 1626 /* XXX init other rings */ 1627 1628 return 0; 1629 } 1630 1631 static void cayman_cp_fini(struct radeon_device *rdev) 1632 { 1633 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1634 cayman_cp_enable(rdev, false); 1635 radeon_ring_fini(rdev, ring); 1636 radeon_scratch_free(rdev, ring->rptr_save_reg); 1637 } 1638 1639 static int cayman_cp_resume(struct radeon_device *rdev) 1640 { 1641 static const int ridx[] = { 1642 RADEON_RING_TYPE_GFX_INDEX, 1643 CAYMAN_RING_TYPE_CP1_INDEX, 1644 CAYMAN_RING_TYPE_CP2_INDEX 1645 }; 1646 static const unsigned cp_rb_cntl[] = { 1647 CP_RB0_CNTL, 1648 CP_RB1_CNTL, 1649 CP_RB2_CNTL, 1650 }; 1651 static const unsigned cp_rb_rptr_addr[] = { 1652 CP_RB0_RPTR_ADDR, 1653 CP_RB1_RPTR_ADDR, 1654 CP_RB2_RPTR_ADDR 1655 }; 1656 static const unsigned cp_rb_rptr_addr_hi[] = { 1657 CP_RB0_RPTR_ADDR_HI, 1658 CP_RB1_RPTR_ADDR_HI, 1659 CP_RB2_RPTR_ADDR_HI 1660 }; 1661 static const unsigned cp_rb_base[] = { 1662 CP_RB0_BASE, 1663 CP_RB1_BASE, 1664 CP_RB2_BASE 1665 }; 1666 static const unsigned cp_rb_rptr[] = { 1667 CP_RB0_RPTR, 1668 CP_RB1_RPTR, 1669 CP_RB2_RPTR 1670 }; 1671 static const unsigned cp_rb_wptr[] = { 1672 CP_RB0_WPTR, 1673 CP_RB1_WPTR, 1674 CP_RB2_WPTR 1675 }; 1676 struct radeon_ring *ring; 1677 int i, r; 1678 1679 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 1680 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 1681 SOFT_RESET_PA | 1682 SOFT_RESET_SH | 1683 SOFT_RESET_VGT | 1684 SOFT_RESET_SPI | 1685 SOFT_RESET_SX)); 1686 RREG32(GRBM_SOFT_RESET); 1687 mdelay(15); 1688 WREG32(GRBM_SOFT_RESET, 0); 1689 RREG32(GRBM_SOFT_RESET); 1690 1691 WREG32(CP_SEM_WAIT_TIMER, 0x0); 1692 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 1693 1694 /* Set the write pointer delay */ 1695 WREG32(CP_RB_WPTR_DELAY, 0); 1696 1697 WREG32(CP_DEBUG, (1 << 27)); 1698 1699 /* set the wb address whether it's enabled or not */ 1700 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 1701 WREG32(SCRATCH_UMSK, 0xff); 1702 1703 for (i = 0; i < 3; ++i) { 1704 uint32_t rb_cntl; 1705 uint64_t addr; 1706 1707 /* Set ring buffer size */ 1708 ring = &rdev->ring[ridx[i]]; 1709 rb_cntl = order_base_2(ring->ring_size / 8); 1710 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; 1711 #ifdef __BIG_ENDIAN 1712 rb_cntl |= BUF_SWAP_32BIT; 1713 #endif 1714 WREG32(cp_rb_cntl[i], rb_cntl); 1715 1716 /* set the wb address whether it's enabled or not */ 1717 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; 1718 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC); 1719 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); 1720 } 1721 1722 /* set the rb base addr, this causes an internal reset of ALL rings */ 1723 for (i = 0; i < 3; ++i) { 1724 ring = &rdev->ring[ridx[i]]; 1725 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); 1726 } 1727 1728 for (i = 0; i < 3; ++i) { 1729 /* Initialize the ring buffer's read and write pointers */ 1730 ring = &rdev->ring[ridx[i]]; 1731 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); 1732 1733 ring->wptr = 0; 1734 WREG32(cp_rb_rptr[i], 0); 1735 WREG32(cp_rb_wptr[i], ring->wptr); 1736 1737 mdelay(1); 1738 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); 1739 } 1740 1741 /* start the rings */ 1742 cayman_cp_start(rdev); 1743 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; 1744 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1745 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1746 /* this only test cp0 */ 1747 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1748 if (r) { 1749 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1750 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1751 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1752 return r; 1753 } 1754 1755 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 1756 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1757 1758 return 0; 1759 } 1760 1761 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev) 1762 { 1763 u32 reset_mask = 0; 1764 u32 tmp; 1765 1766 /* GRBM_STATUS */ 1767 tmp = RREG32(GRBM_STATUS); 1768 if (tmp & (PA_BUSY | SC_BUSY | 1769 SH_BUSY | SX_BUSY | 1770 TA_BUSY | VGT_BUSY | 1771 DB_BUSY | CB_BUSY | 1772 GDS_BUSY | SPI_BUSY | 1773 IA_BUSY | IA_BUSY_NO_DMA)) 1774 reset_mask |= RADEON_RESET_GFX; 1775 1776 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING | 1777 CP_BUSY | CP_COHERENCY_BUSY)) 1778 reset_mask |= RADEON_RESET_CP; 1779 1780 if (tmp & GRBM_EE_BUSY) 1781 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1782 1783 /* DMA_STATUS_REG 0 */ 1784 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); 1785 if (!(tmp & DMA_IDLE)) 1786 reset_mask |= RADEON_RESET_DMA; 1787 1788 /* DMA_STATUS_REG 1 */ 1789 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); 1790 if (!(tmp & DMA_IDLE)) 1791 reset_mask |= RADEON_RESET_DMA1; 1792 1793 /* SRBM_STATUS2 */ 1794 tmp = RREG32(SRBM_STATUS2); 1795 if (tmp & DMA_BUSY) 1796 reset_mask |= RADEON_RESET_DMA; 1797 1798 if (tmp & DMA1_BUSY) 1799 reset_mask |= RADEON_RESET_DMA1; 1800 1801 /* SRBM_STATUS */ 1802 tmp = RREG32(SRBM_STATUS); 1803 if (tmp & (RLC_RQ_PENDING | RLC_BUSY)) 1804 reset_mask |= RADEON_RESET_RLC; 1805 1806 if (tmp & IH_BUSY) 1807 reset_mask |= RADEON_RESET_IH; 1808 1809 if (tmp & SEM_BUSY) 1810 reset_mask |= RADEON_RESET_SEM; 1811 1812 if (tmp & GRBM_RQ_PENDING) 1813 reset_mask |= RADEON_RESET_GRBM; 1814 1815 if (tmp & VMC_BUSY) 1816 reset_mask |= RADEON_RESET_VMC; 1817 1818 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY | 1819 MCC_BUSY | MCD_BUSY)) 1820 reset_mask |= RADEON_RESET_MC; 1821 1822 if (evergreen_is_display_hung(rdev)) 1823 reset_mask |= RADEON_RESET_DISPLAY; 1824 1825 /* VM_L2_STATUS */ 1826 tmp = RREG32(VM_L2_STATUS); 1827 if (tmp & L2_BUSY) 1828 reset_mask |= RADEON_RESET_VMC; 1829 1830 /* Skip MC reset as it's mostly likely not hung, just busy */ 1831 if (reset_mask & RADEON_RESET_MC) { 1832 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1833 reset_mask &= ~RADEON_RESET_MC; 1834 } 1835 1836 return reset_mask; 1837 } 1838 1839 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1840 { 1841 struct evergreen_mc_save save; 1842 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1843 u32 tmp; 1844 1845 if (reset_mask == 0) 1846 return; 1847 1848 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1849 1850 evergreen_print_gpu_status_regs(rdev); 1851 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", 1852 RREG32(0x14F8)); 1853 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", 1854 RREG32(0x14D8)); 1855 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1856 RREG32(0x14FC)); 1857 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1858 RREG32(0x14DC)); 1859 1860 /* Disable CP parsing/prefetching */ 1861 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 1862 1863 if (reset_mask & RADEON_RESET_DMA) { 1864 /* dma0 */ 1865 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); 1866 tmp &= ~DMA_RB_ENABLE; 1867 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); 1868 } 1869 1870 if (reset_mask & RADEON_RESET_DMA1) { 1871 /* dma1 */ 1872 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); 1873 tmp &= ~DMA_RB_ENABLE; 1874 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); 1875 } 1876 1877 udelay(50); 1878 1879 evergreen_mc_stop(rdev, &save); 1880 if (evergreen_mc_wait_for_idle(rdev)) { 1881 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1882 } 1883 1884 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1885 grbm_soft_reset = SOFT_RESET_CB | 1886 SOFT_RESET_DB | 1887 SOFT_RESET_GDS | 1888 SOFT_RESET_PA | 1889 SOFT_RESET_SC | 1890 SOFT_RESET_SPI | 1891 SOFT_RESET_SH | 1892 SOFT_RESET_SX | 1893 SOFT_RESET_TC | 1894 SOFT_RESET_TA | 1895 SOFT_RESET_VGT | 1896 SOFT_RESET_IA; 1897 } 1898 1899 if (reset_mask & RADEON_RESET_CP) { 1900 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT; 1901 1902 srbm_soft_reset |= SOFT_RESET_GRBM; 1903 } 1904 1905 if (reset_mask & RADEON_RESET_DMA) 1906 srbm_soft_reset |= SOFT_RESET_DMA; 1907 1908 if (reset_mask & RADEON_RESET_DMA1) 1909 srbm_soft_reset |= SOFT_RESET_DMA1; 1910 1911 if (reset_mask & RADEON_RESET_DISPLAY) 1912 srbm_soft_reset |= SOFT_RESET_DC; 1913 1914 if (reset_mask & RADEON_RESET_RLC) 1915 srbm_soft_reset |= SOFT_RESET_RLC; 1916 1917 if (reset_mask & RADEON_RESET_SEM) 1918 srbm_soft_reset |= SOFT_RESET_SEM; 1919 1920 if (reset_mask & RADEON_RESET_IH) 1921 srbm_soft_reset |= SOFT_RESET_IH; 1922 1923 if (reset_mask & RADEON_RESET_GRBM) 1924 srbm_soft_reset |= SOFT_RESET_GRBM; 1925 1926 if (reset_mask & RADEON_RESET_VMC) 1927 srbm_soft_reset |= SOFT_RESET_VMC; 1928 1929 if (!(rdev->flags & RADEON_IS_IGP)) { 1930 if (reset_mask & RADEON_RESET_MC) 1931 srbm_soft_reset |= SOFT_RESET_MC; 1932 } 1933 1934 if (grbm_soft_reset) { 1935 tmp = RREG32(GRBM_SOFT_RESET); 1936 tmp |= grbm_soft_reset; 1937 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 1938 WREG32(GRBM_SOFT_RESET, tmp); 1939 tmp = RREG32(GRBM_SOFT_RESET); 1940 1941 udelay(50); 1942 1943 tmp &= ~grbm_soft_reset; 1944 WREG32(GRBM_SOFT_RESET, tmp); 1945 tmp = RREG32(GRBM_SOFT_RESET); 1946 } 1947 1948 if (srbm_soft_reset) { 1949 tmp = RREG32(SRBM_SOFT_RESET); 1950 tmp |= srbm_soft_reset; 1951 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1952 WREG32(SRBM_SOFT_RESET, tmp); 1953 tmp = RREG32(SRBM_SOFT_RESET); 1954 1955 udelay(50); 1956 1957 tmp &= ~srbm_soft_reset; 1958 WREG32(SRBM_SOFT_RESET, tmp); 1959 tmp = RREG32(SRBM_SOFT_RESET); 1960 } 1961 1962 /* Wait a little for things to settle down */ 1963 udelay(50); 1964 1965 evergreen_mc_resume(rdev, &save); 1966 udelay(50); 1967 1968 evergreen_print_gpu_status_regs(rdev); 1969 } 1970 1971 int cayman_asic_reset(struct radeon_device *rdev, bool hard) 1972 { 1973 u32 reset_mask; 1974 1975 if (hard) { 1976 evergreen_gpu_pci_config_reset(rdev); 1977 return 0; 1978 } 1979 1980 reset_mask = cayman_gpu_check_soft_reset(rdev); 1981 1982 if (reset_mask) 1983 r600_set_bios_scratch_engine_hung(rdev, true); 1984 1985 cayman_gpu_soft_reset(rdev, reset_mask); 1986 1987 reset_mask = cayman_gpu_check_soft_reset(rdev); 1988 1989 if (reset_mask) 1990 evergreen_gpu_pci_config_reset(rdev); 1991 1992 r600_set_bios_scratch_engine_hung(rdev, false); 1993 1994 return 0; 1995 } 1996 1997 /** 1998 * cayman_gfx_is_lockup - Check if the GFX engine is locked up 1999 * 2000 * @rdev: radeon_device pointer 2001 * @ring: radeon_ring structure holding ring information 2002 * 2003 * Check if the GFX engine is locked up. 2004 * Returns true if the engine appears to be locked up, false if not. 2005 */ 2006 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2007 { 2008 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); 2009 2010 if (!(reset_mask & (RADEON_RESET_GFX | 2011 RADEON_RESET_COMPUTE | 2012 RADEON_RESET_CP))) { 2013 radeon_ring_lockup_update(rdev, ring); 2014 return false; 2015 } 2016 return radeon_ring_test_lockup(rdev, ring); 2017 } 2018 2019 static void cayman_uvd_init(struct radeon_device *rdev) 2020 { 2021 int r; 2022 2023 if (!rdev->has_uvd) 2024 return; 2025 2026 r = radeon_uvd_init(rdev); 2027 if (r) { 2028 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); 2029 /* 2030 * At this point rdev->uvd.vcpu_bo is NULL which trickles down 2031 * to early fails uvd_v2_2_resume() and thus nothing happens 2032 * there. So it is pointless to try to go through that code 2033 * hence why we disable uvd here. 2034 */ 2035 rdev->has_uvd = 0; 2036 return; 2037 } 2038 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 2039 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); 2040 } 2041 2042 static void cayman_uvd_start(struct radeon_device *rdev) 2043 { 2044 int r; 2045 2046 if (!rdev->has_uvd) 2047 return; 2048 2049 r = uvd_v2_2_resume(rdev); 2050 if (r) { 2051 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); 2052 goto error; 2053 } 2054 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); 2055 if (r) { 2056 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); 2057 goto error; 2058 } 2059 return; 2060 2061 error: 2062 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 2063 } 2064 2065 static void cayman_uvd_resume(struct radeon_device *rdev) 2066 { 2067 struct radeon_ring *ring; 2068 int r; 2069 2070 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) 2071 return; 2072 2073 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2074 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, RADEON_CP_PACKET2); 2075 if (r) { 2076 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); 2077 return; 2078 } 2079 r = uvd_v1_0_init(rdev); 2080 if (r) { 2081 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); 2082 return; 2083 } 2084 } 2085 2086 static void cayman_vce_init(struct radeon_device *rdev) 2087 { 2088 int r; 2089 2090 /* Only set for CHIP_ARUBA */ 2091 if (!rdev->has_vce) 2092 return; 2093 2094 r = radeon_vce_init(rdev); 2095 if (r) { 2096 dev_err(rdev->dev, "failed VCE (%d) init.\n", r); 2097 /* 2098 * At this point rdev->vce.vcpu_bo is NULL which trickles down 2099 * to early fails cayman_vce_start() and thus nothing happens 2100 * there. So it is pointless to try to go through that code 2101 * hence why we disable vce here. 2102 */ 2103 rdev->has_vce = 0; 2104 return; 2105 } 2106 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL; 2107 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096); 2108 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL; 2109 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096); 2110 } 2111 2112 static void cayman_vce_start(struct radeon_device *rdev) 2113 { 2114 int r; 2115 2116 if (!rdev->has_vce) 2117 return; 2118 2119 r = radeon_vce_resume(rdev); 2120 if (r) { 2121 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); 2122 goto error; 2123 } 2124 r = vce_v1_0_resume(rdev); 2125 if (r) { 2126 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); 2127 goto error; 2128 } 2129 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX); 2130 if (r) { 2131 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r); 2132 goto error; 2133 } 2134 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX); 2135 if (r) { 2136 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r); 2137 goto error; 2138 } 2139 return; 2140 2141 error: 2142 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; 2143 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; 2144 } 2145 2146 static void cayman_vce_resume(struct radeon_device *rdev) 2147 { 2148 struct radeon_ring *ring; 2149 int r; 2150 2151 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size) 2152 return; 2153 2154 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; 2155 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); 2156 if (r) { 2157 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); 2158 return; 2159 } 2160 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; 2161 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); 2162 if (r) { 2163 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); 2164 return; 2165 } 2166 r = vce_v1_0_init(rdev); 2167 if (r) { 2168 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r); 2169 return; 2170 } 2171 } 2172 2173 static int cayman_startup(struct radeon_device *rdev) 2174 { 2175 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2176 int r; 2177 2178 /* enable pcie gen2 link */ 2179 evergreen_pcie_gen2_enable(rdev); 2180 /* enable aspm */ 2181 evergreen_program_aspm(rdev); 2182 2183 /* scratch needs to be initialized before MC */ 2184 r = r600_vram_scratch_init(rdev); 2185 if (r) 2186 return r; 2187 2188 evergreen_mc_program(rdev); 2189 2190 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) { 2191 r = ni_mc_load_microcode(rdev); 2192 if (r) { 2193 DRM_ERROR("Failed to load MC firmware!\n"); 2194 return r; 2195 } 2196 } 2197 2198 r = cayman_pcie_gart_enable(rdev); 2199 if (r) 2200 return r; 2201 cayman_gpu_init(rdev); 2202 2203 /* allocate rlc buffers */ 2204 if (rdev->flags & RADEON_IS_IGP) { 2205 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; 2206 rdev->rlc.reg_list_size = 2207 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list); 2208 rdev->rlc.cs_data = cayman_cs_data; 2209 r = sumo_rlc_init(rdev); 2210 if (r) { 2211 DRM_ERROR("Failed to init rlc BOs!\n"); 2212 return r; 2213 } 2214 } 2215 2216 /* allocate wb buffer */ 2217 r = radeon_wb_init(rdev); 2218 if (r) 2219 return r; 2220 2221 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 2222 if (r) { 2223 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2224 return r; 2225 } 2226 2227 cayman_uvd_start(rdev); 2228 cayman_vce_start(rdev); 2229 2230 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 2231 if (r) { 2232 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2233 return r; 2234 } 2235 2236 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 2237 if (r) { 2238 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2239 return r; 2240 } 2241 2242 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 2243 if (r) { 2244 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2245 return r; 2246 } 2247 2248 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 2249 if (r) { 2250 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2251 return r; 2252 } 2253 2254 /* Enable IRQ */ 2255 if (!rdev->irq.installed) { 2256 r = radeon_irq_kms_init(rdev); 2257 if (r) 2258 return r; 2259 } 2260 2261 r = r600_irq_init(rdev); 2262 if (r) { 2263 DRM_ERROR("radeon: IH init failed (%d).\n", r); 2264 radeon_irq_kms_fini(rdev); 2265 return r; 2266 } 2267 evergreen_irq_set(rdev); 2268 2269 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 2270 RADEON_CP_PACKET2); 2271 if (r) 2272 return r; 2273 2274 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2275 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 2276 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2277 if (r) 2278 return r; 2279 2280 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 2281 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, 2282 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2283 if (r) 2284 return r; 2285 2286 r = cayman_cp_load_microcode(rdev); 2287 if (r) 2288 return r; 2289 r = cayman_cp_resume(rdev); 2290 if (r) 2291 return r; 2292 2293 r = cayman_dma_resume(rdev); 2294 if (r) 2295 return r; 2296 2297 cayman_uvd_resume(rdev); 2298 cayman_vce_resume(rdev); 2299 2300 r = radeon_ib_pool_init(rdev); 2301 if (r) { 2302 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2303 return r; 2304 } 2305 2306 r = radeon_vm_manager_init(rdev); 2307 if (r) { 2308 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); 2309 return r; 2310 } 2311 2312 r = radeon_audio_init(rdev); 2313 if (r) 2314 return r; 2315 2316 return 0; 2317 } 2318 2319 int cayman_resume(struct radeon_device *rdev) 2320 { 2321 int r; 2322 2323 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 2324 * posting will perform necessary task to bring back GPU into good 2325 * shape. 2326 */ 2327 /* post card */ 2328 atom_asic_init(rdev->mode_info.atom_context); 2329 2330 /* init golden registers */ 2331 ni_init_golden_registers(rdev); 2332 2333 if (rdev->pm.pm_method == PM_METHOD_DPM) 2334 radeon_pm_resume(rdev); 2335 2336 rdev->accel_working = true; 2337 r = cayman_startup(rdev); 2338 if (r) { 2339 DRM_ERROR("cayman startup failed on resume\n"); 2340 rdev->accel_working = false; 2341 return r; 2342 } 2343 return r; 2344 } 2345 2346 int cayman_suspend(struct radeon_device *rdev) 2347 { 2348 radeon_pm_suspend(rdev); 2349 radeon_audio_fini(rdev); 2350 radeon_vm_manager_fini(rdev); 2351 cayman_cp_enable(rdev, false); 2352 cayman_dma_stop(rdev); 2353 if (rdev->has_uvd) { 2354 uvd_v1_0_fini(rdev); 2355 radeon_uvd_suspend(rdev); 2356 } 2357 evergreen_irq_suspend(rdev); 2358 radeon_wb_disable(rdev); 2359 cayman_pcie_gart_disable(rdev); 2360 return 0; 2361 } 2362 2363 /* Plan is to move initialization in that function and use 2364 * helper function so that radeon_device_init pretty much 2365 * do nothing more than calling asic specific function. This 2366 * should also allow to remove a bunch of callback function 2367 * like vram_info. 2368 */ 2369 int cayman_init(struct radeon_device *rdev) 2370 { 2371 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2372 int r; 2373 2374 /* Read BIOS */ 2375 if (!radeon_get_bios(rdev)) { 2376 if (ASIC_IS_AVIVO(rdev)) 2377 return -EINVAL; 2378 } 2379 /* Must be an ATOMBIOS */ 2380 if (!rdev->is_atom_bios) { 2381 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); 2382 return -EINVAL; 2383 } 2384 r = radeon_atombios_init(rdev); 2385 if (r) 2386 return r; 2387 2388 /* Post card if necessary */ 2389 if (!radeon_card_posted(rdev)) { 2390 if (!rdev->bios) { 2391 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 2392 return -EINVAL; 2393 } 2394 DRM_INFO("GPU not posted. posting now...\n"); 2395 atom_asic_init(rdev->mode_info.atom_context); 2396 } 2397 /* init golden registers */ 2398 ni_init_golden_registers(rdev); 2399 /* Initialize scratch registers */ 2400 r600_scratch_init(rdev); 2401 /* Initialize surface registers */ 2402 radeon_surface_init(rdev); 2403 /* Initialize clocks */ 2404 radeon_get_clock_info(rdev->ddev); 2405 /* Fence driver */ 2406 r = radeon_fence_driver_init(rdev); 2407 if (r) 2408 return r; 2409 /* initialize memory controller */ 2410 r = evergreen_mc_init(rdev); 2411 if (r) 2412 return r; 2413 /* Memory manager */ 2414 r = radeon_bo_init(rdev); 2415 if (r) 2416 return r; 2417 2418 if (rdev->flags & RADEON_IS_IGP) { 2419 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2420 r = ni_init_microcode(rdev); 2421 if (r) { 2422 DRM_ERROR("Failed to load firmware!\n"); 2423 return r; 2424 } 2425 } 2426 } else { 2427 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { 2428 r = ni_init_microcode(rdev); 2429 if (r) { 2430 DRM_ERROR("Failed to load firmware!\n"); 2431 return r; 2432 } 2433 } 2434 } 2435 2436 /* Initialize power management */ 2437 radeon_pm_init(rdev); 2438 2439 ring->ring_obj = NULL; 2440 r600_ring_init(rdev, ring, 1024 * 1024); 2441 2442 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2443 ring->ring_obj = NULL; 2444 r600_ring_init(rdev, ring, 64 * 1024); 2445 2446 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 2447 ring->ring_obj = NULL; 2448 r600_ring_init(rdev, ring, 64 * 1024); 2449 2450 cayman_uvd_init(rdev); 2451 cayman_vce_init(rdev); 2452 2453 rdev->ih.ring_obj = NULL; 2454 r600_ih_ring_init(rdev, 64 * 1024); 2455 2456 r = r600_pcie_gart_init(rdev); 2457 if (r) 2458 return r; 2459 2460 rdev->accel_working = true; 2461 r = cayman_startup(rdev); 2462 if (r) { 2463 dev_err(rdev->dev, "disabling GPU acceleration\n"); 2464 cayman_cp_fini(rdev); 2465 cayman_dma_fini(rdev); 2466 r600_irq_fini(rdev); 2467 if (rdev->flags & RADEON_IS_IGP) 2468 sumo_rlc_fini(rdev); 2469 radeon_wb_fini(rdev); 2470 radeon_ib_pool_fini(rdev); 2471 radeon_vm_manager_fini(rdev); 2472 radeon_irq_kms_fini(rdev); 2473 cayman_pcie_gart_fini(rdev); 2474 rdev->accel_working = false; 2475 } 2476 2477 /* Don't start up if the MC ucode is missing. 2478 * The default clocks and voltages before the MC ucode 2479 * is loaded are not suffient for advanced operations. 2480 * 2481 * We can skip this check for TN, because there is no MC 2482 * ucode. 2483 */ 2484 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { 2485 DRM_ERROR("radeon: MC ucode required for NI+.\n"); 2486 return -EINVAL; 2487 } 2488 2489 return 0; 2490 } 2491 2492 void cayman_fini(struct radeon_device *rdev) 2493 { 2494 radeon_pm_fini(rdev); 2495 cayman_cp_fini(rdev); 2496 cayman_dma_fini(rdev); 2497 r600_irq_fini(rdev); 2498 if (rdev->flags & RADEON_IS_IGP) 2499 sumo_rlc_fini(rdev); 2500 radeon_wb_fini(rdev); 2501 radeon_vm_manager_fini(rdev); 2502 radeon_ib_pool_fini(rdev); 2503 radeon_irq_kms_fini(rdev); 2504 uvd_v1_0_fini(rdev); 2505 radeon_uvd_fini(rdev); 2506 if (rdev->has_vce) 2507 radeon_vce_fini(rdev); 2508 cayman_pcie_gart_fini(rdev); 2509 r600_vram_scratch_fini(rdev); 2510 radeon_gem_fini(rdev); 2511 radeon_fence_driver_fini(rdev); 2512 radeon_bo_fini(rdev); 2513 radeon_atombios_fini(rdev); 2514 ni_fini_microcode(rdev); 2515 kfree(rdev->bios); 2516 rdev->bios = NULL; 2517 } 2518 2519 /* 2520 * vm 2521 */ 2522 int cayman_vm_init(struct radeon_device *rdev) 2523 { 2524 /* number of VMs */ 2525 rdev->vm_manager.nvm = 8; 2526 /* base offset of vram pages */ 2527 if (rdev->flags & RADEON_IS_IGP) { 2528 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET); 2529 tmp <<= 22; 2530 rdev->vm_manager.vram_base_offset = tmp; 2531 } else 2532 rdev->vm_manager.vram_base_offset = 0; 2533 return 0; 2534 } 2535 2536 void cayman_vm_fini(struct radeon_device *rdev) 2537 { 2538 } 2539 2540 /** 2541 * cayman_vm_decode_fault - print human readable fault info 2542 * 2543 * @rdev: radeon_device pointer 2544 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 2545 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 2546 * 2547 * Print human readable fault information (cayman/TN). 2548 */ 2549 void cayman_vm_decode_fault(struct radeon_device *rdev, 2550 u32 status, u32 addr) 2551 { 2552 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT; 2553 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT; 2554 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT; 2555 char *block; 2556 2557 switch (mc_id) { 2558 case 32: 2559 case 16: 2560 case 96: 2561 case 80: 2562 case 160: 2563 case 144: 2564 case 224: 2565 case 208: 2566 block = "CB"; 2567 break; 2568 case 33: 2569 case 17: 2570 case 97: 2571 case 81: 2572 case 161: 2573 case 145: 2574 case 225: 2575 case 209: 2576 block = "CB_FMASK"; 2577 break; 2578 case 34: 2579 case 18: 2580 case 98: 2581 case 82: 2582 case 162: 2583 case 146: 2584 case 226: 2585 case 210: 2586 block = "CB_CMASK"; 2587 break; 2588 case 35: 2589 case 19: 2590 case 99: 2591 case 83: 2592 case 163: 2593 case 147: 2594 case 227: 2595 case 211: 2596 block = "CB_IMMED"; 2597 break; 2598 case 36: 2599 case 20: 2600 case 100: 2601 case 84: 2602 case 164: 2603 case 148: 2604 case 228: 2605 case 212: 2606 block = "DB"; 2607 break; 2608 case 37: 2609 case 21: 2610 case 101: 2611 case 85: 2612 case 165: 2613 case 149: 2614 case 229: 2615 case 213: 2616 block = "DB_HTILE"; 2617 break; 2618 case 38: 2619 case 22: 2620 case 102: 2621 case 86: 2622 case 166: 2623 case 150: 2624 case 230: 2625 case 214: 2626 block = "SX"; 2627 break; 2628 case 39: 2629 case 23: 2630 case 103: 2631 case 87: 2632 case 167: 2633 case 151: 2634 case 231: 2635 case 215: 2636 block = "DB_STEN"; 2637 break; 2638 case 40: 2639 case 24: 2640 case 104: 2641 case 88: 2642 case 232: 2643 case 216: 2644 case 168: 2645 case 152: 2646 block = "TC_TFETCH"; 2647 break; 2648 case 41: 2649 case 25: 2650 case 105: 2651 case 89: 2652 case 233: 2653 case 217: 2654 case 169: 2655 case 153: 2656 block = "TC_VFETCH"; 2657 break; 2658 case 42: 2659 case 26: 2660 case 106: 2661 case 90: 2662 case 234: 2663 case 218: 2664 case 170: 2665 case 154: 2666 block = "VC"; 2667 break; 2668 case 112: 2669 block = "CP"; 2670 break; 2671 case 113: 2672 case 114: 2673 block = "SH"; 2674 break; 2675 case 115: 2676 block = "VGT"; 2677 break; 2678 case 178: 2679 block = "IH"; 2680 break; 2681 case 51: 2682 block = "RLC"; 2683 break; 2684 case 55: 2685 block = "DMA"; 2686 break; 2687 case 56: 2688 block = "HDP"; 2689 break; 2690 default: 2691 block = "unknown"; 2692 break; 2693 } 2694 2695 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n", 2696 protections, vmid, addr, 2697 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read", 2698 block, mc_id); 2699 } 2700 2701 /** 2702 * cayman_vm_flush - vm flush using the CP 2703 * 2704 * @rdev: radeon_device pointer 2705 * 2706 * Update the page table base and flush the VM TLB 2707 * using the CP (cayman-si). 2708 */ 2709 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 2710 unsigned vm_id, uint64_t pd_addr) 2711 { 2712 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); 2713 radeon_ring_write(ring, pd_addr >> 12); 2714 2715 /* flush hdp cache */ 2716 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 2717 radeon_ring_write(ring, 0x1); 2718 2719 /* bits 0-7 are the VM contexts0-7 */ 2720 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); 2721 radeon_ring_write(ring, 1 << vm_id); 2722 2723 /* wait for the invalidate to complete */ 2724 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2725 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2726 WAIT_REG_MEM_ENGINE(0))); /* me */ 2727 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 2728 radeon_ring_write(ring, 0); 2729 radeon_ring_write(ring, 0); /* ref */ 2730 radeon_ring_write(ring, 0); /* mask */ 2731 radeon_ring_write(ring, 0x20); /* poll interval */ 2732 2733 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2734 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2735 radeon_ring_write(ring, 0x0); 2736 } 2737 2738 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) 2739 { 2740 struct atom_clock_dividers dividers; 2741 int r, i; 2742 2743 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 2744 ecclk, false, ÷rs); 2745 if (r) 2746 return r; 2747 2748 for (i = 0; i < 100; i++) { 2749 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS) 2750 break; 2751 mdelay(10); 2752 } 2753 if (i == 100) 2754 return -ETIMEDOUT; 2755 2756 WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK)); 2757 2758 for (i = 0; i < 100; i++) { 2759 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS) 2760 break; 2761 mdelay(10); 2762 } 2763 if (i == 100) 2764 return -ETIMEDOUT; 2765 2766 return 0; 2767 } 2768