1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "drmP.h" 26 #include "radeon.h" 27 #include "radeon_asic.h" 28 #include "radeon_ucode.h" 29 #include "cikd.h" 30 #include "r600_dpm.h" 31 #include "ci_dpm.h" 32 #include "atom.h" 33 #include <linux/seq_file.h> 34 35 #define MC_CG_ARB_FREQ_F0 0x0a 36 #define MC_CG_ARB_FREQ_F1 0x0b 37 #define MC_CG_ARB_FREQ_F2 0x0c 38 #define MC_CG_ARB_FREQ_F3 0x0d 39 40 #define SMC_RAM_END 0x40000 41 42 #define VOLTAGE_SCALE 4 43 #define VOLTAGE_VID_OFFSET_SCALE1 625 44 #define VOLTAGE_VID_OFFSET_SCALE2 100 45 46 static const struct ci_pt_defaults defaults_hawaii_xt = 47 { 48 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000, 49 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 }, 50 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 } 51 }; 52 53 static const struct ci_pt_defaults defaults_hawaii_pro = 54 { 55 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062, 56 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 }, 57 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 } 58 }; 59 60 static const struct ci_pt_defaults defaults_bonaire_xt = 61 { 62 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, 63 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 }, 64 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } 65 }; 66 67 #if 0 /* unused */ 68 static const struct ci_pt_defaults defaults_bonaire_pro = 69 { 70 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062, 71 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F }, 72 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB } 73 }; 74 #endif 75 76 static const struct ci_pt_defaults defaults_saturn_xt = 77 { 78 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000, 79 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D }, 80 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 } 81 }; 82 83 #if 0 /* unused */ 84 static const struct ci_pt_defaults defaults_saturn_pro = 85 { 86 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000, 87 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A }, 88 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 } 89 }; 90 #endif 91 92 static const struct ci_pt_config_reg didt_config_ci[] = 93 { 94 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 95 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 96 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 97 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 98 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 99 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 100 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 101 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 102 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 103 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 104 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 105 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 106 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 107 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 108 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 109 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 110 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 111 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 112 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 113 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 114 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 115 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 116 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 117 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 118 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 119 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 120 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 121 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 122 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 123 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 124 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 125 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 126 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 127 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 128 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 129 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 130 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 131 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 132 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 133 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 134 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 135 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 136 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 137 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 138 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 139 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 140 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 141 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 142 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 143 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 144 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 145 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 146 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 147 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 148 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 149 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 150 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 151 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 152 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 153 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 154 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 155 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 156 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 157 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 158 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 159 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 160 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, 161 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, 162 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, 163 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 164 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, 165 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, 166 { 0xFFFFFFFF } 167 }; 168 169 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev); 170 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, 171 u32 arb_freq_src, u32 arb_freq_dest); 172 173 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 174 struct atom_voltage_table_entry *voltage_table, 175 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd); 176 static int ci_set_power_limit(struct radeon_device *rdev, u32 n); 177 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, 178 u32 target_tdp); 179 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate); 180 181 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 182 PPSMC_Msg msg, u32 parameter); 183 184 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev); 185 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev); 186 187 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev) 188 { 189 struct ci_power_info *pi = rdev->pm.dpm.priv; 190 191 return pi; 192 } 193 194 static struct ci_ps *ci_get_ps(struct radeon_ps *rps) 195 { 196 struct ci_ps *ps = rps->ps_priv; 197 198 return ps; 199 } 200 201 static void ci_initialize_powertune_defaults(struct radeon_device *rdev) 202 { 203 struct ci_power_info *pi = ci_get_pi(rdev); 204 205 switch (rdev->pdev->device) { 206 case 0x6649: 207 case 0x6650: 208 case 0x6651: 209 case 0x6658: 210 case 0x665C: 211 case 0x665D: 212 default: 213 pi->powertune_defaults = &defaults_bonaire_xt; 214 break; 215 case 0x6640: 216 case 0x6641: 217 case 0x6646: 218 case 0x6647: 219 pi->powertune_defaults = &defaults_saturn_xt; 220 break; 221 case 0x67B8: 222 case 0x67B0: 223 pi->powertune_defaults = &defaults_hawaii_xt; 224 break; 225 case 0x67BA: 226 case 0x67B1: 227 pi->powertune_defaults = &defaults_hawaii_pro; 228 break; 229 case 0x67A0: 230 case 0x67A1: 231 case 0x67A2: 232 case 0x67A8: 233 case 0x67A9: 234 case 0x67AA: 235 case 0x67B9: 236 case 0x67BE: 237 pi->powertune_defaults = &defaults_bonaire_xt; 238 break; 239 } 240 241 pi->dte_tj_offset = 0; 242 243 pi->caps_power_containment = true; 244 pi->caps_cac = false; 245 pi->caps_sq_ramping = false; 246 pi->caps_db_ramping = false; 247 pi->caps_td_ramping = false; 248 pi->caps_tcp_ramping = false; 249 250 if (pi->caps_power_containment) { 251 pi->caps_cac = true; 252 if (rdev->family == CHIP_HAWAII) 253 pi->enable_bapm_feature = false; 254 else 255 pi->enable_bapm_feature = true; 256 pi->enable_tdc_limit_feature = true; 257 pi->enable_pkg_pwr_tracking_feature = true; 258 } 259 } 260 261 static u8 ci_convert_to_vid(u16 vddc) 262 { 263 return (6200 - (vddc * VOLTAGE_SCALE)) / 25; 264 } 265 266 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev) 267 { 268 struct ci_power_info *pi = ci_get_pi(rdev); 269 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; 270 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; 271 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; 272 u32 i; 273 274 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) 275 return -EINVAL; 276 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) 277 return -EINVAL; 278 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != 279 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) 280 return -EINVAL; 281 282 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { 283 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { 284 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); 285 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); 286 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); 287 } else { 288 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); 289 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); 290 } 291 } 292 return 0; 293 } 294 295 static int ci_populate_vddc_vid(struct radeon_device *rdev) 296 { 297 struct ci_power_info *pi = ci_get_pi(rdev); 298 u8 *vid = pi->smc_powertune_table.VddCVid; 299 u32 i; 300 301 if (pi->vddc_voltage_table.count > 8) 302 return -EINVAL; 303 304 for (i = 0; i < pi->vddc_voltage_table.count; i++) 305 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); 306 307 return 0; 308 } 309 310 static int ci_populate_svi_load_line(struct radeon_device *rdev) 311 { 312 struct ci_power_info *pi = ci_get_pi(rdev); 313 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 314 315 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; 316 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; 317 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; 318 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; 319 320 return 0; 321 } 322 323 static int ci_populate_tdc_limit(struct radeon_device *rdev) 324 { 325 struct ci_power_info *pi = ci_get_pi(rdev); 326 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 327 u16 tdc_limit; 328 329 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; 330 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); 331 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = 332 pt_defaults->tdc_vddc_throttle_release_limit_perc; 333 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; 334 335 return 0; 336 } 337 338 static int ci_populate_dw8(struct radeon_device *rdev) 339 { 340 struct ci_power_info *pi = ci_get_pi(rdev); 341 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 342 int ret; 343 344 ret = ci_read_smc_sram_dword(rdev, 345 SMU7_FIRMWARE_HEADER_LOCATION + 346 offsetof(SMU7_Firmware_Header, PmFuseTable) + 347 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl), 348 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, 349 pi->sram_end); 350 if (ret) 351 return -EINVAL; 352 else 353 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; 354 355 return 0; 356 } 357 358 static int ci_populate_fuzzy_fan(struct radeon_device *rdev) 359 { 360 struct ci_power_info *pi = ci_get_pi(rdev); 361 362 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) || 363 (rdev->pm.dpm.fan.fan_output_sensitivity == 0)) 364 rdev->pm.dpm.fan.fan_output_sensitivity = 365 rdev->pm.dpm.fan.default_fan_output_sensitivity; 366 367 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = 368 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity); 369 370 return 0; 371 } 372 373 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev) 374 { 375 struct ci_power_info *pi = ci_get_pi(rdev); 376 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; 377 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; 378 int i, min, max; 379 380 min = max = hi_vid[0]; 381 for (i = 0; i < 8; i++) { 382 if (0 != hi_vid[i]) { 383 if (min > hi_vid[i]) 384 min = hi_vid[i]; 385 if (max < hi_vid[i]) 386 max = hi_vid[i]; 387 } 388 389 if (0 != lo_vid[i]) { 390 if (min > lo_vid[i]) 391 min = lo_vid[i]; 392 if (max < lo_vid[i]) 393 max = lo_vid[i]; 394 } 395 } 396 397 if ((min == 0) || (max == 0)) 398 return -EINVAL; 399 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; 400 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; 401 402 return 0; 403 } 404 405 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev) 406 { 407 struct ci_power_info *pi = ci_get_pi(rdev); 408 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; 409 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; 410 struct radeon_cac_tdp_table *cac_tdp_table = 411 rdev->pm.dpm.dyn_state.cac_tdp_table; 412 413 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256; 414 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256; 415 416 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); 417 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); 418 419 return 0; 420 } 421 422 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev) 423 { 424 struct ci_power_info *pi = ci_get_pi(rdev); 425 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; 426 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; 427 struct radeon_cac_tdp_table *cac_tdp_table = 428 rdev->pm.dpm.dyn_state.cac_tdp_table; 429 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 430 int i, j, k; 431 const u16 *def1; 432 const u16 *def2; 433 434 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; 435 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; 436 437 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; 438 dpm_table->GpuTjMax = 439 (u8)(pi->thermal_temp_setting.temperature_high / 1000); 440 dpm_table->GpuTjHyst = 8; 441 442 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; 443 444 if (ppm) { 445 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); 446 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); 447 } else { 448 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); 449 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); 450 } 451 452 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient); 453 def1 = pt_defaults->bapmti_r; 454 def2 = pt_defaults->bapmti_rc; 455 456 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) { 457 for (j = 0; j < SMU7_DTE_SOURCES; j++) { 458 for (k = 0; k < SMU7_DTE_SINKS; k++) { 459 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); 460 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); 461 def1++; 462 def2++; 463 } 464 } 465 } 466 467 return 0; 468 } 469 470 static int ci_populate_pm_base(struct radeon_device *rdev) 471 { 472 struct ci_power_info *pi = ci_get_pi(rdev); 473 u32 pm_fuse_table_offset; 474 int ret; 475 476 if (pi->caps_power_containment) { 477 ret = ci_read_smc_sram_dword(rdev, 478 SMU7_FIRMWARE_HEADER_LOCATION + 479 offsetof(SMU7_Firmware_Header, PmFuseTable), 480 &pm_fuse_table_offset, pi->sram_end); 481 if (ret) 482 return ret; 483 ret = ci_populate_bapm_vddc_vid_sidd(rdev); 484 if (ret) 485 return ret; 486 ret = ci_populate_vddc_vid(rdev); 487 if (ret) 488 return ret; 489 ret = ci_populate_svi_load_line(rdev); 490 if (ret) 491 return ret; 492 ret = ci_populate_tdc_limit(rdev); 493 if (ret) 494 return ret; 495 ret = ci_populate_dw8(rdev); 496 if (ret) 497 return ret; 498 ret = ci_populate_fuzzy_fan(rdev); 499 if (ret) 500 return ret; 501 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev); 502 if (ret) 503 return ret; 504 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev); 505 if (ret) 506 return ret; 507 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset, 508 (u8 *)&pi->smc_powertune_table, 509 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); 510 if (ret) 511 return ret; 512 } 513 514 return 0; 515 } 516 517 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable) 518 { 519 struct ci_power_info *pi = ci_get_pi(rdev); 520 u32 data; 521 522 if (pi->caps_sq_ramping) { 523 data = RREG32_DIDT(DIDT_SQ_CTRL0); 524 if (enable) 525 data |= DIDT_CTRL_EN; 526 else 527 data &= ~DIDT_CTRL_EN; 528 WREG32_DIDT(DIDT_SQ_CTRL0, data); 529 } 530 531 if (pi->caps_db_ramping) { 532 data = RREG32_DIDT(DIDT_DB_CTRL0); 533 if (enable) 534 data |= DIDT_CTRL_EN; 535 else 536 data &= ~DIDT_CTRL_EN; 537 WREG32_DIDT(DIDT_DB_CTRL0, data); 538 } 539 540 if (pi->caps_td_ramping) { 541 data = RREG32_DIDT(DIDT_TD_CTRL0); 542 if (enable) 543 data |= DIDT_CTRL_EN; 544 else 545 data &= ~DIDT_CTRL_EN; 546 WREG32_DIDT(DIDT_TD_CTRL0, data); 547 } 548 549 if (pi->caps_tcp_ramping) { 550 data = RREG32_DIDT(DIDT_TCP_CTRL0); 551 if (enable) 552 data |= DIDT_CTRL_EN; 553 else 554 data &= ~DIDT_CTRL_EN; 555 WREG32_DIDT(DIDT_TCP_CTRL0, data); 556 } 557 } 558 559 static int ci_program_pt_config_registers(struct radeon_device *rdev, 560 const struct ci_pt_config_reg *cac_config_regs) 561 { 562 const struct ci_pt_config_reg *config_regs = cac_config_regs; 563 u32 data; 564 u32 cache = 0; 565 566 if (config_regs == NULL) 567 return -EINVAL; 568 569 while (config_regs->offset != 0xFFFFFFFF) { 570 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) { 571 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); 572 } else { 573 switch (config_regs->type) { 574 case CISLANDS_CONFIGREG_SMC_IND: 575 data = RREG32_SMC(config_regs->offset); 576 break; 577 case CISLANDS_CONFIGREG_DIDT_IND: 578 data = RREG32_DIDT(config_regs->offset); 579 break; 580 default: 581 data = RREG32(config_regs->offset << 2); 582 break; 583 } 584 585 data &= ~config_regs->mask; 586 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 587 data |= cache; 588 589 switch (config_regs->type) { 590 case CISLANDS_CONFIGREG_SMC_IND: 591 WREG32_SMC(config_regs->offset, data); 592 break; 593 case CISLANDS_CONFIGREG_DIDT_IND: 594 WREG32_DIDT(config_regs->offset, data); 595 break; 596 default: 597 WREG32(config_regs->offset << 2, data); 598 break; 599 } 600 cache = 0; 601 } 602 config_regs++; 603 } 604 return 0; 605 } 606 607 static int ci_enable_didt(struct radeon_device *rdev, bool enable) 608 { 609 struct ci_power_info *pi = ci_get_pi(rdev); 610 int ret; 611 612 if (pi->caps_sq_ramping || pi->caps_db_ramping || 613 pi->caps_td_ramping || pi->caps_tcp_ramping) { 614 cik_enter_rlc_safe_mode(rdev); 615 616 if (enable) { 617 ret = ci_program_pt_config_registers(rdev, didt_config_ci); 618 if (ret) { 619 cik_exit_rlc_safe_mode(rdev); 620 return ret; 621 } 622 } 623 624 ci_do_enable_didt(rdev, enable); 625 626 cik_exit_rlc_safe_mode(rdev); 627 } 628 629 return 0; 630 } 631 632 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable) 633 { 634 struct ci_power_info *pi = ci_get_pi(rdev); 635 PPSMC_Result smc_result; 636 int ret = 0; 637 638 if (enable) { 639 pi->power_containment_features = 0; 640 if (pi->caps_power_containment) { 641 if (pi->enable_bapm_feature) { 642 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 643 if (smc_result != PPSMC_Result_OK) 644 ret = -EINVAL; 645 else 646 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; 647 } 648 649 if (pi->enable_tdc_limit_feature) { 650 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable); 651 if (smc_result != PPSMC_Result_OK) 652 ret = -EINVAL; 653 else 654 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; 655 } 656 657 if (pi->enable_pkg_pwr_tracking_feature) { 658 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable); 659 if (smc_result != PPSMC_Result_OK) { 660 ret = -EINVAL; 661 } else { 662 struct radeon_cac_tdp_table *cac_tdp_table = 663 rdev->pm.dpm.dyn_state.cac_tdp_table; 664 u32 default_pwr_limit = 665 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); 666 667 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; 668 669 ci_set_power_limit(rdev, default_pwr_limit); 670 } 671 } 672 } 673 } else { 674 if (pi->caps_power_containment && pi->power_containment_features) { 675 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) 676 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable); 677 678 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) 679 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 680 681 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) 682 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable); 683 pi->power_containment_features = 0; 684 } 685 } 686 687 return ret; 688 } 689 690 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable) 691 { 692 struct ci_power_info *pi = ci_get_pi(rdev); 693 PPSMC_Result smc_result; 694 int ret = 0; 695 696 if (pi->caps_cac) { 697 if (enable) { 698 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 699 if (smc_result != PPSMC_Result_OK) { 700 ret = -EINVAL; 701 pi->cac_enabled = false; 702 } else { 703 pi->cac_enabled = true; 704 } 705 } else if (pi->cac_enabled) { 706 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 707 pi->cac_enabled = false; 708 } 709 } 710 711 return ret; 712 } 713 714 static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev, 715 bool enable) 716 { 717 struct ci_power_info *pi = ci_get_pi(rdev); 718 PPSMC_Result smc_result = PPSMC_Result_OK; 719 720 if (pi->thermal_sclk_dpm_enabled) { 721 if (enable) 722 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM); 723 else 724 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM); 725 } 726 727 if (smc_result == PPSMC_Result_OK) 728 return 0; 729 else 730 return -EINVAL; 731 } 732 733 static int ci_power_control_set_level(struct radeon_device *rdev) 734 { 735 struct ci_power_info *pi = ci_get_pi(rdev); 736 struct radeon_cac_tdp_table *cac_tdp_table = 737 rdev->pm.dpm.dyn_state.cac_tdp_table; 738 s32 adjust_percent; 739 s32 target_tdp; 740 int ret = 0; 741 bool adjust_polarity = false; /* ??? */ 742 743 if (pi->caps_power_containment) { 744 adjust_percent = adjust_polarity ? 745 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); 746 target_tdp = ((100 + adjust_percent) * 747 (s32)cac_tdp_table->configurable_tdp) / 100; 748 749 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp); 750 } 751 752 return ret; 753 } 754 755 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) 756 { 757 struct ci_power_info *pi = ci_get_pi(rdev); 758 759 if (pi->uvd_power_gated == gate) 760 return; 761 762 pi->uvd_power_gated = gate; 763 764 ci_update_uvd_dpm(rdev, gate); 765 } 766 767 bool ci_dpm_vblank_too_short(struct radeon_device *rdev) 768 { 769 struct ci_power_info *pi = ci_get_pi(rdev); 770 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 771 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; 772 773 /* disable mclk switching if the refresh is >120Hz, even if the 774 * blanking period would allow it 775 */ 776 if (r600_dpm_get_vrefresh(rdev) > 120) 777 return true; 778 779 /* disable mclk switching if the refresh is >120Hz, even if the 780 * blanking period would allow it 781 */ 782 if (r600_dpm_get_vrefresh(rdev) > 120) 783 return true; 784 785 /* disable mclk switching if the refresh is >120Hz, even if the 786 * blanking period would allow it 787 */ 788 if (r600_dpm_get_vrefresh(rdev) > 120) 789 return true; 790 791 /* disable mclk switching if the refresh is >120Hz, even if the 792 * blanking period would allow it 793 */ 794 if (r600_dpm_get_vrefresh(rdev) > 120) 795 return true; 796 797 /* disable mclk switching if the refresh is >120Hz, even if the 798 * blanking period would allow it 799 */ 800 if (r600_dpm_get_vrefresh(rdev) > 120) 801 return true; 802 803 if (vblank_time < switch_limit) 804 return true; 805 else 806 return false; 807 808 } 809 810 static void ci_apply_state_adjust_rules(struct radeon_device *rdev, 811 struct radeon_ps *rps) 812 { 813 struct ci_ps *ps = ci_get_ps(rps); 814 struct ci_power_info *pi = ci_get_pi(rdev); 815 struct radeon_clock_and_voltage_limits *max_limits; 816 bool disable_mclk_switching; 817 u32 sclk, mclk; 818 int i; 819 820 if (rps->vce_active) { 821 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 822 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 823 } else { 824 rps->evclk = 0; 825 rps->ecclk = 0; 826 } 827 828 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 829 ci_dpm_vblank_too_short(rdev)) 830 disable_mclk_switching = true; 831 else 832 disable_mclk_switching = false; 833 834 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) 835 pi->battery_state = true; 836 else 837 pi->battery_state = false; 838 839 if (rdev->pm.dpm.ac_power) 840 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 841 else 842 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 843 844 if (rdev->pm.dpm.ac_power == false) { 845 for (i = 0; i < ps->performance_level_count; i++) { 846 if (ps->performance_levels[i].mclk > max_limits->mclk) 847 ps->performance_levels[i].mclk = max_limits->mclk; 848 if (ps->performance_levels[i].sclk > max_limits->sclk) 849 ps->performance_levels[i].sclk = max_limits->sclk; 850 } 851 } 852 853 /* XXX validate the min clocks required for display */ 854 855 if (disable_mclk_switching) { 856 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 857 sclk = ps->performance_levels[0].sclk; 858 } else { 859 mclk = ps->performance_levels[0].mclk; 860 sclk = ps->performance_levels[0].sclk; 861 } 862 863 if (rps->vce_active) { 864 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 865 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 866 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 867 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 868 } 869 870 ps->performance_levels[0].sclk = sclk; 871 ps->performance_levels[0].mclk = mclk; 872 873 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) 874 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; 875 876 if (disable_mclk_switching) { 877 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) 878 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; 879 } else { 880 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk) 881 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk; 882 } 883 } 884 885 static int ci_thermal_set_temperature_range(struct radeon_device *rdev, 886 int min_temp, int max_temp) 887 { 888 int low_temp = 0 * 1000; 889 int high_temp = 255 * 1000; 890 u32 tmp; 891 892 if (low_temp < min_temp) 893 low_temp = min_temp; 894 if (high_temp > max_temp) 895 high_temp = max_temp; 896 if (high_temp < low_temp) { 897 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 898 return -EINVAL; 899 } 900 901 tmp = RREG32_SMC(CG_THERMAL_INT); 902 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK); 903 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) | 904 CI_DIG_THERM_INTL(low_temp / 1000); 905 WREG32_SMC(CG_THERMAL_INT, tmp); 906 907 #if 0 908 /* XXX: need to figure out how to handle this properly */ 909 tmp = RREG32_SMC(CG_THERMAL_CTRL); 910 tmp &= DIG_THERM_DPM_MASK; 911 tmp |= DIG_THERM_DPM(high_temp / 1000); 912 WREG32_SMC(CG_THERMAL_CTRL, tmp); 913 #endif 914 915 rdev->pm.dpm.thermal.min_temp = low_temp; 916 rdev->pm.dpm.thermal.max_temp = high_temp; 917 918 return 0; 919 } 920 921 static int ci_thermal_enable_alert(struct radeon_device *rdev, 922 bool enable) 923 { 924 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT); 925 PPSMC_Result result; 926 927 if (enable) { 928 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 929 WREG32_SMC(CG_THERMAL_INT, thermal_int); 930 rdev->irq.dpm_thermal = false; 931 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable); 932 if (result != PPSMC_Result_OK) { 933 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 934 return -EINVAL; 935 } 936 } else { 937 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 938 WREG32_SMC(CG_THERMAL_INT, thermal_int); 939 rdev->irq.dpm_thermal = true; 940 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable); 941 if (result != PPSMC_Result_OK) { 942 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n"); 943 return -EINVAL; 944 } 945 } 946 947 return 0; 948 } 949 950 static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 951 { 952 struct ci_power_info *pi = ci_get_pi(rdev); 953 u32 tmp; 954 955 if (pi->fan_ctrl_is_in_default_mode) { 956 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 957 pi->fan_ctrl_default_mode = tmp; 958 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 959 pi->t_min = tmp; 960 pi->fan_ctrl_is_in_default_mode = false; 961 } 962 963 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; 964 tmp |= TMIN(0); 965 WREG32_SMC(CG_FDO_CTRL2, tmp); 966 967 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 968 tmp |= FDO_PWM_MODE(mode); 969 WREG32_SMC(CG_FDO_CTRL2, tmp); 970 } 971 972 static int ci_thermal_setup_fan_table(struct radeon_device *rdev) 973 { 974 struct ci_power_info *pi = ci_get_pi(rdev); 975 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; 976 u32 duty100; 977 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 978 u16 fdo_min, slope1, slope2; 979 u32 reference_clock, tmp; 980 int ret; 981 u64 tmp64; 982 983 if (!pi->fan_table_start) { 984 rdev->pm.dpm.fan.ucode_fan_control = false; 985 return 0; 986 } 987 988 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 989 990 if (duty100 == 0) { 991 rdev->pm.dpm.fan.ucode_fan_control = false; 992 return 0; 993 } 994 995 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 996 do_div(tmp64, 10000); 997 fdo_min = (u16)tmp64; 998 999 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 1000 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 1001 1002 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 1003 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 1004 1005 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 1006 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 1007 1008 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 1009 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 1010 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 1011 1012 fan_table.Slope1 = cpu_to_be16(slope1); 1013 fan_table.Slope2 = cpu_to_be16(slope2); 1014 1015 fan_table.FdoMin = cpu_to_be16(fdo_min); 1016 1017 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 1018 1019 fan_table.HystUp = cpu_to_be16(1); 1020 1021 fan_table.HystSlope = cpu_to_be16(1); 1022 1023 fan_table.TempRespLim = cpu_to_be16(5); 1024 1025 reference_clock = radeon_get_xclk(rdev); 1026 1027 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 1028 reference_clock) / 1600); 1029 1030 fan_table.FdoMax = cpu_to_be16((u16)duty100); 1031 1032 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 1033 fan_table.TempSrc = (uint8_t)tmp; 1034 1035 ret = ci_copy_bytes_to_smc(rdev, 1036 pi->fan_table_start, 1037 (u8 *)(&fan_table), 1038 sizeof(fan_table), 1039 pi->sram_end); 1040 1041 if (ret) { 1042 DRM_ERROR("Failed to load fan table to the SMC."); 1043 rdev->pm.dpm.fan.ucode_fan_control = false; 1044 } 1045 1046 return 0; 1047 } 1048 1049 static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 1050 { 1051 struct ci_power_info *pi = ci_get_pi(rdev); 1052 PPSMC_Result ret; 1053 1054 if (pi->caps_od_fuzzy_fan_control_support) { 1055 ret = ci_send_msg_to_smc_with_parameter(rdev, 1056 PPSMC_StartFanControl, 1057 FAN_CONTROL_FUZZY); 1058 if (ret != PPSMC_Result_OK) 1059 return -EINVAL; 1060 ret = ci_send_msg_to_smc_with_parameter(rdev, 1061 PPSMC_MSG_SetFanPwmMax, 1062 rdev->pm.dpm.fan.default_max_fan_pwm); 1063 if (ret != PPSMC_Result_OK) 1064 return -EINVAL; 1065 } else { 1066 ret = ci_send_msg_to_smc_with_parameter(rdev, 1067 PPSMC_StartFanControl, 1068 FAN_CONTROL_TABLE); 1069 if (ret != PPSMC_Result_OK) 1070 return -EINVAL; 1071 } 1072 1073 pi->fan_is_controlled_by_smc = true; 1074 return 0; 1075 } 1076 1077 static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 1078 { 1079 PPSMC_Result ret; 1080 struct ci_power_info *pi = ci_get_pi(rdev); 1081 1082 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl); 1083 if (ret == PPSMC_Result_OK) { 1084 pi->fan_is_controlled_by_smc = false; 1085 return 0; 1086 } else 1087 return -EINVAL; 1088 } 1089 1090 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 1091 u32 *speed) 1092 { 1093 u32 duty, duty100; 1094 u64 tmp64; 1095 1096 if (rdev->pm.no_fan) 1097 return -ENOENT; 1098 1099 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 1100 duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 1101 1102 if (duty100 == 0) 1103 return -EINVAL; 1104 1105 tmp64 = (u64)duty * 100; 1106 do_div(tmp64, duty100); 1107 *speed = (u32)tmp64; 1108 1109 if (*speed > 100) 1110 *speed = 100; 1111 1112 return 0; 1113 } 1114 1115 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 1116 u32 speed) 1117 { 1118 u32 tmp; 1119 u32 duty, duty100; 1120 u64 tmp64; 1121 struct ci_power_info *pi = ci_get_pi(rdev); 1122 1123 if (rdev->pm.no_fan) 1124 return -ENOENT; 1125 1126 if (pi->fan_is_controlled_by_smc) 1127 return -EINVAL; 1128 1129 if (speed > 100) 1130 return -EINVAL; 1131 1132 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 1133 1134 if (duty100 == 0) 1135 return -EINVAL; 1136 1137 tmp64 = (u64)speed * duty100; 1138 do_div(tmp64, 100); 1139 duty = (u32)tmp64; 1140 1141 tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 1142 tmp |= FDO_STATIC_DUTY(duty); 1143 WREG32_SMC(CG_FDO_CTRL0, tmp); 1144 1145 return 0; 1146 } 1147 1148 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 1149 { 1150 if (mode) { 1151 /* stop auto-manage */ 1152 if (rdev->pm.dpm.fan.ucode_fan_control) 1153 ci_fan_ctrl_stop_smc_fan_control(rdev); 1154 ci_fan_ctrl_set_static_mode(rdev, mode); 1155 } else { 1156 /* restart auto-manage */ 1157 if (rdev->pm.dpm.fan.ucode_fan_control) 1158 ci_thermal_start_smc_fan_control(rdev); 1159 else 1160 ci_fan_ctrl_set_default_mode(rdev); 1161 } 1162 } 1163 1164 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev) 1165 { 1166 struct ci_power_info *pi = ci_get_pi(rdev); 1167 u32 tmp; 1168 1169 if (pi->fan_is_controlled_by_smc) 1170 return 0; 1171 1172 tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 1173 return (tmp >> FDO_PWM_MODE_SHIFT); 1174 } 1175 1176 #if 0 1177 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 1178 u32 *speed) 1179 { 1180 u32 tach_period; 1181 u32 xclk = radeon_get_xclk(rdev); 1182 1183 if (rdev->pm.no_fan) 1184 return -ENOENT; 1185 1186 if (rdev->pm.fan_pulses_per_revolution == 0) 1187 return -ENOENT; 1188 1189 tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 1190 if (tach_period == 0) 1191 return -ENOENT; 1192 1193 *speed = 60 * xclk * 10000 / tach_period; 1194 1195 return 0; 1196 } 1197 1198 static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 1199 u32 speed) 1200 { 1201 u32 tach_period, tmp; 1202 u32 xclk = radeon_get_xclk(rdev); 1203 1204 if (rdev->pm.no_fan) 1205 return -ENOENT; 1206 1207 if (rdev->pm.fan_pulses_per_revolution == 0) 1208 return -ENOENT; 1209 1210 if ((speed < rdev->pm.fan_min_rpm) || 1211 (speed > rdev->pm.fan_max_rpm)) 1212 return -EINVAL; 1213 1214 if (rdev->pm.dpm.fan.ucode_fan_control) 1215 ci_fan_ctrl_stop_smc_fan_control(rdev); 1216 1217 tach_period = 60 * xclk * 10000 / (8 * speed); 1218 tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 1219 tmp |= TARGET_PERIOD(tach_period); 1220 WREG32_SMC(CG_TACH_CTRL, tmp); 1221 1222 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 1223 1224 return 0; 1225 } 1226 #endif 1227 1228 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev) 1229 { 1230 struct ci_power_info *pi = ci_get_pi(rdev); 1231 u32 tmp; 1232 1233 if (!pi->fan_ctrl_is_in_default_mode) { 1234 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 1235 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); 1236 WREG32_SMC(CG_FDO_CTRL2, tmp); 1237 1238 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; 1239 tmp |= TMIN(pi->t_min); 1240 WREG32_SMC(CG_FDO_CTRL2, tmp); 1241 pi->fan_ctrl_is_in_default_mode = true; 1242 } 1243 } 1244 1245 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev) 1246 { 1247 if (rdev->pm.dpm.fan.ucode_fan_control) { 1248 ci_fan_ctrl_start_smc_fan_control(rdev); 1249 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 1250 } 1251 } 1252 1253 static void ci_thermal_initialize(struct radeon_device *rdev) 1254 { 1255 u32 tmp; 1256 1257 if (rdev->pm.fan_pulses_per_revolution) { 1258 tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 1259 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 1260 WREG32_SMC(CG_TACH_CTRL, tmp); 1261 } 1262 1263 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 1264 tmp |= TACH_PWM_RESP_RATE(0x28); 1265 WREG32_SMC(CG_FDO_CTRL2, tmp); 1266 } 1267 1268 static int ci_thermal_start_thermal_controller(struct radeon_device *rdev) 1269 { 1270 int ret; 1271 1272 ci_thermal_initialize(rdev); 1273 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 1274 if (ret) 1275 return ret; 1276 ret = ci_thermal_enable_alert(rdev, true); 1277 if (ret) 1278 return ret; 1279 if (rdev->pm.dpm.fan.ucode_fan_control) { 1280 ret = ci_thermal_setup_fan_table(rdev); 1281 if (ret) 1282 return ret; 1283 ci_thermal_start_smc_fan_control(rdev); 1284 } 1285 1286 return 0; 1287 } 1288 1289 static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev) 1290 { 1291 if (!rdev->pm.no_fan) 1292 ci_fan_ctrl_set_default_mode(rdev); 1293 } 1294 1295 #if 0 1296 static int ci_read_smc_soft_register(struct radeon_device *rdev, 1297 u16 reg_offset, u32 *value) 1298 { 1299 struct ci_power_info *pi = ci_get_pi(rdev); 1300 1301 return ci_read_smc_sram_dword(rdev, 1302 pi->soft_regs_start + reg_offset, 1303 value, pi->sram_end); 1304 } 1305 #endif 1306 1307 static int ci_write_smc_soft_register(struct radeon_device *rdev, 1308 u16 reg_offset, u32 value) 1309 { 1310 struct ci_power_info *pi = ci_get_pi(rdev); 1311 1312 return ci_write_smc_sram_dword(rdev, 1313 pi->soft_regs_start + reg_offset, 1314 value, pi->sram_end); 1315 } 1316 1317 static void ci_init_fps_limits(struct radeon_device *rdev) 1318 { 1319 struct ci_power_info *pi = ci_get_pi(rdev); 1320 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; 1321 1322 if (pi->caps_fps) { 1323 u16 tmp; 1324 1325 tmp = 45; 1326 table->FpsHighT = cpu_to_be16(tmp); 1327 1328 tmp = 30; 1329 table->FpsLowT = cpu_to_be16(tmp); 1330 } 1331 } 1332 1333 static int ci_update_sclk_t(struct radeon_device *rdev) 1334 { 1335 struct ci_power_info *pi = ci_get_pi(rdev); 1336 int ret = 0; 1337 u32 low_sclk_interrupt_t = 0; 1338 1339 if (pi->caps_sclk_throttle_low_notification) { 1340 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); 1341 1342 ret = ci_copy_bytes_to_smc(rdev, 1343 pi->dpm_table_start + 1344 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT), 1345 (u8 *)&low_sclk_interrupt_t, 1346 sizeof(u32), pi->sram_end); 1347 1348 } 1349 1350 return ret; 1351 } 1352 1353 static void ci_get_leakage_voltages(struct radeon_device *rdev) 1354 { 1355 struct ci_power_info *pi = ci_get_pi(rdev); 1356 u16 leakage_id, virtual_voltage_id; 1357 u16 vddc, vddci; 1358 int i; 1359 1360 pi->vddc_leakage.count = 0; 1361 pi->vddci_leakage.count = 0; 1362 1363 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { 1364 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { 1365 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 1366 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0) 1367 continue; 1368 if (vddc != 0 && vddc != virtual_voltage_id) { 1369 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; 1370 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; 1371 pi->vddc_leakage.count++; 1372 } 1373 } 1374 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) { 1375 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { 1376 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 1377 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci, 1378 virtual_voltage_id, 1379 leakage_id) == 0) { 1380 if (vddc != 0 && vddc != virtual_voltage_id) { 1381 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; 1382 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; 1383 pi->vddc_leakage.count++; 1384 } 1385 if (vddci != 0 && vddci != virtual_voltage_id) { 1386 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; 1387 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; 1388 pi->vddci_leakage.count++; 1389 } 1390 } 1391 } 1392 } 1393 } 1394 1395 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 1396 { 1397 struct ci_power_info *pi = ci_get_pi(rdev); 1398 bool want_thermal_protection; 1399 enum radeon_dpm_event_src dpm_event_src; 1400 u32 tmp; 1401 1402 switch (sources) { 1403 case 0: 1404 default: 1405 want_thermal_protection = false; 1406 break; 1407 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 1408 want_thermal_protection = true; 1409 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 1410 break; 1411 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 1412 want_thermal_protection = true; 1413 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 1414 break; 1415 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 1416 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 1417 want_thermal_protection = true; 1418 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 1419 break; 1420 } 1421 1422 if (want_thermal_protection) { 1423 #if 0 1424 /* XXX: need to figure out how to handle this properly */ 1425 tmp = RREG32_SMC(CG_THERMAL_CTRL); 1426 tmp &= DPM_EVENT_SRC_MASK; 1427 tmp |= DPM_EVENT_SRC(dpm_event_src); 1428 WREG32_SMC(CG_THERMAL_CTRL, tmp); 1429 #endif 1430 1431 tmp = RREG32_SMC(GENERAL_PWRMGT); 1432 if (pi->thermal_protection) 1433 tmp &= ~THERMAL_PROTECTION_DIS; 1434 else 1435 tmp |= THERMAL_PROTECTION_DIS; 1436 WREG32_SMC(GENERAL_PWRMGT, tmp); 1437 } else { 1438 tmp = RREG32_SMC(GENERAL_PWRMGT); 1439 tmp |= THERMAL_PROTECTION_DIS; 1440 WREG32_SMC(GENERAL_PWRMGT, tmp); 1441 } 1442 } 1443 1444 static void ci_enable_auto_throttle_source(struct radeon_device *rdev, 1445 enum radeon_dpm_auto_throttle_src source, 1446 bool enable) 1447 { 1448 struct ci_power_info *pi = ci_get_pi(rdev); 1449 1450 if (enable) { 1451 if (!(pi->active_auto_throttle_sources & (1 << source))) { 1452 pi->active_auto_throttle_sources |= 1 << source; 1453 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 1454 } 1455 } else { 1456 if (pi->active_auto_throttle_sources & (1 << source)) { 1457 pi->active_auto_throttle_sources &= ~(1 << source); 1458 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 1459 } 1460 } 1461 } 1462 1463 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev) 1464 { 1465 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) 1466 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt); 1467 } 1468 1469 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev) 1470 { 1471 struct ci_power_info *pi = ci_get_pi(rdev); 1472 PPSMC_Result smc_result; 1473 1474 if (!pi->need_update_smu7_dpm_table) 1475 return 0; 1476 1477 if ((!pi->sclk_dpm_key_disabled) && 1478 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 1479 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel); 1480 if (smc_result != PPSMC_Result_OK) 1481 return -EINVAL; 1482 } 1483 1484 if ((!pi->mclk_dpm_key_disabled) && 1485 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 1486 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel); 1487 if (smc_result != PPSMC_Result_OK) 1488 return -EINVAL; 1489 } 1490 1491 pi->need_update_smu7_dpm_table = 0; 1492 return 0; 1493 } 1494 1495 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable) 1496 { 1497 struct ci_power_info *pi = ci_get_pi(rdev); 1498 PPSMC_Result smc_result; 1499 1500 if (enable) { 1501 if (!pi->sclk_dpm_key_disabled) { 1502 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable); 1503 if (smc_result != PPSMC_Result_OK) 1504 return -EINVAL; 1505 } 1506 1507 if (!pi->mclk_dpm_key_disabled) { 1508 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable); 1509 if (smc_result != PPSMC_Result_OK) 1510 return -EINVAL; 1511 1512 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN); 1513 1514 WREG32_SMC(LCAC_MC0_CNTL, 0x05); 1515 WREG32_SMC(LCAC_MC1_CNTL, 0x05); 1516 WREG32_SMC(LCAC_CPL_CNTL, 0x100005); 1517 1518 udelay(10); 1519 1520 WREG32_SMC(LCAC_MC0_CNTL, 0x400005); 1521 WREG32_SMC(LCAC_MC1_CNTL, 0x400005); 1522 WREG32_SMC(LCAC_CPL_CNTL, 0x500005); 1523 } 1524 } else { 1525 if (!pi->sclk_dpm_key_disabled) { 1526 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable); 1527 if (smc_result != PPSMC_Result_OK) 1528 return -EINVAL; 1529 } 1530 1531 if (!pi->mclk_dpm_key_disabled) { 1532 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable); 1533 if (smc_result != PPSMC_Result_OK) 1534 return -EINVAL; 1535 } 1536 } 1537 1538 return 0; 1539 } 1540 1541 static int ci_start_dpm(struct radeon_device *rdev) 1542 { 1543 struct ci_power_info *pi = ci_get_pi(rdev); 1544 PPSMC_Result smc_result; 1545 int ret; 1546 u32 tmp; 1547 1548 tmp = RREG32_SMC(GENERAL_PWRMGT); 1549 tmp |= GLOBAL_PWRMGT_EN; 1550 WREG32_SMC(GENERAL_PWRMGT, tmp); 1551 1552 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1553 tmp |= DYNAMIC_PM_EN; 1554 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1555 1556 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000); 1557 1558 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN); 1559 1560 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable); 1561 if (smc_result != PPSMC_Result_OK) 1562 return -EINVAL; 1563 1564 ret = ci_enable_sclk_mclk_dpm(rdev, true); 1565 if (ret) 1566 return ret; 1567 1568 if (!pi->pcie_dpm_key_disabled) { 1569 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable); 1570 if (smc_result != PPSMC_Result_OK) 1571 return -EINVAL; 1572 } 1573 1574 return 0; 1575 } 1576 1577 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev) 1578 { 1579 struct ci_power_info *pi = ci_get_pi(rdev); 1580 PPSMC_Result smc_result; 1581 1582 if (!pi->need_update_smu7_dpm_table) 1583 return 0; 1584 1585 if ((!pi->sclk_dpm_key_disabled) && 1586 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 1587 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel); 1588 if (smc_result != PPSMC_Result_OK) 1589 return -EINVAL; 1590 } 1591 1592 if ((!pi->mclk_dpm_key_disabled) && 1593 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 1594 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel); 1595 if (smc_result != PPSMC_Result_OK) 1596 return -EINVAL; 1597 } 1598 1599 return 0; 1600 } 1601 1602 static int ci_stop_dpm(struct radeon_device *rdev) 1603 { 1604 struct ci_power_info *pi = ci_get_pi(rdev); 1605 PPSMC_Result smc_result; 1606 int ret; 1607 u32 tmp; 1608 1609 tmp = RREG32_SMC(GENERAL_PWRMGT); 1610 tmp &= ~GLOBAL_PWRMGT_EN; 1611 WREG32_SMC(GENERAL_PWRMGT, tmp); 1612 1613 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1614 tmp &= ~DYNAMIC_PM_EN; 1615 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1616 1617 if (!pi->pcie_dpm_key_disabled) { 1618 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable); 1619 if (smc_result != PPSMC_Result_OK) 1620 return -EINVAL; 1621 } 1622 1623 ret = ci_enable_sclk_mclk_dpm(rdev, false); 1624 if (ret) 1625 return ret; 1626 1627 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable); 1628 if (smc_result != PPSMC_Result_OK) 1629 return -EINVAL; 1630 1631 return 0; 1632 } 1633 1634 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable) 1635 { 1636 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1637 1638 if (enable) 1639 tmp &= ~SCLK_PWRMGT_OFF; 1640 else 1641 tmp |= SCLK_PWRMGT_OFF; 1642 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1643 } 1644 1645 #if 0 1646 static int ci_notify_hw_of_power_source(struct radeon_device *rdev, 1647 bool ac_power) 1648 { 1649 struct ci_power_info *pi = ci_get_pi(rdev); 1650 struct radeon_cac_tdp_table *cac_tdp_table = 1651 rdev->pm.dpm.dyn_state.cac_tdp_table; 1652 u32 power_limit; 1653 1654 if (ac_power) 1655 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); 1656 else 1657 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256); 1658 1659 ci_set_power_limit(rdev, power_limit); 1660 1661 if (pi->caps_automatic_dc_transition) { 1662 if (ac_power) 1663 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC); 1664 else 1665 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp); 1666 } 1667 1668 return 0; 1669 } 1670 #endif 1671 1672 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 1673 PPSMC_Msg msg, u32 parameter) 1674 { 1675 WREG32(SMC_MSG_ARG_0, parameter); 1676 return ci_send_msg_to_smc(rdev, msg); 1677 } 1678 1679 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev, 1680 PPSMC_Msg msg, u32 *parameter) 1681 { 1682 PPSMC_Result smc_result; 1683 1684 smc_result = ci_send_msg_to_smc(rdev, msg); 1685 1686 if ((smc_result == PPSMC_Result_OK) && parameter) 1687 *parameter = RREG32(SMC_MSG_ARG_0); 1688 1689 return smc_result; 1690 } 1691 1692 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n) 1693 { 1694 struct ci_power_info *pi = ci_get_pi(rdev); 1695 1696 if (!pi->sclk_dpm_key_disabled) { 1697 PPSMC_Result smc_result = 1698 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n); 1699 if (smc_result != PPSMC_Result_OK) 1700 return -EINVAL; 1701 } 1702 1703 return 0; 1704 } 1705 1706 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n) 1707 { 1708 struct ci_power_info *pi = ci_get_pi(rdev); 1709 1710 if (!pi->mclk_dpm_key_disabled) { 1711 PPSMC_Result smc_result = 1712 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n); 1713 if (smc_result != PPSMC_Result_OK) 1714 return -EINVAL; 1715 } 1716 1717 return 0; 1718 } 1719 1720 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n) 1721 { 1722 struct ci_power_info *pi = ci_get_pi(rdev); 1723 1724 if (!pi->pcie_dpm_key_disabled) { 1725 PPSMC_Result smc_result = 1726 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n); 1727 if (smc_result != PPSMC_Result_OK) 1728 return -EINVAL; 1729 } 1730 1731 return 0; 1732 } 1733 1734 static int ci_set_power_limit(struct radeon_device *rdev, u32 n) 1735 { 1736 struct ci_power_info *pi = ci_get_pi(rdev); 1737 1738 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { 1739 PPSMC_Result smc_result = 1740 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n); 1741 if (smc_result != PPSMC_Result_OK) 1742 return -EINVAL; 1743 } 1744 1745 return 0; 1746 } 1747 1748 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, 1749 u32 target_tdp) 1750 { 1751 PPSMC_Result smc_result = 1752 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); 1753 if (smc_result != PPSMC_Result_OK) 1754 return -EINVAL; 1755 return 0; 1756 } 1757 1758 #if 0 1759 static int ci_set_boot_state(struct radeon_device *rdev) 1760 { 1761 return ci_enable_sclk_mclk_dpm(rdev, false); 1762 } 1763 #endif 1764 1765 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev) 1766 { 1767 u32 sclk_freq; 1768 PPSMC_Result smc_result = 1769 ci_send_msg_to_smc_return_parameter(rdev, 1770 PPSMC_MSG_API_GetSclkFrequency, 1771 &sclk_freq); 1772 if (smc_result != PPSMC_Result_OK) 1773 sclk_freq = 0; 1774 1775 return sclk_freq; 1776 } 1777 1778 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev) 1779 { 1780 u32 mclk_freq; 1781 PPSMC_Result smc_result = 1782 ci_send_msg_to_smc_return_parameter(rdev, 1783 PPSMC_MSG_API_GetMclkFrequency, 1784 &mclk_freq); 1785 if (smc_result != PPSMC_Result_OK) 1786 mclk_freq = 0; 1787 1788 return mclk_freq; 1789 } 1790 1791 static void ci_dpm_start_smc(struct radeon_device *rdev) 1792 { 1793 int i; 1794 1795 ci_program_jump_on_start(rdev); 1796 ci_start_smc_clock(rdev); 1797 ci_start_smc(rdev); 1798 for (i = 0; i < rdev->usec_timeout; i++) { 1799 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED) 1800 break; 1801 } 1802 } 1803 1804 static void ci_dpm_stop_smc(struct radeon_device *rdev) 1805 { 1806 ci_reset_smc(rdev); 1807 ci_stop_smc_clock(rdev); 1808 } 1809 1810 static int ci_process_firmware_header(struct radeon_device *rdev) 1811 { 1812 struct ci_power_info *pi = ci_get_pi(rdev); 1813 u32 tmp; 1814 int ret; 1815 1816 ret = ci_read_smc_sram_dword(rdev, 1817 SMU7_FIRMWARE_HEADER_LOCATION + 1818 offsetof(SMU7_Firmware_Header, DpmTable), 1819 &tmp, pi->sram_end); 1820 if (ret) 1821 return ret; 1822 1823 pi->dpm_table_start = tmp; 1824 1825 ret = ci_read_smc_sram_dword(rdev, 1826 SMU7_FIRMWARE_HEADER_LOCATION + 1827 offsetof(SMU7_Firmware_Header, SoftRegisters), 1828 &tmp, pi->sram_end); 1829 if (ret) 1830 return ret; 1831 1832 pi->soft_regs_start = tmp; 1833 1834 ret = ci_read_smc_sram_dword(rdev, 1835 SMU7_FIRMWARE_HEADER_LOCATION + 1836 offsetof(SMU7_Firmware_Header, mcRegisterTable), 1837 &tmp, pi->sram_end); 1838 if (ret) 1839 return ret; 1840 1841 pi->mc_reg_table_start = tmp; 1842 1843 ret = ci_read_smc_sram_dword(rdev, 1844 SMU7_FIRMWARE_HEADER_LOCATION + 1845 offsetof(SMU7_Firmware_Header, FanTable), 1846 &tmp, pi->sram_end); 1847 if (ret) 1848 return ret; 1849 1850 pi->fan_table_start = tmp; 1851 1852 ret = ci_read_smc_sram_dword(rdev, 1853 SMU7_FIRMWARE_HEADER_LOCATION + 1854 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable), 1855 &tmp, pi->sram_end); 1856 if (ret) 1857 return ret; 1858 1859 pi->arb_table_start = tmp; 1860 1861 return 0; 1862 } 1863 1864 static void ci_read_clock_registers(struct radeon_device *rdev) 1865 { 1866 struct ci_power_info *pi = ci_get_pi(rdev); 1867 1868 pi->clock_registers.cg_spll_func_cntl = 1869 RREG32_SMC(CG_SPLL_FUNC_CNTL); 1870 pi->clock_registers.cg_spll_func_cntl_2 = 1871 RREG32_SMC(CG_SPLL_FUNC_CNTL_2); 1872 pi->clock_registers.cg_spll_func_cntl_3 = 1873 RREG32_SMC(CG_SPLL_FUNC_CNTL_3); 1874 pi->clock_registers.cg_spll_func_cntl_4 = 1875 RREG32_SMC(CG_SPLL_FUNC_CNTL_4); 1876 pi->clock_registers.cg_spll_spread_spectrum = 1877 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); 1878 pi->clock_registers.cg_spll_spread_spectrum_2 = 1879 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2); 1880 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 1881 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 1882 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 1883 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 1884 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 1885 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 1886 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 1887 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 1888 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 1889 } 1890 1891 static void ci_init_sclk_t(struct radeon_device *rdev) 1892 { 1893 struct ci_power_info *pi = ci_get_pi(rdev); 1894 1895 pi->low_sclk_interrupt_t = 0; 1896 } 1897 1898 static void ci_enable_thermal_protection(struct radeon_device *rdev, 1899 bool enable) 1900 { 1901 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 1902 1903 if (enable) 1904 tmp &= ~THERMAL_PROTECTION_DIS; 1905 else 1906 tmp |= THERMAL_PROTECTION_DIS; 1907 WREG32_SMC(GENERAL_PWRMGT, tmp); 1908 } 1909 1910 static void ci_enable_acpi_power_management(struct radeon_device *rdev) 1911 { 1912 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 1913 1914 tmp |= STATIC_PM_EN; 1915 1916 WREG32_SMC(GENERAL_PWRMGT, tmp); 1917 } 1918 1919 #if 0 1920 static int ci_enter_ulp_state(struct radeon_device *rdev) 1921 { 1922 1923 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 1924 1925 udelay(25000); 1926 1927 return 0; 1928 } 1929 1930 static int ci_exit_ulp_state(struct radeon_device *rdev) 1931 { 1932 int i; 1933 1934 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 1935 1936 udelay(7000); 1937 1938 for (i = 0; i < rdev->usec_timeout; i++) { 1939 if (RREG32(SMC_RESP_0) == 1) 1940 break; 1941 udelay(1000); 1942 } 1943 1944 return 0; 1945 } 1946 #endif 1947 1948 static int ci_notify_smc_display_change(struct radeon_device *rdev, 1949 bool has_display) 1950 { 1951 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 1952 1953 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL; 1954 } 1955 1956 static int ci_enable_ds_master_switch(struct radeon_device *rdev, 1957 bool enable) 1958 { 1959 struct ci_power_info *pi = ci_get_pi(rdev); 1960 1961 if (enable) { 1962 if (pi->caps_sclk_ds) { 1963 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK) 1964 return -EINVAL; 1965 } else { 1966 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) 1967 return -EINVAL; 1968 } 1969 } else { 1970 if (pi->caps_sclk_ds) { 1971 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) 1972 return -EINVAL; 1973 } 1974 } 1975 1976 return 0; 1977 } 1978 1979 static void ci_program_display_gap(struct radeon_device *rdev) 1980 { 1981 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); 1982 u32 pre_vbi_time_in_us; 1983 u32 frame_time_in_us; 1984 u32 ref_clock = rdev->clock.spll.reference_freq; 1985 u32 refresh_rate = r600_dpm_get_vrefresh(rdev); 1986 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 1987 1988 tmp &= ~DISP_GAP_MASK; 1989 if (rdev->pm.dpm.new_active_crtc_count > 0) 1990 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 1991 else 1992 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE); 1993 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); 1994 1995 if (refresh_rate == 0) 1996 refresh_rate = 60; 1997 if (vblank_time == 0xffffffff) 1998 vblank_time = 500; 1999 frame_time_in_us = 1000000 / refresh_rate; 2000 pre_vbi_time_in_us = 2001 frame_time_in_us - 200 - vblank_time; 2002 tmp = pre_vbi_time_in_us * (ref_clock / 100); 2003 2004 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp); 2005 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64); 2006 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); 2007 2008 2009 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); 2010 2011 } 2012 2013 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 2014 { 2015 struct ci_power_info *pi = ci_get_pi(rdev); 2016 u32 tmp; 2017 2018 if (enable) { 2019 if (pi->caps_sclk_ss_support) { 2020 tmp = RREG32_SMC(GENERAL_PWRMGT); 2021 tmp |= DYN_SPREAD_SPECTRUM_EN; 2022 WREG32_SMC(GENERAL_PWRMGT, tmp); 2023 } 2024 } else { 2025 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); 2026 tmp &= ~SSEN; 2027 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp); 2028 2029 tmp = RREG32_SMC(GENERAL_PWRMGT); 2030 tmp &= ~DYN_SPREAD_SPECTRUM_EN; 2031 WREG32_SMC(GENERAL_PWRMGT, tmp); 2032 } 2033 } 2034 2035 static void ci_program_sstp(struct radeon_device *rdev) 2036 { 2037 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 2038 } 2039 2040 static void ci_enable_display_gap(struct radeon_device *rdev) 2041 { 2042 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); 2043 2044 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK); 2045 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 2046 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK)); 2047 2048 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); 2049 } 2050 2051 static void ci_program_vc(struct radeon_device *rdev) 2052 { 2053 u32 tmp; 2054 2055 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 2056 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT); 2057 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 2058 2059 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0); 2060 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1); 2061 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2); 2062 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3); 2063 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4); 2064 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5); 2065 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6); 2066 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7); 2067 } 2068 2069 static void ci_clear_vc(struct radeon_device *rdev) 2070 { 2071 u32 tmp; 2072 2073 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 2074 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT); 2075 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 2076 2077 WREG32_SMC(CG_FTV_0, 0); 2078 WREG32_SMC(CG_FTV_1, 0); 2079 WREG32_SMC(CG_FTV_2, 0); 2080 WREG32_SMC(CG_FTV_3, 0); 2081 WREG32_SMC(CG_FTV_4, 0); 2082 WREG32_SMC(CG_FTV_5, 0); 2083 WREG32_SMC(CG_FTV_6, 0); 2084 WREG32_SMC(CG_FTV_7, 0); 2085 } 2086 2087 static int ci_upload_firmware(struct radeon_device *rdev) 2088 { 2089 struct ci_power_info *pi = ci_get_pi(rdev); 2090 int i, ret; 2091 2092 for (i = 0; i < rdev->usec_timeout; i++) { 2093 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE) 2094 break; 2095 } 2096 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1); 2097 2098 ci_stop_smc_clock(rdev); 2099 ci_reset_smc(rdev); 2100 2101 ret = ci_load_smc_ucode(rdev, pi->sram_end); 2102 2103 return ret; 2104 2105 } 2106 2107 static int ci_get_svi2_voltage_table(struct radeon_device *rdev, 2108 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 2109 struct atom_voltage_table *voltage_table) 2110 { 2111 u32 i; 2112 2113 if (voltage_dependency_table == NULL) 2114 return -EINVAL; 2115 2116 voltage_table->mask_low = 0; 2117 voltage_table->phase_delay = 0; 2118 2119 voltage_table->count = voltage_dependency_table->count; 2120 for (i = 0; i < voltage_table->count; i++) { 2121 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 2122 voltage_table->entries[i].smio_low = 0; 2123 } 2124 2125 return 0; 2126 } 2127 2128 static int ci_construct_voltage_tables(struct radeon_device *rdev) 2129 { 2130 struct ci_power_info *pi = ci_get_pi(rdev); 2131 int ret; 2132 2133 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 2134 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 2135 VOLTAGE_OBJ_GPIO_LUT, 2136 &pi->vddc_voltage_table); 2137 if (ret) 2138 return ret; 2139 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 2140 ret = ci_get_svi2_voltage_table(rdev, 2141 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2142 &pi->vddc_voltage_table); 2143 if (ret) 2144 return ret; 2145 } 2146 2147 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) 2148 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC, 2149 &pi->vddc_voltage_table); 2150 2151 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 2152 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 2153 VOLTAGE_OBJ_GPIO_LUT, 2154 &pi->vddci_voltage_table); 2155 if (ret) 2156 return ret; 2157 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 2158 ret = ci_get_svi2_voltage_table(rdev, 2159 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2160 &pi->vddci_voltage_table); 2161 if (ret) 2162 return ret; 2163 } 2164 2165 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) 2166 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI, 2167 &pi->vddci_voltage_table); 2168 2169 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { 2170 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 2171 VOLTAGE_OBJ_GPIO_LUT, 2172 &pi->mvdd_voltage_table); 2173 if (ret) 2174 return ret; 2175 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 2176 ret = ci_get_svi2_voltage_table(rdev, 2177 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 2178 &pi->mvdd_voltage_table); 2179 if (ret) 2180 return ret; 2181 } 2182 2183 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) 2184 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD, 2185 &pi->mvdd_voltage_table); 2186 2187 return 0; 2188 } 2189 2190 static void ci_populate_smc_voltage_table(struct radeon_device *rdev, 2191 struct atom_voltage_table_entry *voltage_table, 2192 SMU7_Discrete_VoltageLevel *smc_voltage_table) 2193 { 2194 int ret; 2195 2196 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table, 2197 &smc_voltage_table->StdVoltageHiSidd, 2198 &smc_voltage_table->StdVoltageLoSidd); 2199 2200 if (ret) { 2201 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE; 2202 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE; 2203 } 2204 2205 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE); 2206 smc_voltage_table->StdVoltageHiSidd = 2207 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd); 2208 smc_voltage_table->StdVoltageLoSidd = 2209 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd); 2210 } 2211 2212 static int ci_populate_smc_vddc_table(struct radeon_device *rdev, 2213 SMU7_Discrete_DpmTable *table) 2214 { 2215 struct ci_power_info *pi = ci_get_pi(rdev); 2216 unsigned int count; 2217 2218 table->VddcLevelCount = pi->vddc_voltage_table.count; 2219 for (count = 0; count < table->VddcLevelCount; count++) { 2220 ci_populate_smc_voltage_table(rdev, 2221 &pi->vddc_voltage_table.entries[count], 2222 &table->VddcLevel[count]); 2223 2224 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 2225 table->VddcLevel[count].Smio |= 2226 pi->vddc_voltage_table.entries[count].smio_low; 2227 else 2228 table->VddcLevel[count].Smio = 0; 2229 } 2230 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); 2231 2232 return 0; 2233 } 2234 2235 static int ci_populate_smc_vddci_table(struct radeon_device *rdev, 2236 SMU7_Discrete_DpmTable *table) 2237 { 2238 unsigned int count; 2239 struct ci_power_info *pi = ci_get_pi(rdev); 2240 2241 table->VddciLevelCount = pi->vddci_voltage_table.count; 2242 for (count = 0; count < table->VddciLevelCount; count++) { 2243 ci_populate_smc_voltage_table(rdev, 2244 &pi->vddci_voltage_table.entries[count], 2245 &table->VddciLevel[count]); 2246 2247 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 2248 table->VddciLevel[count].Smio |= 2249 pi->vddci_voltage_table.entries[count].smio_low; 2250 else 2251 table->VddciLevel[count].Smio = 0; 2252 } 2253 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); 2254 2255 return 0; 2256 } 2257 2258 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev, 2259 SMU7_Discrete_DpmTable *table) 2260 { 2261 struct ci_power_info *pi = ci_get_pi(rdev); 2262 unsigned int count; 2263 2264 table->MvddLevelCount = pi->mvdd_voltage_table.count; 2265 for (count = 0; count < table->MvddLevelCount; count++) { 2266 ci_populate_smc_voltage_table(rdev, 2267 &pi->mvdd_voltage_table.entries[count], 2268 &table->MvddLevel[count]); 2269 2270 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) 2271 table->MvddLevel[count].Smio |= 2272 pi->mvdd_voltage_table.entries[count].smio_low; 2273 else 2274 table->MvddLevel[count].Smio = 0; 2275 } 2276 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); 2277 2278 return 0; 2279 } 2280 2281 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev, 2282 SMU7_Discrete_DpmTable *table) 2283 { 2284 int ret; 2285 2286 ret = ci_populate_smc_vddc_table(rdev, table); 2287 if (ret) 2288 return ret; 2289 2290 ret = ci_populate_smc_vddci_table(rdev, table); 2291 if (ret) 2292 return ret; 2293 2294 ret = ci_populate_smc_mvdd_table(rdev, table); 2295 if (ret) 2296 return ret; 2297 2298 return 0; 2299 } 2300 2301 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 2302 SMU7_Discrete_VoltageLevel *voltage) 2303 { 2304 struct ci_power_info *pi = ci_get_pi(rdev); 2305 u32 i = 0; 2306 2307 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 2308 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { 2309 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { 2310 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; 2311 break; 2312 } 2313 } 2314 2315 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) 2316 return -EINVAL; 2317 } 2318 2319 return -EINVAL; 2320 } 2321 2322 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 2323 struct atom_voltage_table_entry *voltage_table, 2324 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd) 2325 { 2326 u16 v_index, idx; 2327 bool voltage_found = false; 2328 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE; 2329 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE; 2330 2331 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 2332 return -EINVAL; 2333 2334 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 2335 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 2336 if (voltage_table->value == 2337 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 2338 voltage_found = true; 2339 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 2340 idx = v_index; 2341 else 2342 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; 2343 *std_voltage_lo_sidd = 2344 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; 2345 *std_voltage_hi_sidd = 2346 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; 2347 break; 2348 } 2349 } 2350 2351 if (!voltage_found) { 2352 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 2353 if (voltage_table->value <= 2354 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 2355 voltage_found = true; 2356 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 2357 idx = v_index; 2358 else 2359 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; 2360 *std_voltage_lo_sidd = 2361 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; 2362 *std_voltage_hi_sidd = 2363 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; 2364 break; 2365 } 2366 } 2367 } 2368 } 2369 2370 return 0; 2371 } 2372 2373 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev, 2374 const struct radeon_phase_shedding_limits_table *limits, 2375 u32 sclk, 2376 u32 *phase_shedding) 2377 { 2378 unsigned int i; 2379 2380 *phase_shedding = 1; 2381 2382 for (i = 0; i < limits->count; i++) { 2383 if (sclk < limits->entries[i].sclk) { 2384 *phase_shedding = i; 2385 break; 2386 } 2387 } 2388 } 2389 2390 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev, 2391 const struct radeon_phase_shedding_limits_table *limits, 2392 u32 mclk, 2393 u32 *phase_shedding) 2394 { 2395 unsigned int i; 2396 2397 *phase_shedding = 1; 2398 2399 for (i = 0; i < limits->count; i++) { 2400 if (mclk < limits->entries[i].mclk) { 2401 *phase_shedding = i; 2402 break; 2403 } 2404 } 2405 } 2406 2407 static int ci_init_arb_table_index(struct radeon_device *rdev) 2408 { 2409 struct ci_power_info *pi = ci_get_pi(rdev); 2410 u32 tmp; 2411 int ret; 2412 2413 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, 2414 &tmp, pi->sram_end); 2415 if (ret) 2416 return ret; 2417 2418 tmp &= 0x00FFFFFF; 2419 tmp |= MC_CG_ARB_FREQ_F1 << 24; 2420 2421 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, 2422 tmp, pi->sram_end); 2423 } 2424 2425 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev, 2426 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table, 2427 u32 clock, u32 *voltage) 2428 { 2429 u32 i = 0; 2430 2431 if (allowed_clock_voltage_table->count == 0) 2432 return -EINVAL; 2433 2434 for (i = 0; i < allowed_clock_voltage_table->count; i++) { 2435 if (allowed_clock_voltage_table->entries[i].clk >= clock) { 2436 *voltage = allowed_clock_voltage_table->entries[i].v; 2437 return 0; 2438 } 2439 } 2440 2441 *voltage = allowed_clock_voltage_table->entries[i-1].v; 2442 2443 return 0; 2444 } 2445 2446 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev, 2447 u32 sclk, u32 min_sclk_in_sr) 2448 { 2449 u32 i; 2450 u32 tmp; 2451 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ? 2452 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK; 2453 2454 if (sclk < min) 2455 return 0; 2456 2457 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { 2458 tmp = sclk / (1 << i); 2459 if (tmp >= min || i == 0) 2460 break; 2461 } 2462 2463 return (u8)i; 2464 } 2465 2466 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 2467 { 2468 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 2469 } 2470 2471 static int ci_reset_to_default(struct radeon_device *rdev) 2472 { 2473 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 2474 0 : -EINVAL; 2475 } 2476 2477 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev) 2478 { 2479 u32 tmp; 2480 2481 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8; 2482 2483 if (tmp == MC_CG_ARB_FREQ_F0) 2484 return 0; 2485 2486 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 2487 } 2488 2489 static void ci_register_patching_mc_arb(struct radeon_device *rdev, 2490 const u32 engine_clock, 2491 const u32 memory_clock, 2492 u32 *dram_timimg2) 2493 { 2494 bool patch; 2495 u32 tmp, tmp2; 2496 2497 tmp = RREG32(MC_SEQ_MISC0); 2498 patch = ((tmp & 0x0000f00) == 0x300) ? true : false; 2499 2500 if (patch && 2501 ((rdev->pdev->device == 0x67B0) || 2502 (rdev->pdev->device == 0x67B1))) { 2503 if ((memory_clock > 100000) && (memory_clock <= 125000)) { 2504 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; 2505 *dram_timimg2 &= ~0x00ff0000; 2506 *dram_timimg2 |= tmp2 << 16; 2507 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { 2508 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; 2509 *dram_timimg2 &= ~0x00ff0000; 2510 *dram_timimg2 |= tmp2 << 16; 2511 } 2512 } 2513 } 2514 2515 2516 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev, 2517 u32 sclk, 2518 u32 mclk, 2519 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs) 2520 { 2521 u32 dram_timing; 2522 u32 dram_timing2; 2523 u32 burst_time; 2524 2525 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk); 2526 2527 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 2528 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 2529 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 2530 2531 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2); 2532 2533 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing); 2534 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2); 2535 arb_regs->McArbBurstTime = (u8)burst_time; 2536 2537 return 0; 2538 } 2539 2540 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev) 2541 { 2542 struct ci_power_info *pi = ci_get_pi(rdev); 2543 SMU7_Discrete_MCArbDramTimingTable arb_regs; 2544 u32 i, j; 2545 int ret = 0; 2546 2547 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable)); 2548 2549 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { 2550 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { 2551 ret = ci_populate_memory_timing_parameters(rdev, 2552 pi->dpm_table.sclk_table.dpm_levels[i].value, 2553 pi->dpm_table.mclk_table.dpm_levels[j].value, 2554 &arb_regs.entries[i][j]); 2555 if (ret) 2556 break; 2557 } 2558 } 2559 2560 if (ret == 0) 2561 ret = ci_copy_bytes_to_smc(rdev, 2562 pi->arb_table_start, 2563 (u8 *)&arb_regs, 2564 sizeof(SMU7_Discrete_MCArbDramTimingTable), 2565 pi->sram_end); 2566 2567 return ret; 2568 } 2569 2570 static int ci_program_memory_timing_parameters(struct radeon_device *rdev) 2571 { 2572 struct ci_power_info *pi = ci_get_pi(rdev); 2573 2574 if (pi->need_update_smu7_dpm_table == 0) 2575 return 0; 2576 2577 return ci_do_program_memory_timing_parameters(rdev); 2578 } 2579 2580 static void ci_populate_smc_initial_state(struct radeon_device *rdev, 2581 struct radeon_ps *radeon_boot_state) 2582 { 2583 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state); 2584 struct ci_power_info *pi = ci_get_pi(rdev); 2585 u32 level = 0; 2586 2587 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { 2588 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= 2589 boot_state->performance_levels[0].sclk) { 2590 pi->smc_state_table.GraphicsBootLevel = level; 2591 break; 2592 } 2593 } 2594 2595 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { 2596 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= 2597 boot_state->performance_levels[0].mclk) { 2598 pi->smc_state_table.MemoryBootLevel = level; 2599 break; 2600 } 2601 } 2602 } 2603 2604 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) 2605 { 2606 u32 i; 2607 u32 mask_value = 0; 2608 2609 for (i = dpm_table->count; i > 0; i--) { 2610 mask_value = mask_value << 1; 2611 if (dpm_table->dpm_levels[i-1].enabled) 2612 mask_value |= 0x1; 2613 else 2614 mask_value &= 0xFFFFFFFE; 2615 } 2616 2617 return mask_value; 2618 } 2619 2620 static void ci_populate_smc_link_level(struct radeon_device *rdev, 2621 SMU7_Discrete_DpmTable *table) 2622 { 2623 struct ci_power_info *pi = ci_get_pi(rdev); 2624 struct ci_dpm_table *dpm_table = &pi->dpm_table; 2625 u32 i; 2626 2627 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { 2628 table->LinkLevel[i].PcieGenSpeed = 2629 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; 2630 table->LinkLevel[i].PcieLaneCount = 2631 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 2632 table->LinkLevel[i].EnabledForActivity = 1; 2633 table->LinkLevel[i].DownT = cpu_to_be32(5); 2634 table->LinkLevel[i].UpT = cpu_to_be32(30); 2635 } 2636 2637 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; 2638 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = 2639 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 2640 } 2641 2642 static int ci_populate_smc_uvd_level(struct radeon_device *rdev, 2643 SMU7_Discrete_DpmTable *table) 2644 { 2645 u32 count; 2646 struct atom_clock_dividers dividers; 2647 int ret = -EINVAL; 2648 2649 table->UvdLevelCount = 2650 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; 2651 2652 for (count = 0; count < table->UvdLevelCount; count++) { 2653 table->UvdLevel[count].VclkFrequency = 2654 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; 2655 table->UvdLevel[count].DclkFrequency = 2656 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; 2657 table->UvdLevel[count].MinVddc = 2658 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2659 table->UvdLevel[count].MinVddcPhases = 1; 2660 2661 ret = radeon_atom_get_clock_dividers(rdev, 2662 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2663 table->UvdLevel[count].VclkFrequency, false, ÷rs); 2664 if (ret) 2665 return ret; 2666 2667 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; 2668 2669 ret = radeon_atom_get_clock_dividers(rdev, 2670 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2671 table->UvdLevel[count].DclkFrequency, false, ÷rs); 2672 if (ret) 2673 return ret; 2674 2675 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; 2676 2677 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); 2678 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); 2679 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); 2680 } 2681 2682 return ret; 2683 } 2684 2685 static int ci_populate_smc_vce_level(struct radeon_device *rdev, 2686 SMU7_Discrete_DpmTable *table) 2687 { 2688 u32 count; 2689 struct atom_clock_dividers dividers; 2690 int ret = -EINVAL; 2691 2692 table->VceLevelCount = 2693 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; 2694 2695 for (count = 0; count < table->VceLevelCount; count++) { 2696 table->VceLevel[count].Frequency = 2697 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; 2698 table->VceLevel[count].MinVoltage = 2699 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2700 table->VceLevel[count].MinPhases = 1; 2701 2702 ret = radeon_atom_get_clock_dividers(rdev, 2703 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2704 table->VceLevel[count].Frequency, false, ÷rs); 2705 if (ret) 2706 return ret; 2707 2708 table->VceLevel[count].Divider = (u8)dividers.post_divider; 2709 2710 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); 2711 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); 2712 } 2713 2714 return ret; 2715 2716 } 2717 2718 static int ci_populate_smc_acp_level(struct radeon_device *rdev, 2719 SMU7_Discrete_DpmTable *table) 2720 { 2721 u32 count; 2722 struct atom_clock_dividers dividers; 2723 int ret = -EINVAL; 2724 2725 table->AcpLevelCount = (u8) 2726 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); 2727 2728 for (count = 0; count < table->AcpLevelCount; count++) { 2729 table->AcpLevel[count].Frequency = 2730 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; 2731 table->AcpLevel[count].MinVoltage = 2732 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; 2733 table->AcpLevel[count].MinPhases = 1; 2734 2735 ret = radeon_atom_get_clock_dividers(rdev, 2736 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2737 table->AcpLevel[count].Frequency, false, ÷rs); 2738 if (ret) 2739 return ret; 2740 2741 table->AcpLevel[count].Divider = (u8)dividers.post_divider; 2742 2743 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); 2744 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); 2745 } 2746 2747 return ret; 2748 } 2749 2750 static int ci_populate_smc_samu_level(struct radeon_device *rdev, 2751 SMU7_Discrete_DpmTable *table) 2752 { 2753 u32 count; 2754 struct atom_clock_dividers dividers; 2755 int ret = -EINVAL; 2756 2757 table->SamuLevelCount = 2758 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; 2759 2760 for (count = 0; count < table->SamuLevelCount; count++) { 2761 table->SamuLevel[count].Frequency = 2762 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; 2763 table->SamuLevel[count].MinVoltage = 2764 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; 2765 table->SamuLevel[count].MinPhases = 1; 2766 2767 ret = radeon_atom_get_clock_dividers(rdev, 2768 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2769 table->SamuLevel[count].Frequency, false, ÷rs); 2770 if (ret) 2771 return ret; 2772 2773 table->SamuLevel[count].Divider = (u8)dividers.post_divider; 2774 2775 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); 2776 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); 2777 } 2778 2779 return ret; 2780 } 2781 2782 static int ci_calculate_mclk_params(struct radeon_device *rdev, 2783 u32 memory_clock, 2784 SMU7_Discrete_MemoryLevel *mclk, 2785 bool strobe_mode, 2786 bool dll_state_on) 2787 { 2788 struct ci_power_info *pi = ci_get_pi(rdev); 2789 u32 dll_cntl = pi->clock_registers.dll_cntl; 2790 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; 2791 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; 2792 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; 2793 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; 2794 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; 2795 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; 2796 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; 2797 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; 2798 struct atom_mpll_param mpll_param; 2799 int ret; 2800 2801 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 2802 if (ret) 2803 return ret; 2804 2805 mpll_func_cntl &= ~BWCTRL_MASK; 2806 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 2807 2808 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 2809 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 2810 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 2811 2812 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 2813 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 2814 2815 if (pi->mem_gddr5) { 2816 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 2817 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 2818 YCLK_POST_DIV(mpll_param.post_div); 2819 } 2820 2821 if (pi->caps_mclk_ss_support) { 2822 struct radeon_atom_ss ss; 2823 u32 freq_nom; 2824 u32 tmp; 2825 u32 reference_clock = rdev->clock.mpll.reference_freq; 2826 2827 if (mpll_param.qdr == 1) 2828 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div); 2829 else 2830 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div); 2831 2832 tmp = (freq_nom / reference_clock); 2833 tmp = tmp * tmp; 2834 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 2835 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 2836 u32 clks = reference_clock * 5 / ss.rate; 2837 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 2838 2839 mpll_ss1 &= ~CLKV_MASK; 2840 mpll_ss1 |= CLKV(clkv); 2841 2842 mpll_ss2 &= ~CLKS_MASK; 2843 mpll_ss2 |= CLKS(clks); 2844 } 2845 } 2846 2847 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 2848 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 2849 2850 if (dll_state_on) 2851 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 2852 else 2853 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 2854 2855 mclk->MclkFrequency = memory_clock; 2856 mclk->MpllFuncCntl = mpll_func_cntl; 2857 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; 2858 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; 2859 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; 2860 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; 2861 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; 2862 mclk->DllCntl = dll_cntl; 2863 mclk->MpllSs1 = mpll_ss1; 2864 mclk->MpllSs2 = mpll_ss2; 2865 2866 return 0; 2867 } 2868 2869 static int ci_populate_single_memory_level(struct radeon_device *rdev, 2870 u32 memory_clock, 2871 SMU7_Discrete_MemoryLevel *memory_level) 2872 { 2873 struct ci_power_info *pi = ci_get_pi(rdev); 2874 int ret; 2875 bool dll_state_on; 2876 2877 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { 2878 ret = ci_get_dependency_volt_by_clk(rdev, 2879 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2880 memory_clock, &memory_level->MinVddc); 2881 if (ret) 2882 return ret; 2883 } 2884 2885 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { 2886 ret = ci_get_dependency_volt_by_clk(rdev, 2887 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2888 memory_clock, &memory_level->MinVddci); 2889 if (ret) 2890 return ret; 2891 } 2892 2893 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { 2894 ret = ci_get_dependency_volt_by_clk(rdev, 2895 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, 2896 memory_clock, &memory_level->MinMvdd); 2897 if (ret) 2898 return ret; 2899 } 2900 2901 memory_level->MinVddcPhases = 1; 2902 2903 if (pi->vddc_phase_shed_control) 2904 ci_populate_phase_value_based_on_mclk(rdev, 2905 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 2906 memory_clock, 2907 &memory_level->MinVddcPhases); 2908 2909 memory_level->EnabledForThrottle = 1; 2910 memory_level->UpH = 0; 2911 memory_level->DownH = 100; 2912 memory_level->VoltageDownH = 0; 2913 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; 2914 2915 memory_level->StutterEnable = false; 2916 memory_level->StrobeEnable = false; 2917 memory_level->EdcReadEnable = false; 2918 memory_level->EdcWriteEnable = false; 2919 memory_level->RttEnable = false; 2920 2921 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2922 2923 if (pi->mclk_stutter_mode_threshold && 2924 (memory_clock <= pi->mclk_stutter_mode_threshold) && 2925 (pi->uvd_enabled == false) && 2926 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 2927 (rdev->pm.dpm.new_active_crtc_count <= 2)) 2928 memory_level->StutterEnable = true; 2929 2930 if (pi->mclk_strobe_mode_threshold && 2931 (memory_clock <= pi->mclk_strobe_mode_threshold)) 2932 memory_level->StrobeEnable = 1; 2933 2934 if (pi->mem_gddr5) { 2935 memory_level->StrobeRatio = 2936 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); 2937 if (pi->mclk_edc_enable_threshold && 2938 (memory_clock > pi->mclk_edc_enable_threshold)) 2939 memory_level->EdcReadEnable = true; 2940 2941 if (pi->mclk_edc_wr_enable_threshold && 2942 (memory_clock > pi->mclk_edc_wr_enable_threshold)) 2943 memory_level->EdcWriteEnable = true; 2944 2945 if (memory_level->StrobeEnable) { 2946 if (si_get_mclk_frequency_ratio(memory_clock, true) >= 2947 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 2948 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2949 else 2950 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 2951 } else { 2952 dll_state_on = pi->dll_default_on; 2953 } 2954 } else { 2955 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock); 2956 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 2957 } 2958 2959 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); 2960 if (ret) 2961 return ret; 2962 2963 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); 2964 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); 2965 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); 2966 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); 2967 2968 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); 2969 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); 2970 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl); 2971 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1); 2972 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2); 2973 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl); 2974 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl); 2975 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl); 2976 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl); 2977 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1); 2978 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2); 2979 2980 return 0; 2981 } 2982 2983 static int ci_populate_smc_acpi_level(struct radeon_device *rdev, 2984 SMU7_Discrete_DpmTable *table) 2985 { 2986 struct ci_power_info *pi = ci_get_pi(rdev); 2987 struct atom_clock_dividers dividers; 2988 SMU7_Discrete_VoltageLevel voltage_level; 2989 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; 2990 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; 2991 u32 dll_cntl = pi->clock_registers.dll_cntl; 2992 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; 2993 int ret; 2994 2995 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 2996 2997 if (pi->acpi_vddc) 2998 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); 2999 else 3000 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); 3001 3002 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; 3003 3004 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; 3005 3006 ret = radeon_atom_get_clock_dividers(rdev, 3007 COMPUTE_GPUCLK_INPUT_FLAG_SCLK, 3008 table->ACPILevel.SclkFrequency, false, ÷rs); 3009 if (ret) 3010 return ret; 3011 3012 table->ACPILevel.SclkDid = (u8)dividers.post_divider; 3013 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 3014 table->ACPILevel.DeepSleepDivId = 0; 3015 3016 spll_func_cntl &= ~SPLL_PWRON; 3017 spll_func_cntl |= SPLL_RESET; 3018 3019 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 3020 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 3021 3022 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; 3023 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; 3024 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; 3025 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; 3026 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; 3027 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; 3028 table->ACPILevel.CcPwrDynRm = 0; 3029 table->ACPILevel.CcPwrDynRm1 = 0; 3030 3031 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); 3032 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); 3033 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); 3034 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); 3035 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); 3036 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); 3037 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); 3038 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); 3039 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); 3040 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); 3041 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); 3042 3043 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; 3044 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; 3045 3046 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 3047 if (pi->acpi_vddci) 3048 table->MemoryACPILevel.MinVddci = 3049 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); 3050 else 3051 table->MemoryACPILevel.MinVddci = 3052 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); 3053 } 3054 3055 if (ci_populate_mvdd_value(rdev, 0, &voltage_level)) 3056 table->MemoryACPILevel.MinMvdd = 0; 3057 else 3058 table->MemoryACPILevel.MinMvdd = 3059 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE); 3060 3061 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 3062 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 3063 3064 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 3065 3066 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); 3067 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); 3068 table->MemoryACPILevel.MpllAdFuncCntl = 3069 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); 3070 table->MemoryACPILevel.MpllDqFuncCntl = 3071 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); 3072 table->MemoryACPILevel.MpllFuncCntl = 3073 cpu_to_be32(pi->clock_registers.mpll_func_cntl); 3074 table->MemoryACPILevel.MpllFuncCntl_1 = 3075 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); 3076 table->MemoryACPILevel.MpllFuncCntl_2 = 3077 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); 3078 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); 3079 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); 3080 3081 table->MemoryACPILevel.EnabledForThrottle = 0; 3082 table->MemoryACPILevel.EnabledForActivity = 0; 3083 table->MemoryACPILevel.UpH = 0; 3084 table->MemoryACPILevel.DownH = 100; 3085 table->MemoryACPILevel.VoltageDownH = 0; 3086 table->MemoryACPILevel.ActivityLevel = 3087 cpu_to_be16((u16)pi->mclk_activity_target); 3088 3089 table->MemoryACPILevel.StutterEnable = false; 3090 table->MemoryACPILevel.StrobeEnable = false; 3091 table->MemoryACPILevel.EdcReadEnable = false; 3092 table->MemoryACPILevel.EdcWriteEnable = false; 3093 table->MemoryACPILevel.RttEnable = false; 3094 3095 return 0; 3096 } 3097 3098 3099 static int ci_enable_ulv(struct radeon_device *rdev, bool enable) 3100 { 3101 struct ci_power_info *pi = ci_get_pi(rdev); 3102 struct ci_ulv_parm *ulv = &pi->ulv; 3103 3104 if (ulv->supported) { 3105 if (enable) 3106 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 3107 0 : -EINVAL; 3108 else 3109 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 3110 0 : -EINVAL; 3111 } 3112 3113 return 0; 3114 } 3115 3116 static int ci_populate_ulv_level(struct radeon_device *rdev, 3117 SMU7_Discrete_Ulv *state) 3118 { 3119 struct ci_power_info *pi = ci_get_pi(rdev); 3120 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; 3121 3122 state->CcPwrDynRm = 0; 3123 state->CcPwrDynRm1 = 0; 3124 3125 if (ulv_voltage == 0) { 3126 pi->ulv.supported = false; 3127 return 0; 3128 } 3129 3130 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { 3131 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) 3132 state->VddcOffset = 0; 3133 else 3134 state->VddcOffset = 3135 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; 3136 } else { 3137 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) 3138 state->VddcOffsetVid = 0; 3139 else 3140 state->VddcOffsetVid = (u8) 3141 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * 3142 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 3143 } 3144 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; 3145 3146 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm); 3147 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1); 3148 state->VddcOffset = cpu_to_be16(state->VddcOffset); 3149 3150 return 0; 3151 } 3152 3153 static int ci_calculate_sclk_params(struct radeon_device *rdev, 3154 u32 engine_clock, 3155 SMU7_Discrete_GraphicsLevel *sclk) 3156 { 3157 struct ci_power_info *pi = ci_get_pi(rdev); 3158 struct atom_clock_dividers dividers; 3159 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; 3160 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; 3161 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; 3162 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; 3163 u32 reference_clock = rdev->clock.spll.reference_freq; 3164 u32 reference_divider; 3165 u32 fbdiv; 3166 int ret; 3167 3168 ret = radeon_atom_get_clock_dividers(rdev, 3169 COMPUTE_GPUCLK_INPUT_FLAG_SCLK, 3170 engine_clock, false, ÷rs); 3171 if (ret) 3172 return ret; 3173 3174 reference_divider = 1 + dividers.ref_div; 3175 fbdiv = dividers.fb_div & 0x3FFFFFF; 3176 3177 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 3178 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 3179 spll_func_cntl_3 |= SPLL_DITHEN; 3180 3181 if (pi->caps_sclk_ss_support) { 3182 struct radeon_atom_ss ss; 3183 u32 vco_freq = engine_clock * dividers.post_div; 3184 3185 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 3186 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 3187 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 3188 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 3189 3190 cg_spll_spread_spectrum &= ~CLK_S_MASK; 3191 cg_spll_spread_spectrum |= CLK_S(clk_s); 3192 cg_spll_spread_spectrum |= SSEN; 3193 3194 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 3195 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 3196 } 3197 } 3198 3199 sclk->SclkFrequency = engine_clock; 3200 sclk->CgSpllFuncCntl3 = spll_func_cntl_3; 3201 sclk->CgSpllFuncCntl4 = spll_func_cntl_4; 3202 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; 3203 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; 3204 sclk->SclkDid = (u8)dividers.post_divider; 3205 3206 return 0; 3207 } 3208 3209 static int ci_populate_single_graphic_level(struct radeon_device *rdev, 3210 u32 engine_clock, 3211 u16 sclk_activity_level_t, 3212 SMU7_Discrete_GraphicsLevel *graphic_level) 3213 { 3214 struct ci_power_info *pi = ci_get_pi(rdev); 3215 int ret; 3216 3217 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); 3218 if (ret) 3219 return ret; 3220 3221 ret = ci_get_dependency_volt_by_clk(rdev, 3222 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3223 engine_clock, &graphic_level->MinVddc); 3224 if (ret) 3225 return ret; 3226 3227 graphic_level->SclkFrequency = engine_clock; 3228 3229 graphic_level->Flags = 0; 3230 graphic_level->MinVddcPhases = 1; 3231 3232 if (pi->vddc_phase_shed_control) 3233 ci_populate_phase_value_based_on_sclk(rdev, 3234 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 3235 engine_clock, 3236 &graphic_level->MinVddcPhases); 3237 3238 graphic_level->ActivityLevel = sclk_activity_level_t; 3239 3240 graphic_level->CcPwrDynRm = 0; 3241 graphic_level->CcPwrDynRm1 = 0; 3242 graphic_level->EnabledForThrottle = 1; 3243 graphic_level->UpH = 0; 3244 graphic_level->DownH = 0; 3245 graphic_level->VoltageDownH = 0; 3246 graphic_level->PowerThrottle = 0; 3247 3248 if (pi->caps_sclk_ds) 3249 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev, 3250 engine_clock, 3251 CISLAND_MINIMUM_ENGINE_CLOCK); 3252 3253 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 3254 3255 graphic_level->Flags = cpu_to_be32(graphic_level->Flags); 3256 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); 3257 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); 3258 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency); 3259 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel); 3260 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3); 3261 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4); 3262 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum); 3263 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); 3264 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); 3265 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1); 3266 3267 return 0; 3268 } 3269 3270 static int ci_populate_all_graphic_levels(struct radeon_device *rdev) 3271 { 3272 struct ci_power_info *pi = ci_get_pi(rdev); 3273 struct ci_dpm_table *dpm_table = &pi->dpm_table; 3274 u32 level_array_address = pi->dpm_table_start + 3275 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); 3276 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) * 3277 SMU7_MAX_LEVELS_GRAPHICS; 3278 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; 3279 u32 i, ret; 3280 3281 memset(levels, 0, level_array_size); 3282 3283 for (i = 0; i < dpm_table->sclk_table.count; i++) { 3284 ret = ci_populate_single_graphic_level(rdev, 3285 dpm_table->sclk_table.dpm_levels[i].value, 3286 (u16)pi->activity_target[i], 3287 &pi->smc_state_table.GraphicsLevel[i]); 3288 if (ret) 3289 return ret; 3290 if (i > 1) 3291 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; 3292 if (i == (dpm_table->sclk_table.count - 1)) 3293 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = 3294 PPSMC_DISPLAY_WATERMARK_HIGH; 3295 } 3296 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; 3297 3298 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; 3299 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = 3300 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); 3301 3302 ret = ci_copy_bytes_to_smc(rdev, level_array_address, 3303 (u8 *)levels, level_array_size, 3304 pi->sram_end); 3305 if (ret) 3306 return ret; 3307 3308 return 0; 3309 } 3310 3311 static int ci_populate_ulv_state(struct radeon_device *rdev, 3312 SMU7_Discrete_Ulv *ulv_level) 3313 { 3314 return ci_populate_ulv_level(rdev, ulv_level); 3315 } 3316 3317 static int ci_populate_all_memory_levels(struct radeon_device *rdev) 3318 { 3319 struct ci_power_info *pi = ci_get_pi(rdev); 3320 struct ci_dpm_table *dpm_table = &pi->dpm_table; 3321 u32 level_array_address = pi->dpm_table_start + 3322 offsetof(SMU7_Discrete_DpmTable, MemoryLevel); 3323 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * 3324 SMU7_MAX_LEVELS_MEMORY; 3325 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; 3326 u32 i, ret; 3327 3328 memset(levels, 0, level_array_size); 3329 3330 for (i = 0; i < dpm_table->mclk_table.count; i++) { 3331 if (dpm_table->mclk_table.dpm_levels[i].value == 0) 3332 return -EINVAL; 3333 ret = ci_populate_single_memory_level(rdev, 3334 dpm_table->mclk_table.dpm_levels[i].value, 3335 &pi->smc_state_table.MemoryLevel[i]); 3336 if (ret) 3337 return ret; 3338 } 3339 3340 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; 3341 3342 if ((dpm_table->mclk_table.count >= 2) && 3343 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) { 3344 pi->smc_state_table.MemoryLevel[1].MinVddc = 3345 pi->smc_state_table.MemoryLevel[0].MinVddc; 3346 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = 3347 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; 3348 } 3349 3350 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); 3351 3352 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; 3353 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = 3354 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 3355 3356 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = 3357 PPSMC_DISPLAY_WATERMARK_HIGH; 3358 3359 ret = ci_copy_bytes_to_smc(rdev, level_array_address, 3360 (u8 *)levels, level_array_size, 3361 pi->sram_end); 3362 if (ret) 3363 return ret; 3364 3365 return 0; 3366 } 3367 3368 static void ci_reset_single_dpm_table(struct radeon_device *rdev, 3369 struct ci_single_dpm_table* dpm_table, 3370 u32 count) 3371 { 3372 u32 i; 3373 3374 dpm_table->count = count; 3375 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) 3376 dpm_table->dpm_levels[i].enabled = false; 3377 } 3378 3379 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table, 3380 u32 index, u32 pcie_gen, u32 pcie_lanes) 3381 { 3382 dpm_table->dpm_levels[index].value = pcie_gen; 3383 dpm_table->dpm_levels[index].param1 = pcie_lanes; 3384 dpm_table->dpm_levels[index].enabled = true; 3385 } 3386 3387 static int ci_setup_default_pcie_tables(struct radeon_device *rdev) 3388 { 3389 struct ci_power_info *pi = ci_get_pi(rdev); 3390 3391 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) 3392 return -EINVAL; 3393 3394 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { 3395 pi->pcie_gen_powersaving = pi->pcie_gen_performance; 3396 pi->pcie_lane_powersaving = pi->pcie_lane_performance; 3397 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { 3398 pi->pcie_gen_performance = pi->pcie_gen_powersaving; 3399 pi->pcie_lane_performance = pi->pcie_lane_powersaving; 3400 } 3401 3402 ci_reset_single_dpm_table(rdev, 3403 &pi->dpm_table.pcie_speed_table, 3404 SMU7_MAX_LEVELS_LINK); 3405 3406 if (rdev->family == CHIP_BONAIRE) 3407 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, 3408 pi->pcie_gen_powersaving.min, 3409 pi->pcie_lane_powersaving.max); 3410 else 3411 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, 3412 pi->pcie_gen_powersaving.min, 3413 pi->pcie_lane_powersaving.min); 3414 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, 3415 pi->pcie_gen_performance.min, 3416 pi->pcie_lane_performance.min); 3417 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, 3418 pi->pcie_gen_powersaving.min, 3419 pi->pcie_lane_powersaving.max); 3420 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, 3421 pi->pcie_gen_performance.min, 3422 pi->pcie_lane_performance.max); 3423 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, 3424 pi->pcie_gen_powersaving.max, 3425 pi->pcie_lane_powersaving.max); 3426 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, 3427 pi->pcie_gen_performance.max, 3428 pi->pcie_lane_performance.max); 3429 3430 pi->dpm_table.pcie_speed_table.count = 6; 3431 3432 return 0; 3433 } 3434 3435 static int ci_setup_default_dpm_tables(struct radeon_device *rdev) 3436 { 3437 struct ci_power_info *pi = ci_get_pi(rdev); 3438 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = 3439 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 3440 struct radeon_clock_voltage_dependency_table *allowed_mclk_table = 3441 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; 3442 struct radeon_cac_leakage_table *std_voltage_table = 3443 &rdev->pm.dpm.dyn_state.cac_leakage_table; 3444 u32 i; 3445 3446 if (allowed_sclk_vddc_table == NULL) 3447 return -EINVAL; 3448 if (allowed_sclk_vddc_table->count < 1) 3449 return -EINVAL; 3450 if (allowed_mclk_table == NULL) 3451 return -EINVAL; 3452 if (allowed_mclk_table->count < 1) 3453 return -EINVAL; 3454 3455 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); 3456 3457 ci_reset_single_dpm_table(rdev, 3458 &pi->dpm_table.sclk_table, 3459 SMU7_MAX_LEVELS_GRAPHICS); 3460 ci_reset_single_dpm_table(rdev, 3461 &pi->dpm_table.mclk_table, 3462 SMU7_MAX_LEVELS_MEMORY); 3463 ci_reset_single_dpm_table(rdev, 3464 &pi->dpm_table.vddc_table, 3465 SMU7_MAX_LEVELS_VDDC); 3466 ci_reset_single_dpm_table(rdev, 3467 &pi->dpm_table.vddci_table, 3468 SMU7_MAX_LEVELS_VDDCI); 3469 ci_reset_single_dpm_table(rdev, 3470 &pi->dpm_table.mvdd_table, 3471 SMU7_MAX_LEVELS_MVDD); 3472 3473 pi->dpm_table.sclk_table.count = 0; 3474 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { 3475 if ((i == 0) || 3476 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != 3477 allowed_sclk_vddc_table->entries[i].clk)) { 3478 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = 3479 allowed_sclk_vddc_table->entries[i].clk; 3480 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = 3481 (i == 0) ? true : false; 3482 pi->dpm_table.sclk_table.count++; 3483 } 3484 } 3485 3486 pi->dpm_table.mclk_table.count = 0; 3487 for (i = 0; i < allowed_mclk_table->count; i++) { 3488 if ((i == 0) || 3489 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != 3490 allowed_mclk_table->entries[i].clk)) { 3491 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = 3492 allowed_mclk_table->entries[i].clk; 3493 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = 3494 (i == 0) ? true : false; 3495 pi->dpm_table.mclk_table.count++; 3496 } 3497 } 3498 3499 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { 3500 pi->dpm_table.vddc_table.dpm_levels[i].value = 3501 allowed_sclk_vddc_table->entries[i].v; 3502 pi->dpm_table.vddc_table.dpm_levels[i].param1 = 3503 std_voltage_table->entries[i].leakage; 3504 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; 3505 } 3506 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; 3507 3508 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; 3509 if (allowed_mclk_table) { 3510 for (i = 0; i < allowed_mclk_table->count; i++) { 3511 pi->dpm_table.vddci_table.dpm_levels[i].value = 3512 allowed_mclk_table->entries[i].v; 3513 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; 3514 } 3515 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; 3516 } 3517 3518 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; 3519 if (allowed_mclk_table) { 3520 for (i = 0; i < allowed_mclk_table->count; i++) { 3521 pi->dpm_table.mvdd_table.dpm_levels[i].value = 3522 allowed_mclk_table->entries[i].v; 3523 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; 3524 } 3525 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; 3526 } 3527 3528 ci_setup_default_pcie_tables(rdev); 3529 3530 return 0; 3531 } 3532 3533 static int ci_find_boot_level(struct ci_single_dpm_table *table, 3534 u32 value, u32 *boot_level) 3535 { 3536 u32 i; 3537 int ret = -EINVAL; 3538 3539 for(i = 0; i < table->count; i++) { 3540 if (value == table->dpm_levels[i].value) { 3541 *boot_level = i; 3542 ret = 0; 3543 } 3544 } 3545 3546 return ret; 3547 } 3548 3549 static int ci_init_smc_table(struct radeon_device *rdev) 3550 { 3551 struct ci_power_info *pi = ci_get_pi(rdev); 3552 struct ci_ulv_parm *ulv = &pi->ulv; 3553 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 3554 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; 3555 int ret; 3556 3557 ret = ci_setup_default_dpm_tables(rdev); 3558 if (ret) 3559 return ret; 3560 3561 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) 3562 ci_populate_smc_voltage_tables(rdev, table); 3563 3564 ci_init_fps_limits(rdev); 3565 3566 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 3567 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 3568 3569 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 3570 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 3571 3572 if (pi->mem_gddr5) 3573 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 3574 3575 if (ulv->supported) { 3576 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); 3577 if (ret) 3578 return ret; 3579 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 3580 } 3581 3582 ret = ci_populate_all_graphic_levels(rdev); 3583 if (ret) 3584 return ret; 3585 3586 ret = ci_populate_all_memory_levels(rdev); 3587 if (ret) 3588 return ret; 3589 3590 ci_populate_smc_link_level(rdev, table); 3591 3592 ret = ci_populate_smc_acpi_level(rdev, table); 3593 if (ret) 3594 return ret; 3595 3596 ret = ci_populate_smc_vce_level(rdev, table); 3597 if (ret) 3598 return ret; 3599 3600 ret = ci_populate_smc_acp_level(rdev, table); 3601 if (ret) 3602 return ret; 3603 3604 ret = ci_populate_smc_samu_level(rdev, table); 3605 if (ret) 3606 return ret; 3607 3608 ret = ci_do_program_memory_timing_parameters(rdev); 3609 if (ret) 3610 return ret; 3611 3612 ret = ci_populate_smc_uvd_level(rdev, table); 3613 if (ret) 3614 return ret; 3615 3616 table->UvdBootLevel = 0; 3617 table->VceBootLevel = 0; 3618 table->AcpBootLevel = 0; 3619 table->SamuBootLevel = 0; 3620 table->GraphicsBootLevel = 0; 3621 table->MemoryBootLevel = 0; 3622 3623 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, 3624 pi->vbios_boot_state.sclk_bootup_value, 3625 (u32 *)&pi->smc_state_table.GraphicsBootLevel); 3626 3627 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, 3628 pi->vbios_boot_state.mclk_bootup_value, 3629 (u32 *)&pi->smc_state_table.MemoryBootLevel); 3630 3631 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; 3632 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; 3633 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; 3634 3635 ci_populate_smc_initial_state(rdev, radeon_boot_state); 3636 3637 ret = ci_populate_bapm_parameters_in_dpm_table(rdev); 3638 if (ret) 3639 return ret; 3640 3641 table->UVDInterval = 1; 3642 table->VCEInterval = 1; 3643 table->ACPInterval = 1; 3644 table->SAMUInterval = 1; 3645 table->GraphicsVoltageChangeEnable = 1; 3646 table->GraphicsThermThrottleEnable = 1; 3647 table->GraphicsInterval = 1; 3648 table->VoltageInterval = 1; 3649 table->ThermalInterval = 1; 3650 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * 3651 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); 3652 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * 3653 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); 3654 table->MemoryVoltageChangeEnable = 1; 3655 table->MemoryInterval = 1; 3656 table->VoltageResponseTime = 0; 3657 table->VddcVddciDelta = 4000; 3658 table->PhaseResponseTime = 0; 3659 table->MemoryThermThrottleEnable = 1; 3660 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; 3661 table->PCIeGenInterval = 1; 3662 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) 3663 table->SVI2Enable = 1; 3664 else 3665 table->SVI2Enable = 0; 3666 3667 table->ThermGpio = 17; 3668 table->SclkStepSize = 0x4000; 3669 3670 table->SystemFlags = cpu_to_be32(table->SystemFlags); 3671 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); 3672 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); 3673 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); 3674 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); 3675 table->SclkStepSize = cpu_to_be32(table->SclkStepSize); 3676 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); 3677 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); 3678 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); 3679 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); 3680 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); 3681 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); 3682 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); 3683 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); 3684 3685 ret = ci_copy_bytes_to_smc(rdev, 3686 pi->dpm_table_start + 3687 offsetof(SMU7_Discrete_DpmTable, SystemFlags), 3688 (u8 *)&table->SystemFlags, 3689 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController), 3690 pi->sram_end); 3691 if (ret) 3692 return ret; 3693 3694 return 0; 3695 } 3696 3697 static void ci_trim_single_dpm_states(struct radeon_device *rdev, 3698 struct ci_single_dpm_table *dpm_table, 3699 u32 low_limit, u32 high_limit) 3700 { 3701 u32 i; 3702 3703 for (i = 0; i < dpm_table->count; i++) { 3704 if ((dpm_table->dpm_levels[i].value < low_limit) || 3705 (dpm_table->dpm_levels[i].value > high_limit)) 3706 dpm_table->dpm_levels[i].enabled = false; 3707 else 3708 dpm_table->dpm_levels[i].enabled = true; 3709 } 3710 } 3711 3712 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev, 3713 u32 speed_low, u32 lanes_low, 3714 u32 speed_high, u32 lanes_high) 3715 { 3716 struct ci_power_info *pi = ci_get_pi(rdev); 3717 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; 3718 u32 i, j; 3719 3720 for (i = 0; i < pcie_table->count; i++) { 3721 if ((pcie_table->dpm_levels[i].value < speed_low) || 3722 (pcie_table->dpm_levels[i].param1 < lanes_low) || 3723 (pcie_table->dpm_levels[i].value > speed_high) || 3724 (pcie_table->dpm_levels[i].param1 > lanes_high)) 3725 pcie_table->dpm_levels[i].enabled = false; 3726 else 3727 pcie_table->dpm_levels[i].enabled = true; 3728 } 3729 3730 for (i = 0; i < pcie_table->count; i++) { 3731 if (pcie_table->dpm_levels[i].enabled) { 3732 for (j = i + 1; j < pcie_table->count; j++) { 3733 if (pcie_table->dpm_levels[j].enabled) { 3734 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) && 3735 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1)) 3736 pcie_table->dpm_levels[j].enabled = false; 3737 } 3738 } 3739 } 3740 } 3741 } 3742 3743 static int ci_trim_dpm_states(struct radeon_device *rdev, 3744 struct radeon_ps *radeon_state) 3745 { 3746 struct ci_ps *state = ci_get_ps(radeon_state); 3747 struct ci_power_info *pi = ci_get_pi(rdev); 3748 u32 high_limit_count; 3749 3750 if (state->performance_level_count < 1) 3751 return -EINVAL; 3752 3753 if (state->performance_level_count == 1) 3754 high_limit_count = 0; 3755 else 3756 high_limit_count = 1; 3757 3758 ci_trim_single_dpm_states(rdev, 3759 &pi->dpm_table.sclk_table, 3760 state->performance_levels[0].sclk, 3761 state->performance_levels[high_limit_count].sclk); 3762 3763 ci_trim_single_dpm_states(rdev, 3764 &pi->dpm_table.mclk_table, 3765 state->performance_levels[0].mclk, 3766 state->performance_levels[high_limit_count].mclk); 3767 3768 ci_trim_pcie_dpm_states(rdev, 3769 state->performance_levels[0].pcie_gen, 3770 state->performance_levels[0].pcie_lane, 3771 state->performance_levels[high_limit_count].pcie_gen, 3772 state->performance_levels[high_limit_count].pcie_lane); 3773 3774 return 0; 3775 } 3776 3777 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev) 3778 { 3779 struct radeon_clock_voltage_dependency_table *disp_voltage_table = 3780 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; 3781 struct radeon_clock_voltage_dependency_table *vddc_table = 3782 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 3783 u32 requested_voltage = 0; 3784 u32 i; 3785 3786 if (disp_voltage_table == NULL) 3787 return -EINVAL; 3788 if (!disp_voltage_table->count) 3789 return -EINVAL; 3790 3791 for (i = 0; i < disp_voltage_table->count; i++) { 3792 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk) 3793 requested_voltage = disp_voltage_table->entries[i].v; 3794 } 3795 3796 for (i = 0; i < vddc_table->count; i++) { 3797 if (requested_voltage <= vddc_table->entries[i].v) { 3798 requested_voltage = vddc_table->entries[i].v; 3799 return (ci_send_msg_to_smc_with_parameter(rdev, 3800 PPSMC_MSG_VddC_Request, 3801 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ? 3802 0 : -EINVAL; 3803 } 3804 } 3805 3806 return -EINVAL; 3807 } 3808 3809 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev) 3810 { 3811 struct ci_power_info *pi = ci_get_pi(rdev); 3812 PPSMC_Result result; 3813 3814 ci_apply_disp_minimum_voltage_request(rdev); 3815 3816 if (!pi->sclk_dpm_key_disabled) { 3817 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3818 result = ci_send_msg_to_smc_with_parameter(rdev, 3819 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3820 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); 3821 if (result != PPSMC_Result_OK) 3822 return -EINVAL; 3823 } 3824 } 3825 3826 if (!pi->mclk_dpm_key_disabled) { 3827 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3828 result = ci_send_msg_to_smc_with_parameter(rdev, 3829 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3830 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3831 if (result != PPSMC_Result_OK) 3832 return -EINVAL; 3833 } 3834 } 3835 #if 0 3836 if (!pi->pcie_dpm_key_disabled) { 3837 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3838 result = ci_send_msg_to_smc_with_parameter(rdev, 3839 PPSMC_MSG_PCIeDPM_SetEnabledMask, 3840 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); 3841 if (result != PPSMC_Result_OK) 3842 return -EINVAL; 3843 } 3844 } 3845 #endif 3846 return 0; 3847 } 3848 3849 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev, 3850 struct radeon_ps *radeon_state) 3851 { 3852 struct ci_power_info *pi = ci_get_pi(rdev); 3853 struct ci_ps *state = ci_get_ps(radeon_state); 3854 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; 3855 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; 3856 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; 3857 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; 3858 u32 i; 3859 3860 pi->need_update_smu7_dpm_table = 0; 3861 3862 for (i = 0; i < sclk_table->count; i++) { 3863 if (sclk == sclk_table->dpm_levels[i].value) 3864 break; 3865 } 3866 3867 if (i >= sclk_table->count) { 3868 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3869 } else { 3870 /* XXX check display min clock requirements */ 3871 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK) 3872 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; 3873 } 3874 3875 for (i = 0; i < mclk_table->count; i++) { 3876 if (mclk == mclk_table->dpm_levels[i].value) 3877 break; 3878 } 3879 3880 if (i >= mclk_table->count) 3881 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3882 3883 if (rdev->pm.dpm.current_active_crtc_count != 3884 rdev->pm.dpm.new_active_crtc_count) 3885 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; 3886 } 3887 3888 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev, 3889 struct radeon_ps *radeon_state) 3890 { 3891 struct ci_power_info *pi = ci_get_pi(rdev); 3892 struct ci_ps *state = ci_get_ps(radeon_state); 3893 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; 3894 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; 3895 struct ci_dpm_table *dpm_table = &pi->dpm_table; 3896 int ret; 3897 3898 if (!pi->need_update_smu7_dpm_table) 3899 return 0; 3900 3901 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) 3902 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; 3903 3904 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) 3905 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; 3906 3907 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { 3908 ret = ci_populate_all_graphic_levels(rdev); 3909 if (ret) 3910 return ret; 3911 } 3912 3913 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 3914 ret = ci_populate_all_memory_levels(rdev); 3915 if (ret) 3916 return ret; 3917 } 3918 3919 return 0; 3920 } 3921 3922 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable) 3923 { 3924 struct ci_power_info *pi = ci_get_pi(rdev); 3925 const struct radeon_clock_and_voltage_limits *max_limits; 3926 int i; 3927 3928 if (rdev->pm.dpm.ac_power) 3929 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3930 else 3931 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3932 3933 if (enable) { 3934 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; 3935 3936 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3937 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3938 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; 3939 3940 if (!pi->caps_uvd_dpm) 3941 break; 3942 } 3943 } 3944 3945 ci_send_msg_to_smc_with_parameter(rdev, 3946 PPSMC_MSG_UVDDPM_SetEnabledMask, 3947 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); 3948 3949 if (pi->last_mclk_dpm_enable_mask & 0x1) { 3950 pi->uvd_enabled = true; 3951 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; 3952 ci_send_msg_to_smc_with_parameter(rdev, 3953 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3954 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3955 } 3956 } else { 3957 if (pi->last_mclk_dpm_enable_mask & 0x1) { 3958 pi->uvd_enabled = false; 3959 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; 3960 ci_send_msg_to_smc_with_parameter(rdev, 3961 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3962 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 3963 } 3964 } 3965 3966 return (ci_send_msg_to_smc(rdev, enable ? 3967 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ? 3968 0 : -EINVAL; 3969 } 3970 3971 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable) 3972 { 3973 struct ci_power_info *pi = ci_get_pi(rdev); 3974 const struct radeon_clock_and_voltage_limits *max_limits; 3975 int i; 3976 3977 if (rdev->pm.dpm.ac_power) 3978 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3979 else 3980 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3981 3982 if (enable) { 3983 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; 3984 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 3985 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 3986 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; 3987 3988 if (!pi->caps_vce_dpm) 3989 break; 3990 } 3991 } 3992 3993 ci_send_msg_to_smc_with_parameter(rdev, 3994 PPSMC_MSG_VCEDPM_SetEnabledMask, 3995 pi->dpm_level_enable_mask.vce_dpm_enable_mask); 3996 } 3997 3998 return (ci_send_msg_to_smc(rdev, enable ? 3999 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ? 4000 0 : -EINVAL; 4001 } 4002 4003 #if 0 4004 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable) 4005 { 4006 struct ci_power_info *pi = ci_get_pi(rdev); 4007 const struct radeon_clock_and_voltage_limits *max_limits; 4008 int i; 4009 4010 if (rdev->pm.dpm.ac_power) 4011 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 4012 else 4013 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 4014 4015 if (enable) { 4016 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0; 4017 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 4018 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 4019 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i; 4020 4021 if (!pi->caps_samu_dpm) 4022 break; 4023 } 4024 } 4025 4026 ci_send_msg_to_smc_with_parameter(rdev, 4027 PPSMC_MSG_SAMUDPM_SetEnabledMask, 4028 pi->dpm_level_enable_mask.samu_dpm_enable_mask); 4029 } 4030 return (ci_send_msg_to_smc(rdev, enable ? 4031 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ? 4032 0 : -EINVAL; 4033 } 4034 4035 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable) 4036 { 4037 struct ci_power_info *pi = ci_get_pi(rdev); 4038 const struct radeon_clock_and_voltage_limits *max_limits; 4039 int i; 4040 4041 if (rdev->pm.dpm.ac_power) 4042 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 4043 else 4044 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 4045 4046 if (enable) { 4047 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0; 4048 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) { 4049 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { 4050 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i; 4051 4052 if (!pi->caps_acp_dpm) 4053 break; 4054 } 4055 } 4056 4057 ci_send_msg_to_smc_with_parameter(rdev, 4058 PPSMC_MSG_ACPDPM_SetEnabledMask, 4059 pi->dpm_level_enable_mask.acp_dpm_enable_mask); 4060 } 4061 4062 return (ci_send_msg_to_smc(rdev, enable ? 4063 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ? 4064 0 : -EINVAL; 4065 } 4066 #endif 4067 4068 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate) 4069 { 4070 struct ci_power_info *pi = ci_get_pi(rdev); 4071 u32 tmp; 4072 4073 if (!gate) { 4074 if (pi->caps_uvd_dpm || 4075 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) 4076 pi->smc_state_table.UvdBootLevel = 0; 4077 else 4078 pi->smc_state_table.UvdBootLevel = 4079 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; 4080 4081 tmp = RREG32_SMC(DPM_TABLE_475); 4082 tmp &= ~UvdBootLevel_MASK; 4083 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); 4084 WREG32_SMC(DPM_TABLE_475, tmp); 4085 } 4086 4087 return ci_enable_uvd_dpm(rdev, !gate); 4088 } 4089 4090 static u8 ci_get_vce_boot_level(struct radeon_device *rdev) 4091 { 4092 u8 i; 4093 u32 min_evclk = 30000; /* ??? */ 4094 struct radeon_vce_clock_voltage_dependency_table *table = 4095 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 4096 4097 for (i = 0; i < table->count; i++) { 4098 if (table->entries[i].evclk >= min_evclk) 4099 return i; 4100 } 4101 4102 return table->count - 1; 4103 } 4104 4105 static int ci_update_vce_dpm(struct radeon_device *rdev, 4106 struct radeon_ps *radeon_new_state, 4107 struct radeon_ps *radeon_current_state) 4108 { 4109 struct ci_power_info *pi = ci_get_pi(rdev); 4110 int ret = 0; 4111 u32 tmp; 4112 4113 if (radeon_current_state->evclk != radeon_new_state->evclk) { 4114 if (radeon_new_state->evclk) { 4115 /* turn the clocks on when encoding */ 4116 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false); 4117 4118 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); 4119 tmp = RREG32_SMC(DPM_TABLE_475); 4120 tmp &= ~VceBootLevel_MASK; 4121 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); 4122 WREG32_SMC(DPM_TABLE_475, tmp); 4123 4124 ret = ci_enable_vce_dpm(rdev, true); 4125 } else { 4126 /* turn the clocks off when not encoding */ 4127 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true); 4128 4129 ret = ci_enable_vce_dpm(rdev, false); 4130 } 4131 } 4132 return ret; 4133 } 4134 4135 #if 0 4136 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate) 4137 { 4138 return ci_enable_samu_dpm(rdev, gate); 4139 } 4140 4141 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate) 4142 { 4143 struct ci_power_info *pi = ci_get_pi(rdev); 4144 u32 tmp; 4145 4146 if (!gate) { 4147 pi->smc_state_table.AcpBootLevel = 0; 4148 4149 tmp = RREG32_SMC(DPM_TABLE_475); 4150 tmp &= ~AcpBootLevel_MASK; 4151 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel); 4152 WREG32_SMC(DPM_TABLE_475, tmp); 4153 } 4154 4155 return ci_enable_acp_dpm(rdev, !gate); 4156 } 4157 #endif 4158 4159 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev, 4160 struct radeon_ps *radeon_state) 4161 { 4162 struct ci_power_info *pi = ci_get_pi(rdev); 4163 int ret; 4164 4165 ret = ci_trim_dpm_states(rdev, radeon_state); 4166 if (ret) 4167 return ret; 4168 4169 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = 4170 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); 4171 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = 4172 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); 4173 pi->last_mclk_dpm_enable_mask = 4174 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; 4175 if (pi->uvd_enabled) { 4176 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) 4177 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; 4178 } 4179 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = 4180 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); 4181 4182 return 0; 4183 } 4184 4185 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev, 4186 u32 level_mask) 4187 { 4188 u32 level = 0; 4189 4190 while ((level_mask & (1 << level)) == 0) 4191 level++; 4192 4193 return level; 4194 } 4195 4196 4197 int ci_dpm_force_performance_level(struct radeon_device *rdev, 4198 enum radeon_dpm_forced_level level) 4199 { 4200 struct ci_power_info *pi = ci_get_pi(rdev); 4201 u32 tmp, levels, i; 4202 int ret; 4203 4204 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 4205 if ((!pi->pcie_dpm_key_disabled) && 4206 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 4207 levels = 0; 4208 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; 4209 while (tmp >>= 1) 4210 levels++; 4211 if (levels) { 4212 ret = ci_dpm_force_state_pcie(rdev, level); 4213 if (ret) 4214 return ret; 4215 for (i = 0; i < rdev->usec_timeout; i++) { 4216 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & 4217 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; 4218 if (tmp == levels) 4219 break; 4220 udelay(1); 4221 } 4222 } 4223 } 4224 if ((!pi->sclk_dpm_key_disabled) && 4225 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 4226 levels = 0; 4227 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; 4228 while (tmp >>= 1) 4229 levels++; 4230 if (levels) { 4231 ret = ci_dpm_force_state_sclk(rdev, levels); 4232 if (ret) 4233 return ret; 4234 for (i = 0; i < rdev->usec_timeout; i++) { 4235 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 4236 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; 4237 if (tmp == levels) 4238 break; 4239 udelay(1); 4240 } 4241 } 4242 } 4243 if ((!pi->mclk_dpm_key_disabled) && 4244 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 4245 levels = 0; 4246 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; 4247 while (tmp >>= 1) 4248 levels++; 4249 if (levels) { 4250 ret = ci_dpm_force_state_mclk(rdev, levels); 4251 if (ret) 4252 return ret; 4253 for (i = 0; i < rdev->usec_timeout; i++) { 4254 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 4255 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; 4256 if (tmp == levels) 4257 break; 4258 udelay(1); 4259 } 4260 } 4261 } 4262 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 4263 if ((!pi->sclk_dpm_key_disabled) && 4264 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { 4265 levels = ci_get_lowest_enabled_level(rdev, 4266 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); 4267 ret = ci_dpm_force_state_sclk(rdev, levels); 4268 if (ret) 4269 return ret; 4270 for (i = 0; i < rdev->usec_timeout; i++) { 4271 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 4272 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT; 4273 if (tmp == levels) 4274 break; 4275 udelay(1); 4276 } 4277 } 4278 if ((!pi->mclk_dpm_key_disabled) && 4279 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { 4280 levels = ci_get_lowest_enabled_level(rdev, 4281 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); 4282 ret = ci_dpm_force_state_mclk(rdev, levels); 4283 if (ret) 4284 return ret; 4285 for (i = 0; i < rdev->usec_timeout; i++) { 4286 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & 4287 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT; 4288 if (tmp == levels) 4289 break; 4290 udelay(1); 4291 } 4292 } 4293 if ((!pi->pcie_dpm_key_disabled) && 4294 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { 4295 levels = ci_get_lowest_enabled_level(rdev, 4296 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); 4297 ret = ci_dpm_force_state_pcie(rdev, levels); 4298 if (ret) 4299 return ret; 4300 for (i = 0; i < rdev->usec_timeout; i++) { 4301 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & 4302 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT; 4303 if (tmp == levels) 4304 break; 4305 udelay(1); 4306 } 4307 } 4308 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 4309 if (!pi->pcie_dpm_key_disabled) { 4310 PPSMC_Result smc_result; 4311 4312 smc_result = ci_send_msg_to_smc(rdev, 4313 PPSMC_MSG_PCIeDPM_UnForceLevel); 4314 if (smc_result != PPSMC_Result_OK) 4315 return -EINVAL; 4316 } 4317 ret = ci_upload_dpm_level_enable_mask(rdev); 4318 if (ret) 4319 return ret; 4320 } 4321 4322 rdev->pm.dpm.forced_level = level; 4323 4324 return 0; 4325 } 4326 4327 static int ci_set_mc_special_registers(struct radeon_device *rdev, 4328 struct ci_mc_reg_table *table) 4329 { 4330 struct ci_power_info *pi = ci_get_pi(rdev); 4331 u8 i, j, k; 4332 u32 temp_reg; 4333 4334 for (i = 0, j = table->last; i < table->last; i++) { 4335 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4336 return -EINVAL; 4337 switch(table->mc_reg_address[i].s1 << 2) { 4338 case MC_SEQ_MISC1: 4339 temp_reg = RREG32(MC_PMG_CMD_EMRS); 4340 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 4341 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 4342 for (k = 0; k < table->num_entries; k++) { 4343 table->mc_reg_table_entry[k].mc_data[j] = 4344 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 4345 } 4346 j++; 4347 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4348 return -EINVAL; 4349 4350 temp_reg = RREG32(MC_PMG_CMD_MRS); 4351 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 4352 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 4353 for (k = 0; k < table->num_entries; k++) { 4354 table->mc_reg_table_entry[k].mc_data[j] = 4355 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 4356 if (!pi->mem_gddr5) 4357 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 4358 } 4359 j++; 4360 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4361 return -EINVAL; 4362 4363 if (!pi->mem_gddr5) { 4364 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 4365 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 4366 for (k = 0; k < table->num_entries; k++) { 4367 table->mc_reg_table_entry[k].mc_data[j] = 4368 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 4369 } 4370 j++; 4371 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4372 return -EINVAL; 4373 } 4374 break; 4375 case MC_SEQ_RESERVE_M: 4376 temp_reg = RREG32(MC_PMG_CMD_MRS1); 4377 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 4378 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 4379 for (k = 0; k < table->num_entries; k++) { 4380 table->mc_reg_table_entry[k].mc_data[j] = 4381 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 4382 } 4383 j++; 4384 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4385 return -EINVAL; 4386 break; 4387 default: 4388 break; 4389 } 4390 4391 } 4392 4393 table->last = j; 4394 4395 return 0; 4396 } 4397 4398 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 4399 { 4400 bool result = true; 4401 4402 switch(in_reg) { 4403 case MC_SEQ_RAS_TIMING >> 2: 4404 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 4405 break; 4406 case MC_SEQ_DLL_STBY >> 2: 4407 *out_reg = MC_SEQ_DLL_STBY_LP >> 2; 4408 break; 4409 case MC_SEQ_G5PDX_CMD0 >> 2: 4410 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2; 4411 break; 4412 case MC_SEQ_G5PDX_CMD1 >> 2: 4413 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2; 4414 break; 4415 case MC_SEQ_G5PDX_CTRL >> 2: 4416 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2; 4417 break; 4418 case MC_SEQ_CAS_TIMING >> 2: 4419 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 4420 break; 4421 case MC_SEQ_MISC_TIMING >> 2: 4422 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 4423 break; 4424 case MC_SEQ_MISC_TIMING2 >> 2: 4425 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 4426 break; 4427 case MC_SEQ_PMG_DVS_CMD >> 2: 4428 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2; 4429 break; 4430 case MC_SEQ_PMG_DVS_CTL >> 2: 4431 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2; 4432 break; 4433 case MC_SEQ_RD_CTL_D0 >> 2: 4434 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 4435 break; 4436 case MC_SEQ_RD_CTL_D1 >> 2: 4437 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 4438 break; 4439 case MC_SEQ_WR_CTL_D0 >> 2: 4440 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 4441 break; 4442 case MC_SEQ_WR_CTL_D1 >> 2: 4443 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 4444 break; 4445 case MC_PMG_CMD_EMRS >> 2: 4446 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 4447 break; 4448 case MC_PMG_CMD_MRS >> 2: 4449 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 4450 break; 4451 case MC_PMG_CMD_MRS1 >> 2: 4452 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 4453 break; 4454 case MC_SEQ_PMG_TIMING >> 2: 4455 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 4456 break; 4457 case MC_PMG_CMD_MRS2 >> 2: 4458 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 4459 break; 4460 case MC_SEQ_WR_CTL_2 >> 2: 4461 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 4462 break; 4463 default: 4464 result = false; 4465 break; 4466 } 4467 4468 return result; 4469 } 4470 4471 static void ci_set_valid_flag(struct ci_mc_reg_table *table) 4472 { 4473 u8 i, j; 4474 4475 for (i = 0; i < table->last; i++) { 4476 for (j = 1; j < table->num_entries; j++) { 4477 if (table->mc_reg_table_entry[j-1].mc_data[i] != 4478 table->mc_reg_table_entry[j].mc_data[i]) { 4479 table->valid_flag |= 1 << i; 4480 break; 4481 } 4482 } 4483 } 4484 } 4485 4486 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) 4487 { 4488 u32 i; 4489 u16 address; 4490 4491 for (i = 0; i < table->last; i++) { 4492 table->mc_reg_address[i].s0 = 4493 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 4494 address : table->mc_reg_address[i].s1; 4495 } 4496 } 4497 4498 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, 4499 struct ci_mc_reg_table *ci_table) 4500 { 4501 u8 i, j; 4502 4503 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4504 return -EINVAL; 4505 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 4506 return -EINVAL; 4507 4508 for (i = 0; i < table->last; i++) 4509 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 4510 4511 ci_table->last = table->last; 4512 4513 for (i = 0; i < table->num_entries; i++) { 4514 ci_table->mc_reg_table_entry[i].mclk_max = 4515 table->mc_reg_table_entry[i].mclk_max; 4516 for (j = 0; j < table->last; j++) 4517 ci_table->mc_reg_table_entry[i].mc_data[j] = 4518 table->mc_reg_table_entry[i].mc_data[j]; 4519 } 4520 ci_table->num_entries = table->num_entries; 4521 4522 return 0; 4523 } 4524 4525 static int ci_register_patching_mc_seq(struct radeon_device *rdev, 4526 struct ci_mc_reg_table *table) 4527 { 4528 u8 i, k; 4529 u32 tmp; 4530 bool patch; 4531 4532 tmp = RREG32(MC_SEQ_MISC0); 4533 patch = ((tmp & 0x0000f00) == 0x300) ? true : false; 4534 4535 if (patch && 4536 ((rdev->pdev->device == 0x67B0) || 4537 (rdev->pdev->device == 0x67B1))) { 4538 for (i = 0; i < table->last; i++) { 4539 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4540 return -EINVAL; 4541 switch(table->mc_reg_address[i].s1 >> 2) { 4542 case MC_SEQ_MISC1: 4543 for (k = 0; k < table->num_entries; k++) { 4544 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || 4545 (table->mc_reg_table_entry[k].mclk_max == 137500)) 4546 table->mc_reg_table_entry[k].mc_data[i] = 4547 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) | 4548 0x00000007; 4549 } 4550 break; 4551 case MC_SEQ_WR_CTL_D0: 4552 for (k = 0; k < table->num_entries; k++) { 4553 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || 4554 (table->mc_reg_table_entry[k].mclk_max == 137500)) 4555 table->mc_reg_table_entry[k].mc_data[i] = 4556 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | 4557 0x0000D0DD; 4558 } 4559 break; 4560 case MC_SEQ_WR_CTL_D1: 4561 for (k = 0; k < table->num_entries; k++) { 4562 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || 4563 (table->mc_reg_table_entry[k].mclk_max == 137500)) 4564 table->mc_reg_table_entry[k].mc_data[i] = 4565 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | 4566 0x0000D0DD; 4567 } 4568 break; 4569 case MC_SEQ_WR_CTL_2: 4570 for (k = 0; k < table->num_entries; k++) { 4571 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || 4572 (table->mc_reg_table_entry[k].mclk_max == 137500)) 4573 table->mc_reg_table_entry[k].mc_data[i] = 0; 4574 } 4575 break; 4576 case MC_SEQ_CAS_TIMING: 4577 for (k = 0; k < table->num_entries; k++) { 4578 if (table->mc_reg_table_entry[k].mclk_max == 125000) 4579 table->mc_reg_table_entry[k].mc_data[i] = 4580 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | 4581 0x000C0140; 4582 else if (table->mc_reg_table_entry[k].mclk_max == 137500) 4583 table->mc_reg_table_entry[k].mc_data[i] = 4584 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | 4585 0x000C0150; 4586 } 4587 break; 4588 case MC_SEQ_MISC_TIMING: 4589 for (k = 0; k < table->num_entries; k++) { 4590 if (table->mc_reg_table_entry[k].mclk_max == 125000) 4591 table->mc_reg_table_entry[k].mc_data[i] = 4592 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | 4593 0x00000030; 4594 else if (table->mc_reg_table_entry[k].mclk_max == 137500) 4595 table->mc_reg_table_entry[k].mc_data[i] = 4596 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | 4597 0x00000035; 4598 } 4599 break; 4600 default: 4601 break; 4602 } 4603 } 4604 4605 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3); 4606 tmp = RREG32(MC_SEQ_IO_DEBUG_DATA); 4607 tmp = (tmp & 0xFFF8FFFF) | (1 << 16); 4608 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3); 4609 WREG32(MC_SEQ_IO_DEBUG_DATA, tmp); 4610 } 4611 4612 return 0; 4613 } 4614 4615 static int ci_initialize_mc_reg_table(struct radeon_device *rdev) 4616 { 4617 struct ci_power_info *pi = ci_get_pi(rdev); 4618 struct atom_mc_reg_table *table; 4619 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; 4620 u8 module_index = rv770_get_memory_module_index(rdev); 4621 int ret; 4622 4623 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 4624 if (!table) 4625 return -ENOMEM; 4626 4627 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 4628 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 4629 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY)); 4630 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0)); 4631 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1)); 4632 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL)); 4633 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD)); 4634 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL)); 4635 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 4636 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 4637 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 4638 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 4639 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 4640 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 4641 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 4642 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 4643 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 4644 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 4645 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 4646 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 4647 4648 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 4649 if (ret) 4650 goto init_mc_done; 4651 4652 ret = ci_copy_vbios_mc_reg_table(table, ci_table); 4653 if (ret) 4654 goto init_mc_done; 4655 4656 ci_set_s0_mc_reg_index(ci_table); 4657 4658 ret = ci_register_patching_mc_seq(rdev, ci_table); 4659 if (ret) 4660 goto init_mc_done; 4661 4662 ret = ci_set_mc_special_registers(rdev, ci_table); 4663 if (ret) 4664 goto init_mc_done; 4665 4666 ci_set_valid_flag(ci_table); 4667 4668 init_mc_done: 4669 kfree(table); 4670 4671 return ret; 4672 } 4673 4674 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev, 4675 SMU7_Discrete_MCRegisters *mc_reg_table) 4676 { 4677 struct ci_power_info *pi = ci_get_pi(rdev); 4678 u32 i, j; 4679 4680 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { 4681 if (pi->mc_reg_table.valid_flag & (1 << j)) { 4682 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) 4683 return -EINVAL; 4684 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); 4685 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); 4686 i++; 4687 } 4688 } 4689 4690 mc_reg_table->last = (u8)i; 4691 4692 return 0; 4693 } 4694 4695 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry, 4696 SMU7_Discrete_MCRegisterSet *data, 4697 u32 num_entries, u32 valid_flag) 4698 { 4699 u32 i, j; 4700 4701 for (i = 0, j = 0; j < num_entries; j++) { 4702 if (valid_flag & (1 << j)) { 4703 data->value[i] = cpu_to_be32(entry->mc_data[j]); 4704 i++; 4705 } 4706 } 4707 } 4708 4709 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 4710 const u32 memory_clock, 4711 SMU7_Discrete_MCRegisterSet *mc_reg_table_data) 4712 { 4713 struct ci_power_info *pi = ci_get_pi(rdev); 4714 u32 i = 0; 4715 4716 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { 4717 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 4718 break; 4719 } 4720 4721 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) 4722 --i; 4723 4724 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], 4725 mc_reg_table_data, pi->mc_reg_table.last, 4726 pi->mc_reg_table.valid_flag); 4727 } 4728 4729 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 4730 SMU7_Discrete_MCRegisters *mc_reg_table) 4731 { 4732 struct ci_power_info *pi = ci_get_pi(rdev); 4733 u32 i; 4734 4735 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) 4736 ci_convert_mc_reg_table_entry_to_smc(rdev, 4737 pi->dpm_table.mclk_table.dpm_levels[i].value, 4738 &mc_reg_table->data[i]); 4739 } 4740 4741 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev) 4742 { 4743 struct ci_power_info *pi = ci_get_pi(rdev); 4744 int ret; 4745 4746 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); 4747 4748 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); 4749 if (ret) 4750 return ret; 4751 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); 4752 4753 return ci_copy_bytes_to_smc(rdev, 4754 pi->mc_reg_table_start, 4755 (u8 *)&pi->smc_mc_reg_table, 4756 sizeof(SMU7_Discrete_MCRegisters), 4757 pi->sram_end); 4758 } 4759 4760 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev) 4761 { 4762 struct ci_power_info *pi = ci_get_pi(rdev); 4763 4764 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) 4765 return 0; 4766 4767 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); 4768 4769 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); 4770 4771 return ci_copy_bytes_to_smc(rdev, 4772 pi->mc_reg_table_start + 4773 offsetof(SMU7_Discrete_MCRegisters, data[0]), 4774 (u8 *)&pi->smc_mc_reg_table.data[0], 4775 sizeof(SMU7_Discrete_MCRegisterSet) * 4776 pi->dpm_table.mclk_table.count, 4777 pi->sram_end); 4778 } 4779 4780 static void ci_enable_voltage_control(struct radeon_device *rdev) 4781 { 4782 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); 4783 4784 tmp |= VOLT_PWRMGT_EN; 4785 WREG32_SMC(GENERAL_PWRMGT, tmp); 4786 } 4787 4788 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev, 4789 struct radeon_ps *radeon_state) 4790 { 4791 struct ci_ps *state = ci_get_ps(radeon_state); 4792 int i; 4793 u16 pcie_speed, max_speed = 0; 4794 4795 for (i = 0; i < state->performance_level_count; i++) { 4796 pcie_speed = state->performance_levels[i].pcie_gen; 4797 if (max_speed < pcie_speed) 4798 max_speed = pcie_speed; 4799 } 4800 4801 return max_speed; 4802 } 4803 4804 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev) 4805 { 4806 u32 speed_cntl = 0; 4807 4808 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 4809 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 4810 4811 return (u16)speed_cntl; 4812 } 4813 4814 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev) 4815 { 4816 u32 link_width = 0; 4817 4818 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; 4819 link_width >>= LC_LINK_WIDTH_RD_SHIFT; 4820 4821 switch (link_width) { 4822 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4823 return 1; 4824 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4825 return 2; 4826 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4827 return 4; 4828 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4829 return 8; 4830 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4831 /* not actually supported */ 4832 return 12; 4833 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4834 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4835 default: 4836 return 16; 4837 } 4838 } 4839 4840 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev, 4841 struct radeon_ps *radeon_new_state, 4842 struct radeon_ps *radeon_current_state) 4843 { 4844 struct ci_power_info *pi = ci_get_pi(rdev); 4845 enum radeon_pcie_gen target_link_speed = 4846 ci_get_maximum_link_speed(rdev, radeon_new_state); 4847 enum radeon_pcie_gen current_link_speed; 4848 4849 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 4850 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state); 4851 else 4852 current_link_speed = pi->force_pcie_gen; 4853 4854 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 4855 pi->pspp_notify_required = false; 4856 if (target_link_speed > current_link_speed) { 4857 switch (target_link_speed) { 4858 #ifdef CONFIG_ACPI 4859 case RADEON_PCIE_GEN3: 4860 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 4861 break; 4862 pi->force_pcie_gen = RADEON_PCIE_GEN2; 4863 if (current_link_speed == RADEON_PCIE_GEN2) 4864 break; 4865 case RADEON_PCIE_GEN2: 4866 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 4867 break; 4868 #endif 4869 default: 4870 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); 4871 break; 4872 } 4873 } else { 4874 if (target_link_speed < current_link_speed) 4875 pi->pspp_notify_required = true; 4876 } 4877 } 4878 4879 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 4880 struct radeon_ps *radeon_new_state, 4881 struct radeon_ps *radeon_current_state) 4882 { 4883 struct ci_power_info *pi = ci_get_pi(rdev); 4884 enum radeon_pcie_gen target_link_speed = 4885 ci_get_maximum_link_speed(rdev, radeon_new_state); 4886 u8 request; 4887 4888 if (pi->pspp_notify_required) { 4889 if (target_link_speed == RADEON_PCIE_GEN3) 4890 request = PCIE_PERF_REQ_PECI_GEN3; 4891 else if (target_link_speed == RADEON_PCIE_GEN2) 4892 request = PCIE_PERF_REQ_PECI_GEN2; 4893 else 4894 request = PCIE_PERF_REQ_PECI_GEN1; 4895 4896 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 4897 (ci_get_current_pcie_speed(rdev) > 0)) 4898 return; 4899 4900 #ifdef CONFIG_ACPI 4901 radeon_acpi_pcie_performance_request(rdev, request, false); 4902 #endif 4903 } 4904 } 4905 4906 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev) 4907 { 4908 struct ci_power_info *pi = ci_get_pi(rdev); 4909 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = 4910 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 4911 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table = 4912 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; 4913 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table = 4914 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; 4915 4916 if (allowed_sclk_vddc_table == NULL) 4917 return -EINVAL; 4918 if (allowed_sclk_vddc_table->count < 1) 4919 return -EINVAL; 4920 if (allowed_mclk_vddc_table == NULL) 4921 return -EINVAL; 4922 if (allowed_mclk_vddc_table->count < 1) 4923 return -EINVAL; 4924 if (allowed_mclk_vddci_table == NULL) 4925 return -EINVAL; 4926 if (allowed_mclk_vddci_table->count < 1) 4927 return -EINVAL; 4928 4929 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; 4930 pi->max_vddc_in_pp_table = 4931 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 4932 4933 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; 4934 pi->max_vddci_in_pp_table = 4935 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 4936 4937 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = 4938 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 4939 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = 4940 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 4941 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = 4942 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 4943 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = 4944 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 4945 4946 return 0; 4947 } 4948 4949 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc) 4950 { 4951 struct ci_power_info *pi = ci_get_pi(rdev); 4952 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; 4953 u32 leakage_index; 4954 4955 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { 4956 if (leakage_table->leakage_id[leakage_index] == *vddc) { 4957 *vddc = leakage_table->actual_voltage[leakage_index]; 4958 break; 4959 } 4960 } 4961 } 4962 4963 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci) 4964 { 4965 struct ci_power_info *pi = ci_get_pi(rdev); 4966 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; 4967 u32 leakage_index; 4968 4969 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { 4970 if (leakage_table->leakage_id[leakage_index] == *vddci) { 4971 *vddci = leakage_table->actual_voltage[leakage_index]; 4972 break; 4973 } 4974 } 4975 } 4976 4977 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 4978 struct radeon_clock_voltage_dependency_table *table) 4979 { 4980 u32 i; 4981 4982 if (table) { 4983 for (i = 0; i < table->count; i++) 4984 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 4985 } 4986 } 4987 4988 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev, 4989 struct radeon_clock_voltage_dependency_table *table) 4990 { 4991 u32 i; 4992 4993 if (table) { 4994 for (i = 0; i < table->count; i++) 4995 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); 4996 } 4997 } 4998 4999 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 5000 struct radeon_vce_clock_voltage_dependency_table *table) 5001 { 5002 u32 i; 5003 5004 if (table) { 5005 for (i = 0; i < table->count; i++) 5006 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 5007 } 5008 } 5009 5010 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, 5011 struct radeon_uvd_clock_voltage_dependency_table *table) 5012 { 5013 u32 i; 5014 5015 if (table) { 5016 for (i = 0; i < table->count; i++) 5017 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); 5018 } 5019 } 5020 5021 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev, 5022 struct radeon_phase_shedding_limits_table *table) 5023 { 5024 u32 i; 5025 5026 if (table) { 5027 for (i = 0; i < table->count; i++) 5028 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); 5029 } 5030 } 5031 5032 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev, 5033 struct radeon_clock_and_voltage_limits *table) 5034 { 5035 if (table) { 5036 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); 5037 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); 5038 } 5039 } 5040 5041 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev, 5042 struct radeon_cac_leakage_table *table) 5043 { 5044 u32 i; 5045 5046 if (table) { 5047 for (i = 0; i < table->count; i++) 5048 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); 5049 } 5050 } 5051 5052 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev) 5053 { 5054 5055 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5056 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5057 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5058 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5059 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5060 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); 5061 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev, 5062 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5063 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5064 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); 5065 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5066 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); 5067 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5068 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); 5069 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, 5070 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); 5071 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev, 5072 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); 5073 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, 5074 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); 5075 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, 5076 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); 5077 ci_patch_cac_leakage_table_with_vddc_leakage(rdev, 5078 &rdev->pm.dpm.dyn_state.cac_leakage_table); 5079 5080 } 5081 5082 static void ci_get_memory_type(struct radeon_device *rdev) 5083 { 5084 struct ci_power_info *pi = ci_get_pi(rdev); 5085 u32 tmp; 5086 5087 tmp = RREG32(MC_SEQ_MISC0); 5088 5089 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) == 5090 MC_SEQ_MISC0_GDDR5_VALUE) 5091 pi->mem_gddr5 = true; 5092 else 5093 pi->mem_gddr5 = false; 5094 5095 } 5096 5097 static void ci_update_current_ps(struct radeon_device *rdev, 5098 struct radeon_ps *rps) 5099 { 5100 struct ci_ps *new_ps = ci_get_ps(rps); 5101 struct ci_power_info *pi = ci_get_pi(rdev); 5102 5103 pi->current_rps = *rps; 5104 pi->current_ps = *new_ps; 5105 pi->current_rps.ps_priv = &pi->current_ps; 5106 } 5107 5108 static void ci_update_requested_ps(struct radeon_device *rdev, 5109 struct radeon_ps *rps) 5110 { 5111 struct ci_ps *new_ps = ci_get_ps(rps); 5112 struct ci_power_info *pi = ci_get_pi(rdev); 5113 5114 pi->requested_rps = *rps; 5115 pi->requested_ps = *new_ps; 5116 pi->requested_rps.ps_priv = &pi->requested_ps; 5117 } 5118 5119 int ci_dpm_pre_set_power_state(struct radeon_device *rdev) 5120 { 5121 struct ci_power_info *pi = ci_get_pi(rdev); 5122 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 5123 struct radeon_ps *new_ps = &requested_ps; 5124 5125 ci_update_requested_ps(rdev, new_ps); 5126 5127 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); 5128 5129 return 0; 5130 } 5131 5132 void ci_dpm_post_set_power_state(struct radeon_device *rdev) 5133 { 5134 struct ci_power_info *pi = ci_get_pi(rdev); 5135 struct radeon_ps *new_ps = &pi->requested_rps; 5136 5137 ci_update_current_ps(rdev, new_ps); 5138 } 5139 5140 5141 void ci_dpm_setup_asic(struct radeon_device *rdev) 5142 { 5143 int r; 5144 5145 r = ci_mc_load_microcode(rdev); 5146 if (r) 5147 DRM_ERROR("Failed to load MC firmware!\n"); 5148 ci_read_clock_registers(rdev); 5149 ci_get_memory_type(rdev); 5150 ci_enable_acpi_power_management(rdev); 5151 ci_init_sclk_t(rdev); 5152 } 5153 5154 int ci_dpm_enable(struct radeon_device *rdev) 5155 { 5156 struct ci_power_info *pi = ci_get_pi(rdev); 5157 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5158 int ret; 5159 5160 if (ci_is_smc_running(rdev)) 5161 return -EINVAL; 5162 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 5163 ci_enable_voltage_control(rdev); 5164 ret = ci_construct_voltage_tables(rdev); 5165 if (ret) { 5166 DRM_ERROR("ci_construct_voltage_tables failed\n"); 5167 return ret; 5168 } 5169 } 5170 if (pi->caps_dynamic_ac_timing) { 5171 ret = ci_initialize_mc_reg_table(rdev); 5172 if (ret) 5173 pi->caps_dynamic_ac_timing = false; 5174 } 5175 if (pi->dynamic_ss) 5176 ci_enable_spread_spectrum(rdev, true); 5177 if (pi->thermal_protection) 5178 ci_enable_thermal_protection(rdev, true); 5179 ci_program_sstp(rdev); 5180 ci_enable_display_gap(rdev); 5181 ci_program_vc(rdev); 5182 ret = ci_upload_firmware(rdev); 5183 if (ret) { 5184 DRM_ERROR("ci_upload_firmware failed\n"); 5185 return ret; 5186 } 5187 ret = ci_process_firmware_header(rdev); 5188 if (ret) { 5189 DRM_ERROR("ci_process_firmware_header failed\n"); 5190 return ret; 5191 } 5192 ret = ci_initial_switch_from_arb_f0_to_f1(rdev); 5193 if (ret) { 5194 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n"); 5195 return ret; 5196 } 5197 ret = ci_init_smc_table(rdev); 5198 if (ret) { 5199 DRM_ERROR("ci_init_smc_table failed\n"); 5200 return ret; 5201 } 5202 ret = ci_init_arb_table_index(rdev); 5203 if (ret) { 5204 DRM_ERROR("ci_init_arb_table_index failed\n"); 5205 return ret; 5206 } 5207 if (pi->caps_dynamic_ac_timing) { 5208 ret = ci_populate_initial_mc_reg_table(rdev); 5209 if (ret) { 5210 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n"); 5211 return ret; 5212 } 5213 } 5214 ret = ci_populate_pm_base(rdev); 5215 if (ret) { 5216 DRM_ERROR("ci_populate_pm_base failed\n"); 5217 return ret; 5218 } 5219 ci_dpm_start_smc(rdev); 5220 ci_enable_vr_hot_gpio_interrupt(rdev); 5221 ret = ci_notify_smc_display_change(rdev, false); 5222 if (ret) { 5223 DRM_ERROR("ci_notify_smc_display_change failed\n"); 5224 return ret; 5225 } 5226 ci_enable_sclk_control(rdev, true); 5227 ret = ci_enable_ulv(rdev, true); 5228 if (ret) { 5229 DRM_ERROR("ci_enable_ulv failed\n"); 5230 return ret; 5231 } 5232 ret = ci_enable_ds_master_switch(rdev, true); 5233 if (ret) { 5234 DRM_ERROR("ci_enable_ds_master_switch failed\n"); 5235 return ret; 5236 } 5237 ret = ci_start_dpm(rdev); 5238 if (ret) { 5239 DRM_ERROR("ci_start_dpm failed\n"); 5240 return ret; 5241 } 5242 ret = ci_enable_didt(rdev, true); 5243 if (ret) { 5244 DRM_ERROR("ci_enable_didt failed\n"); 5245 return ret; 5246 } 5247 ret = ci_enable_smc_cac(rdev, true); 5248 if (ret) { 5249 DRM_ERROR("ci_enable_smc_cac failed\n"); 5250 return ret; 5251 } 5252 ret = ci_enable_power_containment(rdev, true); 5253 if (ret) { 5254 DRM_ERROR("ci_enable_power_containment failed\n"); 5255 return ret; 5256 } 5257 5258 ret = ci_power_control_set_level(rdev); 5259 if (ret) { 5260 DRM_ERROR("ci_power_control_set_level failed\n"); 5261 return ret; 5262 } 5263 5264 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5265 5266 ret = ci_enable_thermal_based_sclk_dpm(rdev, true); 5267 if (ret) { 5268 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n"); 5269 return ret; 5270 } 5271 5272 ci_thermal_start_thermal_controller(rdev); 5273 5274 ci_update_current_ps(rdev, boot_ps); 5275 5276 return 0; 5277 } 5278 5279 static int ci_set_temperature_range(struct radeon_device *rdev) 5280 { 5281 int ret; 5282 5283 ret = ci_thermal_enable_alert(rdev, false); 5284 if (ret) 5285 return ret; 5286 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5287 if (ret) 5288 return ret; 5289 ret = ci_thermal_enable_alert(rdev, true); 5290 if (ret) 5291 return ret; 5292 5293 return ret; 5294 } 5295 5296 int ci_dpm_late_enable(struct radeon_device *rdev) 5297 { 5298 int ret; 5299 5300 ret = ci_set_temperature_range(rdev); 5301 if (ret) 5302 return ret; 5303 5304 ci_dpm_powergate_uvd(rdev, true); 5305 5306 return 0; 5307 } 5308 5309 void ci_dpm_disable(struct radeon_device *rdev) 5310 { 5311 struct ci_power_info *pi = ci_get_pi(rdev); 5312 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5313 5314 ci_dpm_powergate_uvd(rdev, false); 5315 5316 if (!ci_is_smc_running(rdev)) 5317 return; 5318 5319 ci_thermal_stop_thermal_controller(rdev); 5320 5321 if (pi->thermal_protection) 5322 ci_enable_thermal_protection(rdev, false); 5323 ci_enable_power_containment(rdev, false); 5324 ci_enable_smc_cac(rdev, false); 5325 ci_enable_didt(rdev, false); 5326 ci_enable_spread_spectrum(rdev, false); 5327 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5328 ci_stop_dpm(rdev); 5329 ci_enable_ds_master_switch(rdev, false); 5330 ci_enable_ulv(rdev, false); 5331 ci_clear_vc(rdev); 5332 ci_reset_to_default(rdev); 5333 ci_dpm_stop_smc(rdev); 5334 ci_force_switch_to_arb_f0(rdev); 5335 ci_enable_thermal_based_sclk_dpm(rdev, false); 5336 5337 ci_update_current_ps(rdev, boot_ps); 5338 } 5339 5340 int ci_dpm_set_power_state(struct radeon_device *rdev) 5341 { 5342 struct ci_power_info *pi = ci_get_pi(rdev); 5343 struct radeon_ps *new_ps = &pi->requested_rps; 5344 struct radeon_ps *old_ps = &pi->current_rps; 5345 int ret; 5346 5347 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps); 5348 if (pi->pcie_performance_request) 5349 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 5350 ret = ci_freeze_sclk_mclk_dpm(rdev); 5351 if (ret) { 5352 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n"); 5353 return ret; 5354 } 5355 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps); 5356 if (ret) { 5357 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n"); 5358 return ret; 5359 } 5360 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps); 5361 if (ret) { 5362 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n"); 5363 return ret; 5364 } 5365 5366 ret = ci_update_vce_dpm(rdev, new_ps, old_ps); 5367 if (ret) { 5368 DRM_ERROR("ci_update_vce_dpm failed\n"); 5369 return ret; 5370 } 5371 5372 ret = ci_update_sclk_t(rdev); 5373 if (ret) { 5374 DRM_ERROR("ci_update_sclk_t failed\n"); 5375 return ret; 5376 } 5377 if (pi->caps_dynamic_ac_timing) { 5378 ret = ci_update_and_upload_mc_reg_table(rdev); 5379 if (ret) { 5380 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n"); 5381 return ret; 5382 } 5383 } 5384 ret = ci_program_memory_timing_parameters(rdev); 5385 if (ret) { 5386 DRM_ERROR("ci_program_memory_timing_parameters failed\n"); 5387 return ret; 5388 } 5389 ret = ci_unfreeze_sclk_mclk_dpm(rdev); 5390 if (ret) { 5391 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n"); 5392 return ret; 5393 } 5394 ret = ci_upload_dpm_level_enable_mask(rdev); 5395 if (ret) { 5396 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n"); 5397 return ret; 5398 } 5399 if (pi->pcie_performance_request) 5400 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 5401 5402 return 0; 5403 } 5404 5405 #if 0 5406 void ci_dpm_reset_asic(struct radeon_device *rdev) 5407 { 5408 ci_set_boot_state(rdev); 5409 } 5410 #endif 5411 5412 void ci_dpm_display_configuration_changed(struct radeon_device *rdev) 5413 { 5414 ci_program_display_gap(rdev); 5415 } 5416 5417 union power_info { 5418 struct _ATOM_POWERPLAY_INFO info; 5419 struct _ATOM_POWERPLAY_INFO_V2 info_2; 5420 struct _ATOM_POWERPLAY_INFO_V3 info_3; 5421 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 5422 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 5423 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 5424 }; 5425 5426 union pplib_clock_info { 5427 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 5428 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 5429 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 5430 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 5431 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 5432 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 5433 }; 5434 5435 union pplib_power_state { 5436 struct _ATOM_PPLIB_STATE v1; 5437 struct _ATOM_PPLIB_STATE_V2 v2; 5438 }; 5439 5440 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev, 5441 struct radeon_ps *rps, 5442 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 5443 u8 table_rev) 5444 { 5445 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 5446 rps->class = le16_to_cpu(non_clock_info->usClassification); 5447 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 5448 5449 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 5450 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 5451 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 5452 } else { 5453 rps->vclk = 0; 5454 rps->dclk = 0; 5455 } 5456 5457 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 5458 rdev->pm.dpm.boot_ps = rps; 5459 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 5460 rdev->pm.dpm.uvd_ps = rps; 5461 } 5462 5463 static void ci_parse_pplib_clock_info(struct radeon_device *rdev, 5464 struct radeon_ps *rps, int index, 5465 union pplib_clock_info *clock_info) 5466 { 5467 struct ci_power_info *pi = ci_get_pi(rdev); 5468 struct ci_ps *ps = ci_get_ps(rps); 5469 struct ci_pl *pl = &ps->performance_levels[index]; 5470 5471 ps->performance_level_count = index + 1; 5472 5473 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 5474 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16; 5475 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 5476 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16; 5477 5478 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 5479 pi->sys_pcie_mask, 5480 pi->vbios_boot_state.pcie_gen_bootup_value, 5481 clock_info->ci.ucPCIEGen); 5482 pl->pcie_lane = r600_get_pcie_lane_support(rdev, 5483 pi->vbios_boot_state.pcie_lane_bootup_value, 5484 le16_to_cpu(clock_info->ci.usPCIELane)); 5485 5486 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 5487 pi->acpi_pcie_gen = pl->pcie_gen; 5488 } 5489 5490 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { 5491 pi->ulv.supported = true; 5492 pi->ulv.pl = *pl; 5493 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; 5494 } 5495 5496 /* patch up boot state */ 5497 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 5498 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; 5499 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; 5500 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; 5501 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; 5502 } 5503 5504 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 5505 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 5506 pi->use_pcie_powersaving_levels = true; 5507 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) 5508 pi->pcie_gen_powersaving.max = pl->pcie_gen; 5509 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) 5510 pi->pcie_gen_powersaving.min = pl->pcie_gen; 5511 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) 5512 pi->pcie_lane_powersaving.max = pl->pcie_lane; 5513 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) 5514 pi->pcie_lane_powersaving.min = pl->pcie_lane; 5515 break; 5516 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 5517 pi->use_pcie_performance_levels = true; 5518 if (pi->pcie_gen_performance.max < pl->pcie_gen) 5519 pi->pcie_gen_performance.max = pl->pcie_gen; 5520 if (pi->pcie_gen_performance.min > pl->pcie_gen) 5521 pi->pcie_gen_performance.min = pl->pcie_gen; 5522 if (pi->pcie_lane_performance.max < pl->pcie_lane) 5523 pi->pcie_lane_performance.max = pl->pcie_lane; 5524 if (pi->pcie_lane_performance.min > pl->pcie_lane) 5525 pi->pcie_lane_performance.min = pl->pcie_lane; 5526 break; 5527 default: 5528 break; 5529 } 5530 } 5531 5532 static int ci_parse_power_table(struct radeon_device *rdev) 5533 { 5534 struct radeon_mode_info *mode_info = &rdev->mode_info; 5535 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 5536 union pplib_power_state *power_state; 5537 int i, j, k, non_clock_array_index, clock_array_index; 5538 union pplib_clock_info *clock_info; 5539 struct _StateArray *state_array; 5540 struct _ClockInfoArray *clock_info_array; 5541 struct _NonClockInfoArray *non_clock_info_array; 5542 union power_info *power_info; 5543 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 5544 u16 data_offset; 5545 u8 frev, crev; 5546 u8 *power_state_offset; 5547 struct ci_ps *ps; 5548 5549 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 5550 &frev, &crev, &data_offset)) 5551 return -EINVAL; 5552 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 5553 5554 state_array = (struct _StateArray *) 5555 (mode_info->atom_context->bios + data_offset + 5556 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 5557 clock_info_array = (struct _ClockInfoArray *) 5558 (mode_info->atom_context->bios + data_offset + 5559 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 5560 non_clock_info_array = (struct _NonClockInfoArray *) 5561 (mode_info->atom_context->bios + data_offset + 5562 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 5563 5564 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 5565 state_array->ucNumEntries, GFP_KERNEL); 5566 if (!rdev->pm.dpm.ps) 5567 return -ENOMEM; 5568 power_state_offset = (u8 *)state_array->states; 5569 for (i = 0; i < state_array->ucNumEntries; i++) { 5570 u8 *idx; 5571 power_state = (union pplib_power_state *)power_state_offset; 5572 non_clock_array_index = power_state->v2.nonClockInfoIndex; 5573 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 5574 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 5575 if (!rdev->pm.power_state[i].clock_info) 5576 return -EINVAL; 5577 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL); 5578 if (ps == NULL) { 5579 kfree(rdev->pm.dpm.ps); 5580 return -ENOMEM; 5581 } 5582 rdev->pm.dpm.ps[i].ps_priv = ps; 5583 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 5584 non_clock_info, 5585 non_clock_info_array->ucEntrySize); 5586 k = 0; 5587 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 5588 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 5589 clock_array_index = idx[j]; 5590 if (clock_array_index >= clock_info_array->ucNumEntries) 5591 continue; 5592 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS) 5593 break; 5594 clock_info = (union pplib_clock_info *) 5595 ((u8 *)&clock_info_array->clockInfo[0] + 5596 (clock_array_index * clock_info_array->ucEntrySize)); 5597 ci_parse_pplib_clock_info(rdev, 5598 &rdev->pm.dpm.ps[i], k, 5599 clock_info); 5600 k++; 5601 } 5602 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 5603 } 5604 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 5605 5606 /* fill in the vce power states */ 5607 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 5608 u32 sclk, mclk; 5609 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 5610 clock_info = (union pplib_clock_info *) 5611 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 5612 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 5613 sclk |= clock_info->ci.ucEngineClockHigh << 16; 5614 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 5615 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 5616 rdev->pm.dpm.vce_states[i].sclk = sclk; 5617 rdev->pm.dpm.vce_states[i].mclk = mclk; 5618 } 5619 5620 return 0; 5621 } 5622 5623 static int ci_get_vbios_boot_values(struct radeon_device *rdev, 5624 struct ci_vbios_boot_state *boot_state) 5625 { 5626 struct radeon_mode_info *mode_info = &rdev->mode_info; 5627 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 5628 ATOM_FIRMWARE_INFO_V2_2 *firmware_info; 5629 u8 frev, crev; 5630 u16 data_offset; 5631 5632 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 5633 &frev, &crev, &data_offset)) { 5634 firmware_info = 5635 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios + 5636 data_offset); 5637 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage); 5638 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage); 5639 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage); 5640 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev); 5641 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev); 5642 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock); 5643 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock); 5644 5645 return 0; 5646 } 5647 return -EINVAL; 5648 } 5649 5650 void ci_dpm_fini(struct radeon_device *rdev) 5651 { 5652 int i; 5653 5654 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 5655 kfree(rdev->pm.dpm.ps[i].ps_priv); 5656 } 5657 kfree(rdev->pm.dpm.ps); 5658 kfree(rdev->pm.dpm.priv); 5659 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 5660 r600_free_extended_power_table(rdev); 5661 } 5662 5663 int ci_dpm_init(struct radeon_device *rdev) 5664 { 5665 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 5666 SMU7_Discrete_DpmTable *dpm_table; 5667 struct radeon_gpio_rec gpio; 5668 u16 data_offset, size; 5669 u8 frev, crev; 5670 struct ci_power_info *pi; 5671 int ret; 5672 u32 mask; 5673 5674 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); 5675 if (pi == NULL) 5676 return -ENOMEM; 5677 rdev->pm.dpm.priv = pi; 5678 5679 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 5680 if (ret) 5681 pi->sys_pcie_mask = 0; 5682 else 5683 pi->sys_pcie_mask = mask; 5684 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5685 5686 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; 5687 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; 5688 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; 5689 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; 5690 5691 pi->pcie_lane_performance.max = 0; 5692 pi->pcie_lane_performance.min = 16; 5693 pi->pcie_lane_powersaving.max = 0; 5694 pi->pcie_lane_powersaving.min = 16; 5695 5696 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); 5697 if (ret) { 5698 ci_dpm_fini(rdev); 5699 return ret; 5700 } 5701 5702 ret = r600_get_platform_caps(rdev); 5703 if (ret) { 5704 ci_dpm_fini(rdev); 5705 return ret; 5706 } 5707 5708 ret = r600_parse_extended_power_table(rdev); 5709 if (ret) { 5710 ci_dpm_fini(rdev); 5711 return ret; 5712 } 5713 5714 ret = ci_parse_power_table(rdev); 5715 if (ret) { 5716 ci_dpm_fini(rdev); 5717 return ret; 5718 } 5719 5720 pi->dll_default_on = false; 5721 pi->sram_end = SMC_RAM_END; 5722 5723 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; 5724 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; 5725 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; 5726 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; 5727 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; 5728 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; 5729 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; 5730 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; 5731 5732 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; 5733 5734 pi->sclk_dpm_key_disabled = 0; 5735 pi->mclk_dpm_key_disabled = 0; 5736 pi->pcie_dpm_key_disabled = 0; 5737 pi->thermal_sclk_dpm_enabled = 0; 5738 5739 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */ 5740 if ((rdev->pdev->device == 0x6658) && 5741 (rdev->mc_fw->datasize == (BONAIRE_MC_UCODE_SIZE * 4))) { 5742 pi->mclk_dpm_key_disabled = 1; 5743 } 5744 5745 pi->caps_sclk_ds = true; 5746 5747 pi->mclk_strobe_mode_threshold = 40000; 5748 pi->mclk_stutter_mode_threshold = 40000; 5749 pi->mclk_edc_enable_threshold = 40000; 5750 pi->mclk_edc_wr_enable_threshold = 40000; 5751 5752 ci_initialize_powertune_defaults(rdev); 5753 5754 pi->caps_fps = false; 5755 5756 pi->caps_sclk_throttle_low_notification = false; 5757 5758 pi->caps_uvd_dpm = true; 5759 pi->caps_vce_dpm = true; 5760 5761 ci_get_leakage_voltages(rdev); 5762 ci_patch_dependency_tables_with_leakage(rdev); 5763 ci_set_private_data_variables_based_on_pptable(rdev); 5764 5765 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 5766 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 5767 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 5768 ci_dpm_fini(rdev); 5769 return -ENOMEM; 5770 } 5771 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 5772 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 5773 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 5774 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 5775 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 5776 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 5777 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 5778 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 5779 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 5780 5781 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 5782 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 5783 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 5784 5785 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 5786 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 5787 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 5788 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 5789 5790 if (rdev->family == CHIP_HAWAII) { 5791 pi->thermal_temp_setting.temperature_low = 94500; 5792 pi->thermal_temp_setting.temperature_high = 95000; 5793 pi->thermal_temp_setting.temperature_shutdown = 104000; 5794 } else { 5795 pi->thermal_temp_setting.temperature_low = 99500; 5796 pi->thermal_temp_setting.temperature_high = 100000; 5797 pi->thermal_temp_setting.temperature_shutdown = 104000; 5798 } 5799 5800 pi->uvd_enabled = false; 5801 5802 dpm_table = &pi->smc_state_table; 5803 5804 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID); 5805 if (gpio.valid) { 5806 dpm_table->VRHotGpio = gpio.shift; 5807 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; 5808 } else { 5809 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN; 5810 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; 5811 } 5812 5813 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID); 5814 if (gpio.valid) { 5815 dpm_table->AcDcGpio = gpio.shift; 5816 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC; 5817 } else { 5818 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN; 5819 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC; 5820 } 5821 5822 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID); 5823 if (gpio.valid) { 5824 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL); 5825 5826 switch (gpio.shift) { 5827 case 0: 5828 tmp &= ~GNB_SLOW_MODE_MASK; 5829 tmp |= GNB_SLOW_MODE(1); 5830 break; 5831 case 1: 5832 tmp &= ~GNB_SLOW_MODE_MASK; 5833 tmp |= GNB_SLOW_MODE(2); 5834 break; 5835 case 2: 5836 tmp |= GNB_SLOW; 5837 break; 5838 case 3: 5839 tmp |= FORCE_NB_PS1; 5840 break; 5841 case 4: 5842 tmp |= DPM_ENABLED; 5843 break; 5844 default: 5845 DRM_DEBUG("Invalid PCC GPIO: %u!\n", gpio.shift); 5846 break; 5847 } 5848 WREG32_SMC(CNB_PWRMGT_CNTL, tmp); 5849 } 5850 5851 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5852 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5853 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; 5854 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) 5855 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5856 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) 5857 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5858 5859 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { 5860 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 5861 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5862 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) 5863 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5864 else 5865 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; 5866 } 5867 5868 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { 5869 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) 5870 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; 5871 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) 5872 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; 5873 else 5874 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; 5875 } 5876 5877 pi->vddc_phase_shed_control = true; 5878 5879 #if defined(CONFIG_ACPI) 5880 pi->pcie_performance_request = 5881 radeon_acpi_is_pcie_performance_request_supported(rdev); 5882 #else 5883 pi->pcie_performance_request = false; 5884 #endif 5885 5886 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 5887 &frev, &crev, &data_offset)) { 5888 pi->caps_sclk_ss_support = true; 5889 pi->caps_mclk_ss_support = true; 5890 pi->dynamic_ss = true; 5891 } else { 5892 pi->caps_sclk_ss_support = false; 5893 pi->caps_mclk_ss_support = false; 5894 pi->dynamic_ss = true; 5895 } 5896 5897 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 5898 pi->thermal_protection = true; 5899 else 5900 pi->thermal_protection = false; 5901 5902 pi->caps_dynamic_ac_timing = true; 5903 5904 pi->uvd_power_gated = false; 5905 5906 /* make sure dc limits are valid */ 5907 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 5908 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 5909 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 5910 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 5911 5912 pi->fan_ctrl_is_in_default_mode = true; 5913 5914 return 0; 5915 } 5916 5917 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 5918 struct seq_file *m) 5919 { 5920 struct ci_power_info *pi = ci_get_pi(rdev); 5921 struct radeon_ps *rps = &pi->current_rps; 5922 u32 sclk = ci_get_average_sclk_freq(rdev); 5923 u32 mclk = ci_get_average_mclk_freq(rdev); 5924 5925 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); 5926 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis"); 5927 seq_printf(m, "power level avg sclk: %u mclk: %u\n", 5928 sclk, mclk); 5929 } 5930 5931 void ci_dpm_print_power_state(struct radeon_device *rdev, 5932 struct radeon_ps *rps) 5933 { 5934 struct ci_ps *ps = ci_get_ps(rps); 5935 struct ci_pl *pl; 5936 int i; 5937 5938 r600_dpm_print_class_info(rps->class, rps->class2); 5939 r600_dpm_print_cap_info(rps->caps); 5940 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 5941 for (i = 0; i < ps->performance_level_count; i++) { 5942 pl = &ps->performance_levels[i]; 5943 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n", 5944 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane); 5945 } 5946 r600_dpm_print_ps_status(rdev, rps); 5947 } 5948 5949 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev) 5950 { 5951 u32 sclk = ci_get_average_sclk_freq(rdev); 5952 5953 return sclk; 5954 } 5955 5956 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev) 5957 { 5958 u32 mclk = ci_get_average_mclk_freq(rdev); 5959 5960 return mclk; 5961 } 5962 5963 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low) 5964 { 5965 struct ci_power_info *pi = ci_get_pi(rdev); 5966 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 5967 5968 if (low) 5969 return requested_state->performance_levels[0].sclk; 5970 else 5971 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 5972 } 5973 5974 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low) 5975 { 5976 struct ci_power_info *pi = ci_get_pi(rdev); 5977 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); 5978 5979 if (low) 5980 return requested_state->performance_levels[0].mclk; 5981 else 5982 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 5983 } 5984