1 /* 2 * Copyright (c) 2014-2015 François Tigeot 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef LINUX_PCI_H 28 #define LINUX_PCI_H 29 30 #define PCI_ANY_ID (~0u) 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/pciio.h> 35 #include <sys/rman.h> 36 #include <bus/pci/pcivar.h> 37 #include <bus/pci/pcireg.h> 38 39 #include <linux/types.h> 40 #include <linux/device.h> 41 #include <linux/io.h> 42 43 #include <linux/pci_ids.h> 44 45 struct pci_bus; 46 47 struct pci_device_id { 48 uint32_t class; 49 uint32_t class_mask; 50 uint32_t vendor; 51 uint32_t device; 52 uint32_t subvendor; 53 uint32_t subdevice; 54 unsigned long driver_data; 55 }; 56 57 struct pci_dev { 58 struct pci_bus *bus; /* bus device is nailed to */ 59 struct device *dev; /* NOTE the star */ 60 61 unsigned short vendor; /* vendor ID */ 62 unsigned short device; /* device ID */ 63 unsigned short subsystem_vendor; 64 unsigned short subsystem_device; 65 66 unsigned int irq; 67 }; 68 69 struct pci_bus { 70 struct pci_dev *self; /* handle to pdev self */ 71 struct device *dev; /* handle to dev */ 72 73 unsigned char number; /* bus addr number */ 74 }; 75 76 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 77 78 #define PCI_DMA_BIDIRECTIONAL 0 79 80 /* extracted from radeon/si.c radeon/cik.c */ 81 #define PCI_EXP_LNKCTL PCIER_LINKCTRL /* 16 */ 82 #define PCI_EXP_LNKCTL2 48 83 #define PCI_EXP_LNKCTL_HAWD PCIEM_LNKCTL_HAWD /* 0x0200 */ 84 #define PCI_EXP_DEVSTA PCIER_DEVSTS /* 10 */ 85 #define PCI_EXP_DEVSTA_TRPND 0x0020 86 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 87 88 static inline int 89 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 90 { 91 *val = (u16)pci_read_config(pdev->dev, where, 1); 92 return 0; 93 } 94 95 static inline int 96 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 97 { 98 *val = (u16)pci_read_config(pdev->dev, where, 2); 99 return 0; 100 } 101 102 static inline int 103 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 104 { 105 *val = (u32)pci_read_config(pdev->dev, where, 4); 106 return 0; 107 } 108 109 static inline int 110 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 111 { 112 pci_write_config(pdev->dev, where, val, 1); 113 return 0; 114 } 115 116 static inline int 117 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 118 { 119 pci_write_config(pdev->dev, where, val, 2); 120 return 0; 121 } 122 123 static inline int 124 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 125 { 126 pci_write_config(pdev->dev, where, val, 4); 127 return 0; 128 } 129 130 /* extracted from drm/radeon/evergreen.c */ 131 static inline int 132 pcie_get_readrq(struct pci_dev *pdev) 133 { 134 u16 ctl; 135 int err, cap; 136 137 err = pci_find_extcap(pdev->dev, PCIY_EXPRESS, &cap); 138 WARN_ON(err); 139 140 cap += PCIER_DEVCTRL; 141 142 ctl = pci_read_config(pdev->dev, cap, 2); 143 144 return 128 << ((ctl & PCIEM_DEVCTL_MAX_READRQ_MASK) >> 12); 145 } 146 147 /* valid rq sizes: 128, 256, 512, 1024, 2048, 4096 (^2N) */ 148 static inline int 149 pcie_set_readrq(struct pci_dev *pdev, int rq) 150 { 151 u16 ctl; 152 int err, cap; 153 154 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 155 return -EINVAL; 156 157 err = pci_find_extcap(pdev->dev, PCIY_EXPRESS, &cap); 158 if (err) 159 return (-1); 160 161 cap += PCIER_DEVCTRL; 162 163 ctl = pci_read_config(pdev->dev, cap, 2); 164 ctl &= ~PCIEM_DEVCTL_MAX_READRQ_MASK; 165 ctl |= ((ffs(rq) - 8) << 12); 166 pci_write_config(pdev->dev, cap, ctl, 2); 167 return 0; 168 } 169 170 static inline struct pci_dev * 171 pci_dev_get(struct pci_dev *dev) 172 { 173 /* Linux increments a reference count here */ 174 return dev; 175 } 176 177 static inline struct pci_dev * 178 pci_dev_put(struct pci_dev *dev) 179 { 180 /* Linux decrements a reference count here */ 181 return dev; 182 } 183 184 185 static inline int 186 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 187 { 188 return -EIO; 189 } 190 191 static inline int 192 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 193 { 194 return -EIO; 195 } 196 197 typedef int pci_power_t; 198 199 #define PCI_D0 0 200 #define PCI_D1 1 201 #define PCI_D2 2 202 #define PCI_D3hot 3 203 #define PCI_D3cold 4 204 205 #include <asm/pci.h> 206 207 static inline struct resource_list_entry* 208 _pci_get_rle(struct pci_dev *pdev, int bar) 209 { 210 struct pci_devinfo *dinfo; 211 struct device *dev = pdev->dev; 212 struct resource_list_entry *rle; 213 214 dinfo = device_get_ivars(dev); 215 216 /* Some child devices don't have registered resources, they 217 * are only present in the parent */ 218 if (dinfo == NULL) { 219 kprintf("_pci_get_rle: dinfo was NULL, trying again with parent\n"); 220 dev = device_get_parent(dev); 221 } 222 dinfo = device_get_ivars(dev); 223 if (dinfo == NULL) 224 return NULL; 225 226 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, PCIR_BAR(bar)); 227 if (rle == NULL) { 228 rle = resource_list_find(&dinfo->resources, 229 SYS_RES_IOPORT, PCIR_BAR(bar)); 230 } 231 232 return rle; 233 } 234 235 /* 236 * Returns the first address (memory address or I/O port number) 237 * associated with one of the PCI I/O regions.The region is selected by 238 * the integer bar (the base address register), ranging from 0–5 (inclusive). 239 * The return value can be used by ioremap() 240 */ 241 static inline phys_addr_t 242 pci_resource_start(struct pci_dev *pdev, int bar) 243 { 244 struct resource_list_entry *rle; 245 246 rle = _pci_get_rle(pdev, bar); 247 if (rle == NULL) 248 return -1; 249 250 kprintf("pci_resource_start(0x%x, 0x%x) = 0x%lx\n", 251 pdev->device, PCIR_BAR(bar), rman_get_start(rle->res)); 252 253 return rman_get_start(rle->res); 254 } 255 256 static inline phys_addr_t 257 pci_resource_len(struct pci_dev *pdev, int bar) 258 { 259 struct resource_list_entry *rle; 260 261 rle = _pci_get_rle(pdev, bar); 262 if (rle == NULL) 263 return -1; 264 265 kprintf("pci_resource_len(0x%x, 0x%x) = 0x%lx\n", 266 pdev->device, PCIR_BAR(bar), rman_get_size(rle->res)); 267 268 return rman_get_size(rle->res); 269 } 270 271 #endif /* LINUX_PCI_H */ 272