xref: /dflybsd-src/sys/dev/drm/include/asm/cpufeature.h (revision c406748ed04d4d129afc2aa465cf148403725af1)
1*c406748eSFrançois Tigeot /*
2*c406748eSFrançois Tigeot  * Copyright (c) 2016 François Tigeot
3*c406748eSFrançois Tigeot  * All rights reserved.
4*c406748eSFrançois Tigeot  *
5*c406748eSFrançois Tigeot  * Redistribution and use in source and binary forms, with or without
6*c406748eSFrançois Tigeot  * modification, are permitted provided that the following conditions
7*c406748eSFrançois Tigeot  * are met:
8*c406748eSFrançois Tigeot  * 1. Redistributions of source code must retain the above copyright
9*c406748eSFrançois Tigeot  *    notice unmodified, this list of conditions, and the following
10*c406748eSFrançois Tigeot  *    disclaimer.
11*c406748eSFrançois Tigeot  * 2. Redistributions in binary form must reproduce the above copyright
12*c406748eSFrançois Tigeot  *    notice, this list of conditions and the following disclaimer in the
13*c406748eSFrançois Tigeot  *    documentation and/or other materials provided with the distribution.
14*c406748eSFrançois Tigeot  *
15*c406748eSFrançois Tigeot  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16*c406748eSFrançois Tigeot  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17*c406748eSFrançois Tigeot  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18*c406748eSFrançois Tigeot  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19*c406748eSFrançois Tigeot  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20*c406748eSFrançois Tigeot  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21*c406748eSFrançois Tigeot  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22*c406748eSFrançois Tigeot  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23*c406748eSFrançois Tigeot  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24*c406748eSFrançois Tigeot  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25*c406748eSFrançois Tigeot  */
26*c406748eSFrançois Tigeot 
27*c406748eSFrançois Tigeot #ifndef _ASM_CPUFEATURE_H_
28*c406748eSFrançois Tigeot #define _ASM_CPUFEATURE_H_
29*c406748eSFrançois Tigeot 
30*c406748eSFrançois Tigeot #include <asm/pci-dma-compat.h>
31*c406748eSFrançois Tigeot 
32*c406748eSFrançois Tigeot /* All amd64 CPUs have the clflush instruction */
33*c406748eSFrançois Tigeot #define cpu_has_clflush		1
34*c406748eSFrançois Tigeot 
35*c406748eSFrançois Tigeot #endif	/* _ASM_CPUFEATURE_H_ */
36