xref: /dflybsd-src/sys/dev/drm/include/asm/cpufeature.h (revision 54097f44c44a0078891c808ba5d6ff99d421e8f1)
1c406748eSFrançois Tigeot /*
2c6002f72SFrançois Tigeot  * Copyright (c) 2016-2019 François Tigeot <ftigeot@wolfpond.org>
3c406748eSFrançois Tigeot  * All rights reserved.
4c406748eSFrançois Tigeot  *
5c406748eSFrançois Tigeot  * Redistribution and use in source and binary forms, with or without
6c406748eSFrançois Tigeot  * modification, are permitted provided that the following conditions
7c406748eSFrançois Tigeot  * are met:
8c406748eSFrançois Tigeot  * 1. Redistributions of source code must retain the above copyright
9c406748eSFrançois Tigeot  *    notice unmodified, this list of conditions, and the following
10c406748eSFrançois Tigeot  *    disclaimer.
11c406748eSFrançois Tigeot  * 2. Redistributions in binary form must reproduce the above copyright
12c406748eSFrançois Tigeot  *    notice, this list of conditions and the following disclaimer in the
13c406748eSFrançois Tigeot  *    documentation and/or other materials provided with the distribution.
14c406748eSFrançois Tigeot  *
15c406748eSFrançois Tigeot  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16c406748eSFrançois Tigeot  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17c406748eSFrançois Tigeot  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18c406748eSFrançois Tigeot  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19c406748eSFrançois Tigeot  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20c406748eSFrançois Tigeot  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21c406748eSFrançois Tigeot  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22c406748eSFrançois Tigeot  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23c406748eSFrançois Tigeot  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24c406748eSFrançois Tigeot  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25c406748eSFrançois Tigeot  */
26c406748eSFrançois Tigeot 
27c406748eSFrançois Tigeot #ifndef _ASM_CPUFEATURE_H_
28c406748eSFrançois Tigeot #define _ASM_CPUFEATURE_H_
29c406748eSFrançois Tigeot 
30c6002f72SFrançois Tigeot #include <asm/processor.h>
31c6002f72SFrançois Tigeot 
328621f407SFrançois Tigeot #include <asm/cpufeatures.h>
33c406748eSFrançois Tigeot 
348621f407SFrançois Tigeot static inline bool
358621f407SFrançois Tigeot static_cpu_has(uint16_t feature)
368621f407SFrançois Tigeot {
378621f407SFrançois Tigeot 	switch(feature) {
388621f407SFrançois Tigeot 	case X86_FEATURE_CLFLUSH:
39c406748eSFrançois Tigeot 		/* All amd64 CPUs have the clflush instruction */
408621f407SFrançois Tigeot 		return true;
41*54097f44SFrançois Tigeot 	case X86_FEATURE_HYPERVISOR:
42*54097f44SFrançois Tigeot 		return ((cpu_feature2 & CPUID2_VMM) != 0);
438621f407SFrançois Tigeot 	default:
448621f407SFrançois Tigeot 		return false;
458621f407SFrançois Tigeot 	}
468621f407SFrançois Tigeot }
47c406748eSFrançois Tigeot 
48c59a5c48SFrançois Tigeot #define boot_cpu_has(bit)	static_cpu_has(bit)
49c59a5c48SFrançois Tigeot 
50c406748eSFrançois Tigeot #endif	/* _ASM_CPUFEATURE_H_ */
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